KR20180125657A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device capable of generating an address in which refresh is performed. The semiconductor device comprises: an operation clock generation circuit for generating a first operation clock to perform a cumulative storage mode, and generating a random mode operation clock to perform a random storage mode; and a refresh address generation circuit including first and second address storage circuits in which an input address is stored in the cumulative storage mode, and including a third address storage circuit in which the input address is stored in the random storage mode.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device capable of performing refreshing.

A semiconductor device has a plurality of memory cells for storing data. Each of the memory cells is composed of a cell capacitor and a cell transistor. The semiconductor device stores data through an operation of charging or discharging a charge in the cell capacitor, and the amount of charge stored in the cell capacitor should ideally be always constant. However, the amount of charge stored in the cell capacitor changes due to the voltage difference with the peripheral circuit. The change of the charge amount of the cell capacitor in this way means that the data stored in the cell capacitor is changed, which means that the stored data is lost. The semiconductor device performs a refresh operation in order to prevent the data from being lost.

 On the other hand, as the process technology is developed, the degree of integration of the semiconductor devices increases gradually, so that the interval between the memory cells is reduced and the interval between the word lines connected to each of the memory cells is reduced. If the spacing between the word lines is narrowed, an interference effect occurs between adjacent word lines, so that the data stored in the memory cells connected to the word lines can not be maintained. That is, the probability that data may be lost increases.

Recently, a semiconductor device performs an additional refresh operation on an adjacent word line adjacent to a target word line in which access is concentrated due to an interference effect between word lines, thereby obtaining data of a memory cell connected to an adjacent word line Thereby preventing the data from being lost due to the interference effect between the word lines. Performing a refresh on an adjacent word line when the target word line is active is referred to as smart refresh.

The present invention provides a semiconductor device capable of generating an address where refreshing is performed.

To this end, the present invention comprises an operation clock generation circuit for generating a first operation clock for performing a cumulative storage mode, and for generating an arbitrary mode operation clock for performing an arbitrary storage mode; And a third address storage circuit including a first address storage circuit and a second address storage circuit in which an input address is stored in the cumulative storage mode and in which the input address is stored in the arbitrary storage mode, The counter code corresponding to the address stored in the third address storage circuit is set to be counted by a larger number of bits than the counter code corresponding to the address stored in the first address storage circuit or the second address storage circuit And a semiconductor device.

The invention also relates to a method for generating a refresh address comprising a first address storage circuit and a second address storage circuit in which an input address is stored in a cumulative storage mode and a third address storage circuit in which the input address is stored in an arbitrary storage mode Circuit; And generating a first counter code corresponding to the address stored in the first address storage circuit and generating a second counter code corresponding to the address stored in the second address storage circuit, And a counter code generation circuit for generating a third counter code corresponding to the second counter code.

According to the present invention, it is possible to monitor an address requiring refresh by storing an address at which an active operation is performed and a code value corresponding to the address.

In addition, according to the present invention, an address to be refreshed is selected according to a code value among addresses to which an active operation is performed, thereby preventing unnecessary refreshing and reducing power consumption.

In addition, according to the present invention, an arbitrary storage method in which a code value is counted by the number of times the weight value is given is provided, thereby refreshing can be performed in various ways.

1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.
2 is a circuit diagram according to an embodiment of the arbitrary storage mode signal generation circuit included in the semiconductor device shown in FIG.
3 is a diagram illustrating a configuration according to an embodiment of an operation clock generation circuit included in the semiconductor device shown in FIG.
4 is a diagram showing a configuration according to an embodiment of the refresh address generating circuit included in the semiconductor device shown in FIG.
5 is a table for explaining an operation in which an input control signal is generated in the refresh address generating circuit shown in Fig.
6 is a table for explaining the operation in which the output control signal is generated in the refresh address generating circuit shown in Fig.
7 is a circuit diagram according to an embodiment of the storage selection signal generation circuit included in the semiconductor device shown in FIG.
8 is a timing chart for explaining the operation of the storage selection signal generation circuit shown in FIG.
9 is a circuit diagram according to one embodiment of the maximum storage selection signal generation circuit included in the semiconductor device shown in FIG.
10 is a timing chart for explaining the operation of the maximum storage selection signal generating circuit shown in FIG.
11 is a circuit diagram according to an embodiment of the comparison code generation circuit included in the semiconductor device shown in FIG.
12 is a diagram for explaining the operation of the comparison code generation circuit shown in Fig.
13 is a circuit diagram according to an embodiment of the code comparison signal generation circuit included in the semiconductor device shown in FIG.
FIG. 14 is a diagram illustrating a configuration of a sense signal generation circuit included in the semiconductor device shown in FIG. 1 according to an embodiment of the present invention.
15 is a table for explaining an operation in which the address comparison selection signal is generated in the sense signal generation circuit shown in FIG.
16 is a table for explaining an operation in which a code comparison selection signal is generated in the sense signal generation circuit shown in FIG.
17 is a circuit diagram according to an embodiment of a decoder included in the sense signal generation circuit shown in FIG.
18 is a table for explaining the operation of the decoder shown in Fig.
19 is a block diagram showing a configuration according to an embodiment of a comparison clock generation circuit included in the semiconductor device shown in FIG.
20 is a circuit diagram according to an embodiment of the counter selection generation circuit included in the semiconductor device shown in FIG.
21 is a table for explaining the operation of the counter selection generating circuit shown in Fig.
22 is a circuit diagram according to one embodiment of the counter reset signal generation circuit included in the semiconductor device shown in FIG.
23 is a block diagram showing a configuration according to an embodiment of the counter code generation circuit included in the semiconductor device shown in FIG.
24 is a block diagram showing a configuration according to an embodiment of the first counter code generation circuit included in the counter code generation circuit shown in FIG.
25 is a block diagram showing a configuration according to an embodiment of a second counter code generation circuit included in the counter code generation circuit shown in FIG.
26 is a block diagram showing a configuration according to an embodiment of the third counter code generation circuit included in the counter code generation circuit shown in FIG.
27 is a timing chart for explaining the operation of the semiconductor device according to the embodiment of the present invention.
28 is a view showing a configuration according to an embodiment of an electronic system to which the semiconductor device described in Figs. 1 to 27 is applied.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1, a semiconductor device according to an embodiment of the present invention includes an arbitrary storage mode signal generation circuit 1, an operation clock generation circuit 2, a refresh address generation circuit 3, a selection signal control circuit 4, a code comparison control circuit 5, a sense signal generation circuit 6, a counter reset control circuit 7, and a counter code generation circuit 8.

The random storage mode signal generating circuit 1 may generate a random storage mode signal RSM in response to the oscillation signal OSC, the precharge command PCG and the reset signal RST. The arbitrary storage mode signal generation circuit 1 may generate an arbitrary storage mode signal RSM from the oscillation signal OSC when the precharge command PCG is generated a predetermined number of times. The oscillation signal OSC may be generated in an oscillator (not shown) included in the semiconductor device as a periodic signal that toggles with a predetermined period. An arbitrary storage mode can be executed when an arbitrary storage mode signal (RSM) is generated. In the arbitrary storage mode, the code corresponding to the address at which the active operation is performed may be counted a predetermined number of times, and an operation in which an active operation is performed may be performed in a predetermined storage circuit (not shown). The predetermined number of precharge commands PCG for generating the arbitrary storage mode signal RSM may be variously set according to the embodiment. For example, the arbitrary storage mode signal RSM may be generated from the oscillation signal OSC when the precharge command PCG is generated three times. The arbitrary storage mode signal generation circuit 1 can initialize the arbitrary storage mode signal RSM when the reset signal RST is generated. The logic level at which the arbitrary storage mode signal RSM is initialized can be variously set according to the embodiment.

The operation clock generation circuit 2 generates an operation clock CLK by using the active command ACT, the counter reset signal CNT_RST <1: 3>, the arbitrary storage mode signal RSM, the arbitrary mode operation clock R_CLK, The first operation clock S_CLK, the second operation clock X_CLK, the third operation clock H_CLK, and the random mode operation clock (in this case, the first operation clock S_CLK, the second operation clock X_CLK, and the second operation clock H_CLK) in response to the detection signal MIN_DET, the reset signal RST, R_CLK and an end signal STOP. The active command ACT may be generated to perform an active operation. The minimum sense signal MIN_DET may be enabled when the minimum counting code search operation for finding the least counted code among the codes corresponding to the addresses for which the active operation is performed in the cumulative storage mode is completed. The reset signal RST may be generated in the initialization operation. The maximum sense signal MAX_DET may be enabled when the maximum counting code search operation for finding the most counted code among the codes corresponding to the addresses in which the active operation is performed in the random storage mode or the cumulative storage mode is completed. The operation clock generation circuit 2 may generate the first operation clock S_CLK to perform the cumulative storage mode. In the cumulative storage mode, a code corresponding to an address at which an active operation is performed is counted by one bit, and an address in which an active operation is performed is stored in a storage circuit (not shown) And storing the executed address in a storage circuit in which the address is stored. The operation clock generation circuit 2 may generate the second operation clock X_CLK to perform the maximum counting code search operation. The operation clock generation circuit 2 may generate the third operation clock H_CLK to perform the minimum counting code search operation. The operation clock generation circuit 2 may generate the third operation clock H_CLK to perform the maximum counting code search operation in the arbitrary storage mode or the cumulative storage mode. The operation clock generation circuit 2 can generate an arbitrary mode operation clock R_CLK for storing an address in which an active operation is performed in an arbitrary storage mode or counting a code corresponding to an address at which an active operation is performed, have. The operation clock generation circuit 2 generates the first operation clock S_CLK when the arbitrary storage mode is performed and generates the end signal STOP enabled to generate the second operation clock X_CLK . The operation clock generation circuit 2 can generate an end signal STOP which is enabled when an address identical to the address stored in the storage circuits (not shown) is inputted after the active operation is performed. The operation clock generation circuit 2 can generate the end signal STOP which is enabled after the minimum counting code search operation is performed or when the reset signal RST occurs.

The refresh address generating circuit 3 generates the refresh address signal ACT and the input address IADD and the storage selection signals S_SEL <1: 2>, the minimum sense signal MIN_DET, the refresh activation signal SREN, 1>: 3> and the refresh address SR_ADD in response to the counter reset signal R_CLK and the counter reset signal CNT_RST <1: 3>. The refresh address generating circuit 3 can store the input address IADD in a state in which the active command ACT is generated. The refresh address generating circuit 3 may count the code corresponding to the stored address if the input address IADD for which the active operation is performed is the same as the address already stored. The refresh address generating circuit 3 includes a storage circuit (not shown) storing an address at which an active operation is performed at least a minimum number of times of storage circuits (not shown) when an input address IADD for performing an active operation differs from an address already stored, Lt; RTI ID = 0.0 &gt; IADD. &Lt; / RTI &gt; The refresh address generating circuit 3 generates an input address IADD (not shown) in a predetermined storage circuit (not shown) of the storage circuits (not shown) when the input address IADD in which the active operation is performed in the arbitrary storage mode differs from the address already stored ). &Lt; / RTI &gt; The refresh activation signal SREN may be a signal that is enabled for refresh execution including smart refresh. The refresh address generating circuit 3 can output the codes corresponding to the stored addresses as the latch codes LC &lt; 1: 3 &gt;. The refresh address generating circuit 3 can output the stored address as the refresh address SR_ADD when the code corresponding to the address stored in the state where the enabled refresh activation signal SREN is input is counted by the preset number of times. Since the cell accessed by the refresh address SR_ADD has been activated a predetermined number of times, refresh can be performed. The refresh performed by the refresh address SR_ADD may include a refresh for the adjacent cell.

The selection signal control circuit 4 may include a storage selection signal generation circuit 41 and a maximum storage selection signal generation circuit 42. [ The storage selection signal generation circuit 41 can generate the storage selection signal S_SEL <1: 2> that is counted in synchronization with the first operation clock S_CLK. The storage selection signal generation circuit 41 generates the storage selection signal generating circuit 41 from '00' to '01' in the initial state in synchronization with the time point (hereinafter referred to as 'rising edge') at which the first operation clock S_CLK transitions from a logic low level to a logic high level. 1 &gt; 2 &gt;), which are sequentially counted up by one bit by one bit in the order of '10' and '11'. The storage select signal S_SEL <1: 2> is '01' indicating that the first bit S_SEL <1> of the storage select signal is at a logic high level and the second bit S_SEL < Which means low level. The maximum storage selection signal generation circuit 42 may generate the maximum storage selection signal M_SEL <1: 2> that is counted in synchronization with the second operation clock X_CLK. The maximum storage selection signal generating circuit 42 sequentially outputs 1 bit in the initial state from '00' to '01', '10', '11' in synchronization with the rising edge of the second operation clock X_CLK (M_SEL &lt; 1: 2 &gt;) to be counted. 1 &quot;) of the maximum storage selection signal is a logic low level and the second bit (M_SEL < 2 >) of the maximum storage selection signal is M_SEL < ) Is a logic high level.

 The code comparison control circuit 5 may include a comparison code generation circuit 51 and a code comparison signal generation circuit 52. [ The comparison code generation circuit 51 generates the code setting signal STA and the comparison code SCD <1: 2> in response to the third operation clock H_CLK, the end signal STOP and the maximum sense signal MAX_DET can do. The comparison code generating circuit 51 may generate a code setting signal STA having a first logic level before the maximum counting code search operation is performed and may generate a code setting signal STA having a second logic level The code setting signal STA can be generated. The first logic level and the second logic level of the code setting signal STA may be set differently according to the embodiment. The comparison code generation circuit 51 may generate a comparison code SCD <1: 2> that is counted in synchronization with the rising edge of the third operation clock H_CLK. The comparison code generation circuit 51 can count the comparison codes SCD <1: 2> in a different manner according to the logic level of the code setting signal STA. When the code setting signal STA is at the first logic level, the comparison code generating circuit 51 generates the comparison code generating circuit 51 in synchronization with the rising edge of the third operation clock H_CLK from '00' to '01', '10' (SCD &lt; 1: 2 &gt;), which is sequentially counted up by 1 bit by 11 bits. When the code setting signal STA is at the second logic level, the comparison code generating circuit 51 generates the comparison code generating circuit 51 in synchronization with the rising edge of the third operation clock H_CLK from '11' to '10', '01' (SCD &lt; 1: 2 &gt;), which is sequentially down-counted by 1 bit to 00 '. The code comparison signal generation circuit 52 compares the comparison code SCD <1: 2> with the first counter code CNT_CD1 <1: 2> to generate the first bit CD_COM <1> of the code comparison signal . The code comparison signal generation circuit 52 compares the comparison code SCD <1: 2> with the second counter code CNT_CD2 <1: 2> to generate the second bit of the code comparison signal CD_COM <2> . The code comparison signal generation circuit 52 compares the comparison code SCD <1: 2> with the third counter code CNT_CD3 <1: 2> to generate the third bit of the code comparison signal CD_COM <3> .

The sense signal generation circuit 6 generates the sense signal S_SEL <1: 2>, the latch code LC <1: 3>, the maximum save selection signal M_SEL < The minimum sense signal MIN_DET and the maximum sense signal MAX_DET in response to the code set signal STA and the comparison code SCD <1: 2> have. The sense signal generation circuit 6 may generate the same sense signal S_DET that is enabled if the input address IADD is the same as the address already stored. The sense signal generation circuit 6 generates a minimum sense signal MIN_DET that is enabled after the minimum counting code search operation for finding the least counted code among the codes corresponding to the addresses where the active operation is performed in the cumulative storage mode is performed, Lt; / RTI > The detection signal generation circuit 6 detects the maximum counted code among the codes corresponding to the addresses where the active operation is performed in the random storage mode or the cumulative storage mode, It is possible to generate the signal MAX_DET.

The counter reset control circuit 7 may include a comparison clock generation circuit 71, a counter selection signal generation circuit 72 and a counter reset signal generation circuit 73. [ The comparison clock generation circuit 71 may generate the comparison clock COM_CLK in response to the same sense signal S_DET and the random storage mode signal RSM. The comparison clock generation circuit 71 can generate a comparison clock COM_CLK that toggles a predetermined number of times when the input address IADD is the same as the address already stored in the arbitrary storage mode. The number of times the comparison clock signal COM_CLK is toggled can be variously set according to the embodiment. The counter selection signal generation circuit 72 can generate the counter selection signal CNT_SEL <1: 3> in response to the storage selection signal S_SEL <1: 2>. The counter selection signal generation circuit 72 can generate a counter selection signal CNT_SEL <1: 3> including a bit selectively enabled in accordance with the logical level combination of the storage selection signals S_SEL <1: 2> have. The counter reset signal generation circuit 73 can generate the counter reset signal CNT_RST <1: 3> in response to the counter selection signals CNT_SEL <1: 3> and the maximum sense signal MAX_DET. The counter reset signal generation circuit 73 generates a counter reset signal CNT_SEL <1: 3> including a bit selectively enabled in accordance with the logic level combination of the counter selection signals CNT_SEL <1: 3> in a state in which the maximum sense signal MAX_DET is enabled. (CNT_RST &lt; 1: 3 &gt;).

The counter code generation circuit 8 generates the counter selection signals CNT_SEL <1: 3>, the counter reset signals CNT_RST <1: 3>, the comparison clock COM_CLK, the same sensing signal S_DET, ), The second counter code CNT_CD2 <1: 2>, and the third counter code CNT_CD2 <1: 2> in response to the random mode operation clock R_CLK and the refresh activation signal SREN CNT_CD3 < 1: 2 >). The counter code generation circuit 8 generates the first counter code CNT_CD1 <1: 2> in response to the counter selection signals CNT_SEL <1: 3>, the comparison clock COM_CLK and the same detection signal S_DET, It is possible to count the counter codes CNT_CD2 <1: 2> and the third counter codes CNT_CD3 <1: 2>. The counter code generation circuit 8 generates the first counter code CNT_CD1 <1: 2> by the counter selection signal CNT_SEL <1: 3> while the same sense signal S_DET is enabled in the cumulative storage mode, It is possible to select and count one of the second counter code CNT_CD2 <1: 2> and the third counter code CNT_CD3 <1: 2>. The counter code generation circuit 8 generates the first counter code CNT_CD1 <1: 2>, the second counter code CNT_CD2 <1: 2> and the second counter code CNT_CD2 <1: 2> each time the comparison clock COM_CLK toggles in the arbitrary storage mode. It is possible to count the code selected by the counter selection signal (CNT_SEL <1: 3>) of the three counter codes (CNT_CD3 <1: 2>). The counter code generation circuit 8 outputs the counter code CNT_CD1 <1: 2>, the second counter code CNT_CD2 <1: 2> and the third counter code CNT_CD1 < (CNT_CD3 <1: 2>) can be initialized. The counter code generation circuit 8 generates a first counter code CNT_CD1 <1: 2>, a second counter code CNT_CD2 <1: 2> and a third counter code CNT_CD3 < 1: 2>), the selected code can be initialized according to the logic level combination of the counter selection signal CNT_SEL <1: 3>.

2, the arbitrary storage mode signal generating circuit 1 may include a first mode latch 11, a second mode latch 12 and a third mode latch 13. [ The first mode latch 11 can latch and output the oscillation signal OSC when the precharge command PCG is generated. The first mode latch 11 can be initialized when the reset signal RST is input. The second mode latch 12 may latch and output the output signal of the first mode latch 11 when the precharge command PCG is generated. The second mode latch 12 can be initialized when the reset signal RST is input. The third mode latch 13 can latch and output the output signal of the second mode latch 12 when the precharge command PCG is generated. The third mode latch 13 can be initialized when the reset signal RST is input. The arbitrary storing mode signal generating circuit 1 can generate an arbitrary storing mode signal RSM which is enabled to perform an arbitrary storing mode from the oscillation signal OSC when the precharge command PCG is generated three times have.

3, the operation clock generation circuit 2 includes a first operation clock generation circuit 21, a second operation clock generation circuit 22, a termination signal buffer circuit 23, and a third operation clock generation circuit 24, . &Lt; / RTI &gt;

The first operation clock generation circuit 21 may include a start signal generation circuit 211, a termination signal generation circuit 212, and a clock output circuit 213. The start signal generating circuit 211 can generate the start signal STR in response to the active command ACT, the counter reset signals CNT_RST <1: 3>, and the arbitrary storage mode signal RSM. The start signal generating circuit 211 generates a start signal STR when the active command ACT is generated while the counter reset signals CNT_RST <1: 3> and the arbitrary storage mode signal RSM are both disabled, Can be generated. The start signal generating circuit 211 may generate a start signal STR which is enabled when all the counter reset signals CNT_RST <1: 3> are disabled when an active operation is performed in the cumulative storage mode.

The termination signal generation circuit 212 may generate the termination signal STOP in response to the arbitrary mode operation clock R_CLK, the same sense signal S_DET, the minimum sense signal MIN_DET and the reset signal RST. The shutdown signal generation circuit 212 stops generation of the first operation clock S_CLK when an arbitrary storage mode is performed and the arbitrary mode operation clock R_CLK is toggled and generates the second operation clock X_CLK And generate a termination signal (STOP) that is enabled to a logic high level. The end signal generation circuit 212 receives an address identical to the address stored in the storage circuits (not shown) after the active operation is performed, and outputs a logic high level when the same sense signal S_DET is enabled to a logic high level. It is possible to generate a termination signal STOP that is enabled. The termination signal generation circuit 212 may generate a termination signal STOP that is enabled to a logic high level when a minimum counting code search operation is performed to enable the minimum sense signal MIN_DET to be a logic high level. The termination signal generation circuit 212 may generate a termination signal STOP that is enabled to a logic high level when the reset signal RST occurs at a logic high level for an initialization operation.

The clock output circuit 213 may generate a first operation clock S_CLK for performing the cumulative storage mode in response to the start signal STR and the end signal STOP. The clock output circuit 213 may generate the first operation clock S_CLK when the start signal STR is enabled. The clock output circuit 213 can stop the generation of the first operation clock S_CLK when the end signal STOP is enabled.

The second operation clock generation circuit 22 can generate the second operation clock X_CLK in response to the end signal STOP and the maximum sense signal MAX_DET. The second operation clock generation circuit 22 can generate the second operation clock X_CLK when the end signal STOP is enabled. The second operation clock generation circuit 22 can stop the generation of the second operation clock X_CLK when the maximum sense signal MAX_DET is enabled. The second operation clock generation circuit 22 generates a second count clock signal for performing the second count operation to perform the maximum counting code search operation for finding the most counted code among the codes corresponding to the addresses where the active operation is performed in the random storage mode or the cumulative storage mode. It is possible to generate the clock (X_CLK).

The end signal buffer circuit 23 can generate the buffer end signal BSTOP in response to the end signal STOP and the maximum sense signal MAX_DET. The termination signal buffer circuit 23 can generate the buffer termination signal BSTOP by buffering the termination signal STOP in a state in which the maximum sense signal MAX_DET is disabled to a logic low level. The termination signal buffer circuit 23 may generate a logic high level enabled buffer termination signal BSTOP when the maximum sense signal MAX_DET is enabled to a logic high level.

The third operation clock generation circuit 24 generates the third operation clock H_CLK in response to the first operation clock S_CLK, the second operation clock X_CLK, the arbitrary storage mode signal RSM and the buffer end signal BSTOP. And an arbitrary mode operating clock (R_CLK). The third operation clock generation circuit 24 generates the third operation clock H_CLK or the third operation clock H_CLK to perform the minimum counting code search operation and the maximum counting code search operation when the first operation clock S_CLK or the second operation clock X_CLK is generated, Can be generated. The third operating clock generation circuit 24 may generate an arbitrary mode operating clock R_CLK by an arbitrary storage mode signal RSM enabled in an arbitrary storage mode.

4, the refresh address generating circuit 3 includes an input control signal generating circuit 31, an output control signal generating circuit 32, a first latch address generating circuit 33, a second latch address generating circuit 34, A third latch address generating circuit 35, and a refresh address output circuit 36. [

The input control signal generation circuit 31 generates the first input control signal PIN1 and the second input control signal PIN2 in response to the storage selection signals S_SEL <1: 2> and the minimum sensing signal MIN_DET . The input control signal generation circuit 31 generates a logic high level when the logic level combination of the storage select signals S_SEL <1: 2> is '00' in a state where the minimum sense signal MIN_DET is enabled to a logic high level It is possible to generate the first input control signal PIN1 that is enabled. The case where the logic level combination of the storage select signals S_SEL <1: 2> is '00' means that all bits included in the storage select signals S_SEL <1: 2> are logic low levels. The input control signal generation circuit 31 generates a logic high level when the logic level combination of the storage select signals S_SEL <1: 2> is '01' in a state where the minimum sense signal MIN_DET is enabled to a logic high level And generate a second input control signal PIN2 that is enabled. The case where the logic level combination of the storage select signals S_SEL <1: 2> is '01' means that the first bit S_SEL <1> of the storage select signal is a logic high level and the second bit S_SEL &Lt; 2 >) is a logic low level.

The output control signal generation circuit 32 outputs the first output control signal POUT1, the second output control signal POUT2 and the third output control signal POUT2 in response to the refresh activation signal SREN and the counter reset signal CNT_RST <1: 3> It is possible to generate the output control signal POUT3. The output control signal generation circuit 32 generates a logic high level when the logic level combination of the counter reset signal CNT_RST <1: 3> is '001' in a state where the refresh activation signal SREN is enabled to a logic high level It is possible to generate the first output control signal POUT1 to be enabled. When the logic level combination of the counter reset signal CNT_RST <1: 3> is '001', the first bit CNT_RST <1> of the counter reset signal is at a logic high level and the second bit CNT_RST <2>) and the third bit (CNT_RST <3>) of the counter reset signal is a logic low level. The output control signal generation circuit 32 generates a logic high level when the logic level combination of the counter reset signal CNT_RST <1: 3> is '010' in a state where the refresh activation signal SREN is enabled to a logic high level It is possible to generate the second output control signal POUT2 to be enabled. The case where the logic level combination of the counter reset signal CNT_RST <1: 3> is '010' means that the first bit CNT_RST <1> of the counter reset signal and the third bit CNT_RST <3> Logic low level, and the second bit (CNT_RST < 2 >) of the counter reset signal is a logic high level. The output control signal generation circuit 32 generates a logic high level when the logic level combination of the counter reset signal CNT_RST <1: 3> is '100' in a state where the refresh activation signal SREN is enabled to a logic high level It is possible to generate the third output control signal POUT3 to be enabled. The case where the logic level combination of the counter reset signal CNT_RST <1: 3> is "100" means that the first bit CNT_RST <1> of the counter reset signal and the second bit CNT_RST <2> Logic low level, and the third bit (CNT_RST <3>) of the counter reset signal is a logic high level.

The first latch address generating circuit 33 may include a first address comparing circuit 331, a first address comparing signal latch 332, and a first address storing circuit 333. The first address comparison circuit 331 can generate the first address comparison signal A_COM1 whose logic level is set by comparing the input address IADD and the first latch address LADD1. The first address comparison circuit 331 can generate the first address comparison signal A_COM1 having a logic high level when the input address IADD and the first latch address LADD1 are the same, And generates a first address comparison signal A_COM1 of a logic low level when one latch address LADD1 is different. The first address comparison signal latch 332 can latch the first address comparison signal A_COM1 in response to the active command ACT and output it as the first latch code LC <1>. The first address comparison signal latch 332 can latch the first address comparison signal A_COM1 and output it as the first latch code LC <1> while the active operation is performed and the active command ACT is generated have. The first address storage circuit 333 stores the input address IADD in response to the first input control signal PIN1 and the first output control signal POUT1 and outputs the first latch address LADD1 . The first address storage circuit 333 may store the input address IADD when the first input control signal PIN1 is enabled. The first address storage circuit 333 may output the stored input address IADD to the first latch address LADD1 when the first output control signal POUT1 is enabled.

The second latch address generating circuit 34 may include a second address comparing circuit 341, a second address comparing signal latch 342 and a second address storing circuit 343. [ The second address comparison circuit 341 can compare the input address IADD and the second latch address LADD2 to generate the second address comparison signal A_COM2 whose logic level is set. The second address comparison circuit 341 can generate the second address comparison signal A_COM2 of a logic high level when the input address IADD and the second latch address LADD2 are the same, And generates a second address comparison signal A_COM2 of a logic low level when the two latch addresses LADD2 are different from each other. The second address comparison signal latch 342 can latch the second address comparison signal A_COM2 in response to the active command ACT and output it as the second latch code LC <2>. The second address comparison signal latch 342 can latch the second address comparison signal A_COM2 and output it as the second latch code LC <2> in a state where the active operation is performed and the active command ACT is generated have. The second address storage circuit 343 stores the input address IADD and outputs the second latch address LADD2 in response to the second input control signal PIN2 and the second output control signal POUT2 . The second address storage circuit 343 may store the input address IADD when the second input control signal PIN2 is enabled. The second address storage circuit 343 may output the stored input address IADD to the second latch address LADD2 when the second output control signal POUT2 is enabled.

The third latch address generating circuit 35 may include a third address comparing circuit 351, a third address comparing signal latch 352 and a third address storing circuit 353. [ The third address comparison circuit 351 can compare the input address IADD and the third latch address LADD3 to generate the third address comparison signal A_COM3 whose logic level is set. The third address comparison circuit 351 can generate the third address comparison signal A_COM3 of a logic high level when the input address IADD and the third latch address LADD3 are the same, And generates a third address comparison signal A_COM3 of a logic low level when the three latch addresses LADD3 are different from each other. The third address comparison signal latch 352 can latch the third address comparison signal A_COM3 in response to the active command ACT and output it to the third latch code LC <3>. The third address comparison signal latch 352 can latch the third address comparison signal A_COM3 and output it as the third latch code LC <3> in a state where the active operation is performed and the active command ACT is generated have. The third address storage circuit 353 stores the input address IADD in response to the arbitrary mode operation clock R_CLK and the third output control signal POUT3 and outputs the third latch address LADD3. The third address storage circuit 353 may store the input address IADD when an arbitrary mode operation clock R_CLK is generated. The third address storage circuit 353 may output the stored input address IADD to the third latch address LADD3 when the third output control signal POUT3 is enabled.

The refresh address output circuit 36 buffers one of the first latch address LADD1, the second latch address LADD2 and the third latch address LADD3 in response to the refresh activation signal SREN to output the refresh address SR_ADD, . The refresh address output circuit 36 outputs the first latch address LADD1 to the first address storage circuit 333 when the first output control signal POUT1 is enabled in a state in which the refresh activation signal SREN is enabled, The first latch address LADD1 may be output as the refresh address SR_ADD. The refresh address output circuit 36 outputs the second latch address LADD2 to the second address storage circuit 343 when the second output control signal POUT2 is enabled while the refresh activation signal SREN is enabled The second latch address LADD2 may be output as the refresh address SR_ADD. The refresh address output circuit 36 outputs the third latch control signal POUT3 to the third latch address LADD3 from the third address storage circuit 353 when the refresh activation signal SREN is enabled, The third latch address LADD3 may be output as the refresh address SR_ADD.

Referring to FIG. 5, the first input control signal PIN1 and the second input control signal PIN2, which are selectively enabled according to the storage selection signals S_SEL <1: 2> and the minimum sensing signal MIN_DET, have. The first input control signal < RTI ID = 0.0 > (1) &lt; / RTI &gt; that is enabled to a logic high level when the logic level combination of the storage select signals S_SEL & PIN1) is generated. And a second input control signal (e. G., A logic high level) which is enabled to a logic high level when the logic level combination of the storage select signals S_SEL &lt; 1: 2 &gt; is '01' while the minimum sense signal MIN_DET is enabled to a logic high level PIN2) is generated.

6, the first output control signal POUT1, the second output control signal POUT2, and the third output control signal POUT3 selectively enabled according to the refresh enable signal SREN and the counter reset signal CNT_RST <1: 3> The output control signal POUT3 can be confirmed. The logic level combination of the counter reset signal CNT_RST < 1: 3 > is '001' in a state where the refresh enable signal SREN is enabled to a logic high level, POUT1) is generated. The logic level combination of the counter reset signal CNT_RST < 1: 3 > is '010' in the state that the refresh enable signal SREN is enabled to the logic high level, POUT2) is generated. The logic level combination of the counter reset signals CNT_RST <1: 3> is '100' in a state where the refresh enable signal SREN is enabled to a logic high level, and a third output control signal POUT3) is generated.

Referring to FIG. 7, the storage select signal generating circuit 41 may include a first storage latch 411 and a second storage latch 412. The first storage latch 411 latches the output signal of the first inverting output terminal QB1 input through the first input terminal D1 in synchronization with the first operation clock S_CLK and outputs the latched output signal to the first output terminal Q1 . The first storage latch 411 may output the first bit (S_SEL < 1 >) of the storage select signal through the first inverting output QB1. The first storage latch 411 initializes the output signals of the first output terminal Q1 and the first inverted output terminal QB1 when the reset signal RST is generated. The second storage latch 412 latches the output signal of the second inverting output terminal QB2 input through the second input terminal D2 in synchronization with the output signal of the first output terminal Q1 of the first storage latch 411, And outputs it to the second output terminal Q2. The second storage latch 412 may output the second bit (S_SEL <2>) of the storage select signal via the second inverting output QB2. The second storage latch 412 initializes the output signals of the second output terminal Q2 and the second inverted output terminal QB2 when the reset signal RST is generated.

The operation of the storage selection signal generation circuit 41 will be described with reference to FIG. The output signals of the first output terminal Q1, the first inverted output terminal QB1, the second output terminal Q2 and the second inverted output terminal QB2 are respectively at a logic low level, a logic high level, a logic low level And logic high level. The output signal of the first output terminal Q1 transitions from the logic low level to the logic high level in synchronization with the rising edge of the first operation clock S_CLK generated at the time T11 and the output signal of the first inverted output terminal QB1 The output signal of the second output Q2 transitions from a logic low level to a logic high level and the output signal of the second inverting output QB2 transitions from a logic high level to a logic low level . At the time T12, the output signal of the first output terminal Q1 transitions from a logic high level to a logic low level in synchronization with the rising edge of the first operation clock S_CLK, and the output signal of the first inverted output terminal QB1 changes to a logic low Level to a logic high level. At time T13, the output signal of the first output terminal Q1 transitions from a logic low level to a logic high level in synchronization with the rising edge of the first operation clock S_CLK, and the output signal of the first inverted output terminal QB1 transitions from a logic high Level to a logic low level. At time T13, the output signal of the second output terminal Q2 transitions from a logic high level to a logic low level in synchronization with the rising edge of the output signal of the first output terminal Q1, and the output signal of the second inversion output terminal QB2 Transition from a logic low level to a logic high level. At the time T14, the output signal of the first output terminal Q1 transitions from a logic high level to a logic low level in synchronization with the rising edge of the first operation clock S_CLK, and the output signal of the first inverted output terminal QB1 becomes logic low Level to a logic high level.

As described above, the logic level combination of the storage select signal S_SEL <1: 2> output through the first inverted output terminal QB1 and the second inverted output terminal QB2 of the storage select signal generating circuit 41 is' 00 ',' 01 ',' 10 ', and' 11 '. That is, the storage selection signal generation circuit 41 generates a storage selection signal S_SEL <1: 2> in which the logic level combination is counted up by one bit in synchronization with the rising edge of the first operation clock S_CLK do.

Referring to FIG. 9, the maximum storage select signal generating circuit 42 may include a first maximum storage latch 421 and a second maximum storage latch 422. The first maximum storage latch 421 latches the output signal of the first inverting output terminal QB1 input through the first input terminal D1 in synchronization with the second operation clock X_CLK and outputs it to the first output terminal Q1 do. The first maximum storage latch 421 may output the first bit (M_SEL < 1 >) of the maximum storage select signal via the first inverting output QB1. The first maximum storage latch 421 initializes the output signals of the first output terminal Q1 and the first inverted output terminal QB1 when the reset signal RST is generated. The second maximum storage latch 422 receives the output signal of the second inverting output terminal QB2 input through the second input terminal D2 in synchronization with the output signal of the first output terminal Q1 of the first maximum storage latch 421, And outputs it to the second output terminal Q2. The second maximum storage latch 422 may output the second bit (S_SEL < 2 >) of the maximum storage select signal via the second inversion output QB2. The second maximum storage latch 422 initializes the output signals of the second output Q2 and the second inverting output QB2 when the reset signal RST is generated.

The operation of the maximum storage selection signal generating circuit 42 will be described with reference to FIG. The output signals of the first output terminal Q1, the first inverted output terminal QB1, the second output terminal Q2 and the second inverted output terminal QB2 are respectively at a logic low level, a logic high level, a logic low level And logic high level. The output signal of the first output terminal Q1 transitions from the logic low level to the logic high level in synchronization with the rising edge of the second operation clock X_CLK generated at the time T21 and the output signal of the first inversion output terminal QB1 The output signal of the second output Q2 transitions from a logic low level to a logic high level and the output signal of the second inverting output QB2 transitions from a logic high level to a logic low level . At the time T22, the output signal of the first output terminal Q1 transitions from a logic high level to a logic low level in synchronization with the rising edge of the second operation clock X_CLK, and the output signal of the first inversion output terminal QB1 changes to a logic low Level to a logic high level. At time T23, the output signal of the first output terminal Q1 transitions from a logic low level to a logic high level in synchronization with the rising edge of the second operation clock X_CLK, and the output signal of the first inversion output terminal QB1 transitions from a logic high Level to a logic low level. At time T23, the output signal of the second output terminal Q2 transitions from a logic high level to a logic low level in synchronization with the rising edge of the output signal of the first output terminal Q1, and the output signal of the second inversion output terminal QB2 Transition from a logic low level to a logic high level. At time T24, the output signal of the first output terminal Q1 transitions from a logic high level to a logic low level in synchronization with the rising edge of the second operation clock X_CLK, and the output signal of the first inversion output terminal QB1 changes to a logic low Level to a logic high level.

The logic level combination of the maximum storage selection signal M_SEL <1: 2> output through the first inverted output terminal QB1 and the second inverted output terminal QB2 of the maximum storage selection signal generating circuit 42, Are sequentially counted in the order of '00', '01', '10', '11'. That is, the maximum storage selection signal generation circuit 42 generates a maximum storage selection signal M_SEL <1: 2> in which the logic level combination is counted up by one bit in synchronization with the rising edge of the second operation clock X_CLK, .

11, the comparison code generation circuit 51 includes a first comparison latch 511, a second comparison latch 512, a code setting signal generation circuit 513, a first code synthesizer 514, (515). The first comparison latch 511 latches the output signal of the first inverting output terminal QB1 input through the first input terminal D1 in synchronization with the third operation clock H_CLK and outputs the latched output signal to the first output terminal Q1 . The second comparison latch 512 outputs the output signal of the second inverting output terminal QB2 input through the second input terminal D2 in synchronization with the output signal of the first output terminal Q1 of the first comparison latch 511, And outputs it to the second output terminal Q2. The code setting signal generation circuit 513 can generate the code setting signal STA in response to the end signal STOP and the maximum sense signal MAX_DET. The code setting signal generation circuit 513 can generate a code setting signal STA driven at a logic low level with the maximum sense signal MAX_DET being disabled to a logic low level. The code setting signal generation circuit 513 can generate a code setting signal STA driven to a logic high level when the termination signal STOP is enabled to a logic high level. The first code synthesizer 514 can generate the first bit SCD < 1 > of the comparison code in response to the code setting signal STA and the output signal of the first comparison latch 511. [ The first code synthesizer 514 can buffer and output the output signal of the first comparison latch 511 when the code setting signal STA is at a logic low level and when the code setting signal STA is at a logic high level The output signal of the first comparison latch 511 can be reversely buffered and output. The second code synthesizer 515 may generate the second bit of the comparison code SCD < 2 > in response to the code setting signal STA and the output signal of the second comparison latch 512. [ The second code synthesizer 515 can buffer and output the output signal of the second comparison latch 512 when the code setting signal STA is at a logic low level and when the code setting signal STA is at a logic high level The output signal of the second comparison latch 512 can be reversely buffered and output.

The operation of generating the comparison code SCD <1: 2> with reference to FIG. 12 will be described below.

As shown in FIG. 12, since the code setting signal STA is set to a logic low level before the maximum counting code search operation is performed, the logic level combination of the comparison codes SCD <1: 2> Are sequentially counted up by 1 bit by '01', '10', and '11', respectively. The logic level combination of the comparison codes SCD <1: 2> is changed from '11' to '10', '01', and so on because the code setting signal STA is set to a logic high level when the maximum counting code search operation is performed. Are sequentially counted down by one bit by '00'.

13, the code comparison signal generation circuit 52 may include a first code comparison signal generation circuit 521, a second code comparison signal generation circuit 522 and a third code comparison signal generation circuit 523 have. The first code comparison signal generation circuit 521 compares the first comparison code SCD <1: 2> with the first counter code CNT_CD1 <1: 2> and outputs the first bit CD_COM <1> Can be generated. The second code comparison signal generation circuit 522 compares the second bit (CD_COM <2>) of the code comparison signal by comparing the comparison code SCD <1: 2> with the second counter code CNT_CD2 < Can be generated. The third code comparison signal generation circuit 523 compares the third bit (CD_COM <3>) of the code comparison signal by comparing the comparison code SCD <1: 2> with the third counter code CNT_CD3 < Can be generated.

14, the sense signal generation circuit 6 may include an address comparison signal selection circuit 61, a code comparison signal selection circuit 62, and a decoder 63. [

The address comparison signal selection circuit 61 can generate the address comparison selection signal ACOM_SEL in response to the storage selection signal S_SEL <1: 2> and the latch code LC <1: 3>. The address comparison signal selection circuit 61 selects one of the bits included in the latch code LC <1: 3> according to the logic level combination of the storage selection signal S_SEL <1: 2> to the address comparison selection signal ACOM_SEL ) Can be selected and output. The bits included in the latch code LC <1: 3> selected by the address comparison selection signal ACOM_SEL according to the logic level combination of the storage selection signals S_SEL <1: 2> are variously set according to the embodiment .

The code comparison signal selection circuit 62 selects one of the code setting signal STA, the storage selection signal S_SEL <1: 2>, the maximum storage selection signal M_SEL <1: 2> and the code comparison signal CD_COM < >) To generate a code comparison selection signal CCOM_SEL. The code comparison signal selection circuit 62 selects the code comparison signal CD_COM <1: 3> included in the code comparison signal CD_COM <1: 3> according to the logic level combination of the code selection signal STA and the storage selection signal S_SEL < One of the bits can be selected and output as the code comparison selection signal CCOM_SEL. The bits included in the code comparison signal CD_COM <1: 3> selected by the code comparison selection signal CCOM_SEL according to the logic level combination of the storage selection signals S_SEL <1: 2> .

The decoder 63 responds to the address comparison selection signal ACOM_SEL, the code comparison selection signal CCOM_SEL, the comparison code SCD <1: 2> and the code setting signal STA to output the same sensing signal S_DET, The signal MIN_DET and the maximum sense signal MAX_DET. The decoder 63 can generate the same sense signal S_DET whose logic level is determined according to the logic level combination of the comparison codes SCD <1: 2> and the logic level of the address comparison selection signal ACOM_SEL. The decoder 63 can generate the minimum sensing signal MIN_DET whose logic level is determined according to the logic levels of the code comparison selection signal CCOM_SEL and the code setting signal STA. The decoder 63 can generate the maximum sense signal MAX_DET whose logic level is determined according to the logic levels of the code comparison selection signal CCOM_SEL and the code setting signal STA. The logic level of the minimum sensing signal MIN_DET and the maximum sensing signal MAX_DET generated according to the logic levels of the code comparison selection signal CCOM_SEL and the code setting signal STA may be variously set according to the embodiment.

15, a bit selected by the address comparison selection signal ACOM_SEL according to a logic level combination of the storage selection signals S_SEL <1: 2> among the bits included in the latch codes LC <1: 3> Can be confirmed. When the storage select signal S_SEL <1: 2> is '00', the first bit (LC <1>) of the latch code is selected as the address compare select signal ACOM_SEL. The case where the storage select signal S_SEL <1: 2> is '00' means that all bits included in the storage select signal S_SEL <1: 2> are logic low level. When the storage select signals S_SEL <1: 2> are '01', the second bit (LC <2>) of the latch code is selected as the address comparison select signal ACOM_SEL. The case where the storage select signal S_SEL <1: 2> is '01' means that the first bit S_SEL <1> of the storage select signal is at a logic high level and the second bit S_SEL < &Lt; / RTI &gt; is a logic low level. When the storage selection signal S_SEL <1: 2> is '10', the third bit (LC <3>) of the latch code is selected as the address comparison selection signal ACOM_SEL. The case where the storage select signal S_SEL <1: 2> is "10" means that the first bit S_SEL <1> of the storage select signal is a logic low level and the second bit S_SEL < &Lt; / RTI &gt; is a logic high level.

16, among the bits included in the code comparison signal CD_COM <1: 3>, the code setting signal STA, the first and second storage selection signals S_SEL <1: 2> It is possible to confirm the bit selected by the code comparison selection signal CCOM_SEL according to the logic level combination of the two maximum storage selection signals M_SEL <1: 2>. When the code setting signal STA is at a logic low level and the storage selection signal S_SEL <1: 2> is '00', the first bit (CD_COM <1>) of the code comparison signal is supplied to the code comparison selection signal CCOM_SEL Is selected. When the code setting signal STA is at a logic low level and the storage selection signal S_SEL <1: 2> is 01, the second bit of the code comparison signal CD_COM <2> is set to the code comparison selection signal CCOM_SEL Is selected. When the code setting signal STA is at a logic low level and the storage selection signal S_SEL <1: 2> is "10", the third bit (CD_COM <3>) of the code comparison signal is set to the code comparison selection signal CCOM_SEL Is selected. The first bit of the code comparison signal CD_COM <1> is the code comparison selection signal CCOM_SEL when the code setting signal STA is at a logic high level and the maximum storage selection signal M_SEL <1: 2> . The second bit of the code comparison signal CD_COM <2> is the code comparison selection signal CCOM_SEL when the code setting signal STA is at a logic high level and the maximum storage selection signal M_SEL <1: 2> . The third bit of the code comparison signal CD_COM <3> is the code comparison selection signal CCOM_SEL when the code setting signal STA is at a logic high level and the maximum storage selection signal M_SEL <1: 2> .

Referring to FIG. 17, the decoder 63 may include inverters IV61, IV62, and IV63 and AND gates AND61, AND62, and AND63. The AND gate AND61 receives the second bit SCD <2> of the inverted buffered comparison code, the first bit SCD <1> of the inverted buffered comparison code, and the address comparison selection signal ACOM_SEL, To generate the same sense signal S_DET. The AND gate AND62 receives the code comparison selection signal CCOM_SEL and the inverted buffered code setting signal STA and performs an AND operation to generate the minimum sensing signal MIN_DET. The AND gate AND63 receives the code comparison selection signal CCOM_SEL and the code setting signal STA and performs an AND operation to generate the maximum sensing signal MAX_DET.

Referring to FIG. 18, in accordance with the logical levels of the comparison codes SCD <1: 2>, the address comparison selection signal ACOM_SEL, the code comparison selection signal CCOM_SEL, and the code setting signal STA, The signal S_DET, the minimum sensing signal MIN_DET, and the maximum sensing signal MAX_DET. The same sense signal S_DET is enabled to a logic high level when the address comparison selection signal ACOM_SEL is at a logic high level while the comparison code SCD <1: 2> is '00'. When the code comparison signal CCOM_SEL is at a logic high level while the code setting signal STA is at a logic low level, the minimum sensing signal MIN_DET is enabled to a logic high level. When the code comparison signal CCOM_SEL is at a logic high level while the code setting signal STA is at a logic high level, the maximum sensing signal MAX_DET is enabled to a logic high level.

Referring to FIG. 19, the comparison clock generation circuit 71 may include a comparison input circuit 711 and a comparison clock output circuit 712. The comparison input circuit 711 may receive the same sense signal S_DET and the arbitrary storage mode signal RSM to perform an AND operation. The comparison input circuit 711 can output a logic high level when both the same sense signal S_DET and the arbitrary storage mode signal RSM are enabled to a logic high level. The comparison clock output circuit 712 can generate a comparison clock COM_CLK that toggles the output signal of the comparison input circuit 711 a predetermined number of times when the output signal of the comparison input circuit 711 is at a logic high level. The number of times the comparison clock signal COM_CLK is toggled can be variously set according to the embodiment.

20, the counter selection generating circuit 72 may include inverters IV71 and IV72 and AND gates AND71, AND72 and AND73. The AND gate AND71 receives the first bit (S_SEL <1>) of the inverted buffered storage selection signal and the second bit (S_SEL <2>) of the inverted buffered storage selection signal and performs a logical product operation to generate a counter selection signal The first bit (CNT_SEL <1>) can be generated. The AND gate AND72 receives the first bit (S_SEL <1>) of the storage selection signal and the second bit (S_SEL <2>) of the inverted buffered storage selection signal and performs a logical product operation to generate a second bit CNT_SEL < 2 >). The AND gate AND73 receives the first bit (S_SEL <1>) of the inverted buffered storage selection signal and the second bit (S_SEL <2>) of the storage selection signal and performs a logical product operation to generate a third bit CNT_SEL < 3 >).

Referring to FIG. 21, a bit to be enabled can be confirmed according to a logic level combination of the storage selection signal S_SEL <1: 2> among the bits included in the counter selection signal CNT_SEL <1: 3>. When the storage select signal S_SEL <1: 2> is '00', the first bit CNT_SEL <1> of the counter selection signal is enabled to a logic high level. When the storage select signal S_SEL <1: 2> is '01', the second bit CNT_SEL <2> of the counter selection signal is enabled to a logic high level. The third bit (CNT_SEL <3>) of the counter selection signal is enabled to a logic high level when the storage select signals S_SEL <1: 2> are '10'.

Referring to FIG. 22, the counter reset signal generation circuit 73 may include AND gates AND75, AND76, and AND77. The AND gate AND75 receives the first bit CNT_SEL <1> and the maximum sense signal MAX_DET of the counter selection signal and performs an AND operation to generate the first bit CNT_RST <1> of the counter reset signal have. The AND gate AND76 receives the second bit (CNT_SEL <2>) and the maximum sense signal (MAX_DET) of the counter selection signal and performs an AND operation to generate a second bit (CNT_RST <2>) of the counter reset signal have. The AND gate AND77 receives the third bit (CNT_SEL <3>) and the maximum sense signal (MAX_DET) of the counter selection signal and performs an AND operation to generate the third bit (CNT_RST <3>) of the counter reset signal have. The first bit of the counter reset signal CNT_RST <1> is enabled to a logic high level when both the first bit of the counter selection signal CNT_SEL <1> and the maximum sense signal MAX_DET are both enabled to a logic high level. The second bit CNT_RST <2> of the counter reset signal is enabled to a logic high level when the second bit of the counter selection signal CNT_SEL <2> and the maximum sense signal MAX_DET are both enabled to a logic high level. The third bit of the counter reset signal CNT_RST <3> is enabled to a logic high level when the third bit of the counter selection signal CNT_SEL <3> and the maximum sense signal MAX_DET are both enabled to a logic high level.

23, the counter code generation circuit 8 may include a first counter code generation circuit 81, a second counter code generation circuit 82 and a third counter code generation circuit 83. [

The first counter code generating circuit 81 generates a first counter code SC1 and a counter reset signal SR2 based on the comparison clock COM_CLK, the same sensing signal S_DET, the first bit CNT_SEL <1> of the counter selection signal, the refresh activation signal SREN, (CNT_CD1 < 1: 2 >) in response to the minimum sense signal (CNT_RST <1>) and the minimum sense signal (MIN_DET). The first counter code generation circuit 81 may count the first counter code CNT_CD1 <1: 2> by a preset number of times in synchronization with the comparison clock COM_CLK in the arbitrary storage mode. The first counter code generation circuit 81 may count the first counter code CNT_CD1 <1: 2> when the same sense signal S_DET is enabled. The first counter code generating circuit 81 can generate the refresh end signal SR_END in synchronization with the end of the refresh performed by the refresh activation signal SREN. The first counter code generation circuit 81 generates the first counter code CNT_CD1 <1: 2> when the first bit CNT_RST <1> of the counter reset signal is enabled in the state where the refresh end signal SR_END is generated, Can be initialized to a predetermined logic level combination. The first counter code generation circuit 81 generates the first counter code CNT_CD1 <1: 2> when the minimum sense signal MIN_DET and the first bit CNT_SEL <1> of the counter selection signal are all enabled to a logic high level, ) Can be initialized to a predetermined logic level combination.

The second counter code generation circuit 82 generates the second counter code CLK by comparing the second comparison signal COM_CLK, the same sensing signal S_DET, the second bit CNT_SEL <2> of the counter selection signal, the refresh activation signal SREN, (CNT_CD2 < 1: 2 >) in response to the refresh start signal CNT_RST <2>, the refresh end signal SR_END and the minimum sense signal MIN_DET. The second counter code generation circuit 82 may count the second counter code CNT_CD2 <1: 2> by a preset number of times in synchronization with the comparison clock COM_CLK in the arbitrary storage mode. The second counter code generation circuit 82 may count the second counter code CNT_CD2 <1: 2> when the same sense signal S_DET is enabled. The second counter code generation circuit 82 generates the second counter code CNT_CD2 <1: 2> when the second bit CNT_RST <2> of the counter reset signal is enabled in the state where the refresh end signal SR_END is generated, Can be initialized to a predetermined logic level combination. The second counter code generation circuit 82 generates a second counter code CNT_CD2 <1: 2> when the minimum sense signal MIN_DET and the second bit CNT_SEL <2> of the counter selection signal are both enabled to a logic high level, ) Can be initialized to a predetermined logic level combination.

The third counter code generation circuit 83 generates the third counter code SCL3 for the comparison clock COM_CLK, the same sense signal S_DET, the third bit CNT_SEL <3> of the counter selection signal, the refresh activation signal SREN, (CNT_CD3 < 1: 2 >) in response to the refresh operation signal CNT_RST <3>, the refresh end signal SR_END and the arbitrary mode operation clock R_CLK. The third counter code generation circuit 83 can count the third counter code CNT_CD3 <1: 2> by a predetermined number of times in synchronization with the comparison clock COM_CLK in the arbitrary storage mode. The third counter code generation circuit 83 may count the third counter code CNT_CD3 <1: 2> when the same sense signal S_DET is enabled. The third counter code generation circuit 83 generates a third counter code CNT_CD3 <1: 2> when the third bit CNT_RST <3> of the counter reset signal is enabled in the state where the refresh end signal SR_END is generated, Can be initialized to a predetermined logic level combination. The counter code generation circuit 82 can initialize the third counter code CNT_CD3 <1: 2> to a predetermined logic level combination in synchronization with the timing at which the arbitrary mode operation clock R_CLK is generated.

24, the first counter code generation circuit 81 includes a first counter clock generation circuit 811, a first storage reset signal generation circuit 812, a first counter latch 813, and a second counter latch 814 ).

The first counter clock generation circuit 811 can generate the first counter clock C_CLK1 in response to the comparison clock signal COM_CLK, the same sense signal S_DET, and the first bit CNT_SEL <1> of the counter selection signal . The first counter clock generation circuit 811 generates a first counter clock signal CLK when the first comparison clock signal COM_CLK or the same sensing signal S_DET is generated in a state where the first bit CNT_SEL < It is possible to generate the counter clock C_CLK1.

The first storage reset signal generation circuit 812 may include a refresh end signal generation circuit 816 and a first storage reset signal output circuit 817. The refresh end signal generation circuit 816 can generate the refresh end signal SR_END in response to the refresh activation signal SREN. The refresh end signal generating circuit 816 can generate the refresh end signal SR_END in synchronization with the timing at which the refresh is ended and the refresh activation signal SREN transits from the logic high level to the logic low level. The first storage reset signal output circuit 817 outputs the first bit CNT_SEL <1> of the counter reset signal, the first bit CNT_RST <1> of the counter reset signal, the refresh end signal SR_END, the minimum sense signal MIN_DET, To generate a first store reset signal (C_RST1). The first storage reset signal output circuit 817 can generate the first store reset signal C_RST1 when the first bit CNT_RST <1> of the counter reset signal is enabled. The first storage reset signal output circuit 817 can generate the first storage reset signal C_RST1 when the refresh end signal SR_END is generated. The first storage reset signal output circuit 817 generates the first storage reset signal C_RST1 when the same sense signal S_DET and the first bit CNT_SEL <1> of the counter selection signal are all enabled to a logic high level .

The first counter latch 813 latches the output signal of the first inverting output terminal QB1 input through the first input terminal D1 in synchronization with the first counter clock C_CLK and outputs the latched output signal to the first output terminal Q1 . The first counter latch 813 may output the first bit CNT_CD1 <1> of the first counter code through the first inverting output QB1. The first counter latch 813 initializes the output signals of the first output terminal Q1 and the first inverted output terminal QB1 when the first store reset signal C_RST1 is generated.

The second counter latch 814 latches the output signal of the second inverting output terminal QB2 input through the second input terminal D2 in synchronization with the output signal of the first output terminal Q1 of the first counter latch 813, And outputs it to the second output terminal Q2. The second counter latch 814 may output the second bit (CNT_CD1 < 2 >) of the first counter code through the second inverting output QB2. The second counter latch 814 initializes the output signals of the second output terminal Q2 and the second inverted output terminal QB2 when the first store reset signal C_RST1 is generated.

 25, the second counter code generation circuit 82 includes a second counter clock generation circuit 821, a second storage reset signal generation circuit 822, a third counter latch 823, and a fourth counter latch 824 ).

The second counter clock generation circuit 821 can generate the second counter clock C_CLK2 in response to the comparison clock COM_CLK, the same sense signal S_DET, and the second bit CNT_SEL <2> of the counter selection signal . The second counter clock generation circuit 821 generates the second counter clock signal CLK when the comparison clock signal COM_CLK or the same sensing signal S_DET is generated in a state where the second bit CNT_SEL <2> The counter clock C_CLK2 can be generated.

The second storage reset signal generation circuit 822 generates a second storage reset signal by using the second bit CNT_SEL <2> of the counter reset signal, the refresh end signal SR_END, the minimum sense signal MIN_DET, The second storage reset signal C_RST2 may be generated. The second storage reset signal generation circuit 822 may generate the second storage reset signal C_RST2 when the second bit CNT_RST <2> of the counter reset signal is enabled. The second storage reset signal generation circuit 822 can generate the second storage reset signal C_RST2 when the refresh end signal SR_END is generated. The second storage reset signal generation circuit 822 generates a second storage reset signal C_RST2 when the same sense signal S_DET and the second bit CNT_SEL <2> of the counter selection signal are all enabled to a logic high level .

The third counter latch 823 latches the output signal of the first inverting output terminal QB1 input through the first input terminal D1 in synchronization with the second counter clock C_CLK2 and outputs the latched output signal to the first output terminal Q1 . The third counter latch 823 may output the first bit CNT_CD2 <1> of the second counter code through the first inverting output QB1. The third counter latch 823 initializes the output signals of the first output terminal Q1 and the first inverted output terminal QB1 when the second store reset signal C_RST2 is generated.

The fourth counter latch 824 latches the output signal of the second inverting output terminal QB2 input through the second input terminal D2 in synchronization with the output signal of the first output terminal Q1 of the third counter latch 823, And outputs it to the second output terminal Q2. The fourth counter latch 824 can output the second bit (CNT_CD2 < 2 >) of the second counter code through the second inverting output QB2. The fourth counter latch 824 initializes the output signals of the second output terminal Q2 and the second inverted output terminal QB2 when the second store reset signal C_RST2 is generated.

26, the third counter code generation circuit 83 includes a third counter clock generation circuit 831, a third storage reset signal generation circuit 832, a fifth counter latch 833 and a sixth counter latch 834 ).

The third counter clock generation circuit 831 can generate the third counter clock C_CLK3 in response to the comparison clock signal COM_CLK, the same sense signal S_DET, and the third bit CNT_SEL <3> of the counter selection signal . The third counter clock generation circuit 831 generates the third counter clock signal CLK when the third clock signal CNT_SEL <3> of the counter selection signal is enabled to a logic high level and the comparison clock signal COM_CLK or the same detection signal S_DET is generated. The counter clock C_CLK3 can be generated.

The third storage reset signal generation circuit 832 may generate the third storage reset signal C_RST3 in response to the third bit CNT_RST <3> of the counter reset signal and the refresh end signal SR_END. The third storage reset signal generation circuit 832 may generate the third storage reset signal C_RST3 when the third bit CNT_RST <3> of the counter reset signal is enabled. The third storage reset signal generation circuit 832 may generate the third storage reset signal C_RST3 when the refresh end signal SR_END is generated.

The fifth counter latch 833 latches the output signal of the first inverting output terminal QB1 input through the first input terminal D1 in synchronization with the third counter clock C_CLK3 and outputs the latched output signal to the first output terminal Q1 . The fifth counter latch 833 can output the first bit CNT_CD3 <1> of the third counter code through the first inverting output terminal QB1. The fifth counter latch 833 initializes the output signals of the first output terminal Q1 and the first inverted output terminal QB1 when the third store reset signal C_RST3 or the arbitrary mode operation clock R_CLK is generated.

The sixth counter latch 834 latches the output signal of the second inverting output terminal QB2 input through the second input terminal D2 in synchronization with the output signal of the first output terminal Q1 of the fifth counter latch 833, And outputs it to the second output terminal Q2. The sixth counter latch 834 may output the second bit (CNT_CD3 <2>) of the third counter code through the second inverting output QB2. The sixth counter latch 834 initializes the output signals of the second output terminal Q2 and the second inverted output terminal QB2 when the third store reset signal C_RST3 or the arbitrary mode operation clock R_CLK is generated.

The operation of the semiconductor device constructed as described above will be described with reference to FIG.

At time T31, the A address and the B address are stored, the code value corresponding to the A address is set to 2, and the code value corresponding to the B address is set to 1. When the A address is input in the cumulative storage mode at the time T32, the code value corresponding to the A address is counted up by one bit at the time T33. The code value corresponding to the A address is set to 3. When the D address is input at the time of T34 and the D address is input, D is stored instead of B where the minimum counting code check operation result code value is set to the minimum at T35. The code value corresponding to the newly stored D is set to one. On the other hand, if the E address is inputted in the arbitrary storage mode at the time T36, the E address is stored instead of the C address stored in the storage circuit used only in the arbitrary storage mode at the time T37. The code value corresponding to newly stored E in the random storage method is set to 4. [ When the refresh activation signal SREN is enabled at time T38, the refresh operation is performed on the E address corresponding to the code value counted most as a result of the maximum counting code check operation at time T39.

As described above, the semiconductor device according to the present embodiment can monitor the addresses requiring refresh by storing the addresses where the active operation is performed and the code values corresponding to the addresses. In addition, the semiconductor device according to the present embodiment also has an effect of reducing power consumption by preventing an unnecessary refresh from being performed by selecting an address to be refreshed according to a code value among addresses to which an active operation is performed. In addition, the semiconductor device according to the present embodiment can perform a refresh in various ways by providing an arbitrary storage method in which code values are counted as many times as the weight is given.

1 to 27 can be applied to an electronic system including a memory system, a graphics system, a computing system, and a mobile system. 28, an electronic system 1000 according to an embodiment of the present invention includes a data storage unit 1001, a memory controller 1002, a buffer memory 1003, and an input / output interface 1004 .

The data storage unit 1001 stores data applied from the memory controller 1002 in accordance with a control signal from the memory controller 1002, reads the stored data, and outputs the read data to the memory controller 1002. The data storage unit 1001 may include the semiconductor device shown in FIG. Meanwhile, the data storage unit 1001 may include a nonvolatile memory that can store data without losing data even when the power is turned off. The non-volatile memory may be a non-volatile memory such as a NOR flash memory, a PRAM, a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Memory Access Memory (STTRAM), and Magnetic Random Access Memory (MRAM).

The memory controller 1002 decodes a command applied from an external device (host device) through the input / output interface 1004 and controls data input / output to the data storage unit 1001 and the buffer memory 1003 according to the decoded result . Although the memory controller 1002 is shown as one block in FIG. 28, the memory controller 1002 can be configured so that the controller for controlling the data storage unit 1001 and the controller for controlling the buffer memory 1003, which is a volatile memory, Lt; / RTI &gt;

The buffer memory 1003 may temporarily store data to be processed in the memory controller 1002, that is, data to be input to and output from the data storage unit 1001. [ The buffer memory 1003 can store data (DATA) applied from the memory controller 1002 according to a control signal. The buffer memory 1003 reads the stored data and outputs it to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a dynamic random access memory (DRAM), a mobile DRAM, and a static random access memory (SRAM).

The input / output interface 1004 provides a physical connection between the memory controller 1002 and an external device (host) so that the memory controller 1002 can receive control signals for data input / output from external devices and exchange data with external devices It will help. The input / output interface 1004 may include one of various interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI,

The electronic system 1000 can be used as an auxiliary storage device or an external storage device of the host apparatus. The electronic system 1000 may include a hard disk such as a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a secure digital (SD) card, a mini Secure Digital card (mSD) A micro SD card, a Secure Digital High Capacity (SDHC) card, a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC) , An embedded multimedia card (eMMC), a compact flash (CF) card, and the like.

1: random storage mode signal generation circuit 2: operation clock generation circuit
3: refresh address generation circuit 4: selection signal control circuit
5: code comparison control circuit 6: sense signal generation circuit
7: counter reset control circuit 8: counter code generation circuit
41: storage selection signal generation circuit 42: maximum storage selection signal generation circuit
51: comparison code generation circuit 52: code comparison signal generation circuit
71: comparison clock generation circuit 72: counter selection signal generation circuit
73: Counter reset signal generation circuit 11: First mode latch
12: second mode latch 13: third mode latch
21: first operation clock generation circuit 22: second operation clock generation circuit
23: Termination signal buffer circuit 24: Third operation clock generation circuit
211: start signal generating circuit 212: end signal generating circuit
213: Clock output circuit 31: Input control signal generation circuit
32: output control signal generating circuit 33: first latch address generating circuit
34: second latch address generating circuit 35: third latch address generating circuit
36: Refresh address output circuit
331: first address comparison circuit 332: first address comparison signal latch
333: first address storage circuit
341: second address comparison circuit 342: second address comparison signal latch
343: Second address storage circuit
351: Third address comparison circuit 352: Third address comparison signal latch
353: third address storage circuit 411: first storage latch
412: Second storage latch 421: First maximum storage latch
422: second maximum storage latch 511: first comparison latch
512: second comparison latch 513: code setting signal generation circuit
514: first code synthesizer 515: second code synthesizer
521: first code comparison signal generation circuit 522: second code comparison signal generation circuit
523: third code comparison signal generation circuit 61: address comparison signal selection circuit
62: Code comparison signal selection circuit 63:
711: comparison input circuit 712: comparison clock output circuit
81: First counter code generation circuit 82: Second counter code generation circuit
83: Third counter code generation circuit 811: First counter clock generation circuit
812: first storage reset signal generation circuit 813: first counter latch signal
814: second counter latch 816: refresh end signal generation circuit
817: first storage reset signal output circuit 821: second counter clock generation circuit
822: Second storage reset signal generation circuit 823: Third counter latch latch
824: fourth counter latch 831: third counter clock generation circuit
832: third storage reset signal generation circuit 833: fifth counter latch
834: sixth counter latch

Claims (30)

An operation clock generation circuit for generating a first operation clock to perform the cumulative storage mode and generating an arbitrary mode operation clock for performing the arbitrary storage mode; And
And a third address storage circuit including a first address storage circuit and a second address storage circuit in which the input address is stored in the accumulation storage mode and in which the input address is stored in the arbitrary storage mode However,
The counter code corresponding to the address stored in the third address storage circuit is set to be counted by a bit number larger than the counter code corresponding to the address stored in the first address storage circuit or the second address storage circuit, .
The semiconductor device according to claim 1, wherein the arbitrary storage mode enters when a precharge command is generated a predetermined number of times.
2. The semiconductor memory device according to claim 1, wherein the operation clock generation circuit
And a first operation clock generation circuit for generating said first operation clock in response to said start signal and for stopping generation of said first operation clock in response to an end signal.
4. The semiconductor device of claim 3, wherein the start signal is enabled when an active command occurs in the cumulative storage mode.
4. The memory device according to claim 3, wherein the end signal includes a counter corresponding to an address in which the random storage mode is performed or an address identical to the address stored in the first address storage circuit or the second address storage circuit is input or an active operation is performed, Is enabled when a minimum counting code search operation to find the least counted code among the codes is completed or when a reset signal is enabled.
4. The semiconductor memory device according to claim 3, wherein the operation clock generation circuit
A second operation clock generation circuit for generating a second operation clock for performing a maximum counting code search operation for finding a most counted code among counter codes corresponding to addresses for which an active operation is performed in response to the termination signal &Lt; / RTI &gt;
7. The semiconductor memory device according to claim 6, wherein the operation clock generation circuit
And a second operation clock generation circuit for generating a third operation clock for the maximum counting code search operation or the minimum counting code search operation when the first operation clock or the second operation clock is generated.
The semiconductor integrated circuit according to claim 1, wherein the refresh address generating circuit
And a first latch address generating circuit for generating a first latch code and a first latch address in response to the input address, the active command, the first input control signal, and the first output control signal.
9. The semiconductor memory device according to claim 8, wherein the first latch address generating circuit
An address comparison circuit for comparing the input address and the first latch address to generate an address comparison signal;
An address comparison signal latch for outputting the address comparison signal to the first latch code in response to the active command; And
And the first address storage circuit storing the input address in response to the first input control signal and outputting the stored input address as the first latch address in response to the first output control signal.
9. The semiconductor integrated circuit according to claim 8, wherein the refresh address generating circuit
A second latch address generating circuit for generating a second latch code and a second latch address in response to the input address, the active command, the second input control signal, and the second output control signal; And
And a third latch address generating circuit for generating a third latch code and a third latch address in response to the input address, the active command, the arbitrary mode operation clock, and the third output control signal.
11. The semiconductor memory device according to claim 10, wherein the third latch address generating circuit
An address comparison circuit for comparing the input address and the third latch address to generate an address comparison signal;
An address comparison signal latch for outputting the address comparison signal to the third latch code in response to the active command; And
And the third address storage circuit storing the input address in response to the arbitrary mode operation clock and outputting the stored input address as the third latch address in response to the third output control signal.
11. The semiconductor memory device according to claim 10, wherein the refresh address generating circuit
And a refresh address output circuit responsive to the refresh enable signal for outputting one of the first latch address, the second latch address, and the third latch address to a refresh address to be refreshed.
The method according to claim 1,
Generates a first counter code corresponding to the address stored in the first address storage circuit, generates a second counter code corresponding to the address stored in the second address storage circuit, And a counter code generation circuit for generating a counter code corresponding to the third counter code.
14. The apparatus of claim 13, wherein the counter code generation circuit
A first counter code generation circuit for generating the first counter code counted by a first number of bits when an address identical to an address stored in the first address storage circuit is input;
A second counter code generation circuit for generating the second counter code counted by the first number of bits when an address identical to the address stored in the second address storage circuit is input; And
And a third counter code generation circuit for counting the third counter code corresponding to an address stored in the third address storage circuit in the arbitrary storage mode by a second number of bits, The number of bits being set larger than the number of bits.
15. The apparatus of claim 14, wherein the first counter code generation circuit
A counter clock generating circuit responsive to the counter selection signal for generating a counter clock in response to the comparison clock and the same sensing signal;
A storage reset signal generation circuit for generating a storage reset signal from the counter reset signal in synchronization with the end of the refresh and generating the storage reset signal in response to the counter selection signal and the minimum sensing signal; And
And a counter latch for generating the first counter code counted in response to the counter clock and the store reset signal.
15. The apparatus of claim 14, wherein the third counter code generation circuit
A counter clock generating circuit responsive to the counter selection signal for generating a counter clock in response to the comparison clock and the same sensing signal;
A store reset signal generating circuit for generating a store reset signal from the counter reset signal in synchronization with the end of the refresh; And
And a counter latch for generating the third counter code counted in response to the counter clock and the store reset signal.
The method according to claim 1,
Further comprising: a sense signal generation circuit that generates the same sense signal, the minimum sense signal, and the maximum sense signal in response to the storage selection signal, the maximum storage selection signal, the code setting signal, the latch code, and the code comparison signal.
18. The semiconductor device of claim 17, wherein the storage select signal has a logic level combination that varies by the first operating clock.
18. The semiconductor device of claim 17, wherein the maximum storage select signal has a logic level combination that varies by a second operating clock generated to perform a maximum counting code search operation.
18. The semiconductor device of claim 17, wherein the code setting signal has a first logic level when a minimum counting code search operation is performed and a second logic level when a maximum counting code search operation is performed.
18. The method of claim 17, wherein the same sense signal is enabled if the input address is the same as the address stored in the first address store circuit or the second address store circuit, And wherein the maximum sense signal is enabled when the maximum counting code search operation is completed.
A refresh address generating circuit including a first address storage circuit and a second address storage circuit in which an input address is stored in a cumulative storage mode, and a third address storage circuit in which the input address is stored in an arbitrary storage mode; And
Generates a first counter code corresponding to the address stored in the first address storage circuit, generates a second counter code corresponding to the address stored in the second address storage circuit, And a counter code generation circuit for generating a counter code corresponding to the third counter code.
23. The semiconductor device according to claim 22, wherein the arbitrary storage mode is entered when a precharge command is generated a predetermined number of times.
23. The semiconductor memory device according to claim 22, wherein the refresh address generating circuit
And a first latch address generating circuit for generating a first latch code and a first latch address in response to the input address, the active command, the first input control signal, and the first output control signal.
25. The semiconductor memory device according to claim 24, wherein the refresh address generating circuit
A second latch address generating circuit for generating a second latch code and a second latch address in response to the input address, the active command, the second input control signal, and the second output control signal; And
And a third latch address generating circuit for generating a third latch code and a third latch address in response to the input address, the active command, the arbitrary mode operation clock, and the third output control signal.
23. The apparatus of claim 22, wherein the counter code generation circuit
A first counter code generation circuit for generating the first counter code counted by a first number of bits when an address identical to an address stored in the first address storage circuit is input;
A second counter code generation circuit for generating the second counter code counted by the first number of bits when an address identical to the address stored in the second address storage circuit is input; And
And counting the third counter code corresponding to an address stored in the third address storage circuit in the arbitrary storing mode by a second number of bits, wherein the second number of bits is set to be larger than the first number of bits.
27. The apparatus of claim 26, wherein the first counter code generation circuit
A counter clock generating circuit responsive to the counter selection signal for generating a counter clock in response to the comparison clock and the same sensing signal;
A storage reset signal generation circuit for generating a storage reset signal from the counter reset signal in synchronization with the end of the refresh and generating the storage reset signal in response to the counter selection signal and the minimum sensing signal; And
And a counter latch for generating the first counter code counted in response to the counter clock and the store reset signal.
23. The method of claim 22,
Further comprising: a sense signal generation circuit that generates the same sense signal, the minimum sense signal, and the maximum sense signal in response to the storage selection signal, the maximum storage selection signal, the code setting signal, the latch code, and the code comparison signal.
29. The method of claim 28, wherein the store select signal has a logic level combination variable by a first operating clock generated to perform an accumulative storage mode, and wherein the maximum store select signal is generated Wherein the code setting signal has a first logic level when a minimum counting code search operation is performed and a second logic level when a maximum counting code search operation is performed, .
29. The method of claim 28, wherein the same sense signal is enabled if the input address is the same as the address stored in the first address store circuit or the second address store circuit, And wherein the maximum sense signal is enabled when the maximum counting code search operation is completed.

Images