KR20180123393A - Siso decoding method, decoder and semiconductor memory system using the same - Google Patents

Abstract

Provided is a decoding method about a channel output of a component code. The decoding method includes: a step of mapping each bit of a channel output as a preset first value; a step of generating candidate code words corresponding to the channel output through an error bit correction based on the mapped first value; a step of detecting a candidate code word which has a minimum distance from the channel output as a first code word among the candidate code words based on a distance from the channel output represented as a sum of confidence values corresponding to bits of the error bit-corrected candidate code words; a step of detecting a candidate code word which has the minimum distance from the channel output as a second code word in which an i^th bit value is the inverse value of the i^th bit value of the first code word among the candidate code words based on a distance from the channel output represented as a sum of confidence values corresponding to bits of the error bit-corrected candidate code words; and a step of determining soft decision data based on the existence of the second code word. The present invention is able to decode soft in soft out (SISO) even in a general environment of a flash memory.

Description

[0001] The present invention relates to a SISO decoding method, a decoder, and a semiconductor memory system (SISO DECODING METHOD, DECODER AND SEMICONDUCTOR MEMORY SYSTEM USING THE SAME)

The present invention relates to a semiconductor memory system and a method of operating the same.

The semiconductor memory device includes a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like, a read only memory (ROM), a magnetic random access memory (MROM), a programmable ROM (PROM), an erasable ROM (EPROM) Volatile memory devices such as electrically erasable ROM, FRAM, PRAM, MRAM, RRAM, and flash memory.

Volatile memory devices lose stored data when power is turned off, but nonvolatile memories can preserve stored data even when the power is turned off. In particular, flash memory has been widely used as a storage medium in computer systems and the like because it has advantages of high programming speed, low power consumption, and large data storage.

Non-volatile memories, for example flash memories, can determine data states storable in each memory cell according to the number of bits stored in each memory cell. A memory cell storing one bit of data in one memory cell is a single-bit cell or a single-level cell (SLC). A memory cell that stores 2-bit data in one memory cell is a multi-bit cell, a multi-level cell (MLC), or a multi-state cell. A memory cell that stores 3-bit data in one memory cell is a triple-level cell (TLC). MLC and TLC have advantages advantageous for high integration of memory. However, as the number of bits programmed into one memory cell increases, the reliability decreases and the read failure rate increases.

For example, to program k bits in one memory cell, one of 2 ^k threshold voltages is formed in the memory cell. Due to the difference in electrical characteristics between the memory cells, the threshold voltages of the memory cells in which the same data are programmed form a certain range of threshold voltage distributions. Each threshold voltage distribution corresponds to each of the 2 ^k data values that can be generated by k bits.

However, since the voltage window over which the threshold voltage distributions can be placed is limited, as k increases, the distance between adjacent threshold voltage distributions decreases and adjacent threshold voltage distributions can overlap each other. As adjacent threshold voltage distributions are superimposed, the read data may contain many error bits (e.g., several error bits or dozens of error bits).

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a threshold voltage dispersion graph showing the programmed and erased states of a 3 bit triple level cell (TLC) nonvolatile memory device.

2 is a threshold voltage scatter graph showing program states and erase states that may be modified due to characteristic degradation of a 3-bit triple level cell non-volatile memory device.

Programming three bits (i. E., K = 3) in a single memory cell of a TLC nonvolatile memory device, for example TLC flash memory, one of 2 ³ , i.e., 8 threshold voltage distributions, .

Due to the difference in electrical characteristics between the plurality of memory cells, each of the threshold voltages of each of the memory cells with the same data programmed forms a certain range of threshold voltage distributions. In the case of a 3-bit TLC, a threshold voltage distribution (E) of a threshold voltage distribution of seven program states (P1 to P7) and one erase state is formed as shown in the figure. FIG. 1 is an ideal scatter diagram, in which no state scatter is overlapped, and a lead voltage margin is within a certain range for each scatter of each threshold voltage.

As shown in FIG. 2, in the case of a flash memory, over time, a charge loss occurs in which electrons trapped in a floating gate or a tunnel oxide are emitted. . Further, the tunnel oxide is deteriorated while the program and erase are repeated, and the charge loss can be further increased. The charge loss can reduce the threshold voltage. For example, the dispersion of the threshold voltage can be shifted to the left.

Also, program disturbances, erasure disturbances, and / or back pattern dependency phenomena can increase the dispersion of the threshold voltage with each other. Therefore, due to the characteristic deterioration of the memory cell due to the above-described reason, the threshold voltage distributions of adjacent states E and P1 to P7 as shown in FIG. 1B can overlap each other.

If the threshold voltage spreads overlap, the data being read may contain many errors. For example, when the third read voltage Vread3 is applied, if the memory cell is on, it is determined that the memory cell is in the second program state P2 and the memory cell is off ), It is determined that the memory cell concerned has the third program state (P3). On the other hand, if the third read voltage Vread3 is applied in a period in which the second program state P2 and the third program state P3 overlap, the memory cell is turned on, State. Thus, as the threshold voltage spreads overlap, many bits of error may be included in the read data.

Therefore, there is a need for a technique capable of accurately reading data stored in a memory cell of a semiconductor memory device.

It is an object of the present invention to provide a decoding method, a decoder, and a semiconductor memory system capable of SISO (Soft In Soft Out) decoding even in a general environment of a flash memory.

번째 비트 값이 상기 제 1 코드워드의 제

번째 비트 값의 반전 값이며, 상기 채널 출력과의 거리가 최소인 후보 코드워드를 제 2 코드워드로 검출하는 단계; 및 상기 제 2 코드워드의 존재 여부에 기초하여 연 판정 데이터를 결정하는 단계를 포함하는 복호 방법을 제공할 수 있다.According to an embodiment of the present invention, there is provided a decoding method for a channel output of a configuration code, the method comprising: mapping each bit of the channel output to a predetermined first value; Generating candidate codewords corresponding to the channel output through error bit correction based on the mapped first value; A candidate code word having a minimum distance from the channel output from the candidate code words based on the distance from the channel output represented by the sum of the reliability values corresponding to the bits of the error- 1 code word; And a channel output, which is expressed as a sum of the reliability values corresponding to the bits of the error-bit corrected candidate codewords, from among the candidate codewords

Th bit of the first code word

Detecting a candidate codeword having a minimum distance from the channel output as a second codeword; And determining the soft decision data based on the presence or absence of the second code word.

 Preferably, the first codeword can be detected by the following equation (1).

(1)

는 임의의 코드워드,

은 채널 출력,

는 채널 출력

을 구성하는 각 비트

가 사전 설정된 값으로 매핑된 제 1값,

는 채널 출력이 임의의 코드워드가 되는 과정에서 정정된 비트 인덱스 들의 집합을 의미할 수 있다.In the above equation (1)

Is an arbitrary code word,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

May refer to a set of corrected bit indices in the course of the channel output being an arbitrary codeword.

Preferably, the second code word can be detected by the following equation (2).

(2)

는 상기 제 1 코드워드

의 제

비트 값의 반전된 값을 갖는 임의의 코드워드,

은 채널 출력,

는 채널 출력

을 구성하는 각 비트

가 사전 설정된 값으로 매핑된 제 1 값,

는 채널 출력

이 임의의 코드워드

로 되는 과정에서 정정된 비트 인덱스 들의 집합을 의미할 수 있다.In Equation (2)

Lt; RTI ID = 0.0 >

Of

Any code word having an inverted value of the bit value,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

This arbitrary code word

Lt; RTI ID = 0.0 > a < / RTI > set of corrected bit indices.

Advantageously, the step of determining soft decision data further comprises: if the second code word is present, adjusting the size of the soft decision data from the distance between the second codeword and the channel output to the first codeword And a code of the soft decision data may be determined based on the first code word.

Advantageously, the soft decision data can be provided by the following equation (3).

(3)

는 연 판정 출력데이터

의 제

번째 비트 값,

는 상기 제 2 코드워드

와 채널 출력

간의 거리,

는 상기 제 1 코드워드

와 채널 출력

간의 거리,

은 상기 제 1 코드워드

의 제

번째 비트 값,

는 채널 출력

을 구성하는 각 비트

가 사전 설정된 값으로 매핑된 제 1 값,

는 채널 출력

이 상기 제 2 코드워드

되는 과정에서 정정된 비트 인덱스 들의 집합,

는 채널 출력

이 상기 제 1 코드워드

되는 과정에서 정정된 비트 인덱스 들의 집합을 의미할 수 있다.In Equation (3)

The soft decision output data

Of

Th bit value,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

Of

Th bit value,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

The second codeword

A set of corrected bit indices in the process,

Channel output

Lt; RTI ID = 0.0 >

Lt; RTI ID = 0.0 > a < / RTI > set of corrected bit indices.

Preferably, the step of determining the soft decision data may include the steps of: determining the size of the soft decision data as a second predetermined value when the second code word does not exist; Can be determined based on the first code word.

Advantageously, the predetermined first value may be a log likelihood ratio (LLR) value or a constant multiple of the LLR value.

Advantageously, the step of generating the candidate codewords may generate the candidate codewords through chase decoding.

번째 비트 값이 상기 제 1 코드워드의 제

번째 비트 값의 의 반전 값이며, 상기 채널 출력과의 거리가 최소인 후보 코드워드를 제 2 코드워드로 검출하는 제 2 검출부; 및 상기 제 2 코드워드의 존재 여부에 기초하여 연 판정 데이터를 결정하는 결정부를 포함하는 디코더를 제공할 수 있다.According to an embodiment of the present invention, a mapping unit maps each bit of the channel output to a predetermined first value. A generator for generating candidate codewords corresponding to the channel output based on the mapped first value through error bit correction; A candidate code word having a minimum distance from the channel output from the candidate code words based on the distance from the channel output represented by the sum of the reliability values corresponding to the bits of the error- A first detecting unit for detecting the first code word; And a channel output, which is expressed as a sum of the reliability values corresponding to the bits of the error-bit corrected candidate codewords, from among the candidate codewords

Th bit of the first code word

Th bit value and a minimum distance from the channel output is a second code word; And a determination unit that determines soft decision data based on the presence or absence of the second code word.

Preferably, the first detecting unit may detect the first codeword by the following expression (1).

(4)

는 임의의 코드워드,

은 채널 출력,

는 채널 출력

을 구성하는 각 비트

가 사전 설정된 값으로 매핑된 제 1값,

는 채널 출력이 임의의 코드워드가 되는 과정에서 정정된 비트 인덱스 들의 집합을 의미할 수 있다.In Equation (4)

Is an arbitrary code word,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

May refer to a set of corrected bit indices in the course of the channel output being an arbitrary codeword.

Preferably, the second detecting unit can detect a second code word by the following expression (2).

(5)

는 상기 제 1 코드워드

의 제

비트 값의 반전된 값을 갖는 임의의 코드워드,

은 채널 출력,

는 채널 출력

을 구성하는 각 비트

가 사전 설정된 값으로 매핑된 제 1 값,

는 채널 출력

이 임의의 코드워드

로 되는 과정에서 정정된 비트 인덱스 들의 집합을 의미할 수 있다.In Equation (5)

Lt; RTI ID = 0.0 >

Of

Any code word having an inverted value of the bit value,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

This arbitrary code word

Lt; RTI ID = 0.0 > a < / RTI > set of corrected bit indices.

Preferably, the determination unit for determining the soft decision data may further include a soft decision unit for selecting the soft decision data from the distance between the second codeword and the channel output, if the second codeword is present, And a code of the soft decision data may be determined based on the first code word.

Preferably, the determination unit may determine the soft decision data by the following equation (6).

(6)

는 연 판정 출력데이터

의 제

번째 비트 값,

는 상기 제 2 코드워드

와 채널 출력

간의 거리,

는 상기 제 1 코드워드

와 채널 출력

간의 거리,

은 상기 제 1 코드워드

의 제

번째 비트 값,

는 채널 출력

을 구성하는 각 비트

가 사전 설정된 값으로 매핑된 제 1 값,

는 채널 출력

이 상기 제 2 코드워드

되는 과정에서 정정된 비트 인덱스 들의 집합,

는 채널 출력

이 상기 제 1 코드워드

되는 과정에서 정정된 비트 인덱스 들의 집합을 의미할 수 있다.In Equation (6)

The soft decision output data

Of

Th bit value,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

Of

Th bit value,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

The second codeword

A set of corrected bit indices in the process,

Channel output

Lt; RTI ID = 0.0 >

Lt; RTI ID = 0.0 > a < / RTI > set of corrected bit indices.

Preferably, the determination unit for determining the soft decision data determines the size of the soft decision data as a second predetermined value if the second code word does not exist, and outputs the sign of the soft decision data to the first It can be determined to follow the codeword.

Advantageously, the predetermined first value may be a log likelihood ratio (LLR) value or a constant multiple of the LLR value.

Advantageously, the generator is capable of generating the candidate codewords through chase decoding.

번째 비트 값이 상기 제 1 코드워드의 제

번째 비트 값의 반전 값이며, 상기 채널 출력과의 거리가 최소인 후보 코드워드를 제 2 코드워드로 검출하는 제 2 검출부; 및 상기 제 2 코드워드의 존재 여부에 기초하여 연 판정 데이터를 결정하는 결정부를 포함하는, 반도체 메모리 시스템을 제공할 수 있다.According to an embodiment of the present invention, there is provided a semiconductor memory system comprising: a semiconductor memory device; And a controller, the controller comprising: a mapping unit for mapping each bit of the channel output to a predetermined first value; A generator for generating candidate codewords corresponding to the channel output through error bit correction based on the mapped first value; A candidate code word having a minimum distance from the channel output from the candidate code words based on the distance from the channel output represented by the sum of the reliability values corresponding to the bits of the error- A first detecting unit for detecting the first code word; And a channel output, which is expressed as a sum of the reliability values corresponding to the bits of the error-bit corrected candidate codewords, from among the candidate codewords

Th bit of the first code word

A second detector for detecting a candidate code word having a minimum distance from the channel output as a second code word; And a determination unit that determines soft decision data based on whether or not the second code word is present.

Preferably, the determination unit for determining the soft decision data may further include a soft decision unit for determining, when the second code word exists, a size of the soft decision data from the distance between the second code word and the channel output, And a code of the soft decision data may be determined based on the first code word.

Preferably, the determination unit for determining the soft decision data may determine the magnitude of the soft decision data as a second predetermined value, when the second code word does not exist, 1 < / RTI > codeword.

Advantageously, the generator is capable of generating the candidate codewords through chase decoding.

According to an embodiment of the present invention, SISO decoding is also possible in a general environment of a flash memory.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a threshold voltage scatter graph showing the programmed and erased states of a 3 bit multi-level cell (MLC) non-volatile memory device, respectively.
2 is a threshold voltage scatter graph showing program states and erase states that may be modified due to characteristic degradation of a 3-bit multi-level cell nonvolatile memory device.
3 is a block diagram illustrating a semiconductor memory system in accordance with an embodiment of the present invention.
4A is a detailed block diagram showing the semiconductor memory system shown in FIG.
4B is a block diagram illustrating the memory block shown in FIG. 4A.
4C is a block diagram showing the ECC unit shown in FIG. 4A.
5 is a flowchart showing the operation of the memory controller shown in FIG. 4A.
FIG. 6A is a conceptual diagram showing a 2-bit soft decision read operation as the soft decision read operation shown in FIG. 5; FIG.
6B is a conceptual diagram showing a 3-bit soft decision read operation as the soft decision read operation shown in FIG.
7 is a block diagram illustrating a decoder in accordance with an embodiment of the present invention.
8 is a flowchart showing a decoding method of a decoder according to an embodiment of the present invention.
9 is a block diagram illustrating an electronic device including a semiconductor memory system in accordance with an embodiment of the present invention.
10 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
11 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
12 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
13 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
14 is a block diagram illustrating a data processing system including the electronic device shown in Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory only and are not restrictive of the invention, .

3 is a block diagram illustrating a semiconductor memory system 10 in accordance with one embodiment of the present invention.

FIG. 4A is a detailed block diagram showing the semiconductor memory system 10 shown in FIG. 3, and FIG. 4B is a block diagram showing the memory block 211 shown in FIG. 4A.

5 is a flowchart showing the operation of the memory controller 100 included in the semiconductor memory system 10. As shown in FIG.

3 to 5, the semiconductor memory system 10 may include a semiconductor memory device 200 and the memory controller 100.

The semiconductor memory device 200 may perform erase, write, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive the command CMD, the address ADDR, and the data DATA from the memory controller 100 through the input / output line. The semiconductor memory device 200 may also receive the power supply PWR from the memory controller 100 via the power supply line and receive the control signal CTRL from the memory controller 100 via the control line. The control signal CTRL may include a command latch enable CLE, an address latch enable ALE, a chip enable nCE, a write enable nWE, a read enable nRE, and the like.

The memory controller 100 can control operation of the semiconductor memory device 200 as a whole. The memory controller 100 may include an ECC unit 130 for correcting error bits. The ECC unit 130 may include an encoder 131 and a decoder 133.

The encoder 131 performs error correction encoding on the data to be programmed in the semiconductor memory device 200 to form data having a parity bit added thereto. The parity bit may be stored in semiconductor memory device 200.

The decoder 133 can perform error correction decoding on the data read from the semiconductor memory device 200. [ The decoder 133 can determine whether or not the error correction decoding has succeeded and output an instruction signal according to the determination result. The decoder 133 can correct the error bit of the data using the parity bit generated in the encoding process.

On the other hand, if the number of error bits exceeds a correctable error bit threshold value, the ECC unit 130 can not correct the error bit. In this case, an error correction fail signal may be generated.

The ECC unit 130 includes an LDPC (Low Density Parity Check) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo product code (TPC), a Reed-Solomon code, a convolution code, error correction may be performed using coded modulation such as code, trellis-coded modulation (TCM), or block coded modulation (BCM), but the present invention is not limited thereto. The ECC unit 130 may include all circuits, systems, or devices for error correction. The ECC unit 130 may include any circuit, system or device for error correction.

According to an embodiment of the present invention, the ECC unit 130 can perform error bit correction using hard decision data and soft decision data.

The memory controller 100 and the semiconductor memory device 200 can be integrated into one semiconductor device. Illustratively, the memory controller 100 and the semiconductor memory device 200 may be integrated into a single semiconductor device to form a solid state drive (SSD). The solid state drive may include a storage device configured to store data in a semiconductor memory. When the semiconductor memory system 10 is used as a solid state drive (SSD), the operation speed of a host connected to the semiconductor memory system 10 can be remarkably improved.

The memory controller 100 and the semiconductor memory device 200 may be integrated into one semiconductor device to form a memory card. For example, the memory controller 100 and the semiconductor memory device 200 may be integrated into a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM) (SD), miniSD, microSD, SDHC), universal flash memory (UFS), and the like can be constituted by a memory card (SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro)

As another example, semiconductor device 10 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, Such as a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, Device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a 3-dimensional television, a smart television, a digital audio recorder, Digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, and data centers. story One of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID Device, or one of various components that constitute a computing system, and so on.

4A, the memory controller 100 may include a storage unit 110, a CPU 120, an ECC unit 130, a host interface 140, a memory interface 150, and a system bus 160 have. The storage unit 110 may be used as an operation memory of the CPU 120.

The host interface 140 may be a USB (Universal Serial Bus), a Multi-Media Card (MMC), a Peripheral Component Interconnect-Express (PCI-E), a Serial Attached SCSI (SAS), a Serial Advanced Technology Attachment Parallel Advanced Technology Attachment, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and the like.

The ECC unit 130 can detect and correct an error included in the data read from the semiconductor memory device 200 as described above. The memory interface 150 may interface with the semiconductor memory device 200. 4A illustrates an embodiment in which the ECC unit 130 includes both the encoder 131 and the decoder 133. In practice, however, the encoder 131 and the decoder 133 are substantially Or may be implemented in a separate configuration. The CPU 120 can perform overall control operations.

According to an embodiment of the present invention, in a program operation, the ECC unit 130 may perform encoding on original data with respect to data to be programmed into the semiconductor memory device 200. [ In this case, in the read operation, the ECC unit 130 performs decoding on the encoded data, that is, the codeword, programmed in the semiconductor memory device 200. The ECC unit 130 can recover the original data before being encoded by decoding the encoded data stored in the semiconductor memory device 200, that is, the code word.

As described below with reference to FIG. 5, the read operation for the data stored in the semiconductor memory device 200 may include the hard decision read operation at step S511 and the soft decision read operation at step S531. The hard decision read operation is an operation of reading data from the semiconductor memory device 200 at the hard decision lead voltage V _HD . The soft decision lead operation is an operation of reading data from the semiconductor memory device 200 with soft decision lead voltages V _SD having a different level from the hard decision lead voltage V _HD . For example, in the binary memory cells read by the hard decision of said read voltage (V _HD), a further read operation the soft decision by using the above soft decision read voltage (V _SD) can be performed.

The soft decision read operation is not an operation of simply reading data stored in the semiconductor memory device 200 but a log likelihood ratio which is information capable of adding reliability to the data read by the hard decision read operation ; LLR) by the soft decision read voltages V _SD .

The LLR can be decoded by the ECC unit 130. The ECC unit 130 can detect and correct errors of the encoded data read from the semiconductor memory device 200, that is, code words using the LLR.

The semiconductor memory device 200 may include a cell array 210, a control circuit 220, a voltage supply 230, a voltage transfer portion 240, a read / write circuit 250, and a column select portion 260 have.

The cell array 210 may include a plurality of memory blocks 211. The memory block 211 may store user data.

Referring to FIG. 4B, the memory block 211 may include a plurality of cell strings 221 connected to bit lines BL0 to BLm-1, respectively. The cell string 221 of each column may include at least one drain select transistor (DST) and at least one source select transistor (SST). A plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each memory cell MC0 to MCn-1 may be constituted by an MLC storing a plurality of bits of data information per cell. Strings 221 may be electrically connected to corresponding bit lines BL0 to BLm-1, respectively.

FIG. 4B exemplarily shows a memory block 211 composed of NAND-type flash memory cells. However, the memory block 211 of the memory device of the present invention is not limited to the NAND flash memory but may be a NOR-type flash memory, a hybrid flash memory in which at least two types of memory cells are mixed, And a built-in One-NAND flash memory. The operation characteristics of the semiconductor device can be applied not only to a flash memory device in which the charge storage layer is made of a conductive floating gate but also to a charge trap flash (CTF) in which the charge storage layer is made of an insulating film.

Referring to FIG. 4C, the ECC encoder 131 of the ECC unit 130 may convert the write data (DATA _IN ) into a write code word (CW _IN ) to be stored in the memory cell array 210. For example, the write code word CW _IN may include the input data DATA _IN and an error correction code (e.g., a parity bit). For example, the ECC encoder 131 may generate the write code word (CW _IN ) using the BCH code constituting the TPC.

The ECC decoder 133 of the ECC unit 130 may convert the read code word CW _OUT read from the cell array 210 into the read data DATA _OUT . The read code word CW _OUT may include read data (DATA _OUT ) read from the cell array 210 and an error correction code. The ECC decoder 133 can correct the error of the read data (DATA _OUT ) based on the error correction code included in the read code word (CW _OUT ) and provide it to the memory controller (100).

The ECC decoder 133 may include a hard decision unit 401 and a soft decision unit 403. The light decision unit 401 operates in accordance with step S510 of FIG. 5 to be described below, and the decision unit 403 can operate in accordance with step S530 of FIG. 5, which will be described below.

For example, the light decision unit 401 may perform hard decision ECC decoding on the TPC code message. That is, the light decision unit 401 can decode the read code word (CW _OUT ) read out from the cell array 210 according to the hard decision lead voltage (V _HD ). For example, it performs error correction as a TPC code message or a BCH code message and outputs error location information (LOC _ER ).

The light decision unit 401 performs ECC decoding on the TPC code message composed of a plurality of BCH code messages in units of the BCH code message, performs error correction, and determines whether there is an error on a block-by-block basis. The TPC code is an error-correctable code on a block-by-block basis. The block of the TPC code may include a message block and a parity block. The TPC code may be composed of BCH codes in the row and column directions. One row BCH code and one column BCH code share one block. For example, the BCH code can correct " t " bit errors within the code with a total of " n " bits, a protecting message " k "

The light decision unit 401 determines the presence of an error with respect to the read code word (CW _OUT ) read from the cell array 210 as the TPC code message, and identifies the row code and column code in which the error occurred. The identified error position is provided to the determination section 403 as the error position information (LOC _ER ).

When the hard decision ECC decoding for the TPC code message by the light decision unit 401 is unsuccessful, the soft decision unit 403 determines that the N error bits included in the message block which is not finally error- It is possible to perform the soft decision ECC decoding with the soft decision lead voltage (V _SD ) based on the error reliability. The present invention may be a decoding operation in the soft decision unit 403. [

Returning to Fig. 4A, the control circuit 220 may control all operations related to the program, erase, and read operations of the semiconductor memory device 200. Fig.

The voltage supply circuit 230 is connected to the word line voltages (e.g., program voltage, read voltage, pass voltage, etc.) to be supplied to the respective word lines in accordance with the operation mode, Lt; RTI ID = 0.0 > well region). ≪ / RTI > The voltage generating operation of the voltage supplying circuit 230 may be performed under the control of the control circuit 220. [

The voltage supply circuit 230 may generate a plurality of variable lead voltages to generate a plurality of lead data.

The voltage transfer unit 240 selects one of the memory blocks (or sectors) of the memory cell array 210 in response to the control of the control circuit 220 and selects one of the word lines of the selected memory block have. The voltage transfer portion 240 may provide the word line voltage generated from the voltage supply circuit 230 in response to the control of the control circuit 220 to selected word lines and unselected word lines, respectively.

The read / write circuit 250 is controlled by the control circuit 220 and may operate as a sense amplifier or as a write driver depending on the mode of operation. For example, in the case of a verify / normal read operation, the read / write circuit 250 may operate as a sense amplifier for reading data from the memory cell array 210. In a normal read operation, the column selection unit 260 may output data read from the read / write circuit 250 to the outside (for example, a controller) in response to column address information. Alternatively, the data read during the verify read operation may be provided to a pass / fail verify circuit (not shown) in the semiconductor memory device 200, and used to determine whether the memory cells are successfully programmed.

In the case of a program operation, the read / write circuit 250 may operate as a write driver that drives bit lines in accordance with data to be stored in the cell array 210. The read / write circuit 250 may receive data to be used for the cell array 210 during a program operation from a buffer (not shown), and may drive bit lines according to the input data. To this end, the read / write circuit 250 may comprise a plurality of page buffers (PB) 251, each corresponding to columns (or bit lines) or a pair of columns (or bit line pairs). A plurality of latches may be provided in each page buffer 251.

Referring to FIGS. 4A and 5, the operation method of the memory controller 100 includes a hard decision decoding step S510, and a soft decision decoding step S530 may be additionally configured. The target data of the hard and soft decision decoding steps S510 and S530, that is, the data stored in the semiconductor memory device 200, is encoded data (i.e., code word codeword.

For example, the hard decision decoding step S510 may be a hard decision decoding step for the hard decision lead data of a predetermined length read from the memory cell of the memory block 211 with the hard decision lead voltage V _HD . The hard decision decoding step S510 may include steps S511 to S515.

For example, in the soft decision decoding step S530, when the hard decision decoding has finally failed in the hard decision decoding step S510, the soft decision data is set to the hard decision lead voltage V _HD And performs a soft decision decoding step of performing decoding. The soft decision decryption step (S530) may comprise steps S531 to S535.

As described above, the hard decision lead data can be read out from the semiconductor memory device 200 at the hard decision lead voltages (V _HD ) at step S511 which is the hard decision lead stage. The memory controller 100 may transmit a read command and an address to the semiconductor memory device 200. [ The semiconductor memory device 200 may read the hard decision lead data from the semiconductor memory device 200 at the hard decision lead voltages V _HD in response to the read command and the address. The read hard decision lead data may be transferred to the memory controller 100.

In step S513, the hard decision decoding may be performed as the first decoding. The ECC unit 130 can perform hard decision decoding using the hard decision judgment data using the hard decision judgment lead data from the semiconductor memory device 200 using the hard decision lead voltages V _HD .

In step S515, it is determined whether or not the hard decision decoding is successful. That is, in step S515, it is determined in step S513 whether the error of the hard-decision data decoded in hard decision is corrected. For example, the memory controller 100 determines whether an error of the hard-decision decoded data is corrected using the hard-decision data and the parity check matrix. For example, when the calculation result of the hard decision decoded data and the parity check matrix is a zero matrix (' 0 '), the hard decision data to be decoded can be determined to be correct data. On the other hand, when the hard decision decoded data and the operation result of the parity check matrix are not a zero matrix (' 0 '), the hard decision data to be decoded can be determined to be not correct data.

If it is determined in step S515 that the hard decision decoding in step S513 is successful, in step S520, the read operation based on the hard decision lead voltage (V _HD ) in step S511 is evaluated as successful and the error correction decoding ends . The hard-decision data subjected to the hard-decision SISO decoding in the step S513 may be output to the outside of the memory controller 100 or used inside the memory controller 100 as error-corrected data.

If it is determined in step S515 that the hard decision decoding in step S513 is failed, the soft decision decoding step S530 may be performed.

As described above, in step S531 which is the soft decision lead step, the soft decision lead data can be read from the semiconductor memory device 200 with the soft decision lead voltages V _SD . For example, in the binary memory cells read by the hard decision of said read voltage (V _HD), an additional lead using said soft decision read voltage (V _SD) can be performed. The soft decision lead voltages V _SD may have different levels from the hard decision lead voltages V _HD .

In step S533, the soft decision decoding may be performed as the second decoding. The soft decision decoding may be performed based on soft decision lead data and soft decision lead data including data read using the soft decision read voltages (V _SD ). The hard decision lead voltages V _HD and soft decision lead voltages V _SD may have different levels.

For example, each of the memory cells MC0 to MCn-1 of the semiconductor memory device 200 has a threshold voltage distribution (P1 to P7) of seven program states illustrated in FIG. 2 and one erase state state threshold voltage distribution (E).

Each of the hard decision lead voltages V _HD may have a voltage level between two adjacent logic states of the plurality of states. Each of the soft decision read voltages V _SD has a level between two adjacent logic states among the plurality of states, and may have a level different from the hard decision lead voltages V _HD .

The hard decision lead data value read to the hard decision lead voltage V _HD in the memory cells MC0 to MCn-1 may be different from the soft decision lead data value read out to the soft decision read voltage V _SD . For example, there may be tail cells with threshold voltages that are lower or higher than the voltage distribution of the normal logic state among the memory cells. The data value read to the hard decision lead voltage V _HD and the data value read to the soft decision read voltage V _SD in the tail cells may be different from each other. In addition to the lead according to the hard decision read voltage (V _HD), if the soft decision further read in accordance with read voltage (V _SD) is performed, additional to the threshold voltage of the memory cells (MC0 to MCn-1) LLR (e.g., information on tail cells), which is information capable of adding reliability to the data read by the hard decision lead operation, can be obtained.

If the additional information is obtained, the probability that the data stored by the memory cells MC0 to MCn-1 is a first state (e.g., '1') or a second state (e.g., '0' The accuracy of the likelihood ratio can be increased. That is, the reliability of decoding can be increased. The memory controller 100 can perform the soft decision decoding using the hard decision lead voltage V _HD and the soft decision lead data read to the soft decision lead voltage V _SD . The relationship between the hard decision lead voltage V _HD and the soft decision lead voltage V _SD will be described later with reference to FIGS. 6A and 6B.

In step S535, it is determined whether or not the soft decision decoding is successful. That is, in step S535, it is determined in step S533 whether the error of the soft decision decoded soft decision data is corrected. For example, the memory controller 100 determines whether or not the error of the soft decision decoded soft decision data is corrected using the soft decision decoded soft decision data and the parity check matrix (Parity Check Matrix). For example, when the calculation result of the soft decision SISO decoded soft decision data and the parity check matrix is a zero matrix (' 0 '), the soft decision decoded soft decision data can be determined to be correct data. On the other hand, when the soft decision decoded soft decision data and the operation result of the parity check matrix are not a zero matrix (' 0 '), the soft decision decoded data can be determined as not correct data.

Calculation of the soft decision decoded soft decision data and the parity check matrix and calculation of the hard decision decoded data and the parity check matrix can be performed in the same manner.

If it is determined in step S535 that the soft decision decoding in step S533 is successful, in step S520, the read operation based on the soft decision read voltage (V _SD ) in step S531 is evaluated as being successful and the error correction decoding Can be terminated. The soft decision decoded soft decision data in step S533 can be output to the outside of the memory controller 100 as error corrected data or can be used inside the memory controller 100. [

If it is determined in step S535 that the soft decision decoding in step S533 is unsuccessful, in step S540, the read operation based on the soft decision read voltage (V _SD ) in step S531 is evaluated as failure and the error correction decoding Can be terminated.

FIG. 6A is a conceptual diagram showing a 2-bit soft decision read operation shown in FIG. 5, and FIG. 6B is a conceptual diagram showing a 3-bit soft decision read operation as a soft decision read operation shown in FIG.

Referring to FIG. 6A, when the hard decision lead voltage V _HD is applied to the memory cell of the semiconductor memory device 200 in the hard decision decoding step S510 described with reference to FIG. 5, The hard decision data (2-1) may have a value of either 1 or 0 depending on the on-off state.

In the soft decision decode step S530, the soft decision lead operation is performed by supplying a plurality of soft decision lead voltages V _{SD1 ,} V _SD2 having a constant voltage difference with respect to the hard decision lead voltage V _HD to the memory cell Information that adds reliability to the hard decision lead data, that is, LLR can be formed.

As shown in FIG. 6A, in the case of the 2-bit soft decision read operation, when the first soft decision read voltage V _SD1 of the plurality of soft decision read voltages V _{SD1 and} V _SD2 is applied to the memory cell , And the first soft decision read data value (2-2) may be " 1000 " in accordance with the on or off state of the memory cell. Similarly, the second soft decision lead data value 2-3 may be " 1110 " in accordance with the second soft decision lead voltage V _SD2 of the plurality of soft decision lead voltages V _{SD1 and} V _SD2 have.

For example, the ECC unit 130 performs an exclusive NOR (XNOR) operation on the first and second soft decision lead data values 2-2 and 2-3 to generate soft decision data 2-4, , I.e., an LLR. The LLR (2-4) can add reliability to the hard decision data (2-1).

For example, the soft decision data 2-4 " 1 " may indicate the first state (e.g., '1') or the second state (e.g., 1 ") of the hard decision data 2-1 or a second state (for example, " 0 ") of the hard decision data 2-1, ) Is likely to be weak.

Referring to FIG. 6B, when the hard decision lead voltage V _HD is applied to the memory cell of the semiconductor memory device 200 in the hard decision decoding step S510 described with reference to FIG. 5, The hard decision data (3-1) may have a value of either 1 or 0 depending on the on-off state.

In the soft decision decode step S530, the soft decision lead operation is performed by applying a plurality of soft decision lead voltages V _SD1 to V _SD6 having a constant voltage difference with respect to the hard decision lead voltage V _HD to the memory cell Information that adds reliability to the hard decision lead data, that is, LLR can be formed.

6B, in the case of the 3-bit soft decision read operation, the first and second soft decision read voltages V _{SD1 and} V _SD2 of the plurality of soft decision read voltages V _SD1 to V _SD6 are When the data is applied to the memory cell, first and second soft decision read data values are generated as described with reference to FIG. 6A, and an exclusive NOR (XNOR) operation is performed on the first and second soft decision read data values The first soft decision data (3-2) " 1001 " can be generated.

When the third to sixth soft decision read voltages V _SD3 to V _SD6 having a constant voltage difference centering on the first and second soft decision read voltages V _{SD1 and} V _SD2 are applied to the memory cell, The third to sixth soft decision lead data values are generated similarly to those described with reference to FIG. 6A, and an XNOR (exclusive NOR) operation is performed on the third to sixth soft decision lead data values to generate the second soft decision data 3 -3), that is, LLR " 10101 " The LLR 3-3 may assign a weight to the first soft decision data 3-2.

For example, the second soft decision data 3-3 "1" is very strong at the first state (for example, "1") of the first soft decision data 3-2 , And " 0 " may indicate that the probability of being the first state (e.g., '1') of the first soft decision data 3-2 is strong.

Likewise, the second soft decision data 3-3 " 1 " is very weak (i.e., weak) in the second state (e.g., '0') of the first soft decision data 3-2, , And "0" may indicate that the probability of being weak in the second state (eg, '0') of the first soft decision data 3-2 is weak. That is, similar to that described in FIG. 6A, the LLR 3-3 can add more reliability to the hard decision data 3-1.

7 and 8 are views showing the structure of the decoder 133 and the decoding operation of the decoder 133 according to an embodiment of the present invention. Hereinafter, the configuration code may mean the write code word (CW _IN ) described in FIG. 4C. Assume that the constituent code is a BCH code and a decoding operation will be described. However, this is only an assumption for convenience of explanation, and is not limited thereto.

It is assumed that the operating environment of the conventional SISO decoder is a BI-AWGN (Binary Input Additive White Gaussian Noise) channel environment. However, BI-AWGN channel environment is difficult to apply in general flash memory. The reason is that the BI-AWGN channel input is a binary input, the channel output is not a quantized environment, but the channel input of the flash memory is a non-binary input and the channel output is a quantized environment . In addition, the conventional SISO decoder requires complicated operations such as multiplication in the output operation. For example, chase decoding utilizes Euclidean distances, resulting in a complex output computation process. As a result, the processing time of the entire decoding may be delayed. On the other hand, the present invention can provide a simple decoder that can be utilized in a general environment of a flash memory and has a simple operation process.

7 is a diagram illustrating the structure of a soft decoder 403 in a decoder 133 according to an embodiment of the present invention.

The soft decoder 403 may include a mapping unit 710, a generating unit 720, a first detecting unit 730, a second detecting unit 740, and a determining unit 750.

에 대하여, 도 8에 도시된 복호 방법에 따라 복호 동작을 수행한다. 상기 구성부호의 채널 출력

도 4C를 참조하여 설면된, 상기 셀 어레이(210)로부터 경 판정 리드 전압(V_HD)에 따라 판독된 판독 코드워드(CW_OUT)일 수 있다. 채널 출력

은 도 5 를 참조하여 설명된 디코더(133)의 연 판정 복호 단계(S530)에 의해 출력데이터

로 디코딩될 수 있다.The decoder 133 receives the channel output of the component code received via the channel

The decoding operation is performed according to the decoding method shown in Fig. The channel output

(CW _OUT ) read from the cell array 210 according to the hard decision lead voltage V _HD , which is described with reference to FIG. 4C. Channel output

By the soft decision decoding step (S530) of the decoder 133 described with reference to Fig. 5,

Lt; / RTI >

의 각 비트를 사전 설정된 제 1 값으로 매핑할 수 있다. 생성부(720)는 상기 매핑된 제 1 값을 신뢰도로 활용하여 후보 코드워드를 생성할 수 있다. 제 1 검출부(730) 및 제 2 검출부(740)는 상기 후보 코드워드로부터 제 1 코드워드 및 제 2 코드워드를 검출할 수 있다. 결정부(750)는 상기 제 2 코드워드의 존재 여부에 기초하여 연 판정 데이터

의 크기 및 부호를 결정할 수 있다.The mapping unit 710 receives the channel output of the configuration code received via the channel

May be mapped to a predetermined first value. The generator 720 may generate the candidate codeword using the mapped first value as a reliability. The first detection unit 730 and the second detection unit 740 may detect the first code word and the second code word from the candidate code word. Based on the presence or absence of the second code word,

And the size and the sign of the image.

8 is a flowchart showing a decoding operation of a decoder according to an embodiment of the present invention.

을 구성하는 각 비트

를 대응하는 LLR값 혹은 상기 LLR값의 상수배(constant)에 해당하는 제 1 값

으로 매핑(mapping)할 수 있다. 연 판정 디코더(403)는 LLR값 혹은 상기 LLR값의 상수배로 복호를 수행할 수 있다. 하지만 일반적인 채널 환경에서의 양자화된 채널 출력

은 LLR값과 선형 관계를 성립하지 않는다. 따라서 매핑부(710)는 LLR값과 선형 관계를 형성하기 위하여 단계 S810을 수행할 수 있다. 상기 LLR값 및 제 1 값

은 사전 설정될 수 있다.In step S810, the mapping unit 710 receives the channel output

Each bit

To a corresponding LLR value or a first value corresponding to a constant of the LLR value

As shown in FIG. The soft decision decoder 403 may perform decoding with an LLR value or a constant multiple of the LLR value. However, the quantized channel output

Does not establish a linear relationship with the LLR value. Accordingly, the mapping unit 710 may perform step S810 to form a linear relationship with the LLR value. The LLR value and the first value

Lt; / RTI >

를 출력하기 위하여 체이스 디코딩(Chase-decoding) 등의 복호 과정을 통하여 구성부호의 채널 출력

에 대응하는 후보 코드워드들(candidate codewords)을 생성할 수 있다.In step S820, the generation unit 720 generates soft decision data

A channel output of the configuration code is output through a decoding process such as chase decoding.

And may generate candidate codewords corresponding to the codewords.

의 크기를 신뢰도 값으로 사용하여 상기 채널 출력

에 대한 신뢰도 배열

과 부호배열

을 생성할 수 있다. 상기 신뢰도 배열

은 상기 제 1 값

의 크기를 배열한 비트열이다. 상기 부호배열

은 상기 제 1 값

의 부호를 배열한 비트열로서, 상기 신뢰도 배열

에 대응할 수 있다. 예를 들어, 상기 신뢰도 배열

의 비트 값이 0보다 큰 경우, 상기 부호배열

의 비트 값은 1일 수 있다. 그렇지 않은 경우 상기 부호배열

의 대응하는 비트 값은 0일 수 있다.The generator 720 may generate the candidate codewords using the mapped first value < RTI ID = 0.0 >

Is used as the reliability value,

Reliability array for

And a code array

Can be generated. The reliability array

Lt; RTI ID = 0.0 >

Is a bit string in which the size of the bit stream is arranged. The code array

Lt; RTI ID = 0.0 >

A bit string in which the reliability array

. For example,

When the bit value of the code array is larger than 0,

Lt; RTI ID = 0.0 > 1 < / RTI > Otherwise,

Lt; / RTI > may be zero.

에서 가장 작은 신뢰도 값(즉, 상기 매핑된 제 1값

중에서 가장 작은 값)을 갖는

개 비트의 위치, 즉 최소 신뢰도 위치를 찾을 수 있다.

의 크기는 제한되지 아니한다.The generation unit 720 generates the reliability array

(I.e., the mapped first value < RTI ID = 0.0 >

Lt; RTI ID = 0.0 >

It is possible to find the position of the bit, that is, the minimum reliability position.

Is not limited.

의 상기

개의 최소 신뢰도 위치에서 가능한 모든 이진 조합을 구성하여,

개의 검사 패턴을 갖는 검사 패턴 군

을 생성할 수 있다. 상기 이진 조합 과정에서 상기

개의 최소 신뢰도 위치 이외에 나머지 위치에는 모두 0의 값이 할당될 수 있다. 그 결과,

는

이다.The generation unit 720 generates the reliability array

Of

All possible binary combinations at the minimum reliability locations are constructed,

Test pattern group having a number of test patterns

Can be generated. In the binary combining process,

All of the remaining positions other than the minimum reliability positions of 0 can be assigned a value of zero. As a result,

The

to be.

과 검사 패턴 군

을 구성하는 검사 패턴 각각을 합한 값에 대한 모듈로2 연산(즉, XOR연산)을 통하여

개의 검사 배열로 구성되는 검사 배열 군

을 생성할 수 있다. 도 8은 상기 검사 패턴 군

을

로 표시한다.The generation unit 720 generates the code array

And test pattern group

(I.e., XOR operation) on the sum of the inspection patterns constituting the inspection pattern

The test array group consisting of the test array

Can be generated. FIG. 8 is a graph

of

.

을 구성하는 검사 배열

각각에 대해 구성부호의 검사 행렬

과 내적하여 신드롬 배열

를 생성할 수 있다. 상기 신드롬 배열

이 0 이 아니면 당해 검사 배열

은 에러를 포함할 가능성이 있다. 이 경우, 당해 검사 배열

은 비트 에러(bit-error)를 포함하는 것으로 간주될 수 있다. 상기 검사 배열 군

을 구성하는 검사 배열

중에서 상기 비트 에러를 포함하는 것으로 간주되고 당해 에러비트가 정정된 검사 배열

들이 상기 후보 코드워드들일 수 있다.The generation unit 720 generates the test array group

The test arrangement

The check matrix of the constituent code for each

And inward syndrome arrangement

Lt; / RTI > The syndrome sequence

If this is not 0,

May contain errors. In this case,

May be considered to include a bit-error. The test array group

The test arrangement

Lt; RTI ID = 0.0 > error bit < / RTI >

May be the candidate codewords.

In step S830, the first detection unit 730 detects the first code word from the candidate code words generated by the generation unit 720 in step S820, and the second detection unit 740 detects the first code word, The second codeword can be detected from the words.

으로부터 최소 거리를 갖는 후보 코드워드를 상기 제 1 코드워드

로서 검출할 수 있다. 상기 채널 출력

으로부터 후보 코드워드들 각각과의 거리는 상기 단계 S820에서 상기 후보 코드워드들의 에러 정정된 비트들 각각에 대응되는 신뢰도 값들(즉, 상기 매핑된 제 1 값

들)의 합으로 계산될 수 있다. 제 1 검출부(730)는 아래의 수학식 1을 통하여 채널 출력

으로부터 최소 거리를 갖는 상기 제 1 코드워드

를 검출할 수 있다.The first detection unit 730 detects the channel output < RTI ID = 0.0 >

To a first codeword < RTI ID = 0.0 >

Can be detected. The channel output

The distance from each of the candidate codewords to each of the error correction bits in the candidate codewords in step S820 (i. E., The mapped first value < RTI ID = 0.0 >

). ≪ / RTI > The first detector 730 detects the channel output < RTI ID = 0.0 >

Lt; RTI ID = 0.0 >

Can be detected.

(1)

는 상기 단계 S820에서 상기 후보 코드워드들의 에러 정정된 비트들의 인덱스 집합을 의미한다.In Equation (1)

Denotes an index set of error-corrected bits of the candidate codewords in step S820.

번째 비트 값이 상기 제 1 코드워드

의 제

번째 비트 값의 반전된 값이며, 상기 채널 출력

으로부터 거리가 최소인 제 2 코드워드

를 검출할 수 있다. 제 2 검출부(740)는 아래의 수학식 2를 통하여 상기 제 2 코드워드

를 검출할 수 있다.In step S840, the second detection unit 740 determines whether or not the candidate code words generated in step S820

Th < / RTI > bit value is <

Of

Th bit value, and the channel output

Lt; RTI ID = 0.0 >

Can be detected. The second detector 740 detects the second code word < RTI ID = 0.0 >

Can be detected.

(2)

는 상기 단계 S820에서 상기 후보 코드워드들 중 제

번째 비트 값이 제 1 코드워드

의 제

번째 비트 값의 반전된 값을 갖는 후보 코드워드의 에러 정정된 비트들의 인덱스 집합을 의미한다.In Equation (2)

Lt; RTI ID = 0.0 > S820 < / RTI >

Th bit value is the first code word

Of

Lt; th > bit value of the candidate codeword.

의 존재 여부에 기초하여 상기 연 판정 출력데이터

를 생성할 수 있다. In step S850, the determination unit 750 determines whether or not the second code word

The soft decision output data < RTI ID = 0.0 >

Lt; / RTI >

가 존재한다면(상기 단계 S850에서 “no”), 단계 S851에서, 결정부(750)는 상기 제 2 코드워드

와 채널 출력

간의 거리(

)로부터 상기 제 1 코드워드

와 채널 출력

간의 거리(

)를 감한 값을 크기로 하는 상기 연 판정 출력데이터

를 생성할 수 있다. 상기 연 판정 출력데이터

의 제

번째 비트 값

의 크기는 아래의 수학식 3으로 계산될 수 있다.If it is determined in step S850 that the second codeword

("No" in step S850), in step S851, the determination unit 750 determines whether the second codeword

And channel output

Distance between

) To the first codeword

And channel output

Distance between

) Obtained by subtracting the soft decision output data

Lt; / RTI > The soft decision output data

Of

Th bit value

Can be calculated by the following equation (3).

(3)

의 제

번째 비트 값

에 기초하여 상기 연 판정 출력데이터

의 제

번째 비트 값

의 부호(sign)를 결정할 수 있다. 예를 들어, 상기 제 1 코드워드

의 제

번째 비트 값

이 0인 경우에는 '+', 상기 제 1 코드워드

의 제

번째 비트 값

이 1인 경우에는 '-'로 정의하는 경우, 상기 연 판정 출력데이터

의 제

번째 비트

는 수학식 4로 결정될 수 있다.Here, the determination unit 750 determines whether or not the first code word

Of

Th bit value

Based on the soft decision output data

Of

Th bit value

Can be determined. For example, the first codeword

Of

Th bit value

&Quot; + " when the first codeword is 0,

Of

Th bit value

Is " 1 ", the soft decision output data

Of

Th bit

Can be determined by Equation (4).

(4)

가 존재하지 않는다면(상기 단계 S850에서 “yes”), 단계 S852에서, 결정부(750)는 상기 연 판정 출력데이터

의 제

번째 비트 값

의 크기를 사전 설정된 제 2 값

으로 결정하며, 상기 연 판정 출력데이터

의 제

번째 비트 값

의 부호(sign)를 상기 제 1 코드워드

의 제

번째 비트 값

에 기초하여 결정함으로써 상기 연 판정 출력데이터

생성할 수 있다. 이 경우 상기 연 판정 출력데이터

의 제

번째 비트

는 아래 수학식 5로 결정될 수 있다.If it is determined in step S850 that the second codeword

(&Quot; yes " in step S850), the determination unit 750 determines in step S852 that the soft decision output data

Of

Th bit value

To a predetermined second value

, And the soft decision output data

Of

Th bit value

Sign of the first code word < RTI ID = 0.0 >

Of

Th bit value

Determination output data < RTI ID = 0.0 >

Can be generated. In this case, the soft decision output data

Of

Th bit

Can be determined by Equation (5) below.

(5)

에 대하여 연 판정 입력으로 변환하기 위해 매핑을 하는 단계이며, 따라서 이미 연 판정 입력으로 변환을 마친 이상 단계 S810을 반복할 필요가 없기 때문에, 단계 S810은 최초 1반복에서만 수행될 수 있다. 상기 디코더(133)가 반복 복호에 사용될 경우, 상기 사전 설정된 제 2 값

은 반복(iteration)에 따라 변형될 수 있으며, 연 판정 출력데이터

도 반복(iteration)에 따라 스케일링(scaling)될 수 있다.The decoder 133 can be used for iterative decoding. For example, when performing a decoding operation on a concatenated BCH code (BCH code), when the decoding process of steps S810 to S852 is one iteration, the odd repetition may be decoding for the row code, And may be decoding for a column code. However, in step S810,

So that step S810 can be performed only in the first one iteration, since it is not necessary to repeat the above-described abnormal step S810 that has already been converted to the soft decision input. When the decoder 133 is used for iterative decoding, the predetermined second value

May be modified according to iteration, and the soft decision output data

May also be scaled according to iteration.

The decoding of soft decision data by conventional chase-decoding is very complicated to perform. However, as described above, the complexity of the decoder is reduced by outputting the soft decision data by only simple addition, subtraction, and minimal multiplication operations. Therefore, the operating speed of the decoder can be improved.

Figure 9 is an electronic device including a semiconductor memory system according to one embodiment of the present invention, including a memory controller 15000 and a semiconductor memory device 16000, according to one embodiment of the present invention. Block diagram.

9, an electronic device 10000, such as a cellular phone, a smart phone, or a tablet PC, may be coupled to a semiconductor memory device 16000, such as a flash memory device, And a memory controller 15000 capable of controlling the operation of the semiconductor memory device 16000. [

The semiconductor memory device 16000 corresponds to the semiconductor memory device 200 described with reference to Figs. 3 to 4B. The semiconductor memory device 16000 may store random data.

The memory controller 15000 corresponds to the memory controller 100 described with reference to Fig. Memory controller 15000 may be controlled by processor 11000 that controls the overall operation of the electronic device.

The data stored in the semiconductor memory device 16000 can be displayed through the display 13000 under the control of the memory controller 15000 operating under the control of the processor 11000. [

The wireless transceiver 12000 may provide or receive a wireless signal via the antenna ANT. For example, the wireless transceiver 12000 may convert the wireless signal received via the antenna ANT into a signal that the processor 11000 can process. The processor 11000 may therefore process the signal output from the wireless transceiver 12000 and store the processed signal in the semiconductor memory device 16000 via the memory controller 15000 or through the display 13000 .

The wireless transceiver 12000 may convert the signal output from the processor 11000 into a wireless signal and output the converted wireless signal to the outside through the antenna ANT.

The input device 14000 is a device that can input control signals for controlling the operation of the processor 11000 or data to be processed by the processor 11000 and includes a touch pad and a computer mouse May be implemented with the same pointing device, keypad, or keyboard.

The processor 11000 may be configured to display data output from the semiconductor memory device 16000, a wireless signal output from the wireless transceiver 12000, or data output from the input device 14000, 13000).

10 is an electronic device including a semiconductor memory system according to another embodiment of the present invention. The electronic device 20000 includes a memory controller 24000 and a semiconductor memory device 25000 according to an embodiment of the present invention. Block diagram.

The memory controller 24000 and the semiconductor memory device 25000 may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Fig.

10, a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP) , An MP3 player, or an MP4 player, includes a semiconductor memory device 25000 such as a flash memory device, a memory capable of controlling the operation of the semiconductor memory device 25000, And may include a controller 24000.

The electronic device 20000 may include a processor 21000 for controlling the overall operation of the electronic device 20000. The memory controller 24000 can be controlled by the processor 21000.

The processor 21000 can display data stored in the semiconductor memory device through a display according to an input signal generated by the input device 22000. For example, the input device 22000 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

11 is an electronic device including a semiconductor memory system according to still another embodiment of the present invention. The electronic device includes a memory controller 32000 and a semiconductor memory device 34000 according to another embodiment of the present invention 30000).

The memory controller 32000 and the semiconductor memory device 34000 may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Fig.

11, an electronic device 30000 may include a card interface 31000, a memory controller 32000, and a semiconductor memory device 34000, such as a flash memory device.

The electronic device 30000 can issue or receive data with the host (HOST) through the card interface 31000. According to one embodiment, card interface 31000 may be, but is not limited to, a secure digital (SD) card interface or a multi-media card (MMC) interface. Card interface 31000 may interface data exchange between host (HOST) and memory controller 32000 in accordance with the communication protocol of the host (HOST) capable of communicating with electronic device 30000.

The memory controller 32000 controls the overall operation of the electronic device 30000 and can control the exchange of data between the card interface 31000 and the semiconductor memory device 34000. In addition, the buffer memory 325 of the memory controller 32000 can buffer data exchanged between the card interface 31000 and the semiconductor memory device 34000.

The memory controller 32000 can be connected to the card interface 31000 and the semiconductor memory device 34000 via the data bus DATA and the address bus ADDRESS. According to one embodiment, the memory controller 32000 can receive the address of the data to be read or written from the card interface 31000 via the address bus ADDRESS and transmit it to the semiconductor memory device 34000.

In addition, the memory controller 32000 can receive or transmit data to be read or written via the data bus (DATA) connected to the card interface 31000 or the semiconductor memory device 34000, respectively.

When the electronic device 30000 of Fig. 11 is connected to a host (HOST) such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set- May receive or receive data stored in the semiconductor memory device 34000 via the card interface 31000 and the memory controller 32000.

12 is an electronic device including a semiconductor memory system according to still another embodiment of the present invention. The electronic device includes a memory controller 44000 and a semiconductor memory device 45000 according to another embodiment of the present invention. Fig.

The memory controller 44000 and the semiconductor memory device 45000 may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Fig.

12, the electronic device 40000 includes a semiconductor memory device 45000 such as a flash memory device, a memory controller 44000 for controlling the data processing operation of the semiconductor memory device 45000, and an electronic device 40000, And an image sensor 41000 that can control the overall operation of the image sensor.

The image sensor 42000 of the electronic device 40000 converts the optical signal to a digital signal and the converted digital signal is stored in the semiconductor memory device 45000 under the control of the image sensor 41000 or is read out through the display 43000 Can be displayed. In addition, the digital signal stored in the semiconductor memory device 45000 can be displayed through the display 43000 under the control of the image sensor 41000.

13 is an electronic device including a semiconductor memory system according to another embodiment of the present invention, including a memory controller 61000 and semiconductor memory devices 62000A, 62000B, and 62000C according to another embodiment of the present invention Gt; 60000 < / RTI >

The memory controller 61000 and the semiconductor memory devices 62000A, 62000B and 62000C may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Fig.

Referring to FIG. 13, the electronic device 60000 may be implemented as a data storage device such as a solid state drive (SSD).

The electronic device 60000 includes a plurality of semiconductor memory devices 62000A, 62000B and 62000C and a memory controller 61000 capable of controlling the data processing operation of each of the plurality of semiconductor memory devices 62000A, 62000B and 62000C . The electronic device 60000 may be implemented as a memory system or a memory module. In accordance with one embodiment of the present invention, the memory controller 61000 may be implemented inside or outside of the electronic device 60000.

14 is a block diagram of a data processing system including the electronic device 60000 shown in FIG.

13 and 14, a data storage device 70000, which can be implemented as a RAID (Redundant Array of Independent Disks) system, includes a RAID controller 71000 and a plurality of memory systems 72000A, 72999B to 72000N .

Each of the plurality of memory systems 72000A, 72999B to 72000N may be the electronic device 60000 shown in Fig. A plurality of memory systems (72000A, 72999B to 72000N) may constitute a RAID array. The data storage device 70000 can be implemented as an SSD.

During the program operation, the RAID controller 71000 transmits the program data output from the host to a plurality of memory systems 72000A, 72999B (in accordance with one RAID level selected based on the RAID level information output from the host among the plurality of RAID levels) to 72000N) to any one of the memory systems.

During the read operation, the RAID controller 71000 acquires, from among a plurality of RAID levels, one of a plurality of memory systems (72000A, 72999B to 72000N) in accordance with one selected RAID level based on the RAID level information output from the host The data read from one memory system can be transferred to the host.

Although the present invention has been described in detail with reference to the exemplary embodiments, it is to be understood that various changes and modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited by the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

Claims (20)

A decoding method for a channel output of a configuration code,
Mapping each bit of the channel output to a predetermined first value;
Generating candidate codewords corresponding to the channel output through error bit correction based on the mapped first value;
A candidate code word having a minimum distance from the channel output from the candidate code words based on the distance from the channel output represented by the sum of the reliability values corresponding to the bits of the error- 1 code word;
And a channel output, which is expressed as a sum of the reliability values corresponding to the bits of the error-bit corrected candidate codewords, from among the candidate codewords

Th bit of the first code word

Detecting a candidate codeword having a minimum distance from the channel output as a second codeword; And
Determining soft decision data based on the presence or absence of the second code word
.
The method according to claim 1,
The first codeword
Is detected by the following equation (1)
Decoding method.
(1)

In the above equation (1)

Is an arbitrary code word,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

Denotes a set of corrected bit indices in the course of channel output being an arbitrary codeword.
The method according to claim 1,
The second code word
Is detected by the following equation (2)
Decoding method.
(2)

In Equation (2)

Lt; RTI ID = 0.0 >

Of

Any code word having an inverted value of the bit value,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

This arbitrary code word

Which is a set of corrected bit indices.
The method according to claim 1,
Determining the soft decision data comprises:
If the second codeword is present,
Determining a size of the soft decision data as a value obtained by subtracting a distance between the first codeword and the channel output from a distance between the second codeword and the channel output,
Determining a code of the soft decision data based on the first code word
Decoding method.
5. The method of claim 4,
The soft decision data
Is generated by the following equation (3)
Decoding method.
(3)

In Equation (3)

The soft decision output data

Of

Th bit value,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

Of

Th bit value,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

The second codeword

A set of corrected bit indices in the process,

Channel output

Lt; RTI ID = 0.0 >

And a set of the bit indexes corrected in the process.
The method according to claim 1,
Determining the soft decision data comprises:
If the second code word does not exist,
Determining a size of the soft decision data as a second predetermined value,
Determining a code of the soft decision data based on the first code word
Decoding method.
The method according to claim 1,
The predetermined first value
A log likelihood ratio (LLR) value or a constant multiple of the LLR value
Decoding method.
The method according to claim 1,
The step of generating the candidate codewords
And generates the candidate codewords through chase decoding
Decoding method.
A mapping unit for mapping each bit of the channel output to a predetermined first value;
A generator for generating candidate codewords corresponding to the channel output based on the mapped first value through error bit correction;
A candidate code word having a minimum distance from the channel output from the candidate code words based on the distance from the channel output represented by the sum of the reliability values corresponding to the bits of the error- A first detecting unit for detecting the first code word;
And a channel output, which is expressed as a sum of the reliability values corresponding to the bits of the error-bit corrected candidate codewords, from among the candidate codewords

Th bit of the first code word

Th bit value and a minimum distance from the channel output is a second code word; And
Determining a soft decision data based on the presence or absence of the second code word;
/ RTI >
10. The method of claim 9,
The first detection unit
The first code word is detected by the following equation (1)
Decoder.
(4)

In Equation (4)

Is an arbitrary code word,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

Denotes a set of corrected bit indices in the course of channel output being an arbitrary codeword. 10. The method of claim 9,
The second detection unit
The second code word is detected by the following equation (2)
Decoder.
(5)

In Equation (5)

Lt; RTI ID = 0.0 >

Of

Any code word having an inverted value of the bit value,

Channel output,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

This arbitrary code word

Which is a set of corrected bit indices.
10. The method of claim 9,
Wherein the determination unit determines the soft decision data,
If the second codeword is present,
Determining the soft decision data as a value obtained by subtracting the distance between the first codeword and the channel output from the distance between the second codeword and the channel output,
Determining a code of the soft decision data based on the first code word
Decoder.
13. The method of claim 12,
The determination unit
The soft decision data is determined by the following equation (6)
Decoder.
(6)

In Equation (6)

The soft decision output data

Of

Th bit value,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

And channel output

Distance,

Lt; RTI ID = 0.0 >

Of

Th bit value,

Channel output

Each bit

A first value mapped to a predetermined value,

Channel output

The second codeword

A set of corrected bit indices in the process,

Channel output

Lt; RTI ID = 0.0 >

And a set of the bit indexes corrected in the process.
10. The method of claim 9,
The determination unit determines the soft decision data
If the second code word does not exist,
Determining a size of the soft decision data as a second predetermined value,
And determines that the code of the soft decision data conforms to the first code word
Decoder.
10. The method of claim 9,
The predetermined first value
A log likelihood ratio (LLR) value or a constant multiple of the LLR value
Decoder.
10. The method of claim 9,
The generating unit
And generates the candidate codewords through chase decoding
Decoder. In a semiconductor memory system,
A semiconductor memory device; And
A controller,
The controller
A mapping unit for mapping each bit of the channel output to a predetermined first value;
A generator for generating candidate codewords corresponding to the channel output through error bit correction based on the mapped first value;
A candidate code word having a minimum distance from the channel output from the candidate code words based on the distance from the channel output represented by the sum of the reliability values corresponding to the bits of the error- A first detecting unit for detecting the first code word;
And a channel output, which is expressed as a sum of the reliability values corresponding to the bits of the error-bit corrected candidate codewords, from among the candidate codewords

Th bit of the first code word

A second detector for detecting a candidate code word having a minimum distance from the channel output as a second code word; And
And a determination unit that determines soft decision data based on the presence or absence of the second code word.
Semiconductor memory system. 18. The method of claim 17,
The determination unit determines the soft decision data
If the second codeword is present,
Determining a size of the soft decision data as a value obtained by subtracting a distance between the first codeword and the channel output from a distance between the second codeword and the channel output,
Determining a code of the soft decision data based on the first code word
Semiconductor memory system.
18. The method of claim 17,
The determination unit determines the soft decision data
If the second code word does not exist,
Determining a size of the soft decision data as a second predetermined value,
Determining a code of the soft decision data based on the first code word
≪ / RTI >
18. The method of claim 17,
The generating unit
And generates the candidate codewords through chase decoding
Semiconductor memory system.

Images