KR20180120551A - Method and apparatus for frequent pattern mining - Google Patents

Abstract

Disclosed are a frequent pattern mining method and an apparatus using the same. The apparatus according to an embodiment of the present invention, copies each of different relative memory addresses of candidate item sets from a main memory to each of device memories of GPUs, copies at least one identical transaction block required for calculation of supports of the candidate item sets from the main memory to each of the device memories, and synchronizes partial supports processed by the GPUs to update the supports of the candidate item sets.

Description

[0001] METHOD AND APPARATUS FOR FREQUENT PATTERN MINING [0002]

The following embodiments are directed to a method and apparatus for mining frequent patterns.

In data mining, Frequent Item Set Mining (FIM) is a fundamental technique. Frequent item set mining is widely used in a variety of fields such as market basket analysis, web usage mining, social network analysis, intrusion detection, bioinformatics and recommendation systems. However, although the size of the data is increasing, existing methods are less applicable due to the relatively slow processing speed performance. The deluge of data generated from automated systems for diagnostic or analytical purposes is making it difficult to apply frequent item-set mining techniques in many applications.

Many sequential frequent item set mining methods have been proposed. However, these methods have limitations in the performance that can be obtained from a single thread, and occasionally fail to find frequent item sets from big data in a reasonable amount of time. In terms of computation time, the frequent item set mining method is still faced with a problem that has not been fully solved yet.

There are many sequential frequent item set mining methods using a single CPU (Central Processing Unit) thread. However, since the clock speed of the CPU generally does not increase anymore, these methods have a fundamental limitation on the mining performance.

In order to overcome the above-described limitations, various parallel methods using many cores of a CPU's multi-cores, a multi-machine or a GPU (Graphic Processing Unit) have been proposed. However, these methods also have disadvantages such as relatively slow performance, limited size of processable data, and poor scalability due to workload skewness.

To overcome performance limitations, a number of parallel item set mining methods have been proposed. These methods fall into three groups: (1) a (CPU-based) multi-thread method, (2) a distributed method, and (3) a GPU-based method. Since the GPU-based method presupposes multi-threading, " multi-threading " may be omitted in the GPU-based method.

The first group, the multi-thread method, focuses on utilizing a multi-core CPU to improve single-threaded performance. Actually, the multi-thread method can improve the performance compared to the sequential frequent item set mining method. However, the theoretical performance of the CPU is much lower than the recent GPU, and the performance gap between the CPU and the GPU is getting larger and larger, so the multi-thread method is hard to see in terms of performance.

The second group, the distribution method, attempts to accelerate performance using multiple machines. In general, a serious disadvantage of the distributed method is the large overhead of network communication.

The third group, the GPU-based method, focuses on improving performance by leveraging the many cores of the GPU. The continued development of GPU technology continues to improve the theoretical computing performance of modern computers. Because the theoretical computing power of the GPU is much better than the CPU, the use of the GPU is becoming increasingly important in a wide range of problems, including frequent pattern mining. However, existing GPU-based methods suffer from limited data size due to limited GPU memory. In general, the size of GPU memory is much smaller than main memory, and most GPU-based methods can find frequent patterns that are limited to data stored in GPU memory. In the GPU-based approach, Frontier Expansion is the latest technology to handle larger sets of data than GPU memory. However, this technique is still unable to process as much data as the CPU-based method, because large amounts of data at the mid-level of the pattern space can not be kept in GPU memory.

Conventional FIM methods tend to require computationally intensive processing proportional to the size of the data set. Conventional FIM methods may fail mining operations due to large intermediate data. Even if the input data set enters the memory, the intermediate data may become too large to fit in the memory. This phenomenon can be more prominent when the FIM is performed using the GPU because of the small capacity of the GPU's device memory.

Existing parallel methods have problems due to workload asymmetry. Workload asymmetry is very common, but it has a significant impact on the performance of parallel computing. Existing parallel methods divide the exploration space of explored patterns into multiple pieces (e.g., equivalent classes) and assign each piece to each processor (or machine). Each subtree of an enumeration tree is likely to be responsible for a different amount of workload (size). As a result, existing parallel methods are less scalable in terms of CPU, machine or GPU count. That is, existing parallel methods have a problem that the rate-improvement ratio does not increase proportionally even if the number of processors increases.

The inefficiency of wasting GPU clocks by holding a large amount of intermediate level data in GPU memory, the constraint of having a large amount of data transfer overhead between main memory and GPU memory, the constraint of poor scalability of mining techniques in terms of GPU count Data mining techniques are needed to improve the

The frequent pattern mining method according to an embodiment attempts to solve the problem that the amount of calculation of GPUs increases as the size of a data set increases.

The frequent pattern mining method according to an exemplary embodiment attempts to reduce the possibility of pattern mining failure due to the size of the intermediate data being too large as compared with the memory of the GPU.

The frequent pattern mining method according to an embodiment attempts to solve the problem of inefficiency in terms of performance and memory usage of the GPU architecture caused by maintaining and utilizing patterns at intermediate levels of an enumeration tree.

The frequent pattern mining method according to one embodiment attempts to solve the problem of workload asymmetry between GPUs.

A frequent pattern mining method according to an exemplary embodiment includes generating blocks from bit vectors corresponding to frequent 1-item sets; Copying different relative memory addresses of candidate k-item sets, respectively, from the main memory of a central processing unit (CPU) to each of the device memories of GPUs (graphic processing units); Copying at least one identical block from the main memory to each of the device memories, each of the at least one identical block required for calculating the votes of the candidate k-itemsets of the blocks; And updating the scores of the candidate k-itemsets by synchronizing partial scores calculated by the GPUs.

According to one embodiment, copying each of the different relative memory addresses comprises: copying the relative memory address of the first candidate k-itemset into the device memory of the first GPU; And copying the relative memory address of the second candidate k-item set to the device memory of the second GPU, wherein copying each of the at least one identical block comprises copying a first one of the blocks to the first Copying to the device memory of the GPU; And copying the first block to the device memory of the second GPU.

A frequent pattern mining method according to an embodiment includes vertically partitioning a transaction bitmap including the bit vectors, the transaction bitmap being represented by a vertical bitmap layout to generate transaction blocks And wherein the blocks may be the transaction blocks.

According to one embodiment, the step of copying each of the different relative memory addresses, respectively, comprises: using a dictionary mapping a frequent 1-item set of the transaction bitmap to a relative memory address, Gt; And copying each of the generated relative memory addresses as an outer operand to each of the device memories.

According to one embodiment, generating the relative memory addresses comprises: identifying frequent 1-item sets included in a candidate k-itemset; And combining the relative memory addresses of the identified frequent 1-item sets to generate a relative memory address of the candidate k-item set.

According to one embodiment, copying each of the at least one identical block comprises copying one of the transaction blocks into each of the device memories as an inner operand, Updating the supports may comprise: each GPU computing partial supports corresponding to each of the relative memory addresses using the transaction block and each of the relative memory addresses; And updating the support ratings of the candidate k-item sets by synchronizing the partial supports corresponding to the relative memory addresses.

A frequent pattern mining method according to an exemplary embodiment of the present invention includes dividing the frequent 1-item sets into fragments; Generating item sets that are all combinations of the frequent 1-item sets in the fragments for each of the fragments; Calculating bit vectors corresponding to the generated item sets; And a transaction bitmap including the calculated bit vectors, the transaction bitmap being vertically partitioned by a vertical bitmap layout, and generating fragment blocks by dividing the transaction bits into the fragments , And the blocks may be the fragment blocks.

According to one embodiment, the copying of the different relative memory addresses, respectively, may include generating a relative memory address of the candidate k-item sets using a dictionary mapping an item set of the transaction bitmap to a relative memory address step; And copying each of the relative memory addresses as an outer operand into each of the device memories.

According to one embodiment, generating the relative memory addresses comprises: identifying sets of items included in a candidate k-itemset; And combining the relative memory addresses of the identified item sets to generate a relative memory address of the candidate k-item set.

According to one embodiment, the step of copying each of the at least one identical block comprises copying at least one fragment block of the fragment blocks into each of the device memories as an inner operand, Updating the supports may comprise: each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the fragment block and the respective relative memory addresses; And updating the support ratings of the candidate k-item sets by synchronizing the partial supports corresponding to the relative memory addresses.

The frequent pattern mining method according to an embodiment includes mining 1-item sets frequently from transaction data; A transaction bitmap containing bit vectors corresponding to the frequent 1-item sets, the transaction bitmap being represented by a vertical bitmap layout, to vertically partition transaction blocks step; Using GPUs, calculating support ratings of candidate k-item sets from the transaction blocks; And mining frequent k-item sets based on the ratings.

According to one embodiment, calculating the supports comprises: generating relative memory addresses of the candidate k-item sets using a dictionary that maps a frequent 1-item set of the transaction bitmap to a relative memory address; Copying each of the relative memory addresses as an outer operand into each of the device memories of the GPUs; Copying any one of the transaction blocks as an inner operand into each of the device memories; Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the transaction block and the respective relative memory addresses; And updating the scores of the candidate k-itemsets by synchronizing the partial votes

According to one embodiment, calculating the supports comprises: copying a second transaction block into each of the device memories as an inner operand; Each of the GPUs calculating second partial supports corresponding to the respective relative memory addresses using the second transaction block and the respective relative memory addresses; And updating the scores of the candidate k-itemsets by synchronizing the second partial scores.

The frequent pattern mining method according to an embodiment includes mining 1-item sets frequently from transaction data; Dividing the frequent 1-item sets into fragments; Generating item sets that are all combinations of the frequent 1-item sets in the fragments for each of the fragments; Calculating bit vectors corresponding to the generated item sets; Vertically partitioning a transaction bitmap including the calculated bit vectors, the transaction bitmap being represented by a vertical bitmap layout, and generating fragment blocks by dividing the transaction bitmap into the fragments step; Calculating, using GPUs, the scores of the candidate k-itemsets from the fragment blocks; And mining frequent k-item sets based on the ratings.

According to one embodiment, calculating the supports comprises: generating relative memory addresses of the candidate k-item sets using a dictionary that maps a set of items of the transaction bitmap to a relative memory address; Copying each of the relative memory addresses as an outer operand into each of the device memories of the GPUs; Copying at least one fragment block of the fragment blocks into each of the device memories as an inner operand; Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the fragment block and the respective relative memory addresses; And updating the scores of the candidate k-item sets by synchronizing the partial scores.

According to one embodiment, calculating the supports comprises: copying at least one second fragment block into each of the device memories as an inner operand; Each of the GPUs calculating second partial degrees of support corresponding to the respective relative memory addresses using the second fragment block and the respective relative memory addresses; And updating the scores of the candidate k-itemsets by synchronizing the second partial scores.

The frequent pattern mining method according to an embodiment includes mining 1-item sets frequently from transaction data; Selecting a TFL (Traversal from the First Level) strategy or a HIL (Hopping from Intermediate Level) strategy; Generating blocks from the bit vectors corresponding to the frequent 1-item sets based on the selected strategy; Using the GPUs, calculating support ratings of candidate k-item sets from the blocks; And mining frequent k-item sets based on the ratings.

A frequent pattern mining apparatus according to an embodiment includes a CPU; And a main memory, the CPU generating blocks from bit vectors corresponding to the frequent 1-item sets, transferring from the main memory to each of the device memories of the GPUs, Copying each of the addresses from the main memory to each of the device memories and copying at least one identical block needed to compute the votes of the candidate k-itemsets of the blocks, Item supports can be updated by synchronizing partial supports.

The frequent pattern mining method according to one embodiment can maximize computation efficiency by simultaneously processing large-scale data at the same time by making maximum use of the calculation power of GPUs.

The frequent pattern mining method according to one embodiment can provide a robust FIM technique by not materializing intermediate data.

The frequent pattern mining method according to one embodiment performs a large amount of calculations on a small amount of data (e.g., mining a frequent 1-item set at the first level of the enumeration tree) It can be utilized efficiently.

The frequent pattern mining method according to an exemplary embodiment may perform an appropriate amount of calculation based on an appropriate amount of data to improve processing performance of a data set including a long pattern.

The frequent pattern mining method according to an embodiment can improve the workload asymmetry problem by distributing the relative memory addresses of the candidate item sets to each GPUs and streaming the transaction blocks to all the GPUs.

The frequent pattern mining method according to one embodiment can solve the workload asymmetry problem and linearly improve the mining processing performance as the number of GPUs increases.

1 is a diagram for explaining a frequent pattern mining method according to an embodiment.
2 is a view for explaining a transaction block according to an embodiment.
3 is a view for explaining the operation of the TFL strategy according to an embodiment.
4 is a diagram for explaining a kernel function according to an embodiment.
5 is a view for explaining a fragment block according to an embodiment.
6 is a diagram for explaining the operation of the HIL strategy according to an embodiment.
7 is a diagram for explaining an operation of utilizing multiple GPUs according to an embodiment.
FIG. 8 is a diagram illustrating an exemplary configuration of a frequent pattern mining apparatus according to an embodiment of the present invention. Referring to FIG.
FIG. 9 is a flowchart for explaining a frequent pattern mining method according to an embodiment.
FIG. 10 is a flowchart illustrating system initialization according to an embodiment.
11 is a flowchart for explaining an operation of calculating the support degree according to an embodiment.
12 is a flowchart for explaining an operation of calculating a partial support according to an embodiment.

Specific structural or functional descriptions of embodiments are set forth for illustration purposes only and may be embodied with various changes and modifications. Accordingly, the embodiments are not intended to be limited to the particular forms disclosed, and the scope of the present disclosure includes changes, equivalents, or alternatives included in the technical idea.

The terms first or second, etc. may be used to describe various elements, but such terms should be interpreted solely for the purpose of distinguishing one element from another. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected or connected to the other element, although other elements may be present in between.

The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms " comprises ", or " having ", and the like, are used to specify one or more of the described features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

"Overview"

The frequent pattern mining device according to an exemplary embodiment may use the GPU to mine frequent patterns from large-scale data. A frequent pattern mining device is an apparatus for mining frequent patterns from data, for example, can be used to mine frequent item sets from transaction data, and can be implemented as a software module, a hardware module, or a combination thereof.

Frequent Item Set Mining (FIM) is a technique for finding frequent item sets from given data. The FIM is given by a given transaction database D = {t ₁ ; t ₂ ; :::; t _n }, where each transaction t _i is a subset of the items in I [1, N]. However, in the following, the concept of support is used instead of the fraction, and support of the item set means the number of occurrences of the item set.

In Table 1, Tid is the identifier corresponding to the transaction, and transaction is the set of items corresponding to Tid. For example, the transaction corresponding to one Tid is {Beer, Nuts, Diaper}.

If the transaction data D is given and the minimum support is given as minsup as shown in Table 1, the FIM can find all itemsets from D that have a number equal to or greater than minsup. The degree of support refers to the frequency of occurrences of the item set in D, and the set of items that occur more than D is called the frequent item set. For example, in transaction data D in Table 1, if minsup is 3, the FIM can find the item sets {Beer}, {Diaper} and {Beer, Diaper} from the input D Here, the {Beer}, {Diaper} and {Beer, Diaper} found can be output as frequent item sets. A frequent-item set with n items in the item set is called a frequent n-item set. In transaction data D of Table 1, {Beer} and {Diaper} are frequent 1-item sets and {Beer, Diaper} are frequent 2-item sets.

The GPU-based frequent item set mining technique according to an embodiment is referred to as GMiner, and a method of performing such a technique is referred to as a frequent pattern mining method. The frequent pattern mining device can perform frequent pattern mining by GMiner.

GMiner can take advantage of the power of GPUs to improve the speed performance of mining operations. The GMiner can handle large-scale data like the CPU-based method and solve the above-mentioned problems in the conventional GPU-based method. GMiner proposes the following concepts: GMiner can mine frequent patterns from the first level of the enumeration tree, instead of maintaining and utilizing patterns at intermediate levels of the enumeration tree. Because GMiner does not materialize intermediate data, it can provide a very effective and robust FIM technique in terms of performance and memory usage of the GPU-based method. According to one embodiment, GMiner proposes a TFL (Traversal from the First Level) strategy.

According to the TFL strategy, the frequent pattern mining device does not maintain the frequent item sets of intermediate levels (in the enumeration tree) of the device memory of the projected database and the GPU, (Denoted as F ₁ ) can be used to find all the frequent item sets. According to the TFL strategy, frequent pattern mining devices can improve the performance of mining processing while reducing the amount of GPU device memory usage.

The TFL strategy may be appropriate for GPU architectures with a very large gap between processor speed and memory speed. In the GPU architecture, performing a large amount of calculations based on a relatively small set of F ₁ to mine frequent n-item sets is based on a relatively large set of (n-1) To mine the frequent n-item sets. According to the TFL strategy, frequent pattern mining devices can maximize the performance improvements of the latest parallel methods including multithreading, distributed and GPU based techniques.

According to one embodiment, GMiner proposes a TFL strategy as well as a Hopping from Intermediate Level (HIL) strategy to improve mining performance on data sets comprising long patterns. According to the HIL strategy, frequent pattern mining devices can reduce the amount of computation by using the device memory of many GPUs, which can improve mining performance for long patterns.

The frequent pattern mining device can improve the workload asymmetry that existed in the conventional parallel method in addition to using the memory efficiently and increasing the mining speed. As a result, the performance of the GMiner can be improved linearly as the number of GPUs increases. GMiner proposes a concept of transaction block and relative memory address to improve workload asymmetry.

A transaction block is a fixed-size chunk of a bitwise representation of transactions, and a relative memory address is an array representation of a set of candidate items. In the case of parallel processing, the frequent pattern mining device may divide the array of relative memory addresses into multiple subarrays of the same size without dividing the search space of the enumeration tree into subtrees . The frequent pattern mining device can then store each subarray in each GPU and perform the mining by streaming the transaction blocks to all GPUs. This allows each GPU to have the same amount of workload to each other.

Hereinafter, an overview of a frequent pattern mining method according to an embodiment will be described with reference to FIG. 1, an embodiment related to a TFL strategy will be described with reference to FIG. 2 to FIG. 4, An embodiment related to strategy will be described, and an embodiment of an operation using multiple GPUs with reference to Fig. 7 will be described. Referring to FIG. 8, the components of a frequent pattern mining apparatus according to an embodiment will be described, and the operation of the frequent pattern mining method according to an embodiment will be described with reference to FIGS.

1 is a diagram for explaining a frequent pattern mining method according to an embodiment.

Referring to FIG. 1, a frequent pattern mining device may load transaction data and may minify frequent 1-item sets 101 from loaded transaction data. Here, the transaction data includes at least one transaction corresponding to at least one item as target data of a frequent pattern. As described above, the frequent pattern mining apparatus can mine frequent patterns using the GMiner technique, and the operations described below can be performed by the GMiner technique.

The frequent pattern mining device may generate blocks 103 from bit vectors 102 corresponding to frequent 1-item sets 101. The frequent pattern mining device can use the CPU 104 to handle operations related to frequent pattern mining. According to one embodiment, the frequent pattern mining device includes a CPU 104, main memory 105 and GPUs 106 and 107. [ GPUs 106 and 107 include device memories 108 and 109, respectively. However, the frequent pattern mining device may be implemented by at least one of the CPU 104 and the GPUs 106 and 107.

The frequent pattern mining device may use the CPU 104 to control the main memory 105 and the GPUs 106 and 107 such that data read / write operations associated with the main memory 105 and GPUs 106 and 107 associated with the device memories 108 and 109 and control commands or processes associated with the AND operation of the GPUs 106 and 107. [ The frequent pattern mining apparatus can write the generated blocks 103 in the main memory 105. Specific contents related to the generation of the blocks 103 will be described later.

The frequent pattern mining device is responsible for mapping the different relative memory addresses 110 and 112 of the candidate k-item sets from the main memory 105 of the CPU 104 to each of the device memories 108 and 109 of the GPUs 106 and 107, 111), respectively. For example, the frequent pattern mining device may copy the relative memory address RA ₁ 110 to the device memory 108 and copy the relative memory address RA ₂ 111 to the device memory 109. The relative memory address is an address for identifying any one of the candidate k-item sets, and may be expressed based on items in the candidate k-item set. Details related to the creation and copying of the relative memory addresses 110 and 111 will be described later.

The frequent pattern mining device may copy at least one identical block from the main memory 105 to each of the device memories 108 and 109, each of which is necessary for the calculation of the scores of the candidate k-item sets of the blocks 103 . For example, the frequent pattern mining apparatus is equally copying a block TB ₁ (112) of main memory blocks from the (105) TB ₁ and TB ₂ (103) in the device memory 108 and the device memory 109 have. Concrete contents related to the copying of the blocks 103 will be described later.

The frequent pattern mining device may update the scores of the candidate k-item sets by synchronizing the partial supports 113 and 114 calculated by the GPUs 106 and 107. [ The GPU ₁ 106 can calculate the partial support PS ₁ 113 of the candidate k-item set corresponding to the relative memory address RA ₁ based on the relative memory address RA ₁ and block TB ₁ copied into the device memory 108 have. Similarly, the GPU ₂ (107) is a memory device 109, the external memory address RA ₂ and blocks TB ₁ relative memory addresses RA ₂ PS ₂ (114) approval ratings of the candidate k- set of entries corresponding to the copy on the basis of the Can be calculated. The frequent pattern mining device may copy partial supports PS ₁ 113 and PS ₂ 114 computed by GPUs 106 and 107 to main memory. The frequent pattern mining device can update the scores of the candidate k-item sets based on the partial ratings copied into the main memory. The frequent pattern mining device can mine at least one frequent k-item set of candidate k-item sets by comparing the updated supports with a predefined minimum support. Details regarding the calculation of the partial supports 113 and 114 and the updating of the support scores will be described later.

" TFL (Traversal from the First Level) Strategy "

The Traversal from the First Level (TFL) strategy is a technique for mining frequent patterns from the first level of the enumeration tree - F ₁ -. The frequent pattern mining device can perform frequent item set mining on large - scale data at high speed using TFL strategy. According to the TFL strategy, the frequent pattern mining device does not maintain the frequent item sets of intermediate levels of the enumeration tree and the projected database (transaction data) in the GPU's device memory, but instead uses only F ₁ You can find frequent item sets.

The frequent pattern mining device uses the TFL strategy to significantly reduce the amount of device memory in the GPU, allowing large-scale data to be processed without running out of memory. The frequent pattern mining device concurrently performs pattern mining while streaming transactional data from main memory to the GPU's device memory, thereby eliminating data transfer overhead between the main memory and the GPU's device memory. Streaming includes the concept of streaming copying. The frequent pattern mining device can solve the workload asymmetry problem by using the block-based streaming method. Hereinafter, the transaction block, the block-based streaming technique, and the algorithm of the TFL strategy will be described respectively.

&Quot; Transaction Blocks "

2 is a view for explaining a transaction block according to an embodiment.

To fully exploit the computing power of GPUs, constructing regular memory access patterns and simplifying data structures is important for workload balancing and coalesced memory access among thousands of GPU cores. The memory system and arithmetic and logic units (ALUs) of the GPUs compute complex and variable-sized data structures, including sets, lists, maps, and combinations thereof, in comparison to the CPU's memory system and arithmetic logic units It can be inefficient to process. GPUs have limited device memory, and limited memory size can limit the use of GPUs to mine frequent item sets from large and / or dense data sets.

In consideration of the computation efficiency, the frequent pattern mining apparatus can employ a vertical bitmap layout for data representation. Horizonal and vertical layouts are complex and irregular, which may be unsuitable for GPU computational efficiency. Referring to FIG. 2, transaction data 201 represented in a horizontal layout, which is a horizontal format, is shown.

According to one embodiment, a frequent pattern mining device can perform bitwise AND operations from a large-scale bitmap using a vertical bitmap layout. The frequent pattern mining device can perform bitwise AND operations using GPUs, thereby improving the processing speed performance as compared to using CPUs. The frequent pattern mining device utilizes a vertical bitmap layout so that it can be partitioned into sub databases so that the input database can fit into the device memory of the main memory or GPU, respectively.

The input data D expressed in the vertical bitmap layout is called a transaction bitmap. Frequent pattern mining apparatus can databasing the transaction bitmap represented by a 1-frequency set of entries in the mining F _1, F _1, from the transaction data to the vertical bit map layout.

Referring to FIG. 2, the transaction bitmap 202 includes bit vectors that correspond to frequent 1-item sets, respectively, and is represented by a vertical bitmap layout. For example, the bit vector corresponding to the frequent 1-item set A is {100111001010}. According to one embodiment, the frequent pattern mining device may obtain or directly generate a transaction bitmap containing the bit vectors of F ₁ .

According to one embodiment, the frequent pattern mining device may vertically partition the transaction bitmap 202 to a predefined size. The frequent pattern mining device may generate transaction blocks TB ₁ , TB _2, and TB ₃ (203, 204, and 205) based on the vertically partitioned transaction bitmap. The frequent pattern mining device can generate transaction blocks considering the size of the device memories of the GPUs. Definition 1 below defines the vertical partitioning of the transaction bitmap.

Definition 1. (Transactional bitmap Partitioning ) If you want to create a transactional bitmap TB (Transaction Bitmap) with the same width R  Non-redundant With partitions  Vertically dividing it means. here , Partitions TB _{1: R} in  Quot; TB _k The  The k-th Partition  (1 ≤ k ≤ R).

The transaction block created by the vertical partitioning means the partition created by the transaction bitmap partitioning of " Definition 1 ". TB _{1: R} The k- th block of the transaction is referred to as TB _k. Since the frequent pattern mining device starts mining from the frequent 1-item sets F ₁ , the size of TB is | F ₁ | x | D < / RTI > Here, | D | is the total number of transactions. For example, in the transaction bitmap 202 of FIG. 2, F ₁ | = 7, | D | = 12. The width of a single partition of the transactional bitmap is denoted by W. The size of TB _k is | F ₁ | x W. For example, since W in the transaction block of FIG. 2 is 4, the size of TB ₁ 203 is 7 x 4. To ensure that the widths of transaction blocks are W, the frequent pattern mining device is TB _{1: R} If the width of the last transaction block TB _R is less than W, preprocessing can be performed to pad at least one 0 to TB _R.

According to one embodiment, the frequent pattern mining device may set the parameter W to a size sufficiently small that each TB _k can fit into the device memory of the GPU. The frequent pattern mining device can consecutively allocate each transaction block to main memory or store it as a chunk in a secondary storage such as a disk page. Although an embodiment in which a transaction bitmap is represented in a vertical format has been described, a frequent pattern mining device may also create transaction blocks by partitioning a transaction represented in a horizontal format in consideration of design intent, system environment, or efficiency. Although an embodiment has been described in which transaction blocks are partitioned to the same size width, a frequent pattern mining device may generate transaction blocks of different size widths considering design intent, system environment or efficiency.

Frequent itemset 1-x (x ∈ F ₁₎ has a length in the TB | has a bit vector (bit vector) of | D. Referring to FIG. 2, a frequent 1-item set {A} corresponds to a bit vector " 100111001010 " The TB can be divided into R bit vectors, length W, by vertical partitioning. TB _k-bit vector of the x is denoted as TB _k (x). Referring to FIG. 2, TB ₁ ({A}) is " 1001 ". As described above, TB includes only bit vectors corresponding to frequent 1-item sets. Thus, if x is a frequent n- _th item set, x has n bit vectors in TB _k , {TB _k (i) | i ∈ x}. Definition 2 below defines the concept of a set of physical pointers of bit vectors for the frequent item set x in the transaction bitmap.

Definition 2.  (Relative memory address Relative memory address )) The relative memory address of item i is denoted RA (i) TB _k of  From starting memory address TB _k (i)  As the distance in bytes to the starting memory address Is defined. frequency  The set of relative memory addresses of item set x is denoted RA (x), and {RA (i) | i ∈ x}.

The concept of a relative memory address is for fast access to the memory location (or memory locations of the item sets) of items in a single transaction block on the main memory or GPU's device memory. The frequent pattern mining device can use RA (x) as a kind of identifier of the item set x. Let | x | be the number of entries in x and | RA (x) | the number of distinct memory addresses in RA (x). Since each item i ∈ x has a unique memory address in TB _k , | x | = | RA (x) |. RA (x) of the frequent item set x does not change at all TB _k (1 ≤ k ≤ R). That is, since the size of TB _k is fixed, RA (x) always has the same relative memory address.

&Quot; Nested-Loop Streaming "

The frequent pattern mining device can find frequent item sets at each level of the item set lattice by repeating the two main steps of candidate generation and test method (support counting). In the two steps, the test step may be more computationally intensive than the candidate generation step. We can concentrate on accelerating the test phase by using frequent pattern mining GPUs, and can perform the candidate generation step using CPUs.

According to one embodiment, the frequent pattern mining device is not a traversal of depth-first search (DFS) in order to fully utilize the large-scale parallel processing of GPUs and achieve a balance of workloads, -First Search; BFS) It is possible to perform mining using traversal. However, frequent pattern mining devices may use DFS traversal depending on design intent or system efficiency.

When BFS traversal is used for pattern mining, the number of frequent item sets at a particular level may be kept in the device memory of a limited amount of GPUs and may be too large to be used for counting the support of the next level of candidate item sets. This problem can be exacerbated as the number of transactions grows, but frequent pattern mining devices can solve this problem using the TFL strategy.

The frequent pattern mining device can mine frequent item sets for large data sets without degrading performance within the limited device memory of the GPU. The entire set of frequent 1-item sets is referred to as the first level of the item set lattice. Likewise, the different levels of the item aggregation lattice are referred to as intermediate levels . If the frequent item sets of intermediate levels are specified to reduce the computational overhead, a large amount of intermediate data may be generated to cause problems due to lack of memory, and since the capacity of the GPU's device memory is limited to the capacity of the main memory, The trend is even more pronounced when using GPUs.

The frequent pattern mining device may use the TFL strategy to test all candidate sets of intermediate levels using only the first level, i.e., F ₁ . Although the GPU has very powerful computing capabilities, such as bitwise operations, the device memory of the GPU is relatively small compared to main memory, so the frequent pattern mining device performs mining using only F ₁ . In the GPU architecture, frequency using 1-candidate set of items (n + 1) - s The test items set frequency n- entry set (i.e., F _n) used by the candidate (n + 1) a - the set of items It is much faster than testing. Copying of F _n on the GPU device memory is much larger data transmission overhead than copying F _1, and is approaching your F _n GPU memory on the device more rain than to access the F ₁ - This is why non-coalesced memory access occurs.

To mine large-scale data, a technique referred to as nested-loop streaming is proposed, which mines a new set of items on GPUs. A single series of candidate generation and testing steps is called iteration . The frequent pattern mining device can perform nested-loop streaming at each iteration. The frequent pattern mining device may perform nested loop streaming to copy information of candidate item sets to GPUs as external operands. Specifically, the frequent pattern mining device may copy the relative memory addresses of the candidate item sets into GPUs as external operands, instead of the candidate item sets themselves.

Let the candidate itemsets at level L be C _L. The frequent pattern mining device is RA (C _L ) = {RA (x) | x ∈ C _L } to the GPUs. If there is no ambiguity, RA (C _L ) may simply be denoted RA. The frequent pattern mining device may copy the first level transaction blocks, TB _{1: R} , as GPUs as internal operands. External operand RA, internal operand TB _{1: R,} or both may not fit in the GPU's device memory. Therefore, the frequent pattern mining device can partition the outer operand RA into RA _{1: Q} and copy each RA _j (1 ≤ j ≤ Q) one at a time to the GPUs. For each RA _j , a frequent pattern mining device can stream each piece of the internal operand, namely the transaction block TB _k, to the GPUs (1 ≤ k ≤ R). At most intermediate levels, the size of the outer operand RA may be much smaller than the inner operand TB. In particular, if the entire RA can be kept in the GPU memory (i.e., Q = 1), the frequent pattern mining device may stream TB _k to the GPUs.

For each pair of RA _j , TB _k , the frequent pattern mining device can calculate the partial supports of x ∈ RA _j in TB _k . Suppose that the partial supports for RA _j , TB _k are PS _{j , k} . In Definition 3, partial support of item set x is defined.

σ _x (TB _k )이 된다. Definition 3. (partial support) σ _x (TB _k ) is defined as the partial support of item set x in a given transaction block TB _k . Overall transaction bitmap TB _{1: R} in full support of the x σ (x) =

σ _x (TB _k ) .

To calculate the partial support σ _x ( TB _k ) for the item set x = {i ₁ , ..., i _n }, the frequent pattern mining device computes the bit vectors {TB _k (i) | i ∈ x} (N-1) times bitwise AND operation between the input bit vector and the resultant bit vector, and counts the number of 1s of the resultant bit vector. RA (x), so includes x address of the external memory in the memory device the TB _k of the GPU, frequent pattern mining apparatus can efficiently access to the location of the bit vectors TB _k (x). A function that applies a series of (n - 1) bitwise AND operations to an item set x is denoted by ∩ {TB _k (x)}. Further, the function for counting a first number of bits in a given vector is indicated by count (·). Then, σ _x ( TB _k ) = count (∩ {TB _k (x)}).

" TFL  algorithm( TFL  Algorithm) "

3 is a view for explaining the operation of the TFL strategy according to an embodiment.

The frequent pattern mining device can use the algorithm of the TFL strategy. Referring to Figure 3, the overall procedure of the algorithm of the TFL strategy is described. Referring to FIG. 3, an outer operand RA _{1: Q} and an inner operand TB _{1: R} are in main memory 301, and Q = 1 is assumed for convenience of explanation. A buffer for RA _j denoted RABuf and a buffer for TB _k denoted TBBuf are in the device memory 302 of the GPU. The set of candidate item sets at the current level in the item set grid is denoted C _L.

The frequent pattern mining apparatus maps each item set x in the C _L 305 to the relative memory address RA (x) using the dictionary dict 304 and outputs the C _L 305 to the RA 306 using the mapping result. . ≪ / RTI > Here, the dictionary dict 304 is a dictionary that maps the frequent 1-item set xεF ₁ of the transaction block TB _k to RA (x). If the size of the RA is larger than the size of the RABuf in the GPU's device memory, then the RA is logically divided into _Q partitions, RA _{1: Q} , and each partition can enter RABuf.

According to one embodiment, the frequency pattern mining apparatus of using the dictionary dict (304) for mapping the (303) frequency F ₁ l-set of entries in the transaction bitmap to the relative memory addresses, a candidate set of items k- C _L (305) relative memory addresses RA 306 (321). The frequent pattern mining device may identify the frequent 1-item sets contained in the candidate k-itemset and generate the relative memory addresses of the candidate k-itemsets by combining the relative memory addresses of the identified frequent 1-item sets . For example, the dictionary dict 304 may include relative memory addresses (e.g., indices) corresponding to the frequent 1-item sets 303, respectively, and the frequent pattern mining device may include dictionary dict 304 0, 1, 2} of the candidate 3-item set {A, B, C} can be generated by combining 0,

The frequent pattern mining device can copy RA _j to RABuf in a streaming manner on the PCI-E bus, and copy each TB _k to TBBuf. According to one embodiment, the frequent pattern mining device may copy each of the relative memory addresses as an outer operand to each of the device memories of the GPUs. 3, since Q = 1 and the device memory 302 is assumed to be one, the frequent pattern mining device stores relative memory addresses RA 306 as external operands into RABuf in the device memory 302 of the GPU (322).

According to one embodiment, a frequent pattern mining device may copy transaction blocks of any of the transaction blocks into the device memories of the GPUs as inner operands. Referring to FIG. 3, the frequent pattern mining apparatus can copy TB ₁ 307 among the transaction blocks to TBBuf in the device memory 302 of the GPU (323).

To store partial supports for all candidate item sets corresponding to RA 306 in each transaction block TB _k , the frequent pattern mining device maintains a two-dimensional array labeled PSArray in main memory 301 , The size of the two-dimensional array is determined by R and | RA |. Where | RA | is the number of candidate item sets. The frequent pattern mining device allocates a buffer for partial support (denoted PSBuf) in the device memory 302 of the GPU.

According to one embodiment, each GPU may calculate partial supports corresponding to each of the relative memory addresses using each of the relative memory addresses copied into the device memory and the transaction block copied into the device memory. Each GPU is computed by using the GPU kernel function -K _TFL for bitwise AND ( bitwise AND ) operations to calculate partial supports 311 corresponding to the candidate item sets 309 in RABuf, Values can be stored in PSBuf. Referring to FIG. 3, since Q = 1 and the device memory 302 is assumed to be one, the frequent pattern mining apparatus stores the transaction block 308 copied to TBBuf and the relative memory addresses 309 copied to RABuf The bit vectors 310 corresponding to the relative memory addresses 309 may be calculated 324 via the GPU. The frequent pattern mining device computes 325 partial support lines 311 corresponding to relative memory addresses 309 from bit vectors 310 corresponding to relative memory addresses 309, (311) to PSBuf (325).

According to one embodiment, a frequent pattern mining device may synchronize partial supports corresponding to relative memory addresses to update the support ratings of candidate k-item sets. 3, the frequent pattern mining apparatus first stores the partial scores calculated in the GPU cores in PSBuf in the device memory 302 of the GPU, and then stores the partial scores 311 in the PSBuf in the main memory 301 ) Copy it back to my PSArray. Here, the frequent pattern mining apparatus can copy the values for TB _k to the kth column of the PSArray. The frequent pattern mining device copies 328 the partial supports 311 written to PSBuf 326 and synchronizes the partial supports corresponding to the RA 306 based on the copied partial supports 312 ), And the supporting scores 313 of the C _L 305 can be updated.

를 얻기 위해 PSArray에서 각 항목집합 x의 부분 지지도들을 합할 수 있다(aggregate). 빈발 패턴 마이닝 장치는 지지도가 주어진 임계 값 minsup보다 크거나 같은 지지도인 빈발 L-항목집합들 F_L을 찾을 수 있다.Frequent pattern mining devices

We can aggregate the partial subsets of each item set x in the PSArray to obtain. A frequent pattern mining device is one in which the support is given a given threshold You can find frequent L-item sets F _L that are greater than or equal to minsup .

Algorithm 1 is the pseudo code of the algorithm of the TFL strategy. In the initialization phase, the frequent pattern mining device loads transaction data D into the main memory MM, assigns a PSArray to the MM, and allocates three buffers TBBuf, RABuf and PSBuf to the device memory DM of the GPU ( Lines 1-3). Then, the frequent pattern mining device uses F ₁ to convert D to a set of transaction blocks TB _{1: R} (Lines 4-5) so that each transaction block fits TBBuf. The frequent pattern mining device constructs a dictionary dict for mapping x to RA (x) (Line 6). Since the TFL strategy uses only TB _{1: R} built as input data for F ₁ , the dictionary does not change during mining of item sets. The main loop consists of a generation phase (Lines 10-11) and a test phase (Lines 12-20). The frequent pattern mining device greatly improves the performance of the testing phase by streaming the transaction blocks of F ₁ to overcome the limitations on the amount of GPU memory, while utilizing GPU computing for rapid, massive parallel computation of partial supports 12-18).

번 호출된다. 즉, TBBuf 내의 동일한 트랜잭션 블록 TB_k에 대해, 빈발 패턴 마이닝 장치는 RA_j의 부분들을 변경하는 동안 커널 함수를 반복적으로 실행한다. 데이터 복사 측면에서, RA는 외부 피연산자가 되고, TB는 내부 피연산자가 된다. 그러나 커널 함수의 호출 측면에서, TB_k는 내부 피연산자가 되고, RA_j는 외부 피연산자가 된다.A frequent pattern mining device can call the kernel function K _TFL several times instead of once (Line 16). This is because there is a limit to the number of GPU blocks that a frequent pattern mining device can determine when calling K _TFL . The K _TFL function can calculate the partial support of a single item set using a single GPU block. For example, if the number of GPU blocks, denoted by maxBlk, is set to 16K, then a single call of K _TFL can calculate partial supports for 16K item sets at once. Therefore, | RA _j | = 100M, then the K _TFL function is

Lt; / RTI > That is, for the same transaction block TB _k in TBBuf, the frequent pattern mining device iteratively executes the kernel function while changing portions of RA _j . In terms of data copying, RA becomes the outer operand and TB becomes the inner operand. However, on the invocation of the kernel function, TB _k is the inner operand, and RA _j is the outer operand.

Algorithm 2 is the pseudo code of GMiner's GPU kernel function. Algorithm 2 kernel functions can be used in HIL strategies as well as TFL strategies. RA _j , TB _k , doneIdx and maxThr are used as inputs. Here, doneIdx is the index of the last candidate previously performed in the RA _j, it is necessary to identify the RA _j portion to the current call handling _TFL K. For example, | RA _j | = 10000 and maxBlk = 1000, the doneIdx is 1000 in the second call of K _TFL . The input maxThr is the maximum number of threads in a single GPU block that can be determined when calling K _TFL , such as maxBlk. BID and TID are system variables that are automatically determined as the IDs of the current GPU block and the GPU thread, respectively. Because many GPU blocks are executing at the same time, some of them may not have corresponding candidate item sets to test. For example, | RA _j | = 100, and maxBlk = 200, then 100 GPU blocks should not perform kernel functions since there are no item sets. Thus, if the current GPU block does not have a corresponding set of items, the kernel function is immediately returned (Lines 1-2). The kernel function prepares two variables, can and sup, in the GPU's shared memory for better performance, because both variables are accessed frequently. The variable can contains the set of items for which the current GPU block BID computes the partial support, and the vector sup can be initialized to zero.

4 is a diagram for explaining a kernel function according to an embodiment.

The main loop of K _TFL performs bitwise AND operations at the same time (Lines 5-8). Under the current architecture of GPUs, a single GPU thread can efficiently perform a bit-wise AND for a single-precision width, i.e., 32 bits. That is, a single GPU block can perform bitwise AND and maxThr x 32 bits at the same time. The width of transaction block W may be much larger than maxThr x 32 bits.

번 반복한다. bitV 내 1들의 수는 소위 popCount 함수를 이용하여 쉽게 계산될 수 있고, sup 벡터에 저장될 수 있다. popCount 함수의 이름은 popc()일 수 있다. 도 4를 참조하면, 부분 지지도들은 sup 벡터에

번 누적된다. 커널 함수는 parallelReduction 함수를 이용하여, sup 내 값들을 후보 항목집합 can에 대한 TB_k 내 단일 부분 지지도로 합할 수 있다(aggregate) (Line 9).Referring to FIG. 4, an example of K _TFL is shown when maxThr = 2 and can = 0, 1, 3. For the sake of simplicity, it is assumed that the GPU thread can perform bitwise AND operation on 4 bits. Since the length of the candidate item set is 3, threads 1 and 2 perform bitwise AND operations twice on {TB (0), TB (1), TB (3)} and store the result bits in bitV . The kernel does this

Repeat times. The number of ones in bitV can easily be calculated using the so-called popCount function, and can be stored in the sup vector. The popCount function can be named popc (). Referring to FIG. 4,

Times. The kernel function can use the parallelReduction function to aggregate the values in sup into a single partial support in TB _k for the candidate item set can (Line 9).

" HIL (Hopping from Intermediate Level) strategy "

The TFL strategy described above can find all the frequent item sets for a large-scale database using only GPUs with a limited amount of GPU memory (device memory). Although the TFL strategy shows excellent performance in most cases, a strategy that exhibits good performance may be required even when the length of frequent item sets is long. A HIL (Hopping from Intermediate Level) strategy is proposed to make the performance of the test step more scalable in terms of lengths of item sets using Fragment Blocks.

" Fragments  Fragment Blocks "

5 is a view for explaining a fragment block according to an embodiment.

프래그먼트 블럭들이 있다.According to the HIL strategy, a frequent pattern mining device horizontally partition each transaction block TB _k into disjoint fragment blocks. The fragment size is defined as the number of frequent 1-itemsets belonging to a single fragment block. The fragment size is fixed and is denoted by H. Therefore, the total number of transactions within each transaction block

There are fragment blocks.

- 1의 빈발 항목집합들까지 각 프래그먼트 블록에서 구체화될 수 있다. 따라서 프래그먼트 블록의 높이는 H 대신

- 1로 설정될 수 있다.According to the HIL strategy, a frequent pattern mining device can materialize all the frequent item sets within each fragment block. Here, the specification of the item set x means to generate a bit vector for x in the corresponding fragment block. Since the fragment size is H,

- Up to 1 frequent item sets can be specified in each fragment block. Therefore, the height of the fragment block is

- 1. ≪ / RTI >

- 1의 높이를 가진다. 프래그먼트 블록은 FID로 표기된 트랜잭션 블록 내 자체 ID를 가진다. 빈발 패턴 마이닝 장치는 각 프래그먼트 블록을 메인 메모리 내 연속적으로(consecutively) 할당할 수 있다(또는 디스크 페이지와 같은 보조 저장소(secondary storage) 내 청크로 저장할 수 있다). TB_k의 l-번째 프래그먼트 블록은 TB_k,l로 표기된다. 프래그먼트 블록 TB_k,l은

- 1의 비트 벡터들로 구성되며, 이러한 비트 벡터들에 대응하는 항목집합들의 집합은 항목집합들(TB_k,l)로 표기된다. According to the HIL strategy, the frequent pattern mining device vertically and horizontally partition the transactional bitmap TB into fragments blocks, each fragment block having a width of W

- Has a height of 1. The fragment block has its own ID in the transaction block marked FID. The frequent pattern mining device can consecutively allocate each fragment block in main memory (or store it as a chunk in secondary storage, such as a disk page). L- second fragment blocks TB of _k is denoted by TB _{k, l.} The fragment blocks TB _{k, l}

- 1 bit vectors, and the set of item sets corresponding to these bit vectors is denoted by item sets TB _{k, l} .

비트 벡터들을 포함한다. 도 5에서, TB_1,2에 대응하는 항목집합들은 {{C}, {D}, {CD}}이다. HIL 전략에 따르면, 프래그먼트 블록 내 n-itemsets(n>1)의 비트 벡터들은 구체화(materialization) 전에 0들로 초기화될 수 있다.Referring to FIG. 5, a total of R x 3 fragment blocks are shown, where H = 2. According to one embodiment, a frequent pattern mining device may generate fragments 502, 503, and 504 by partitioning the frequent 1-item sets 501. The frequent pattern mining device may generate item sets 505, 506, 507, which are all combinations of the frequent 1-item sets in the fragments for each of the fragments 502, 503, 504. For example, a frequent pattern mining device may include a set of items {C}, {D}, {C, D} of all combinations of frequent 1- itemsets {C}, {D} 506). The frequent pattern mining device may calculate the bit vectors corresponding to the item sets 505, 506, 507. Herein, the transaction bitmap including the bit vectors is represented by a vertical bitmap layout, and the frequent pattern mining device vertically partition the transaction bitmap including the bit vectors, and the fragments 502, 503, 504) for each of the divided fragments to block _{TB 1,1, TB 1,2, TB 1,3} , TB R, 1, TB R, 2, TB R, 3 (509, 510, 511, 512, 513, 514). For example, the transaction block TB ₁ is divided into three fragment blocks {TB _1,1 , TB _1,2 , TB _{1, 3} }, and each fragment block

Bit vectors. In FIG. 5, the item sets corresponding to TB _1,2 are {{C}, {D}, {CD}}. According to the HIL strategy, the bit vectors of n-itemsets (n > 1) in a fragment block may be initialized to zeros before materialization.

의 공간을 필요로 한다. 중간 레벨들에서 빈발 항목집합들이 완전히 구체화(full materialization)되는 것과 비교할 때, HIL 전략에 따른 프래그먼트 블록들은 훨씬 적은 양의 메모리를 사용한다. 예를 들어, |D| = 10M 및 |F₁|=500으로 가정하자. 그런 다음, 세번째 레벨들까지의 완전한 구체화는 최대

공간을 필요로 한다. 이에 반해, HIL 전략에 따른 H=5 인 프래그먼트 블록들은

의 공간만을 필요로 한다.In terms of space complexity, the HIL strategy is a bit-by-bit basis for transactional bitmaps

. Fragmented blocks according to the HIL strategy use a much smaller amount of memory when compared to the full materialization of frequent item sets at intermediate levels. For example, | D | = 10M and | F ₁ | = 500. Then, the full elaboration to the third level

Space is needed. In contrast, H = 5 fragment blocks according to the HIL strategy

Of space.

For materialization, the frequent pattern mining device according to the HIL strategy performs frequent item set mining from 2 to H level for each of the R x S fragment blocks. As the size of the database grows, the number of fragment blocks can become very large. For fast realization of a large number of blocks, the nested-loop streaming technique described above is utilized. Since the fragment blocks are not correlated with each other, they can be specified independently.

의 프래그먼트 블록들이 스트리밍 방식으로 GPU 메모리(장치 메모리)로 전송된다. 이러한 블록들 내 항목집합들을 그것들의 상대 메모리 주소들로 매핑하기 위해, 빈발 패턴 마이닝 장치는 사전 dict을 구축한다(Lines 5-6). 그런 다음, 빈발 패턴 마이닝 장치는 F₁을 구체화할 필요가 없으므로 F_H - F₁에 대한 항목집합들만 매핑한다((Line 7). 빈발 패턴 마이닝 장치는 프래그먼트 블록들을 스트리밍하는 동안 동시에 커널 함수 K_HIL을 실행한다(Lines 9-12). 여기서, K_HIL은 기본적으로(basically) K_TFL과 동일하지만, 부분 지지도들을 계산하는 대신에 TBBuf 내 프래그먼트 블록들의 해당 위치에 비트 벡터들 bitV을 저장한다. K_HIL의 슈도 코드는 생략된다. K_HIL의 호출이 완료된 후에, 빈발 패턴 마이닝 장치는 업데이트된 프래그먼트 블록들 TB_{k,[start:end]}을 메인 메모리로 다시 복사한다. GPU 컴퓨팅을 이용한 구체화 기법은 매우 빠르므로 경과 시간(elapsed time)은 거의 무시할 수 있다.Algorithm 3 is an algorithm for specifying fragments blocks. All fragment blocks are used as inputs. First, the frequent pattern mining device calculates the maximum number of fragment blocks that can be specified at a time by using RABuf in the device memory (DM) (Line 1). Here, it is assumed that the calculated maximum number is Q. The frequent pattern mining device then executes the main loop Q times. The frequent pattern mining device can stream fragments blocks of FIDs between the start and end of all transaction blocks, FB _{1: R, begin: end} . That is,

Are transferred to the GPU memory (device memory) in a streaming manner. To map the sets of items in these blocks to their relative memory addresses, the frequent pattern mining device constructs a dictionary dict (Lines 5-6). Maps only set of items for the F ₁ ((Line 7) frequent pattern mining apparatus at the same time, the kernel function while streaming the fragment block K _HIL - then frequent pattern mining apparatus F _H does not need to materialize the F _1. (Lines 9-12), where K _HIL is basically the same as K _TFL , but instead of calculating partial supports, store the bit vectors bitV at the corresponding positions of the fragment blocks in TBBuf K pseudo code for the _HIL is omitted K after calling the _HIL is completed, the frequency pattern mining apparatus of TB _k, the updated fragment _block..: copy back a _{[start end]} to the main memory specified method using the GPU computing is very The elapsed time is almost negligible because it is fast.

" HIL  algorithm( HIL  Algorithm) "

6 is a diagram for explaining the operation of the HIL strategy according to an embodiment.

According to the HIL strategy, frequent pattern mining devices can reduce the number of bitwise AND operations by using fragment blocks, which are a kind of precomputed results. Unlike the TFL strategy, the HIL strategy dynamically determines a set of fragments at each level to reduce the amount of transactional bitmaps sent to the GPUs.

Algorithm 4 is the pseudo code of the HIL strategy. First, the frequent pattern mining device specifies the fragment blocks using algorithm 3 (Lines 1-2). The frequent pattern mining device generates candidate item sets C _L and then finds the minimum set of fragments -B, including all the item sets in C _L (Line 7). If the level L is low, most of the fragments are selected as set B, However, when the level L is large, the number of fragments including C _L is reduced, so that the frequent pattern mining apparatus can reduce the overhead of transmitting fragment blocks. Since the set of fragments at each level is changed, the relative memory addresses of the candidate item sets in C _L can also be changed. Therefore, the frequent pattern mining device constructs a dict using only itemsets in B at each level, and converts C _L into RA _{1: Q} (Lines 8-9). When streaming transactional bitmaps to GPUs, the frequent pattern mining device is responsible for the entire transaction block TB _k Instead, only the relevant fragment blocks TB _{k, l E B} can be copied.

Referring to FIG. 6, it is assumed that C _L = {{A, B, E}, {B, E, F}} 605 according to the HIL strategy. The frequent pattern mining device can easily identify fragments B = {1, 3} containing all the item sets in C _L (605) (611).

According to one embodiment, the frequent pattern mining device uses the dictionary dict 604, which maps the item sets 603 of the transaction bitmap to the relative memory addresses, to generate candidate k-item sets 605 (e.g., For example, k = 3) relative memory addresses 606 (613). For example, a frequent pattern mining device may identify item sets {A, B}, {E} included in a candidate k-itemset {A, B, E} (612). The frequent pattern mining device can generate the relative memory addresses {2, 3} of the candidate k-itemsets {A, B, E} by combining the relative memory addresses of the item sets {A, B}, {E} (613).

Referring to FIG. 6, the frequent pattern mining apparatus constructs a dictionary dict using the first and third fragments, so RA ({E}) becomes 3 instead of 6. If the item set x ∈ C _L is transformed into RA (x), the length of RA (x) according to the HIL strategy is shorter than the length of the TFL strategy. That is, fewer bitwise AND operations are required in the HIL strategy than in the TFL strategy, in order to obtain partial supports. For example, in the HIL strategy, the length of RA ({A, B, E}) is 2 (ie {2, 3}) whereas in TFL strategy the length is 3.

According to one embodiment, a frequent pattern mining device may copy each of the relative memory addresses from the main memory to each of the device memories as an external operand. Referring to FIG. 6, the frequent pattern mining device may copy 617 the relative memory addresses 606 from the main memory 601 to the device memory 602 of the GPU. According to one embodiment, a frequent pattern mining device may copy at least one fragment block of fragment blocks into each of the device memories as an internal operand. Referring to FIG. 6, the frequent pattern mining apparatus can copy the fragment blocks TB _1,1 (607), TB _1,3 (608) among the fragment blocks to the device memory 602 of the GPU (615). As described above, each RA _j is copied to the RABuf in the GPU's device memory 602, and the first set {TB _1,1 , TB _1,3 } (607, 608) of the fragment blocks in B is stored in the device And may be streamed to TBBuf in memory 602. Next time, a second set of fragment blocks {TB _2,1 , TB _{2, 3} } may be streamed. As described in the TFL strategy, each GPU according to an embodiment may calculate partial supports corresponding to respective relative memory addresses using a fragment block and respective relative memory addresses. The frequent pattern mining device can update the supports of candidate k-item sets by synchronizing partial supports corresponding to relative memory addresses. The contents related to the calculation and update of the support are redundant with those described in the TFL strategy, so the explanation is omitted.

"multiple GPU's  Exploiting Multiple GPUs ) "

7 is a diagram for explaining an operation of utilizing multiple GPUs according to an embodiment.

The frequent pattern mining device according to GMiner can improve performance by easily utilizing multiple GPUs. To use multiple GPUs, a frequent pattern mining device can copy different parts of an external operand to different GPUs and copy the same transaction (or fragments) blocks to all GPUs. This technique is called the transaction bitmap sharing technique. This technique can be applied to both TFL and HIL strategies.

Referring to FIG. 7, a data flow according to a technique using multiple GPUs is illustrated, an embodiment in which the number of GPUs is two, and the number of GPUs can be expanded. The frequent mining device can copy RA ₁ from the main memory 701 of the CPU to the device memory 702 of the GPU ₁ and copy RA ₂ to the device memory 703 of the GPU ₂ . The frequent pattern mining device can copy the same TB ₁ from the main memory 701 of the CPU to the device memory 702 of the GPU ₁ and the device memory 703 of the GPU ₂ . While the kernel function of GPU ₁ calculates the partial supports of RA ₁ , the kernel function of GPU ₂ can calculate the partial supports of RA ₂ . Since there is no common item set for RA ₁ and RA ₂ , the results of the two kernel functions can be copied back into the PSArray in main memory 701 without conflict.

이기 때문에, 빈발 패턴 마이닝 장치는 상술한 기법을 이용하여 GPU들의 수 측면에서 확장성(scalable)을 실현할 수 있다. 또한, 빈발 패턴 마이닝 장치는 상술한 기법을 이용하여 분산 및 병렬 컴퓨팅 방법들의 작업부하 불균형(workload imbalance)을 해소할 수 있다. RA_j 및 RA_k에 대한 계산량들은, 그 계산이 복잡하거나 불규칙한 데이터 구조들의 사용 없이 비트단위 AND 연산들의 수에 크게 의존하기 때문에, RA_j 및 RA_k이 서로 같은 크기를 갖는 한 비대칭이지 않다. 따라서, 사용된 데이터집합들의 특성들과 무관하게, 빈발 패턴 마이닝 장치는 다중 GPU들을 이용하여 안정적인 속도 증가율을 갖는 성능을 나타낼 수 있다.RA _j and RA _k are independent tasks,

, The frequent pattern mining apparatus can realize scalability in terms of the number of GPUs using the above-described technique. In addition, the frequent pattern mining apparatus can solve the workload imbalance of the distributed and parallel computing methods using the above-described technique. Because it largely depends on the amount of calculation for the RA RA _j and _k are, the calculated number of the complex or bitwise AND operation without the use of random data structure, the RA RA _j and _k is not the asymmetry has the same size with each other. Thus, regardless of the characteristics of the data sets used, frequent pattern mining devices can exhibit performance with a steady rate increase rate using multiple GPUs.

FIG. 8 is a diagram illustrating an exemplary configuration of a frequent pattern mining apparatus according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 8, the frequent pattern mining apparatus includes a CPU 801, a main memory 850, and GPUs 860. Here, the CPU 801 and the GPUs 860 may be different independent subjects, and the frequent pattern mining device may be implemented by the CPU 801 or the GPUs 860. [ Data transfer between the CPU 801, the main memory 850 and the GPUs 860 can be performed via the PCI-E INTERFACE.

The CPU 801 includes a loop controller 810, a streaming controller 820, a workload balancing manager 830, and a synchronization manager 840. The loop controller 810 performs operations related to loops such as the above-described nested loop streaming, and the streaming controller 820 performs operations related to the above-described streaming, and the workload balancing manager 830 performs the above- Generation of fragments blocks, and the synchronization manager 840 performs operations related to synchronization such as synchronization of the above-described supports. Main memory 850 stores bit vector data 851, relative address data 852, support data 853, and dictionary data 854. The bit vector data 851 is information related to the above-described bit vector, the relative address data 852 is information related to the relative address described above, the support data 853 is information related to the support described above, and the dictionary data 854 ) Is information related to the dictionary described above.

GPUs 860 include GPU ₁ 860a through GPU _n 860n. GPU ₁ 860a includes cores 861a and device memory 862a and GPU _n 860n includes cores 861n and device memory 862n and includes GPU ₁ 860a ) To GPU _n (860n) can calculate partial supports. The hardware depicted in FIG. 8 may perform the techniques or strategies described above, and redundant descriptions are omitted.

FIG. 9 is a flowchart for explaining a frequent pattern mining method according to an embodiment.

Referring to FIG. 9, the frequent pattern mining device may perform system initialization (901). System initialization is an initialization operation for performing the above-described TFL strategy or HIL strategy, including, for example, generating operations of transaction blocks or fragment blocks, and is described with reference to FIG.

The frequent pattern mining device may set k to 2 (902) and generate a _k -item set C _k (903). The frequent pattern mining device may determine whether C _k is present (904). For example, when the items are A and B, the frequent pattern mining device may determine that C ₃ does not exist and terminate the operation.

The frequent pattern mining apparatus can calculate the degree of support of C _k through an AND operation using the GPU (905). The above-described embodiment can be applied to the operation of calculating the degree of support of C _k , and the description will be supplemented with reference to Figs. 11 to 12.

The frequent pattern mining device may determine whether the support of C _k is greater than or equal to the minimum support (906). The frequent pattern mining device may add C _k to the frequent pattern F if the support of C _k is greater than or equal to the minimum support (907). If the frequent pattern mining apparatus is less than the minimum support of C _k , k + 1 is substituted into k (908) to generate the next set of candidate items, and the above operations can be repeated.

FIG. 10 is a flowchart illustrating system initialization according to an embodiment.

Referring to FIG. 10, the frequent pattern mining device may start an initialization operation (1001) and load transaction data (1002). The frequent pattern mining device may generate a GPU stream (1003). For example, a frequent pattern mining device may assign a stream to a GPU to process a transaction (fragment) block corresponding to a relative address. The frequent pattern mining device may allocate a buffer (1004). The above-described buffers can be allocated to the main memory of the CPU or the device memory of the GPU.

The frequent pattern mining device may scan the transaction data (1005) and generate frequent 1-item sets F ₁ (1006). Frequent pattern mining devices can mine frequent 1-item sets from transaction data.

The frequent pattern mining device may select a TFL strategy or HIL strategy (1007). If the HIL strategy is selected, the frequent pattern mining device may generate fragments from the frequent 1-item sets (1008). The frequent pattern mining device may generate item sets P (1009), which are all combinations of frequent 1-item sets in a fragment for each fragment. The frequent pattern mining device may calculate (1010) the bit vectors of P and partition the bit vectors of P into R fragment blocks (1011).

Frequent pattern mining apparatus TFL if the selected strategy, calculation, and 1012 bits in the vector F _1, F ₁ can be partitioned in the bit vector in the R block transaction 1013. The description of the contents overlapping with those described above will be omitted.

11 is a flowchart for explaining an operation of calculating the support degree according to an embodiment.

Referring to FIG. 11, the frequent pattern mining apparatus generates C _k relative memory addresses (1101) and may chunk copy the C _k relative memory addresses corresponding to the external operands to the device memories of GPUs (1102) . The frequent pattern mining device may perform an inner loop process (1103) and synchronize (1104) the partial supports copied from the GPUs. The inner loop process is a process in which the partial support is calculated by the GPU and is described below with reference to FIG. The process of FIG. 11 may be referred to as an outer loop process.

Frequent pattern mining apparatus is, to determine whether or not i is less than Q to determine whether or not approval rating part of the synchronization completion corresponding to all external memory addresses _{RA j (1 ≤ j ≤ Q} ). The frequent pattern mining device can repeat the computation and synchronization of partial support when i is smaller than Q. The frequent pattern mining device may perform step 906 if i is greater than or equal to Q. [

12 is a flowchart for explaining an operation of calculating a partial support according to an embodiment.

Referring to FIG. 12, the frequent pattern mining apparatus can copy bit vector data corresponding to an internal operand into device memories of GPUs (1201). Here, the bit vector data may be a transaction block or a fragment block described above. The frequent pattern mining device can perform a custom kernel using the GPU (1202). Here, the user defined kernel may be an operation using the above-described kernel function.

The frequent pattern mining device can copy partial supports from the device memories of the GPUs to main memory (1203). Frequent pattern mining apparatus is, to determine whether or not i is less than R in order to determine whether or not copying portions approval rating corresponding to all transactions block _{TB k (1 ≤ k ≤ R} ) to the main memory. The frequent pattern mining device can repeat the calculation and copying of partial support when i is smaller than R. The frequent pattern mining device may synchronize (1204) the GPU thread if i is greater than or equal to R. If the GPU processes all transaction blocks corresponding to one relative memory address, then the frequent pattern mining device can synchronize the threads of the GPUs for processing associated with the next relative memory address.

The embodiments described above may be implemented in hardware components, software components, and / or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, such as an array, a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described with reference to the drawings, various technical modifications and variations may be applied to those skilled in the art. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (25)

Generating blocks from bit vectors corresponding to frequent 1-item sets;
Copying different relative memory addresses of candidate k-item sets, respectively, from the main memory of a central processing unit (CPU) to each of the device memories of GPUs (graphic processing units);
Copying at least one identical block from the main memory to each of the device memories, each of the at least one identical block required for calculating the votes of the candidate k-itemsets of the blocks; And
Updating the scores of the candidate k-item sets by synchronizing partial scores calculated by the GPUs
Containing
Frequent pattern mining methods.
The method according to claim 1,
The step of copying each of the different relative memory addresses
Copying the relative memory address of the first candidate k-item set to the device memory of the first GPU; And
Copying the relative memory address of the second candidate k-item set to the device memory of the second GPU
Lt; / RTI >
Wherein copying each of the at least one identical block comprises:
Copying a first one of the blocks to a device memory of the first GPU; And
Copying the first block to the device memory of the second GPU
/ RTI >
Frequent pattern mining methods.
The method according to claim 1,
Generating transaction blocks by vertically partitioning a transaction bitmap comprising the bit vectors, the transaction bitmap being represented by a vertical bitmap layout,
Further comprising:
Wherein the blocks are transaction blocks,
Frequent pattern mining methods.
The method of claim 3,
The step of copying each of the different relative memory addresses
Generating relative memory addresses of the candidate k-item sets using a dictionary mapping a frequent 1-item set of the transaction bitmap to a relative memory address; And
Copying each of the generated relative memory addresses as an outer operand to each of the device memories
/ RTI >
Frequent pattern mining methods.
5. The method of claim 4,
The step of generating the relative memory addresses
Identifying the frequent 1-item sets included in the candidate k-itemset; And
Combining the relative memory addresses of the identified frequent 1-item sets to generate a relative memory address of the candidate k-
/ RTI >
Frequent pattern mining methods.
5. The method of claim 4,
Wherein copying each of the at least one identical block comprises:
Copying any one of the transaction blocks as an inner operand into each of the device memories
Lt; / RTI >
The step of updating the supports
Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the transaction block and the respective relative memory addresses; And
And updating the supports of the candidate k-item sets by synchronizing the partial supports corresponding to the relative memory addresses
/ RTI >
Frequent pattern mining methods.
The method according to claim 1,
Dividing the frequent 1-item sets into fragments;
Generating item sets that are all combinations of the frequent 1-item sets in the fragments for each of the fragments;
Calculating bit vectors corresponding to the generated item sets; And
Vertically partitioning a transaction bitmap including the calculated bit vectors, the transaction bitmap being represented by a vertical bitmap layout, and generating fragment blocks by dividing the transaction bitmap into the fragments step
Further comprising:
Wherein the blocks are the fragment blocks,
Frequent pattern mining methods.
8. The method of claim 7,
The step of copying each of the different relative memory addresses
Generating relative memory addresses of the candidate k-item sets using a dictionary mapping an item set of the transaction bitmap to a relative memory address; And
Copying each of the relative memory addresses as an outer operand to each of the device memories
/ RTI >
Frequent pattern mining methods.
9. The method of claim 8,
The step of generating the relative memory addresses
Identifying sets of items included in the candidate k-itemset; And
Combining the relative memory addresses of the identified set of items to generate a relative memory address of the candidate k-
/ RTI >
Frequent pattern mining methods.
9. The method of claim 8,
Wherein copying each of the at least one identical block comprises:
Copying at least one fragment block of the fragment blocks into each of the device memories as an inner operand
Lt; / RTI >
The step of updating the supports
Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the fragment block and the respective relative memory addresses; And
And updating the supports of the candidate k-item sets by synchronizing the partial supports corresponding to the relative memory addresses
/ RTI >
Frequent pattern mining methods.
Mining the frequent 1-item sets from the transaction data;
A transaction bitmap containing bit vectors corresponding to the frequent 1-item sets, the transaction bitmap being represented by a vertical bitmap layout, to vertically partition transaction blocks step;
Using GPUs, calculating support ratings of candidate k-item sets from the transaction blocks; And
Based on these ratings, mining the frequent k-item sets
Containing
Frequent pattern mining methods.
12. The method of claim 11,
The step of calculating the supports
Generating relative memory addresses of the candidate k-item sets using a dictionary mapping a frequent 1-item set of the transaction bitmap to a relative memory address;
Copying each of the relative memory addresses as an outer operand into each of the device memories of the GPUs;
Copying any one of the transaction blocks as an inner operand into each of the device memories;
Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the transaction block and the respective relative memory addresses; And
And synchronizing the partial scores to update the scores of the candidate k-itemsets
/ RTI >
Frequent pattern mining methods.
13. The method of claim 12,
The step of calculating the supports
Copying the second transaction block into each of the device memories as an inner operand;
Each of the GPUs calculating second partial supports corresponding to the respective relative memory addresses using the second transaction block and the respective relative memory addresses; And
And synchronizing the second partial scores to update the scores of the candidate k-itemsets
≪ / RTI >
Frequent pattern mining methods.
Mining the frequent 1-item sets from the transaction data;
Dividing the frequent 1-item sets into fragments;
Generating item sets that are all combinations of the frequent 1-item sets in the fragments for each of the fragments;
Calculating bit vectors corresponding to the generated item sets;
Vertically partitioning a transaction bitmap including the calculated bit vectors, the transaction bitmap being represented by a vertical bitmap layout, and generating fragment blocks by dividing the transaction bitmap into the fragments step;
Calculating, using GPUs, the scores of the candidate k-itemsets from the fragment blocks; And
Based on these ratings, mining the frequent k-item sets
Containing
Frequent pattern mining methods.
15. The method of claim 14,
The step of calculating the supports
Generating relative memory addresses of the candidate k-item sets using a dictionary mapping an item set of the transaction bitmap to a relative memory address;
Copying each of the relative memory addresses as an outer operand into each of the device memories of the GPUs;
Copying at least one fragment block of the fragment blocks into each of the device memories as an inner operand;
Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the fragment block and the respective relative memory addresses; And
And synchronizing the partial scores to update the scores of the candidate k-itemsets
/ RTI >
Frequent pattern mining methods.
16. The method of claim 15,
The step of calculating the supports
Copying at least one second fragment block into each of the device memories as an inner operand;
Each of the GPUs calculating second partial degrees of support corresponding to the respective relative memory addresses using the second fragment block and the respective relative memory addresses; And
And synchronizing the second partial scores to update the scores of the candidate k-itemsets
≪ / RTI >
Frequent pattern mining methods.
Mining the frequent 1-item sets from the transaction data;
Selecting a TFL (Traversal from the First Level) strategy or a HIL (Hopping from Intermediate Level) strategy;
Generating blocks from the bit vectors corresponding to the frequent 1-item sets based on the selected strategy;
Using the GPUs, calculating support ratings of candidate k-item sets from the blocks; And
Based on these ratings, mining the frequent k-item sets
Containing
Frequent pattern mining methods.
18. The method of claim 17,
The step of generating the blocks
If the TFL strategy is selected, creating transaction blocks by vertically partitioning a transaction bitmap comprising the bit vectors, the transaction bitmap being represented by a vertical bitmap layout
/ RTI >
Frequent pattern mining methods.
19. The method of claim 18,
The step of calculating the supports
Generating relative memory addresses of the candidate k-item sets using a dictionary mapping a frequent 1-item set of the transaction bitmap to a relative memory address;
Copying each of the relative memory addresses as an outer operand into each of the device memories of the GPUs;
Copying any one of the transaction blocks as an inner operand into each of the device memories;
Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the transaction block and the respective relative memory addresses; And
And synchronizing the partial scores to update the scores of the candidate k-itemsets
/ RTI >
Frequent pattern mining methods.
20. The method of claim 19,
The step of calculating the supports
Copying the second transaction block into each of the device memories as an inner operand;
Each of the GPUs calculating second partial supports corresponding to the respective relative memory addresses using the second transaction block and the respective relative memory addresses; And
And synchronizing the second partial scores to update the scores of the candidate k-itemsets
≪ / RTI >
Frequent pattern mining methods.
18. The method of claim 17,
The step of generating the blocks
If the HIL strategy is selected, fragmenting the frequent 1- item sets to generate fragments;
Generating item sets that are all combinations of the frequent 1-item sets in the fragments for each of the fragments;
Calculating bit vectors corresponding to the generated item sets;
Vertically partitioning a transaction bitmap including the calculated bit vectors, the transaction bitmap being represented by a vertical bitmap layout, and generating fragment blocks by dividing the transaction bitmap into the fragments step
/ RTI >
Frequent pattern mining methods.
22. The method of claim 21,
The step of calculating the supports
Generating relative memory addresses of the candidate k-item sets using a dictionary mapping an item set of the transaction bitmap to a relative memory address;
Copying each of the relative memory addresses as an outer operand into each of the device memories of the GPUs;
Copying at least one fragment block of the fragment blocks into each of the device memories as an inner operand;
Each of the GPUs calculating partial supports corresponding to the respective relative memory addresses using the fragment block and the respective relative memory addresses; And
And synchronizing the partial scores to update the scores of the candidate k-itemsets
/ RTI >
Frequent pattern mining methods.
23. The method of claim 22,
The step of calculating the supports
Copying at least one second fragment block into each of the device memories as an inner operand;
Each of the GPUs calculating second partial degrees of support corresponding to the respective relative memory addresses using the second fragment block and the respective relative memory addresses; And
And synchronizing the second partial scores to update the scores of the candidate k-itemsets
≪ / RTI >
Frequent pattern mining methods.
23. A computer program stored on a recording medium for executing the method of any one of claims 1 to 23 in combination with hardware.
A CPU; And
Main memory
Lt; / RTI >
The CPU
Generates blocks from bit vectors corresponding to frequent 1-item sets,
Copy each of the different relative memory addresses of the candidate k-itemsets from the main memory to each of the device memories of the GPUs,
Copying at least one identical block from each of the main memories to each of the device memories, the at least one identical block necessary for calculating the scores of the candidate k-
And updating the scores of the candidate k-item sets by synchronizing partial scores calculated by the GPUs
Frequent pattern mining device.

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