KR20180117463A - Data processing apparatus and data processing method - Google Patents

Abstract

The present invention relates to a data processing apparatus for appropriately arranging file data to prevent position competition with other data in a cache. According to the present invention, the data processing apparatus comprises: a cache divided into a plurality of zones; a nonvolatile memory including a plurality of block groups including a plurality of blocks corresponding to the plurality of zones; and a processor allocating at least one block corresponding to any one of the plurality of zones to the data and storing the data in the nonvolatile memory.

Description

TECHNICAL FIELD [0001] The present invention relates to a data processing apparatus and a data processing method,

The present disclosure relates to a data processing apparatus and a data processing method.

A single-core or multicore processor has cache memory, and the processor keeps the data referenced from memory in the cache. A single-core or multicore processor can run multiple programs (processes) concurrently, and the operating system and multiple processes compete to take up cache memory during execution.

Recently, core architectures have been widely used, and in such systems, multicore cores share the last level cache (LLC). In this multiprocessor environment, when several processes are executed at the same time, since the lowest level cache is shared, the processes start interfering with data fetched from the memory into the cache.

That is, the data fetched into the cache compete with each other for an arbitrary position in the cache. Thus, processes compete to occupy the lowest level cache and cause cache pollution.

Recently, a nonvolatile memory is used as a storage medium, and a file system of an operating system records information in units of files in a nonvolatile memory similarly to an HDD or an SSD. File data stored in nonvolatile memory is loaded into a specific location in the cache, competing to occupy cache space with other data, and causing cache pollution.

Embodiments are intended to properly arrange file data to prevent location conflicts with other data in the cache.

And, the embodiments are for preventing cache pollution.

A data processing apparatus according to an embodiment of the present invention includes: a cache divided into a plurality of zones; a nonvolatile memory including a plurality of block groups including a plurality of blocks corresponding to a plurality of zones; And a processor for allocating at least one block to store the data in the nonvolatile memory.

Wherein the plurality of blocks includes at least one physical memory address, the physical memory address corresponds to any one of a plurality of colors corresponding to the plurality of zones, and each of the plurality of blocks includes physical memory addresses corresponding to the same color In this case, each of the plurality of block groups includes blocks corresponding to each of the plurality of sequential color groups, and blocks corresponding to each of the plurality of sequential color groups may be n blocks corresponding to sequential n colors.

The processor may designate at least one color of the sequential n colors for the data.

The processor may assign a free block corresponding to at least one color to data if there is a free block corresponding to at least one color in the plurality of block groups.

The processor may redirect at least one of the colors except for at least one of the sequential n colors to the data if there is no free block corresponding to the at least one color in the plurality of block groups.

When the free block corresponding to at least one color in the plurality of block groups is exhausted by the free block allocation, the processor further specifies at least one of the colors excluding at least one of the sequential n colors .

A data processing method according to an embodiment of the present invention includes a cache divided into a plurality of zones, a nonvolatile memory including a plurality of block groups including a plurality of blocks corresponding to a plurality of zones, and a plurality of cores The method comprising the steps of: allocating at least one block corresponding to one of a plurality of zones to data; and storing the data in at least one block.

Wherein the plurality of blocks includes at least one physical memory address, the physical memory address corresponds to any one of a plurality of colors corresponding to the plurality of zones, and each of the plurality of blocks includes physical memory addresses corresponding to the same color In this case, each of the plurality of block groups includes blocks corresponding to each of the plurality of sequential color groups, and blocks corresponding to each of the plurality of sequential color groups may be n blocks corresponding to sequential n colors.

The step of assigning at least one color of the sequential n colors to the data prior to the step of allocating at least one block.

Wherein the step of allocating at least one block corresponding to one of the plurality of zones to data includes the step of, if there is a free block corresponding to at least one color in the plurality of block groups, For example.

Wherein the step of allocating at least one block corresponding to one of the plurality of zones to data includes the step of, if there is no free block corresponding to at least one color in the plurality of block groups, And re-designating at least one of the colors with respect to the data.

Wherein the step of allocating at least one block corresponding to any one of the plurality of zones to the data comprises the steps of, when preblocks corresponding to at least one color in the plurality of block groups are exhausted by preblock allocation, And further designating at least one of the colors excluding at least one color of the colors for the data.

By each of the different processes, the step of fetching the data may further comprise the step of bringing the data into a section in the cache corresponding to the block in which the data is stored.

A data processing apparatus according to an embodiment includes a nonvolatile memory including a plurality of block groups including a plurality of blocks, a processor including a plurality of cores for driving a process of fetching data stored in the nonvolatile memory into the cache on a block- Wherein each of the plurality of blocks corresponds to one of a plurality of colors corresponding to the plurality of zones, each of the plurality of block groups includes blocks corresponding to each of the plurality of the sequential color groups, The blocks corresponding to the respective n color blocks are n blocks corresponding to the sequential n colors, and the processor allocates the input data to the consecutive blocks corresponding to the sequential m colors included in any one of the plurality of sequential color groups do.

According to embodiments, cache pollution can be reduced.

According to embodiments, the performance of the process can be increased.

1 is a block diagram schematically showing a data processing apparatus according to an embodiment.
2 is a block diagram specifically showing a part of the configuration of the data processing apparatus shown in FIG.
3 is a diagram showing an example of assigning a color to an arbitrary physical memory address.
4 is a flowchart showing a data processing method according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

Also, throughout the specification, when an element is referred to as "including" an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise.

1 is a block diagram schematically showing a data processing apparatus according to an embodiment. As shown, the data processing apparatus includes a processor 110 and a memory 120.

The processor 110 includes a plurality of cores 112a-112d and a cache 114. [ For example, the processor 110 may drive an operating system or an application program to control a plurality of hardware or software components connected to the processor 110, and may perform various data processing and operations.

The processor 110 may be implemented as a SoC (system on chip). For example, the processor 110 may include one or more of a central processing unit (CPU), an application processor (AP), or a communication processor (CP).

The processor 110 may perform operations or data processing relating to control and / or communication of at least one other component of the computing device. For example, the processor 110 may refer to a generic-purpose processor capable of executing the operations by executing one or more software programs stored in the memory 120. [

When the data processing apparatus includes a plurality of cores 112a-112d, the plurality of cores may each drive a process. Each core 112a-112d may process a program, such as data stored in memory 120 or cache 114. [

The cache 114 is a high-speed storage device in the form of a buffer for storing instructions or data read from the memory 120. [ Such a cache 114 may be installed between the processor 110 and the memory 120 and is also referred to as a cache memory or a local memory.

The cache 114 has a relatively small memory capacity compared to the memory 120, but is accessible at a higher speed than the memory 120. [ Thus, if the processor 110 needs instructions or data, it can first access the cache 114, rather than the memory 120.

The cache 114 is an area in which data and program instructions frequently accessed by a process are stored for immediate use without repeatedly searching. Multicore cores in multicore systems share the lowest level cache (LLC). This lowest level cache is the shared highest level cache (which may be an L3 cache in certain embodiments) that is called before accessing memory 120. [

In a multiprocessor environment, when multiple processes are running at the same time, the processes may interfere with the data cached between the processes because they share the shared cache 114. Thus, the processes compete to occupy the shared cache 114 and cause cache pollution.

The memory 120 may be configured in units of blocks including a plurality of physical memory addresses. In the following description, the memory 120 may be a flash memory, a phase-change RAM (PRAM), a magnetic RAM, an RRAM, a ferroelectric RAM (FRAM), a one time programmable ROM (OTPROM) ROM), erasable and programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), mask ROM, flash ROM, hard drive, or a solid state drive However, the technical spirit of the present invention can be applied to other memory devices by a person having ordinary skill in the art to which the present invention belongs.

The processor 110 is configured to communicate with the memory 120 via a memory interface. The memory interface is capable of communicating commands, addresses, and data with memory 120 via input / output channels. The memory interface may communicate control signals to the memory 120 via a control channel.

Meanwhile, the file system executed in the processor 100 divides the memory 120 into blocks (or page units) and manages the blocks. The file system creates a file or allocates an unused free block to a file when the file is expanded. In a direct-mapped or set-associative cache, the location in the cache 114 occupied by the file data is determined by the address of the file data, particularly the physical memory address, on the memory 120.

Next, data fetch between the memory 120 and the cache 114 will be described with reference to FIG.

2 is a block diagram specifically showing a part of the configuration of the data processing apparatus shown in FIG.

The cache 114 may be shared by a plurality of cores and may be sliced into a plurality of zones S1-S4. Each of the plurality of zones S1-S4 may be independently accessed by the core to reduce latency and increase parallelism.

The memory 120 includes a plurality of block groups BG0 to BGk. And, each of the plurality of block groups may include a plurality of blocks (e.g., pages). One block (for example, BLK0) includes a plurality of physical memory addresses ADD0 to ADDi-1. In the following, it is assumed that the size of one block is 4 KB.

Each physical memory address ADD0-ADDi-1 may correspond to any one color. For example, each physical memory address (ADD0-ADDi-1) may be assigned a color according to some bits of the physical memory address. Here, the color can be represented by a color bit.

For example, the upper bits of some of the bits representing the block number may be designated with color bits that are shared with the cache 114. As another example, the processor 110 may calculate the color bit of the block using the bits representing the block number of the block. This will be described together with reference to FIG.

3 is a diagram showing an example of assigning a color to a physical memory address ADD0. As shown, one physical memory address ADD0 may include a plurality of bits (e.g., 64 bits).

When using a 4KB block, the block number of the physical memory address ADD0 may be bits a63a62 ... a13a12. (A) and h2 (a) corresponding to each of the plurality of zones S1-S4 of the cache 114 are extracted from the hash functions H1 and H2 by extracting any of the block number bits, Lt; / RTI >

The bits h1 (a) and h2 (a) can be calculated by the following equations (1) and (2) by the hash functions H1 and H2.

May be fetched into the area in cache 114 corresponding to bits h1 (a), h2 (a) if the data stored in that physical memory address ADD0 is fetched into cache 114. [

The color bit of the physical memory address ADD0 may be determined as h2 (a) h1 (a) a16a15a14a13a12. That is, 7 bits of color bits can be determined by concatenating the bits h1 (a) and h2 (a) generated by the five bits a16-a12 and the hash functions H1 and H2.

On the other hand, when a 32 KB block is used, the block number of the physical memory address ADD0 may be bits a63a62 ... a16a15. In this case, the color bit of the physical memory address ADD0 may be determined as h2 (a) h1 (a) a16a15. That is, the 4 bits of color bits can be determined by connecting the bits h1 (a) and h2 (a) generated by the two bits a16-a15 and the hash functions H1 and H2.

Since one block includes a plurality of physical memory addresses, one block may contain physical memory addresses corresponding to one color, or physical memory addresses corresponding to various colors. However, for convenience of explanation, it is assumed that one block includes a plurality of physical memory addresses corresponding to one color.

If any two blocks BLK0 and BLKi + 32 correspond to the same area SO in cache 114 and are more likely to compete to occupy the space in cache 114 than other blocks in the cache 114, Two blocks (BLK0, BLKi + 32) can be defined as having the same color. Other blocks with a low degree of competition at the same time have different colors from the blocks BLK0 and BLKi + 32. In this way, different colors can be allocated to the blocks constituting the memory 120. FIG.

As in the example of FIG. 3 above, when using a block of 4 KB size, 128 (= 27) colors can be defined by 7 bits of color bits. One block corresponds to one color, and between some successive blocks, h2 (a) and h1 (a) are the same.

For example, if the block BLKj has the color C32 by the value of the 5-bit color bit a16a15a14a13a12, the block BLKj + 1 has the color C33 according to the block number increase. The block BLK + 30 and the block BLK + 31 also have a color C62 and a color C63, respectively. This is because h2 (a) and h1 (a) are the same for blocks BLKj + 1 to BLKj + 31 and only a16a15a14a13a12 is different for blocks BLKj + 1 to BLKj + 31. However, the color of the block BLKj + 32 can not be predicted because h2 (a) and h1 (a) may differ between the block BLKj + 31 and the block BLKj + 32.

That is, in the 7-bit color bits, h2 (a) and h1 (a) determined by the hash function can be changed in units of 32 consecutive blocks, but are the same in 32 consecutive blocks.

For example, h2 (a) and h1 (a) among 7 bits are all the same in 32 consecutive blocks. The values of the 5-bit color bits a16-a12 except for h2 (a) and h1 (a) in 7 bits are different from each other within 32 consecutive blocks. By the value of the different color bits, 32 consecutive blocks have sequential colors.

These sequential colors are referred to as sequential color groups (SCG0, SCG1, SCG2, SCG3). The sequential color groups SCG0, SCG1, SCG2, and SCG3 may be changed into 32 consecutive block units within one block group BG0.

That is, if the same colors appear repeatedly between different physically consecutive blocks, they are referred to as a Sequential Color Group.

For example, if physically contiguous blocks BLK0-BLK31 have a color of C0 to C31 and another physically contiguous blocks BLKi + 32-BLKi + 63 have a color of C0 to C31, (C0-C31) correspond to a sequential color group.

2, in memory 120, successive blocks BLK0-BLK31 correspond to sequential colors C0-C31 included in sequential color group SCG0, respectively, The blocks BLK32 to BLK63 correspond to the sequential colors C96 to C127 included in the sequential color group SCG3 and the sequential blocks BLK64 to BLK95 correspond to the sequential colors included in the sequential color group SCG1, And the successive blocks BLK96-BLK127 correspond to the sequential colors C64-C95 included in the sequential color group SCG2, respectively.

On the other hand, when using a 32 KB block, 16 (= 24) colors can be defined by 4 bits of color bits. One block corresponds to one color, and between some successive blocks, h2 (a) and h1 (a) are the same.

That is, in the 4-bit color bits, h2 (a) and h1 (a) determined by the hash function can be changed in units of four consecutive blocks, but they are the same in four consecutive blocks.

For example, h2 (a) and h1 (a) of the four bits are all equal in the four consecutive blocks. The values of the 2-bit color bits a16a15 except for h2 (a) and h1 (a) in 4 bits are different from each other in four consecutive blocks. By the value of the different color bits, the four consecutive blocks have sequential colors.

The blocks in the same sequential color group in memory 120 may be the same in cache 114 within fetched cache 114. Therefore, the blocks included in the same sequential color group compete for the same area in the cache 114. [

For example, it is assumed that each process is performed on the data stored in the blocks BLK0 to BLK31 included in the sequential color group SCG0 in the block group BG0 and the data stored in the blocks BLK0 to BLK31 included in the sequential color group SCG0 in the block group BGk, (BLKj + 32-BLKj + 63), the data stored in each of the blocks may compete in the same area S0 of the cache 114.

Similarly, the data stored in the blocks included in each sequential color group SCG1 included in the different blocks BG1-BGk may compete for the same segment S1 of the cache 114. The data stored in the blocks included in the respective sequential color groups SCG2 included in the different blocks BG1 to BGk may compete for the same area S2 of the cache 114. [ The data stored in the blocks included in the respective sequential color groups SCG3 included in the different blocks BG1 to BGk may compete for the same area S3 of the cache 114. [

When the processor 110 allocates consecutive blocks in the memory 120 to one file, one file may be stored in blocks corresponding to several sequential color groups. Then, if one process invoking the file is performed, the file may be fetched into multiple zones in the cache 114, which may cause cache pollution.

Next, a data processing method according to an embodiment of the present invention will be described with reference to FIG.

4 is a flowchart showing a data processing method according to an embodiment.

First, the processor 110 designates at least one color in a sequential color group (S100) for a file when data (hereinafter, referred to as a file) is stored in the memory 120. [

For example, the processor 110 may specify for the file at least one color of the colors C0-S31 in the sequential color group SCG0. Or the processor 110 may specify for the file at least one color of the colors C0-S31 in the sequential color group SCG0. It is to be appreciated that, in the present embodiment, successive colors (C0, C1, C2) are designated for a file for convenience, but the colors may not necessarily be continuous.

The processor 110 searches for a free block corresponding to the designated color in the block group (S110) and determines whether there is a free block (S120). A free block may refer to a block in which no data or command is stored. At this time, the processor 110 may search for all of the block groups, the free block corresponding to the designated color.

For example, the processor 110 may search for a free block corresponding to a specified color (e.g., C0, C1, C2) within a block group BG0. If the pre-block corresponding to the designated color (C0, C1, C2) in the block group BG0 is not retrieved, the processor 110 can search for the pre-block corresponding to the specified color for other block groups.

When the free block is searched in the block group, the processor 110 allocates the searched free block to the file (S130).

For example, when the prefetch blocks BLK0, BLK1, and BLK2 corresponding to the designated colors C0, C1, and C2 are retrieved in the block group BG0, the processor 110 reads the free blocks BLK0, BLK1, Can be assigned to a file. In addition, the processor 110 may search for other block groups and also allocate the free blocks corresponding to the designated color (C0, C1, C2) to a file.

The processor 110 determines whether the free block is exhausted in all the block groups (S140).

If a free block is not found in all the block groups, or if the free block is exhausted in all the block groups by block allocation, the processor 110 assigns at least one other color to the file (S150).

In step S120, if no block corresponding to the designated color is found in all the block groups, the processor 110 can re-assign the file to the other colors in the sequential color group including the color specified in step S100 . Or processor 110 may redirect the file to colors in other sequential color groups other than the sequential color group containing the color specified in step S100.

For example, if the block corresponding to the specified color (C0-C2) of the sequential color group (SCG0) is not retrieved in all the block groups (BG0-BGk) Lt; RTI ID = 0.0 > (C3-C31) < / RTI > Or the processor 110 determines whether the block corresponding to the designated color C0-C2 of the sequential color group SCG0 is not retrieved in all of the block groups BG0-BGk, the sequential color groups SCG1-SCG3, The color of at least one of the colors C32-S127 in the file can be specified for the file.

Also, in step S140, if the free block is exhausted in all the block groups, the processor 110 can further specify to the file other colors in the sequential color group designated in step S100. Or the processor 110 may further specify in the file the colors in the sequential color groups other than the sequential color group specified in step S100.

For example, when the block corresponding to the designated color (C0-C2) of the sequential color group (SCG0) is exhausted in all the block groups (BG0-BGk) And further specify at least one color of the other colors C3-C31 for the file. Or the processor 110 determines whether the block corresponding to the designated color C0-C2 of the sequential color group SCG0 is exhausted in all of the block groups BG0-BGk, At least one color of the colors C32-S127 may be designated for the file.

According to the data processing apparatus and the data processing method according to the embodiment, data can be stored in the memory 120 so that it can be fetched into one area in the cache 114. [ If multiple data are fetched into the cache 114 by several processes, then each piece of data may not be contending for other areas of the cache 114 with other data.

That is, the data processing apparatus and the data processing method according to the embodiment can reduce cache pollution and increase the performance of the process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute one or more software applications that are executed on an operating system (OS) and an operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing apparatus may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer readable medium may include program instructions, data files, data structures, and the like, alone or in combination. Program instructions to be recorded on the medium may be those specially designed and constructed for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Claims (14)

A cache divided into a plurality of zones,
A nonvolatile memory including a plurality of block groups including a plurality of blocks corresponding to the plurality of zones,
A processor for allocating at least one block corresponding to one of the plurality of zones to data and storing the data in a nonvolatile memory,
To the data processing apparatus. The method according to claim 1,
The plurality of blocks including at least one physical memory address,
Wherein the physical memory address corresponds to any one of a plurality of colors corresponding to the plurality of zones,
Wherein each of the plurality of block groups includes blocks corresponding to each of the plurality of sequential color groups and each of the plurality of sequential color groups corresponding to each of the plurality of sequential color groups Blocks are n blocks corresponding to sequential n colors,
Data processing device. 3. The method of claim 2,
Wherein the processor specifies at least one color of the sequential n colors for the data,
Data processing device. The method of claim 3,
Wherein the processor allocates a free block corresponding to the at least one color to the data if there is a free block corresponding to the at least one color in the plurality of block groups,
Data processing device. 5. The method of claim 4,
Wherein the processor is configured to re-designate at least one of the colors of the sequential n colors excluding the at least one color for the data if there is no free block corresponding to the at least one color in the plurality of block groups doing,
Data processing device. 5. The method of claim 4,
Wherein when the preblock corresponding to the at least one color in the plurality of block groups is exhausted by the preblock allocation, at least one of the colors of the sequential n colors excluding the at least one color Lt; RTI ID = 0.0 > a < / RTI >
Data processing device. A processor including a processor including a cache separated into a plurality of zones, a nonvolatile memory including a plurality of block groups including a plurality of blocks corresponding to the plurality of zones, and a plurality of cores driving different processes In the processing apparatus,
Assigning to the data at least one block corresponding to any of the plurality of zones, and
Storing the data in the at least one block
/ RTI > 8. The method of claim 7,
The plurality of blocks including at least one physical memory address,
Wherein the physical memory address corresponds to any one of a plurality of colors corresponding to the plurality of zones,
Wherein each of the plurality of block groups includes blocks corresponding to each of the plurality of sequential color groups and each of the plurality of sequential color groups corresponding to each of the plurality of sequential color groups Blocks are n blocks corresponding to sequential n colors,
Data processing method. 9. The method of claim 8,
Prior to allocating the at least one block,
Designating at least one of the sequential n colors for the data
Further comprising the steps of: 10. The method of claim 9,
Wherein the step of allocating at least one block corresponding to any one of the plurality of zones to the data comprises:
And allocating a free block corresponding to the at least one color to the data if a free block corresponding to the at least one color exists in the plurality of block groups.
Data processing method. 11. The method of claim 10,
Wherein the step of allocating at least one block corresponding to any one of the plurality of zones to the data comprises:
If there is no free block corresponding to the at least one color in the plurality of block groups, redesignating at least one of the colors of the sequential n colors excluding the at least one color for the data Further included,
Data processing method. 11. The method of claim 10,
Wherein the step of allocating at least one block corresponding to any one of the plurality of zones to the data comprises:
Wherein when the preblock corresponding to the at least one color in the plurality of block groups is exhausted by the preblock allocation, at least one of the colors excluding the at least one color among the sequential n colors, Lt; RTI ID = 0.0 > further < / RTI >
Data processing method. 8. The method of claim 7,
Further comprising, by each of the different processes, fetching the data into a section in the cache corresponding to a block in which the data is stored.
Data processing method. A nonvolatile memory including a plurality of block groups including a plurality of blocks,
A processor that includes a plurality of cores that drives a process of fetching data stored in the non-volatile memory into a cache on a block-
Lt; / RTI >
Wherein each of the plurality of blocks corresponds to any one of a plurality of colors corresponding to the plurality of zones, each of the plurality of block groups includes blocks corresponding to each of the plurality of sequential color groups, The blocks corresponding to each of which are n blocks corresponding to sequential n colors,
Wherein the processor assigns input data to consecutive blocks corresponding to sequential m colors included in any one of the plurality of sequential color groups,
Data processing device.

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