KR20180091143A - Nonvolatile memory device, method of erasing data in the same and electronic system including the same - Google Patents

Abstract

The present invention provides a nonvolatile memory device capable of rapidly performing a data erasing operation. The nonvolatile memory device comprises a substrate, a charge storage region, a channel region, a tunneling insulating layer, a gate structure and a potential applying structure. The charge storage region is formed on the substrate. The channel region is adjacently formed to the charge storage region. The tunneling insulating layer is formed between the charge storage region and the channel region. The gate structure heats the charge storage region. The potential applying structure applies a potential to the channel region. The nonvolatile memory device applies joule heat above a predetermined temperature to the charge storage region by using the gate structure, applies a positive potential above a predetermined potential to the channel region by using the potential applying structure, and performs the data erasing operation emitting at least one charge stored in the charge storage region.

Description

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile memory device, a data erasing method thereof, and an electronic system including the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a memory device, and more particularly, to a non-volatile memory device, a method for erasing data of the non-volatile memory device, and an electronic system including the non-volatile memory device.

The memory device may be divided into a volatile memory device and a nonvolatile memory device depending on whether the stored data is lost when the power supply is interrupted. A non-volatile memory device of a NAND type in a nonvolatile memory device is a device that stores or emits electrons in a charge trapping layer using field emission (Fowler-Nordheim tunneling) Can be written or erased. When such an existing method is used, the time required for the data erase operation may be much longer than the time required for the data write operation, thereby deteriorating the overall performance of the electronic system including the nonvolatile memory element.

It is an object of the present invention to provide a nonvolatile memory device capable of quickly performing a data erase operation.

It is another object of the present invention to provide a method for erasing data in the nonvolatile memory device.

Still another object of the present invention is to provide an electronic system including the nonvolatile memory element.

In order to accomplish the above object, a nonvolatile memory device according to embodiments of the present invention includes a substrate, a charge storage region, a channel region, a tunneling insulation layer, a gate structure, and a potential application structure. The charge storage region is formed on the substrate. The channel region is formed adjacent to the charge storage region. The tunneling insulation layer is formed between the charge storage region and the channel region. The gate structure heats the charge storage region. The potential applying structure applies a potential to the channel region. Applying a Joule heat above a reference temperature to the charge storage region using the gate structure and applying a positive potential above a reference potential to the channel region using the potential application structure, And performs a data erase operation to emit at least one charge.

In one embodiment, when the row of columns is applied to the charge storage region, the at least one charge stored in the charge storage region may be emitted into the channel region through the energy barrier by the tunneling insulation layer .

In one embodiment, when the positive potential is applied to the channel region, the potential difference between the charge storage region and the channel region increases, and the at least one charge stored in the charge storage region is injected into the tunneling insulation layer The number and speed of passage through the energy barrier due to < / RTI >

In one embodiment, when the row of columns is applied to the charge storage region, the row of columns is applied to the tunneling insulation layer adjacent to the charge storage region, and the tunneling insulation layer is self-annealed self-annealing) so that the data retention time and characteristic deterioration can be prevented.

In one embodiment, the gate structure may comprise a connecting electrode, a first gate electrode and a second gate electrode. The connection electrode may be formed adjacent to the charge storage region. The first gate electrode may be connected to the first end of the connection electrode. The second gate electrode may be connected to the second end of the connection electrode. Applying a first potential to the first gate electrode and applying a second potential different from the first potential to the second gate electrode to induce a current flowing along the connection electrode, .

In one embodiment, when viewed in plan, the width of the connecting electrode may be narrower than the width of the first and second gate electrodes.

In one embodiment, the potential applying structure may include a source region and a drain region. The source region may be connected to the first end of the channel region. The drain region may be connected to a second end of the channel region. The positive potential may be applied to at least one of the source region and the drain region to apply a positive potential to the channel region.

In one embodiment, when viewed in plan, the width of the channel region may be narrower than the width of the source region and the drain region.

In one embodiment, the channel region, the source region, and the drain region may be formed of the same material.

In one embodiment, the non-volatile memory device may further include a first support region and a second support region. The first support region may be formed between the substrate and the source region. The second support region may be formed between the substrate and the drain region. The channel region, the source region, and the drain region may all be formed on the substrate. The channel region may be formed in a nanowire structure. The tunneling insulator layer, the charge storage region, and the gate structure may be formed to sequentially surround the first portion of the channel region. An empty space may be present between the substrate and a second portion of the channel region other than the first portion.

In one embodiment, the channel region may be formed of one of a planar structure, a fin structure, and a nano sheet structure.

In one embodiment, the non-volatile memory device may further include a control insulating layer. The control insulating layer may be formed between the charge storage region and the gate structure.

In one embodiment, the charge storage region is formed of a material selected from the group consisting of polysilicon, amorphous silicon, metal oxide, silicon nitride, silicon nano-crystal, And materials having nanocrystals.

In one embodiment, the channel region may be formed of silicon, germanium, silicon-germanium, strained silicon, strained germanium, strained silicon-germanium, And silicon on insulator (SOI).

In one embodiment, the tunneling insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

According to another aspect of the present invention, there is provided a method of erasing data in a nonvolatile memory device, the method comprising: a charge storage region; a channel region formed adjacent to the charge storage region; A gate structure for heating the storage region, and a potential applying structure for applying potential to the channel region. Using the gate structure, Joule heat above a reference temperature is applied to the charge storage region to release at least one charge stored in the charge storage region. And a potential higher than the reference potential is applied to the channel region using the potential applying structure.

In one embodiment, the non-volatile memory device may further include a tunneling insulation layer formed between the charge storage region and the channel region. When the row of columns is applied to the charge storage region, the at least one charge stored in the charge storage region may be emitted into the channel region through the energy barrier by the tunneling insulation layer.

In one embodiment, the non-volatile memory device may further include a tunneling insulation layer formed between the charge storage region and the channel region. Wherein a potential difference between the charge storage region and the channel region increases when the positive potential is applied to the channel region and the at least one charge stored in the charge storage region passes through an energy barrier by the tunneling insulation layer The number and speed of passage can be increased.

In one embodiment, when the row of columns is applied to the charge storage region, the row of columns is applied to the tunneling insulation layer adjacent to the charge storage region, and the tunneling insulation layer is self-annealed self-annealing) so that the data retention time and characteristic deterioration can be prevented.

According to another aspect of the present invention, there is provided an electronic system including a processor and a nonvolatile memory device. The non-volatile memory device stores data processed by the processor. The non-volatile memory device includes a substrate, a charge storage region, a channel region, a tunneling insulation layer, a gate structure, and a potential application structure. The charge storage region is formed on the substrate. The channel region is formed adjacent to the charge storage region. The tunneling insulation layer is formed between the charge storage region and the channel region. The gate structure heats the charge storage region. The potential applying structure applies a potential to the channel region. Applying a Joule heat above a reference temperature to the charge storage region using the gate structure and applying a positive potential above a reference potential to the channel region using the potential application structure, And performs a data erase operation to emit at least one charge.

The nonvolatile memory device according to embodiments of the present invention performs a data erase operation using a thermal electron emission phenomenon accompanied by an electric field. Specifically, a row of columns is applied to the charge storage region using a gate structure, and a potential is applied to the channel region using a potential application structure. Therefore, the electric field formed between the channel region and the charge storage region can further improve the speed, performance and efficiency of the data erase operation with relatively low power consumption. In addition, the tunneling insulating layer can be self-annealed by the row of columns, so that the data retention time and property degradation can be prevented.

1 is a perspective view showing a nonvolatile memory device according to embodiments of the present invention.
2 is a plan view showing the nonvolatile memory device of FIG.
3 is a cross-sectional view taken along line II 'of FIG.
4 is a cross-sectional view taken along line II-II 'of FIG.
5A and 5B are diagrams for explaining a data erase operation of a nonvolatile memory device according to embodiments of the present invention.
6A and 6B are views showing a nonvolatile memory device according to embodiments of the present invention.
7A and 7B are diagrams for explaining the performance of the data erase operation of the nonvolatile memory device according to the embodiments of the present invention.
8 is a cross-sectional view illustrating a nonvolatile memory device according to embodiments of the present invention.
9 is a flowchart illustrating a data erasing method of a nonvolatile memory device according to embodiments of the present invention.
10 is a block diagram illustrating an electronic system including a non-volatile memory device in accordance with embodiments of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a perspective view showing a nonvolatile memory device according to embodiments of the present invention. 2 is a plan view showing the nonvolatile memory device of FIG. 3 is a cross-sectional view taken along line I-I 'of FIG. 4 is a cross-sectional view taken along line II-II 'of FIG.

In this specification, a non-volatile memory device is a NAND (NAND) memory device that divides a memory state into a 1 and a 0 state in such a manner as to store and discharge a charge (e.g., electrons) in a charge trapping layer. Type non-volatile memory device. Hereinafter, embodiments of the present invention will be described, focusing on NAND type nonvolatile memory elements, but embodiments of the present invention can be applied to various types of nonvolatile memory elements.

1, 2, 3 and 4, a non-volatile memory device 10 includes a substrate 110, a charge storage region 120, a channel region 130, a tunneling insulating layer 140, (150) and a potential application structure (160). The nonvolatile memory element 10 may further include a first insulating layer 115, a control insulating layer 145, a first supporting region 172 and a second supporting region 174. [ 1 to 4 show one memory cell included in the nonvolatile memory element.

As the substrate 110, a semiconductor substrate including, for example, single-crystalline silicon or single-crystalline germanium may be used.

The first insulating layer 115 may be formed on the substrate 110. 1, all of the components of the non-volatile memory device 10, i.e., the charge storage region 120, the channel region 130, the tunneling insulating layer 140, the gate structure 150, The first insulating layer 115 may be formed on the substrate 110 and the first insulating layer 115 may be formed on the substrate 110. [ And the constituent elements.

A charge storage region (120) is formed on the substrate (110). For example, charge storage region 120 may be formed of polysilicon, amorphous silicon, metal oxide, silicon nitride, silicon nano-crystal, and metal Oxide nanocrystals, and materials having oxide nanocrystals. The charge storage region 120 may be referred to as a floating gate.

The channel region 130 is formed adjacent to the charge storage region 120. For example, the channel region 130 may be formed of silicon, germanium, silicon-germanium, strained silicon, strained germanium, strained silicon-germanium And a silicon on insulator (SOI). Also, the channel region 130 may include at least one of the Group III-V semiconductor materials.

A tunneling insulating layer 140 is formed between the charge storage region 120 and the channel region 130. The tunneling insulating layer 140 may isolate the charge storage region 120 and the channel region 130 from each other. For example, the tunneling insulating layer 140 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In addition, the tunneling insulating layer 140 may be formed to include at least one of any insulating materials that do not exhibit memory characteristics, to prevent the charge stored in the charge storage region 120 from being released into the channel region 130 May be formed that includes at least one of any materials having a relatively high energy gap serving as the exciton.

The gate structure 150 heats the charge storage region 120. For example, the gate structure 150 may be formed adjacent to the charge storage region 120 to allow heating of the charge storage region 120, and may include two (i. E. And may include a plurality of electrodes as described above.

In one embodiment, the gate structure 150 may include a connecting electrode 152, a first gate electrode 154, and a second gate electrode 156. The connection electrode 152 may be formed adjacent to the charge storage region 120 and may be formed to surround the charge storage region 120. The first gate electrode 154 may be connected to the first end of the connection electrode 152. The second gate electrode 156 may be connected to the second end of the connection electrode 152. 2, the width W2 of the connecting electrode 152 is greater than the width W1 of the first and second gate electrodes 154 and 156 when the substrate 110 is viewed in plan view. And in this case, the generation of joule heat (HT) by the current IH may be more easily generated.

In one embodiment, the gate structure 150 may be formed comprising at least one of doped polysilicon, metal, and metal silicide. In addition, the gate structure 150 may be formed to include at least one of any materials having a relatively low resistivity so as to consume relatively low energy (or power) to generate relatively high heat. For example, the connection electrode 152, the first gate electrode 154, and the second gate electrode 156 may be formed of substantially the same material.

The potential application structure 160 applies a potential to the channel region 130. For example, the potential applying structure 160 may be formed directly connected to the channel region 130 so as to apply a potential to the channel region 130.

In one embodiment, the potential application structure 160 may include a source region 162 and a drain region 164. The source region 162 may be coupled to the first end of the channel region 130. Drain region 164 may be coupled to the second end of the channel region 130. [ In other words, the channel region 130 may be formed between the source region 162 and the drain region 164. 2, the width W4 of the channel region 130 may be narrower than the width W3 of the source and drain regions 162 and 164 when viewed in plan from the substrate 110 have.

In one embodiment, the channel region 130, the source region 162, and the drain region 164 may be formed of substantially the same material. For example, a doping process such as ion implantation is performed using the same n-type impurity in order to fabricate a non-junction device having no junction at the same time while using a plurality of carriers as electrons, A channel region 130, a source region 162, and a drain region 164 including a material can be formed.

The control insulating layer 145 may be formed between the charge storage region 120 and the gate structure 150 (e.g., the connection electrode 152). The control insulating layer 145 may isolate the charge storage region 120 and the gate structure 150 from each other. For example, similar to the tunneling insulating layer 140, the control insulating layer 145 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, or any insulating material that does not exhibit memory properties Or the like.

In one embodiment, the thickness of the control insulating layer 145 may be greater than the thickness of the tunneling insulating layer 140.

A first support region 172 may be formed between the substrate 110 and the source region 162 and may support the source region 162. A second support region 174 may be formed between the substrate 110 and the drain region 164 and may support the drain region 164.

1, the channel region 130, the source region 162, and the drain region 164 may all be formed on the substrate 110. In this case, For example, the channel region 130 may be formed in a nanowire structure. In this case, as shown in FIGS. 3 and 4, the tunneling insulating layer 140, the charge storage region 120, the control insulating layer 145, and the gate structure 150 (e.g., the connection electrode 152) May be formed to sequentially surround a portion of the channel region 130 (e.g., a first portion) and may be formed to surround the remaining portion of the channel region 130 (e.g., the second portion except for the first portion) There may be an empty space between the substrates 110. In other words, the channel region 130 may be supported by the components 140, 120, 145, 150 and floated on the substrate 110. 4, the height H2 of the channel region 130 may be lower than the height H1 of the gate structure 150 when the substrate 110 is viewed in cross section.

The nonvolatile memory element 10 according to the embodiments of the present invention can use at least one charge stored in the charge storage region 120 (for example, (The points in the charge storage region 120 shown in Figures 3 and 4).

More specifically, in the nonvolatile memory device 10 according to the embodiments of the present invention, the gate structure 150 is used to apply a row string HT of a reference temperature or more to the charge storage region 120, And performs an operation. 2, a first electric potential V1 is applied to the first gate electrode 154 and a second electric potential V2 different from the first electric potential V1 is applied to the second gate electrode 156. For example, The current IH exceeding the reference current flowing along the connection electrode 152 can be induced for a very short time by the potential difference between the first and second gate electrodes 154 and 156, (HT) can be instantaneously generated. As described above, since the gate structure 150 (for example, the connection electrode 152) is formed adjacent to the charge storage region 120 and surrounding the charge storage region 120, The column HT can be applied. In this case, the at least one charge stored in the charge storage region 120 by the thermal electron emission phenomenon may be emitted to the channel region 130 through the energy barrier by the tunneling insulation layer 140 .

In the nonvolatile memory device 10 according to the embodiments of the present invention, while applying a row string HT to the charge storage region 120 (e.g., applying a row string HT to the charge storage region 120 ) And applies the positive potential VP above the reference potential to the channel region 130 using the potential applying structure 160 to perform the data erase operation. For example, by applying a positive potential VP to at least one of the source region 162 and the drain region 164, a positive potential VP can be applied to the channel region 130, May have a potential greater than 0V (i.e., V _CH > 0V). In this case, the potential difference between the charge storage region 120 and the channel region 130 may increase, and thus the number and speed of the charge passing through the energy barrier by the tunneling insulator layer 140 may increase . In other words, the positive potential VP applied to the channel region 130 can form an electric field between the channel region 130 and the charge storage region 120, and the electric field is thermally The excited charges can more effectively contribute to the passage of the energy barrier by the tunneling insulating layer 140. [ Therefore, the speed of the data erase operation can be increased, the erasing time required for the data erase operation can be reduced, and the performance of the data erase operation even if a relatively small row line (HT) And efficiency can be improved.

In one embodiment, in the nonvolatile memory element 10 according to the embodiments of the present invention, as the row line HT is applied to the charge storage region 120 to perform the data erase operation, the charge storage region Annealing or self-healing may be applied to the tunneling insulation layer 140 adjacent to the tunneling insulation layer 140 by the string line HT, the data retention time can be reduced and characteristic degradation can be prevented. Generally, as the data write (program) / erase operation is repeated in the nonvolatile memory device, the characteristics of the tunneling insulating layer may deteriorate and the data retention time may be reduced. In the nonvolatile memory device 10 according to the embodiments of the present invention, the film quality of the tunneling insulating layer 140 can be improved by the string of lines (HT) generated for the data erase operation, And deterioration of characteristics can be prevented.

There has been a problem that the speed of the data erase operation is excessively slower than the speed of the data write operation in the case of writing or erasing data using field emission (Fowler-Nordheim tunneling) in a conventional nonvolatile memory device.

In the nonvolatile memory device 10 according to the embodiments of the present invention, by applying the row line HT to the charge storage region 120 using the gate structure 150, the speed and efficiency of the data erase operation can be improved . However, when only the line string HT is used, since a relatively high current is required, power consumption increases, electromigration phenomenon occurs, and thermal interference between adjacent cells increases. Therefore, In a non-volatile memory device 10 according to embodiments, a string of lines HT is applied to the charge storage area 120 and a reference (e.g., substantially simultaneously) And a positive potential VP above the potential is applied to the channel region 130. [ Therefore, by the electric field formed between the channel region 130 and the charge storage region 120, the speed, performance, and efficiency of the data erase operation can be further improved with relatively low power consumption. In addition, the tunneling insulating layer 140 can be self-annealed by the row string HT, so that the data retention time and property degradation can be prevented.

According to the embodiment, the gate structure 150 can further perform the same operation as the gate electrode included in the general nonvolatile memory element. For example, a program voltage may be applied to the gate structure 150 to perform a data write operation, and a read voltage may be applied to the gate structure 150 to perform a data read operation.

Although the gate structure 150 heats the charge storage region 120 and the source and drain electrodes 162 and 164 apply a potential to the channel region 130 with reference to Figures 1-4, The non-volatile memory device according to embodiments may further include a heating structure implemented separately from the gate structure 150 and for heating the charge storage region 120 and may include source and drain electrodes 162 and 164, And may further include a potential application structure for implementing the potential to the channel region 130 separately.

Although the current IH is shown flowing in the first direction from the first gate electrode 154 to the second gate electrode 156 in FIGS. 2 and 4, the current IH flowing through the first and second potentials V1 and V2 Depending on the size, the current may flow along the second direction from the second gate electrode 156 to the first gate electrode 154. Further, according to the embodiment, the direction of the current can be changed in accordance with the number of times of performing the data erase operation. For example, the current can flow along the first direction when the number of times of performing the data erase operation is 1 to N (N is a natural number of 2 or more), and the number of times of performing the data erase operation is (N + 1) times to (2 * N) times, the current may flow along the second direction.

2, a positive potential VP is applied to the source region 162, but the positive potential may be applied to the drain region 164 and the source and drain regions 162 and 164 may be applied according to the embodiment. The positive potential may be applied to all of them.

Although not shown, the nonvolatile memory device 10 may further include a voltage generator that generates a first potential V1, a second potential V2, a positive potential VP, and the like according to an embodiment.

5A and 5B are diagrams for explaining a data erase operation of a nonvolatile memory device according to embodiments of the present invention.

Figure 5a is not applied with the positive potential (VP) to give heat applied only (HT) and the channel region 130 to the charge storage region 120 in the nonvolatile memory device 10 of Figure 1 (i.e., V _CH = (E. G., Electrons) in the case of a voltage of 0 V). 5B is an energy diagram showing the emission of charges when a row of columns HT is applied to the charge storage region 120 and a positive potential VP is applied to the channel region 130 (i.e., V _CH > 0V) to be. In Figures 5A and 5B, CH, TIL, CTL, CIL and GE represent the channel region 130, tunneling isolation layer 140, charge storage region 120, control isolation layer 145 and gate structure 150).

5A, electrons stored in the charge storage region CTL (e.g., points in the charge storage region CTL shown in FIG. 5A) cause the charge storage region CTL to be in the channel region CH. And the energy band of the charge storage region CTL on the energy diagram may be located above the energy bands of the channel region CH and the gate structure GE .

In this situation, when the row line HT is applied to the charge storage region CTL using the gate structure GE, electrons trapped in the charge storage region CTL can be thermally excited, Emission of thermal electrons can occur due to the built-in potential effect caused by the relatively low potential of the region CTL. At this time, the thermal electrons may be emitted to the channel region CH along the first discharge path E1 or to the gate structure GE along the second discharge path E2, for example, the control insulating layer The number of thermoelectrons emitted to the channel region CH along the first emission path E1 may be relatively large when the thickness of the tunneling insulation layer TIL is thicker than the thickness of the tunneling insulation layer TIL.

5B, the energy band of the charge storage region CTL is located above the energy band of the channel region CH and the energy band of the gate structure GE, The emission of the thermal electrons can be substantially the same as that described above with reference to Fig. 5A.

In this situation, when a positive potential (VP in Fig. 1) is applied to the channel region CH using the potential applying structure 160 in Fig. 1, the potential difference between the charge storage region CTL and the channel region CH increases can do. 5B, the energy band of the channel region CH may be located relatively below the charge storage region CTL and the channel region CH in the example of FIG. 5B. In other words, The slope? 'Indicating the potential difference between the charge storage region CTL and the channel region CH in FIG. 5A may be larger than the slope? Indicating the potential difference between the charge storage region CTL and the channel region CH in FIG. Accordingly, in the example of FIG. 5B, the number and the emission rate of the thermal electrons emitted to the channel region CH along the first emission path E1 'can be increased as compared with the example of FIG. 5A.

On the other hand, in the example of Fig. 5B, almost no thermal electrons are emitted along the path corresponding to the second emission path E2 of Fig. 5A.

6A and 6B are views showing a nonvolatile memory device according to embodiments of the present invention.

6A and 6B show a nonvolatile memory device actually fabricated according to the embodiments of the present invention. 6A is a scanning electron microscope (SEM) photograph corresponding to FIG. 1, and FIG. 6B is a transmission electron microscope (TEM) photograph corresponding to FIG.

Referring to FIG. 6A, a current 104 flows due to a potential difference between the gate electrodes 100 and 101 included in the gate structure, and the column current generated by the current 104 is a main factor of the column electron emission do. Further, the potential of the channel region is greater than 0 V by the potential applied to at least one of the source and drain regions 102 and 103 (105), so that an electric field is formed between the channel region and the charge storage region , The electric field applied thereby contributes to more efficiently the electrons thermally excited through the row heat to pass through the energy barrier of the tunneling insulating film.

6B, a tunneling insulating layer 201, a charge storage region 202, a control insulating layer 203, and a gate structure 200 are sequentially formed to surround the channel region 204.

7A and 7B are diagrams for explaining the performance of the data erase operation of the nonvolatile memory device according to the embodiments of the present invention.

7A is a graph showing a change in threshold voltage (V _T ) due to a data write or erase operation. FIG. 7B is a table showing specific conditions of each case in FIG. 7A. FIG. The data in Figs. 7A and 7B are actually measured values obtained from actually fabricated non-volatile memory elements (for example, non-volatile memory elements in Figs. 6A and 6B).

7A and 7B, CASE1 indicates a case where a data write operation is performed, CASE2-1 and CASE2-3 indicate a case where a data erase operation is performed using only a thermal electron emission phenomenon without an electric field, and CASE2- 2 shows a case where a data erase operation is performed using a thermal electron emission phenomenon accompanied by an electric field according to embodiments of the present invention. In Figure 7b, V _TE denotes a potential difference between the gate electrodes (100, 101), I _TE denotes a current (104), V _CH represents the potential 105 of the channel region (204), t _TE is data indicates the time of the erase operation (i.e., I _TE and / or the application time of the V _CH), ΔV _T represents an amount of change in threshold voltage (V _T) due to the execution of the data erase operation, TEMP is the charge storage area (202 ). ≪ / RTI >

6A, 6B, 7A, and 7B, electrons are stored in the charge storage region 202 as a program voltage is applied to the gate electrodes 100 and 101, thereby increasing the threshold voltage V _T. Such a state, such as CASE1, may be referred to as a programmed state.

An indicator for determining the programmed state / erased state in a NAND type nonvolatile memory device is a threshold voltage (V _T ). In case of CASE2-1 in which the data erase operation is performed using only the thermal electron emission phenomenon, the amount of change (V _T ) of the threshold voltage (V _T ) is about 0.3V. In CASE2-1 the case of the remaining conditions are all the same and accompanied by an electric field the data erase operation is performed CASE2-2, the amount of change in threshold voltage (V _T) (ΔV _T) is about 3.1 at least about 10 times the CASE2-1 V. Accordingly, it can be seen that the performance and efficiency of the data erase operation are improved when the data erase operation is performed using the thermal electron emission phenomenon accompanied by the electric field according to the embodiments of the present invention.

In the case of CASE 2-3 in which the data erasing operation is performed using only the thermal electron emission phenomenon so that the performance and efficiency of the data erasing operation are the same as that of CASE2-2, the power consumption is increased by about 2.5 times and the required temperature is increased by about 2 times . In the case where the data erase operation is performed using only the thermal electron emission phenomenon, if the generated heat is too high, thermal interference between adjacent cells may occur. Therefore, when performing the data erase operation using the thermal electron emission phenomenon accompanied by the electric field according to the embodiments of the present invention, it is possible to implement a data erase operation with the same performance and efficiency with relatively low power consumption and low heat , It can be effective not only in terms of power consumption but also in terms of heat interference.

8 is a cross-sectional view illustrating a nonvolatile memory device according to embodiments of the present invention.

8, a non-volatile memory device 20 includes a substrate 210, a charge storage region 220, a channel region 230, a tunneling isolation layer 240, a gate structure 250, and a potential application structure do. The non-volatile memory device 20 may further include a control insulating layer 245, a source region 262, a drain region 264, and a spacer 280. 8 shows one memory cell included in the nonvolatile memory element.

8, a charge storage region 220, a tunneling insulating layer 240, a gate structure 250, a control insulating layer 245, and a spacer 280 may be formed on the substrate 210, A channel region 230, a source region 262, and a drain region 264 may be formed in the substrate. The substrate 210, the charge storage region 220, the channel region 230, the tunneling insulation layer 240, the gate structure 250, the control insulation layer 245, the source region 262, and the drain region (not shown) 264 are formed on the substrate 110, the charge storage region 120, the channel region 130, the tunneling insulation layer 140, the gate structure 150, the control insulation layer 145, the source region 162, Drain regions 164, and redundant explanations for the respective constituent elements are omitted.

A charge storage region 220 is formed on the substrate 210. The channel region 230 is formed adjacent to the charge storage region 220. A tunneling insulating layer 240 is formed between the charge storage region 220 and the channel region 230. The gate structure 250 heats the charge storage region 220. For example, as discussed above with reference to FIGS. 1-4, the gate structure 250 may be implemented with two or more electrodes to generate current for heating. A control insulating layer 245 may be formed between the charge storage region 220 and the gate structure 250. The spacer 280 may be shorted between the components (e.g., 220, 240, 245, 250) on the substrate 210 and the components (e.g., 262, 264) (E. G., 220, 240, 245, 250) on the substrate 210 to maintain the shape of the components.

In one embodiment, the channel region 230 may be formed of a different material from the source region 262 and the drain region 264. For example, a p-type semiconductor substrate is provided and a doping process such as ion implantation is performed using n-type impurities in order to fabricate a device having a plurality of carriers as electrons while having a pn junction. A channel region 230 including the same material can be formed and a source region 262 and a drain region 264 including a material different from the channel region 230 can be formed.

8, the channel region 230, the source region 262, and the drain region 264 may all be formed in the substrate 210. In this case, For example, the channel region 230 may be formed in a planar structure. In this case, the channel region 230 may be formed on the substrate 210 between the source region 262 and the drain region 264.

A non-volatile memory device 20 according to embodiments of the present invention may include at least one non-volatile memory device (not shown) that discharges at least one charge stored in charge storage area 220 (e.g., the dots in charge storage area 220 shown in FIG. 8) When a data erase operation is to be performed, a thermal electron emission phenomenon accompanying an electric field is used. Specifically, the gate structure 250 is used to apply a row of columns HT having a reference temperature or more to the charge storage region 220, and simultaneously, a positive potential above the reference potential is applied to the channel region 230 using the potential application structure. The performance and efficiency of the data erase operation can be improved even if relatively small power consumption and line string HT are used. 8, since the channel region 230 is formed in the substrate 210, the channel region 230 can have a potential greater than 0 V by applying the positive potential directly to the substrate 210 (that is, , V _CH > 0V). In other words, in the example of FIG. 8, the substrate 210 may itself serve as the potential applying structure.

In an embodiment, when the row erase (HT) is applied to the charge storage region 220 as the data erase operation is performed, a row string HT is applied to the tunneling insulating layer 240, The tunneling insulating layer 240 may be self-annealed or self-healed by the tunneling oxide (HT) to reduce data retention time and deterioration of characteristics.

According to an embodiment, the gate structure 250 may further perform the same operation as a general gate electrode. Depending on the embodiment, the non-volatile memory device may further include a heating structure that is implemented separately from the gate structure 250, and may further include a potential application structure that is implemented separately from the substrate 210.

1 to 4 and 8, an example has been described in which the channel region included in the non-volatile memory device is formed of the nanowire structure and the planar structure. However, the channel region included in the non-volatile memory device according to the embodiments of the present invention The structure may be formed of one of various structures such as a vertical fin structure, a nano sheet structure, a vertical or horizontal type nanowire structure, and the like.

1 to 4 and 8, an example of one memory cell included in the non-volatile memory device has been described. However, the non-volatile memory device according to the embodiments of the present invention may have a plurality of memory cells arranged in a planar structure, A structure in which the planar structure is laminated, or a three-dimensional laminated structure. The planar structure is a structure in which the plurality of memory cells are formed in a two-dimensional array on one substrate, and the structure in which the planar structures are stacked is formed by stacking substrates formed according to the planar structure And the three-dimensional laminated structure shows a structure in which the plurality of memory cells are formed in a three-dimensional array on one substrate.

9 is a flowchart illustrating a data erasing method of a nonvolatile memory device according to embodiments of the present invention.

Referring to FIGS. 1 and 9, in a method of erasing data in a non-volatile memory device according to embodiments of the present invention, a non-volatile memory device 10 includes a charge storage region 120, a charge storage region 120, A gate structure 150 that heats the charge storage region 120 and a potential application structure 160 that applies a potential to the channel region 130. The charge storage region 120 may include a channel region 130, And a tunneling insulation layer 140 formed between the channel region 130 and the tunneling insulation layer 140.

The gate structure 150 is used to apply a row of columns HT over the reference temperature to the charge storage region 120 to release at least one charge stored in the charge storage region 120 at step S100. The at least one charge stored in the charge storage region 120 passes through the energy barrier by the tunneling insulation layer 140 to form a channel region 130 ). ≪ / RTI > For example, the gate structure 150 may be formed adjacent to the charge storage region 120 to allow heating of the charge storage region 120, and may include two (i. E. Or more electrodes.

The potential application structure 160 is used to apply a positive potential VP above the reference potential to the channel region 130 while applying the string of lines HT to the charge storage region 120 (e.g., substantially simultaneously) (Step S200). The potential difference between the charge storage region 120 and the channel region 130 increases when a positive potential VP is applied to the channel region 130 and the potential difference between the charge storage region 120 and the channel region 130 increases, The number of charges and the passing speed can be increased. For example, the potential applying structure 160 may be formed directly connected to the channel region 130 to apply a potential to the channel region 130, and the source region 162 and the drain region 164 may be formed . In another example, as shown in Fig. 8, the substrate 210 may itself serve as the potential applying structure.

In one embodiment, when a row of lines HT is applied to the charge storage area 120, a row of lines HT may be applied together with the tunneling insulation layer 140 adjacent to the charge storage area 120, The tunneling insulating layer 140 can be self-annealed or self-healed by the line string HT, so that the data retention time and characteristic deterioration can be prevented.

Meanwhile, the data erasing method of the non-volatile memory device according to the embodiments of the present invention may be implemented in the form of a product or the like including computer-readable program code stored in a computer-readable medium. The computer readable program code may be provided to the processor of the various computers or other data processing apparatus via a reading device. The computer-readable medium may be a computer-readable signal medium or a computer-readable recording medium. The computer-readable recording medium may be any type of medium that can store or contain programs in or on the instruction execution system, equipment or apparatus.

10 is a block diagram illustrating an electronic system including a non-volatile memory device in accordance with embodiments of the present invention.

10, electronic system 1000 includes a processor 1010 and a non-volatile memory element 1040. The electronic system 1000 may further include a communication unit 1020, a volatile memory device 1030, a user interface 1050, and a power supply unit 1060.

The processor 1010 controls the overall operation of the electronic system 1000. For example, the processor 1010 may execute various computing functions, such as certain calculations or tasks. For example, the processor 1010 may be any processor, such as a central processing unit (CPU), a microprocessor, an application processor (AP), and the like.

Volatile memory element 1030 and non-volatile memory element 1040 store data processed by processor 1010. [ For example, the non-volatile memory element 1040 may be a non-volatile memory element according to embodiments of the present invention, and may perform a data erase operation utilizing a thermal electron emission phenomenon accompanied by an electric field, The performance and efficiency of the data erase operation can be improved even if power and row heat are utilized. In addition, the tunneling insulating layer can be self-annealed or self-healed by the string of lines, so that the data retention time and characteristic deterioration can be prevented.

Volatile memory 1030 may include any volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like. In one embodiment, non-volatile memory element 1040 may comprise any non-volatile memory, such as a NAND flash memory or the like.

The communication unit 1020 can perform communication with an external device. For example, the communication unit 1020 may be a universal serial bus (USB) communication, an Ethernet communication, a near field communication (NFC), a radio frequency identification (RFID) (Mobile Telecommunication), memory card communication, and the like. For example, the communication unit 1020 may include a baseband chipset, and may support communication such as GSM, GPRS, WCDMA, and HSxPA.

The user interface 1050 may include one or more input devices such as a keypad, buttons, microphones, touch screens, and / or one or more output devices such as speakers, display devices, and the like. Power supply 1060 may supply the operating voltage of mobile system 1000.

In one embodiment, the electronic system 1000 may be a mobile phone, a smart phone, a tablet PC, a laptop computer, a personal digital assistant (PDA) , A portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, and the like , A personal computer (PC), a server computer, a workstation, a digital television, a set-top box, and the like. The mobile device may be a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a Virtual Reality (VR) device, an Augmented Reality A device, an e-book, and the like.

And can be applied to various apparatuses and systems including the nonvolatile memory element of the present invention. Therefore, the present invention can be applied to mobile phones, smart phones, PDAs, PMPs, digital cameras, camcorders, PCs, server computers, workstations, laptops, digital TVs, It can be usefully used in various electronic devices such as devices, VR devices, AR devices, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. It will be understood.

Claims (20)

Board;
A charge storage region formed on the substrate;
A channel region formed adjacent to the charge storage region;
A tunneling insulation layer formed between the charge storage region and the channel region;
A gate structure for heating the charge storage region; And
And a potential applying structure for applying a potential to the channel region,
Applying a Joule heat above a reference temperature to the charge storage region using the gate structure and applying a positive potential above a reference potential to the channel region using the potential application structure, And performs a data erase operation to emit at least one charge. The method according to claim 1,
Wherein the at least one charge stored in the charge storage region passes through an energy barrier by the tunneling insulation layer and is released to the channel region when the row of columns is applied to the charge storage region. device. The method according to claim 1,
Wherein a potential difference between the charge storage region and the channel region increases when the positive potential is applied to the channel region and the at least one charge stored in the charge storage region passes through an energy barrier by the tunneling insulation layer And the number of the nonvolatile memory elements increases and the passing speed increases. The method according to claim 1,
When the row of columns is applied to the charge storage region, the row of columns is applied to the tunneling insulation layer adjacent to the charge storage region, and the tunneling insulation layer is self-annealed by the row of columns Wherein a reduction in data retention time and deterioration in characteristics are prevented. 2. The device of claim 1,
A connection electrode formed adjacent to the charge storage region;
A first gate electrode connected to a first end of the connection electrode; And
And a second gate electrode connected to a second end of the connection electrode,
Applying a first potential to the first gate electrode and applying a second potential different from the first potential to the second gate electrode to induce a current flowing along the connection electrode, Wherein the nonvolatile memory element is a nonvolatile memory element. 6. The method of claim 5,
Wherein a width of the connecting electrode is narrower than a width of the first and second gate electrodes when the substrate is viewed in a plane. The apparatus of claim 1, wherein the potential applying structure comprises:
A source region coupled to a first end of the channel region; And
And a drain region coupled to a second end of the channel region,
And the positive potential is applied to at least one of the source region and the drain region to apply a positive potential to the channel region. 8. The method of claim 7,
Wherein a width of the channel region is narrower than a width of the source region and the drain region when the substrate is viewed in a plane. 8. The method of claim 7,
Wherein the channel region, the source region, and the drain region are formed of the same material. 8. The method of claim 7,
A first support region formed between the substrate and the source region; And
And a second support region formed between the substrate and the drain region,
The channel region, the source region, and the drain region are all formed on the substrate,
The channel region is formed in a nanowire structure,
Wherein the tunneling insulator layer, the charge storage region, and the gate structure are formed to sequentially surround a first portion of the channel region,
Wherein a void is present between the substrate and a second portion of the channel region other than the first portion. The method according to claim 1,
Wherein the channel region is formed of one of a planar structure, a fin structure, and a nano sheet structure. The method according to claim 1,
And a control insulating layer formed between the charge storage region and the gate structure. The method according to claim 1,
The charge storage region may comprise at least one material selected from the group consisting of polysilicon, amorphous silicon, metal oxide, silicon nitride, silicon nano-crystal and metal oxide nanocrystals Wherein the nonvolatile memory element comprises at least one of a nonvolatile memory element and a nonvolatile memory element. The method according to claim 1,
The channel region may be formed of silicon, germanium, silicon-germanium, strained silicon, strained germanium, strained silicon-germanium, and at least one of silicon on insulator (SOI). The method according to claim 1,
Wherein the tunneling insulating layer comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride. A data erasing method for a nonvolatile memory device including a charge storage region, a channel region formed adjacent to the charge storage region, a gate structure for heating the charge storage region, and a potential applying structure for applying a potential to the channel region, ,
Applying joule heat above a reference temperature to the charge storage region using the gate structure to emit at least one charge stored in the charge storage region; And
And applying a potential higher than a reference potential to the channel region using the potential applying structure. 17. The nonvolatile memory device according to claim 16,
And a tunneling insulation layer formed between the charge storage region and the channel region,
Wherein the at least one charge stored in the charge storage region passes through an energy barrier by the tunneling insulation layer and is released to the channel region when the row of columns is applied to the charge storage region. A method for erasing data of a device. 17. The nonvolatile memory device according to claim 16,
And a tunneling insulation layer formed between the charge storage region and the channel region,
Wherein a potential difference between the charge storage region and the channel region increases when the positive potential is applied to the channel region and the at least one charge stored in the charge storage region passes through an energy barrier by the tunneling insulation layer And the number of times of writing and the speed of passage of the nonvolatile memory element are increased. 17. The method of claim 16,
When the row of columns is applied to the charge storage region, the row of columns is applied to the tunneling insulation layer adjacent to the charge storage region, and the tunneling insulation layer is self-annealed by the row of columns The data storage time and the deterioration of the characteristics of the nonvolatile memory device are prevented. A processor; And
And a non-volatile memory device for storing data processed by the processor,
Wherein the nonvolatile memory element comprises:
Board;
A charge storage region formed on the substrate;
A channel region formed adjacent to the charge storage region;
A tunneling insulation layer formed between the charge storage region and the channel region;
A gate structure for heating the charge storage region; And
And a potential applying structure for applying a potential to the channel region,
Applying a Joule heat above a reference temperature to the charge storage region using the gate structure and applying a positive potential above a reference potential to the channel region using the potential application structure, Wherein the data erase operation causes at least one charge to be emitted.

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