KR20180088259A - Method and system for manufacturing integrated circuit by considering local layout effect - Google Patents

Abstract

According to an exemplary embodiment of the present disclosure, disclosed are a computing system and method for designing an integrated circuit by considering a local layout effect. A method for manufacturing an integrated circuit including instances of standard cells according to an exemplary embodiment of the present invention includes the steps of: arranging a first instance; and arranging a second instance with a front-end-layer pattern which is identical to a context group of the first instance to be adjacent to the first instance. The context group includes information on the front-end-layer pattern of the instances generating the same local layout effect in the first instance and arranged to be adjacent to the first instance. Accordingly, the present invention improve the performance of the integrated circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method and system for manufacturing an integrated circuit,

Technical aspects of the present disclosure relate to an integrated circuit, and more particularly, to a method and system for manufacturing an integrated circuit in consideration of local layout effects.

An integrated circuit for processing digital signals can be designed based on standard cells. The integrated circuit may include instances of standard cells, and instances corresponding to one standard cell may have the same structure, i.e., a layout. Instances are placed and interconnects electrically connecting the instances are created so that the integrated circuit implements the desired functionality, so that a layout of the integrated circuit can be created.

Due to the miniaturization of the semiconductor manufacturing process, standard cells including patterns formed in a plurality of layers not only include patterns of reduced size, but also can reduce the size of standard cells. Thus, an instance of a standard cell included in an integrated circuit may have a large influence from its surrounding structure (i.e., layout). The effect of such a peripheral layout can be referred to as a local layout effect (LLE) or a layout dependent effect (LDE).

The technical idea of the present disclosure relates to a method of designing an integrated circuit in consideration of a local layout effect, and provides a system and a method for generating an integrated circuit layout and manufacturing an integrated circuit reflecting the local layout effect.

According to an aspect of the present disclosure, a method for fabricating an integrated circuit including instances of standard cells includes the steps of: placing a first instance, and creating a front-end-layer placing a second instance having a front-end-layer pattern adjacent to the first instance, wherein the context group generates the same local layout effect on the first instance, And may include information about the front-end-layer pattern of the instances, which are arranged adjacently.

According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device including an integrated circuit, the method comprising: designing the integrated circuit to generate layout data including instances of a standard cell; Wherein the step of designing an integrated circuit includes the steps of: placing a first instance and placing a second instance adjacent to the first instance in a first direction, and designing a front- Determining if the end-layer pattern matches a context group of the first instance; And the context group may include information about the front-end-layer pattern of instances, which generates the same local layout effect on the first instance and is disposed adjacent to the first instance.

A computing system for fabricating an integrated circuit including instances of standard cells, in accordance with an aspect of the teachings of the present disclosure, includes: a memory that stores information including procedures; An instance deployer for deploying a first instance and for arranging the second instance in which a shape of an active area and a context group of a first instance coincide with each other; And a router for generating layout data of the integrated circuit by routing the instances, wherein the context group includes information about the active regions of the instances, which generate the same local layout effect on the first instance and are disposed adjacent to the first instance can do.

A system and method for designing an integrated circuit according to an exemplary embodiment of the present disclosure can design an integrated circuit to place a standard cell adjacent a target standard cell, reflecting the local layout effects that occur in the target standard cell. have. Thus, the performance of the integrated circuit can be improved, and the integrated circuit can be designed optimally.

1 shows a block diagram of a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure;
Figure 2a illustrates a schematic layout of an integrated circuit in accordance with an exemplary embodiment of the present disclosure.
Figure 2B is a diagram illustrating a portion of a schematic layout of the integrated circuit of Figure 2A.
Figure 3 shows a block diagram of the program of Figure 1 in accordance with an exemplary embodiment of the present disclosure.
4 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure.
5 is a graph for explaining the local layout effect generated in the target standard cell.
6 is a diagram illustrating a portion of a schematic layout of an integrated circuit according to an exemplary embodiment of the present disclosure;
7 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure.
8 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure.
9A and 9B are views showing a portion of a schematic layout of an integrated circuit according to an exemplary embodiment of the present disclosure;
Figure 10 shows a block diagram of the program of Figure 1 in accordance with an exemplary embodiment of the present disclosure.
11 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure.
12 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

1 shows a block diagram of a computing system 10 including a memory for storing a program according to an exemplary embodiment of the present disclosure. The operation of designing the integrated circuit in accordance with the exemplary embodiment of the present disclosure may be performed in the computing system 10.

The computing system 10 may be a fixed computing system, such as a desktop computer, a workstation, a server, or the like, or a portable computing system, such as a laptop computer. 1, the computing system 10 includes a central processing unit (CPU) 11, input / output devices 12, a network interface 13, a random access memory (RAM) 14, only memory < / RTI > (15) and a storage device (16). The CPU 11, the input / output devices 12, the network interface 13, the RAM 14, the ROM 15 and the storage device 16 may be connected to the bus 17, Communication can be performed.

CPU 11 may be referred to as a processing unit and may be implemented as any instruction set such as a micro-processor, an application processor, a digital signal processor (DSP), a graphics processing unit (GPU) For example, a core capable of executing IA-32 (Intel Architecture-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, the CPU 11 may access the memory, that is, the RAM 14 or the ROM 15, via the bus 17 and execute the instructions stored in the RAM 14 or the ROM 15. [ 1, the RAM 14 may store a program 20 or at least a portion thereof in accordance with the illustrative embodiment of the present disclosure, and the program 20 may cause the CPU 11 to design an integrated circuit The program 20 may include a plurality of instructions executable by the CPU 11, The plurality of instructions contained in the program 20 may cause the CPU 11 to perform operations for designing an integrated circuit according to the exemplary embodiments of the present disclosure.

The storage device 16 may not lose the stored data even if the power supplied to the computing system 10 is interrupted. For example, the storage device 16 may be a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory ), Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM) Or may include a storage medium such as a magnetic disk. In addition, the storage device 16 may be removable from the computing system 10. The storage device 16 may store the program 20 in accordance with the illustrative embodiment of the present disclosure and may store the program 20 or the program 20 from the storage device 16 prior to being executed by the CPU 11. [ At least a portion of it may be loaded into the RAM 14. The storage device 16 may store a file written in a programming language and the program 20 or at least a part thereof generated by a compiler or the like may be loaded into the RAM 14. [

The storage device 16 may store data to be processed by the CPU 11 or data processed by the CPU 11. [ That is, the CPU 11 can generate new data by processing the data stored in the storage device 16 according to the program 20, and store the generated data in the storage device 16. [ For example, the storage device 16 may store the input data D010 of FIG. 3 processed by the program 20, store the layout data D100 of FIG. 3 generated by the program 20 have.

Input / output devices 12 may include input devices such as keyboards, pointing devices, and the like, and may include output devices such as display devices, printers, and the like. For example, the user may trigger the execution of the program 20 by the CPU 11 or input the input data D010 of Fig. 3 via the input / output devices 12, D100) and / or an error message.

The network interface 13 may provide access to a network outside the computing system 10. For example, a network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links. The input data D010 of Figure 3 may be provided to the computing system 10 via the network interface 13 and the layout data D100 may be provided to the other computing system via the network interface 13. [

2A shows a schematic layout of an integrated circuit 5 according to an exemplary embodiment of the present disclosure. In Fig. 2A, the components included in the integrated circuit 5 may not fit the scale for illustrative convenience, and may be exaggerated or reduced.

Referring to FIG. 2A, the integrated circuit 5 may include instances of standard cells (C01, C02). Instances corresponding to the same standard cell may have the same layout, and instances corresponding to different standard cells may have different layouts, respectively. The instances C01 to C06 may be arranged in a plurality of rows R01 to R04. The instances C01 to C06 may have a length H (i.e., height) defined in a direction perpendicular to the plurality of rows R01 to R04 extending in the X direction (i.e., the Y direction) (I.e., width) in the direction parallel to the rows (i.e., the X direction). Each of the plurality of rows R01 through R04 in which the instances C01 through C06 are aligned may have a height corresponding to a minimum height of the standard cell.

A standard cell to be included in an integrated circuit may be selected from a cell library (for example, D310 in FIG. 3) including information on a plurality of standard cells, based on the physical characteristics of standard cells such as functions, timing characteristics, The layout of the integrated circuit 5 can be created by placing instances of the selected standard cells.

An instance may have physical characteristics that differ from the physical characteristics of a standard cell (i. E. Intrinsic physical characteristics of a standard cell) depending on its surrounding layout. For example, the threshold voltage (Vth) and the drain saturation current (Idsat) of the transistors included in the instance may vary according to the layout around the instance, so that the physical characteristics of the instance included in the integrated circuit May differ from the intrinsic physical properties of the standard cells defined in the library. In this way, the influence of the peripheral layout of the instance can be referred to as a local layout effect (LLE) or a layout dependent effect (LDE).

The physical characteristics of the transistor, for example, the threshold voltage Vth and the drain saturation current Idsat, may be the same as those of the front-end-layer or front-end-of-layer It can be varied by a pattern. The front-end-layer may refer to a layer formed by a front-end-of-line (FEOL) that forms elements such as transistors, capacitors, resistors, etc. in a semiconductor manufacturing process.

According to an exemplary embodiment of the present disclosure, a method of designing an integrated circuit that may be performed in the computing system 10 of FIG. 1 may take into account local layout effects. For example, as described below with reference to FIG. 3 and the like, the computing system 10 may arrange the second instance to be adjacent to the first instance, taking into account the local layout effect that occurs according to the pattern of the front- can do. As a result, the local layout effect allows the first instance to be relatively reduced in delay time or power loss, and the performance of the integrated circuit can be improved.

Fig. 2B is a diagram showing a part of the schematic layout of the integrated circuit 5 of Fig. 2A, in which the first instance C01 and the second instance C02 included in the integrated circuit 5 are connected to the front- And is a view for explaining the formed patterns.

2B, the instances C01 and C02 are defined by the cell boundaries CB1 and CB2 and the instances C01 and C02 are defined by the plurality of pins FN1 and FN2, active regions (e.g., AR1, AR2) and a plurality of gate lines (GL1, GL2, GL3). The cell boundaries CB1 and CB2 are outlines that define the instances C01 and C02 and the Place and Route tool uses the cell boundaries CB1 and CB2 to instantiate the instances C01 and C02 ) Can be recognized. The cell boundaries CB1 and CB2 are composed of four boundary lines.

The plurality of pins FN1 and FN2 may extend in a first direction (e.g., the X direction) and may be disposed parallel to each other along a second direction (e.g., Y direction) perpendicular to the second direction . The first active area AR1 and the second active area AR2 may be arranged in parallel with each other and may have different conductivity types. For example, the first active region AR1 may be an active region for forming a P-type FinFET, and the second active region AR2 may be an active region for forming an N-type FinFET.

In one embodiment, three pins FN may be disposed in each of the first and second active areas AR1 and AR2. However, the present invention is not limited to this, and the number of the plurality of fins FN1, FN2 disposed in each of the first and second active areas AR1, AR2 can be variously changed, . At this time, the plurality of fins FN1 and FN2 disposed in the first and second active areas AR1 and AR2 may be referred to as active pins. 2B, the present invention is not limited to this. Instances C01 and C02 may include cell boundaries CB1 and CB2 and a first active region AR1, first and second active regions AR1 and AR2, And dummy pins disposed in a region between the second active region AR2 and the cell boundary CB1 or CB2 or between the second active region AR2 and the cell boundary CB1 or CB2.

The plurality of gate lines GL1, GL2 and GL3 may extend in a second direction (e.g., the Y direction) and may be disposed parallel to each other along the first direction (e.g., the X direction) . The plurality of gate lines GL1, GL2, and GL3 may be formed of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, or the like. At this time, the gate line GL2 disposed at the interface between the first instance C01 and the second instance C02 may be a dummy gate line.

The physical properties of the first instance C01 may vary due to the local layout effect by the adjacently disposed second instance C02. The local layout effect may vary depending on the shape of the front-end-layer patterns of the second instance C02. For example, the shape of the first and second active regions AR1 and AR2 disposed in the second instance C02 and the shape of the plurality of fins FN1 and FN2 included in the first and second active regions AR1 and AR2, , FN2). The change of the local layout effect according to the shape of the patterns of the front-end-layer will be described later with reference to FIG. 6 and the like.

The computing system 10 in accordance with the exemplary embodiment of the present disclosure is able to determine that when placing the second instance C02 adjacent to the first instance C01 the patterns of the front-end-layer patterns of the second instance C02 The second instance C02 can be arranged in consideration of the local layout effect generated in the first instance C01 according to the shape. Accordingly, the computing system 10 may utilize the effect of the local layout that occurs in the first instance C01 in favor of the performance of the integrated circuit.

FIG. 3 shows a block diagram of program 20 of FIG. 1 in accordance with an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1, program 20 may include a plurality of instructions, and the plurality of instructions contained in program 20 may cause CPU 11 to execute instructions, So that an operation of designing an integrated circuit can be performed. All of the components of the program 20 shown in Figure 3 may be stored in the RAM 14 of Figure 1 and at least some of the components are stored in the RAM 14 of Figure 1, 1 < / RTI >

3, the program 20 may include an implementation group 100, and the implementation group 100 may include a plurality of procedures 120, 140. A procedure may refer to a set of instructions for performing a particular task. A procedure may also be referred to as a function, a routine, a subroutine, a subprogram, or the like. Each of the procedures may process externally provided data (e.g., D010) or data generated by another procedure. In this specification, the CPU 11 of FIG. 1 performs an operation by executing a procedure (for example, 120 or 140) by performing a procedure (for example, 120 or 140) Can also be expressed.

The cell library D310, the design rule D320 and the LLE data D330 may be stored in the storage medium 30, for example the storage medium 30 may be the storage device 16 of Fig. The cell library D310 may include at least one of information on physical characteristics of a plurality of standard cells, for example, function information, timing information, layout information, and power information. In one embodiment, the cell library D310 may include information about standard cells that perform the same function but whose active area patterns of the front-end-layer are different from each other. In one embodiment, the cell library D310 may include information about standard cells that perform the same function, but whose active area patterns in the front-end-layer are symmetric to each other. In addition, the cell library D310 may include information on standard cells that perform the same function but have different active area patterns of the front-end-layer.

Design rule D320 may include rules that an integrated circuit must conform to in order for the integrated circuit to be fabricated by a semiconductor process and / or to prevent degradation of the performance of the integrated circuit.

The LLE data D330 may include information on patterns formed in the front-end-layer of the standard cells stored in the cell library D310. In one embodiment, the information of the front-end-layer patterns that produce the same local layout effect can be categorized into a single context group, and the LLE data D330 can include information about a plurality of context groups have. For example, the context group of the LLE data D330 may contain information about the front-end-layer patterns of standard cells that produce a local layout effect to reduce the delay time of a contiguous standard cell have. Alternatively, the context group of LLE data D330 may include information about the front-end-layer patterns of standard cells that produce a local layout effect to reduce the power consumption of the neighboring standard cells. In one embodiment, the context group may include information about the shape (e.g., the number of active pins) of the active area at the interface adjacent to the target standard cell.

The implementation group 100 may refer to the data D310, D320 and D330 stored in the storage medium 30 and may generate the layout data D100 from the input data D010. The input data D010 may be data defining an integrated circuit, for example a netlist containing information about the instances of standard cells and the electrical connections of those instances. Further, the input data D010 may further include information on the requirements of the integrated circuit, for example, a timing condition, a power condition, an area condition, and the like. The implementation group 100 references the data D310, D320, and D330 stored in the storage medium 30 to generate layout data D100 including the physical information of the layout of the integrated circuit from the input data D010 defining the integrated circuit Can be generated.

In one embodiment, the implementation group 100 refers to the data group D310, D320, D330 stored in the storage medium 30, thereby referring to the context group corresponding to the integrated circuit requirements contained in the input data D010 , The layout data D100 in which the instances are arranged can be generated. Thus, the physical characteristics (front-end-layer) of the second instance disposed adjacent to the first instance of the target standard cell can be determined and the layout data D100 accordingly generated. For example, the implementation group 100 may determine the number of the plurality of fins included in the active region of the second instance so that the shape of the active region of the second instance changes at the interface adjacent to the first instance.

The deployer 120 of the implementation group 100 can refer to the cell library D310 and arrange the instances defined in the input data D010. The deployer 120 can obtain the layout of the instances defined in the input data D010 by referring to the cell library D310 and can obtain information about the requirements of the integrated circuit included in the input data D010 and the design rule D320 (I. E., Layouts of instances) based on the < / RTI >

The deployer 120 may deploy the first instance and place the second instance in an area where the first instance is not located, such that the second instance is adjacent to the first instance. The deployer 120 refers to the LLE data D330 and the design rule D320 to generate an appropriate local layout effect for the first instance based on the information about the context group included in the LLE data D330, A second instance having a shape of a front-end-layer pattern corresponding to a context group of the first instance may be arranged.

However, one embodiment according to the present disclosure is not limited to deploying device 120 sequentially arranging the first instance and the second instance. The deployer 120 may deploy the first instance and the second instance together. The deployer 120 may refer to the LLE data D330 and the design rule D320 and reflect the information about the context group included in the LLE data D330 to relocate the instances including the second instance. Will be described later in the description of FIG. 7 and FIG.

Router 140 may create interconnections that electrically connect instances disposed by deployer 120. For example, the router 140 may use a routing resource, i. E., A plurality of interconnect layers and vias, to create an interconnect that includes patterns and / or vias formed in the interconnect layer. The router 140 can generate the interconnections based on the design rule D320 and information about the connection relationship of the instances defined in the input data D010. In addition, the router 140 may generate interconnections based on information regarding the requirements of the integrated circuit included in the input data D010.

4 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure. Specifically, FIG. 4 shows a method of generating the layout of an integrated circuit in consideration of the local layout effect, and the method shown in FIG. 4 may be performed by the implementation group 100 of FIG.

Referring to FIG. 4, an operation in which a first instance of a target standard cell is disposed may be performed (S110). The first instance may be defined by input data (D010, FIG. 3) and may be placed in consideration of design rule (D320, FIG. 3).

In consideration of the characteristics of the target standard cell, at least one context group corresponding to the first instance among the plurality of context groups included in the LLE data D330 may be selected (S120). Each of the context groups may include contexts for the front-end-layer pattern that produce the same local layout effect on adjacent instances. Therefore, the context group can be selected depending on whether it is important to shorten the delay time of the first instance or to reduce the power consumption of the first instance.

The shape of the front-end-layer pattern formed at the interface adjacent to the first instance may be determined based on the selected context group, and the second instance including the front-end-layer pattern may be placed adjacent to the first instance (S130). The second instance is an instance of a standard cell and can be arranged to comply with design rules (D320, FIG. 3).

Routing connections of the first instance and the second instance may be performed (S140). For example, interconnections may be created that connect the first instance and the second instance, and layout data D100, D100, and D100, including physical information about interconnections and information about the placement of the first and second instances, 3) may be generated.

The method of designing an integrated circuit according to an embodiment of the present disclosure can improve the performance of the integrated circuit by arranging the second instance in advance considering the local layout effect to be applied to the first instance.

5 is a graph for explaining the local layout effect generated in the target standard cell.

Referring to FIG. 2B and FIG. 5, a change in the drain saturation current Idsat of the first instance C01 according to the shape of the active regions AR1 and AR2 of the second instance C02 can be known. The second instance C02 may be disposed adjacent to the first instance C01 of the target standard cell.

The active regions AR1 and AR2 of the second instance C02 may change shapes of the active regions AR1 and AR2 while the number of the pins included in the active regions AR1 and AR2 decreases. The active regions AR1 and AR2 may have an L shape at a point where the shapes of the active regions AR1 and AR2 change. For example, the 'L' shape of the active areas AR1 and AR2 may be formed when the number of pins included in the active areas AR1 and AR2 is reduced from three to two.

Referring to FIG. 6A, in the case of the N-type finFET, the first active region AR1 of the second instance C02 or the second active region AR2 of the second instance C02 from the center of the first instance C01 The value of the drain saturation current Idsat may decrease as the distance D to the 'L' shape is further away. 6 (b), in the case of the P-type finFET, the first active region AR1 or the second active region AR2 of the second instance C02 from the center of the first instance C01 , The value of the drain saturation current Idsat may increase as the distance D to the shape of the 'L'

When the first instance C01 is included in the timing critical path, the active region (for example, the second active region AR2) in which the N-type finFET is formed has a layout having an L shape 2 instances C02 may be disposed adjacent to the first instance C01. At this time, the delay time can be reduced as the 'L' shape is disposed closer to the first instance C01.

In one embodiment, the LLE data D330 stored in the storage medium 30 (FIG. 3) includes information on the shape of the active area (for example, the second active area AR2) in which the N-type finFET is formed, Information about the distance D from the center of the first active area AR2 to the 'L' shape of the second active area AR2 may be stored in one context group.

On the other hand, in the case where the first instance C01 is not included in the timing critical path, in order to reduce the power consumption of the first instance C01, the active region in which the P-type finFET is formed (for example, The second instance C02 having the layout in which the region AR1 has the L shape is adjacent to the first instance C01. At this time, as the 'L' shape is disposed closer to the first instance C01, the consumed power may be reduced.

In one embodiment, the LLE data (D330, Figure 3) includes information about the shape of the active area (e.g., the first active area AR1) where the P-type finFET is formed and the center of the first instance C01 The information on the distance D from the first active area AR1 to the 'L' shape of the first active area AR1 can be stored in one context group.

6 is a diagram showing a part of the schematic layout of the integrated circuit 5_1 according to the exemplary embodiment of the present disclosure. The first instance C01 and the second instance C02_1 included in the integrated circuit 5_1 FIG. 8 is a view for explaining patterns formed on the front-end-layer; FIG.

Referring to FIGS. 4 and 6, the first instance C01 may be disposed in the layout of the integrated circuit 5_1. In one embodiment, the first instance C01 may be included in the timing critical pass. The context group in which the delay time is relatively reduced among the plurality of context groups included in the LLE data D330 (FIG. 3) can be selected in consideration of the local layout effect by the instances disposed around the first instance C01 (S120). However, the present invention is not limited to this. Of the plurality of context groups, the context group of the first instance corresponding to another local layout effect to be generated in the first instance may be selected. The selected context group includes information on the shape of the active region in which the active region (for example, the second active region AR2_1) in which the N-type finFET is formed has the L shape, and the L shape And information about the location where it is located.

Accordingly, the second active area AR2_1 of the first instance C01 may include three pins, and the second instance C02_1 including the two pins in the second active area AR2_1 may be the first active area AR2_1, (C01) (S130). Since the 'L' shape of the second active area AR2_1 can be formed at the interface between the first instance C01 and the second instance C02_1, the second active area AR2_1 can be formed from the center of the first instance C01, The distance D to the shape of the letter 'L' of the second element AR2_1 approaches, and the delay time due to the local layout effect can be reduced.

It should be noted that one embodiment according to the present disclosure may include a second instance C02_1 such that the 'L' shape of the second active area AR2_1 is formed at the interface between the first instance C01 and the second instance C02_1. And an L shape may be formed in the second active area AR2_1 of the second instance C02_1. The second active area AR2_1 of the first instance C01 may include three or more pins and the second active area AR2_1 of the second instance C02_1 may include two or more pins. have.

In this figure, only the shape of the front-end-layer pattern of the second instance C02_1 for reducing the delay time is described, but the present invention is not limited thereto. In order to reduce the power consumption of the target standard cell, the context group in which the power consumption is relatively reduced among the plurality of context groups included in the LLE data (D330, Fig. 3) may be selected. The selected context group includes information on the shape of the active region in which the active region (for example, the first active region AR1) in which the P-type finFET is formed has the L shape, and the L shape And information about the location where it is located. Thus, three pins may be disposed in the first active area AR1 of the first instance C01, and a second instance C02_1 including two pins in the first active area AR1 may be arranged in the first active area AR1, (C01).

7 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure. The method shown in FIG. 7 may be performed by the implementation group 100 of FIG. In comparison with the flowchart of Fig. 4, in Fig. 7, after arranging the second instance adjacent to the first instance, the local layout effect generated in the first instance is taken into consideration and the instance is relocated to the peripheral region of the first instance .

Referring to FIG. 7, an operation in which a first instance is disposed and a second instance is disposed adjacent to the first instance may be performed (S210). The first instance and the second instance may be defined by input data (D010, FIG. 3) and may be placed in consideration of design rule (D320, FIG. 3).

Referring to the input data D010, it can be determined whether the first instance is included in the timing critical path (S220). When the first instance is included in the timing critical path, at least one context group corresponding to the first instance among the plurality of context groups included in the LLE data (D330, FIG. 3) may be selected (S230). For example, the selected context group may include information about the shape of the front-end-layer pattern that may reduce latency. Thus, based on the selected context group, the shape of the front-end-layer pattern of the instance adjacent to the first instance can be determined.

It can be determined if the front-end-layer pattern of the second instance matches the selected context group (S240). Whether the front-end-layer pattern of the second instance matches the selected context group can be determined based on the front-end-layer pattern of the interface where the first instance and the second instance are adjacent to each other.

If the second instance includes a shape of the front-end-layer pattern different from the selected context group, the second instance may be omitted. A third instance, where the shape of the front-end-layer pattern matches the selected context group, may be placed adjacent to the first instance (S250).

The third instance has the same function as the second instance, but the shape of the front-end-layer pattern may be different. In particular, the shape of the front-end-layer pattern on the side adjacent to the first instance may be different. For example, the second instance may include the same front-end-layer pattern as the second instance C02 of FIG. 2B, and the third instance may include the same front-end-layer pattern as the second instance C02_1 of FIG. You can include layer patterns.

If the third instance is disposed adjacent to the first instance, operations of routing connections of the first instance and the third instance may be performed (S260). For example, interconnections connecting the first instance and the third instance may be created, and layout data D100, D100 including physical information on interconnections and information on the placement of the first and third instances, 3) may be generated.

If the first instance is not included in the timing critical path, or if the front-end-layer pattern of the second instance matches the selected context group, an operation of routing connections of the first instance and the second instance may be performed (S270). For example, interconnections may be created that connect the first instance and the second instance, and layout data D100, D100, and D100, including physical information about interconnections and information about the placement of the first and second instances, 3) may be generated.

However, the present invention is not limited to this. The LLE data D330 (FIG. 3) may be used when the first instance has a limitation on the power consumption. However, At least one context group corresponding to the power consumption reduction effect among the plurality of context groups included in the context group may be selected. Based on the selected context group, a third instance having the same function as the second instance but different in the shape of the front-end-layer pattern may be disposed adjacent to the first instance.

The method of designing an integrated circuit according to an embodiment of the present disclosure can improve the performance of the integrated circuit by arranging the second instance in advance considering the local layout effect to be applied to the first instance.

8 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure. The method shown in FIG. 8 may be performed by the implementation group 100 of FIG. In comparison with the flowchart in Fig. 7, Fig. 8 is characterized in that the second instance is relocated in consideration of the local layout effect. In the flowchart of FIG. 8, steps S210, S220, S230, S240, and S270 of FIG. 7 may be performed in the same manner, and FIG. 8 may represent steps performed after step S240.

Referring to FIG. 8, it can be determined whether the front-end-layer pattern of the second instance matches the selected context group (S240). Whether or not the front-end-layer pattern matches the selected context group can be determined based on the front-end-layer pattern of the interface where the first instance and the second instance are adjacent to each other.

If the front-end-layer pattern of the second instance does not match the selected context group, it can be determined whether the symmetric structure of the front-end-layer pattern of the second instance matches the context group (S245). For example, if the front-end-layer pattern of the second instance at the interface adjacent to the first instance does not match the selected context group, the second instance in the face opposite to the face adjacent to the first instance It can be determined whether the front-end-layer pattern of the content group matches the selected context group.

If the symmetric structure of the front-end-layer pattern of the second instance matches the context group, the second instance may be symmetrically transformed and relocated (S235). For example, when the first instance and the second instance are disposed adjacent to each other in the first direction, the second instance can be rearranged after being symmetrically transformed with respect to an axis perpendicular to the first direction. Thereafter, an operation of routing connections of the first instance and the relocated second instance may be performed (S265).

If the symmetric structure of the front-end-layer pattern of the second instance does not match the selected context group, the second instance is dropped, the function is the same as the second instance, but the shape of the front- A third instance may be placed adjacent to the first instance (S250). The front-end-layer pattern of the third instance may match the selected context group. Thereafter, an operation of routing connections of the first instance and the third instance may be performed (S260).

9A and 9B are diagrams showing a part of the schematic layout of the integrated circuits 5_2 and 5_2 'according to the exemplary embodiment of the present disclosure. The first instance C01 included in the integrated circuit 5_1, 2-instance (C02_2, C02_2 ').

Referring to Figs. 8 and 9A, a first instance C01 may be disposed in the layout of the integrated circuit 5_2. In one embodiment, the first instance may be included in the timing critical path. The context group in which the delay time is relatively reduced among the plurality of context groups included in the LLE data D330 (FIG. 3) can be selected in consideration of the local layout effect by the instances disposed around the first instance C01 have. The selected context group includes information on the shape of the active area in which the active area (for example, the second active area AR2_2) in which the N-type finFET is formed has the L shape, and the L shape And information about the location where it is located.

Since the second instance C02_2 includes three fins in the second active area AR2_2 at the interface adjacent to the first instance C01, the second active area AR2_2 is formed in the L shape at the interface I can not make it. Thus, the second instance C02_2 may not coincide with the selected context group. However, since the second instance C02_2 includes two fins in the second active area AR2_2 on the opposite side of the interface adjacent to the first instance C01, the opposite side is connected to the first instance C01, If positioned contiguously, they may coincide with the selected context group.

8, 9A and 9B, the second instance C02_2 may be symmetrically transformed and relocated (S235). For example, the first instance C01 and the second instance C02_2 may be disposed adjacent to each other in the X direction, and the second instance C02_2 may be symmetrically transformed and relocated around an axis parallel to the Y direction . The front-end-layer pattern of the relocated second instance C02_2 'may coincide with the selected context group corresponding to the first instance C01.

On the contiguous side of the first instance C01 and the relocated second instance C02_2 ', three fins may be placed in the second active area AR2_2' of the first instance C01, Two fins may be disposed in the second active area AR2_2 'of the instance C02_2'. Accordingly, since the 'L' shape of the second active area AR2_2 'is formed at the interface between the first instance C01 and the second instance C02_2', the second active area AR2_2 ' The distance to the shape of the letter 'L' of the second element AR2_2 'approaches, and the delay time due to the local layout effect can be reduced.

Figure 10 shows a block diagram of the program of Figure 1 in accordance with an exemplary embodiment of the present disclosure. 11 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure. In FIG. 10, the same reference numerals as those in FIG. 3 denote the same members, and a detailed description of the components that are the same as those in FIG. 3 will be omitted for simplicity.

10 and 11, the program 20a may include an implementation group 100 and an analysis group 200, and the implementation group 100 and the analysis group 200 may include a plurality of procedures 120 , 140 and 220, respectively.

The LLE data D330 may include information on the physical property variation of the standard cell due to the local layout effect. For example, the LLE data D330 may include information about a timing condition or a variation of a power condition of a standard cell due to a local layout effect.

The analysis group 200 can refer to the data D310, D320 and D330 stored in the storage medium 30 and generate the result data D200 from the layout data D100. The layout data D100 may include physical information related to the layout of the integrated circuit, and may include data having a GDSII format, for example. Although the analysis group 200 in FIG. 11 is shown as accessing the layout data D100 generated by the implementation group 100, the layout data D100 may be different from the computing system in which the analysis group 200 is implemented, May be generated by the system and provided to the analysis group 200. The analysis group 200 can analyze the performance of the integrated circuit based on the layout data D100 and generate the result data D200 that includes information on the performance of the integrated circuit.

The performance analyzer 220 can generate the result data D200 by analyzing the performance of the integrated circuit based on the physical characteristics of the instance included in the layout data D100. For example, the performance analyzer 220 can analyze the timing characteristics, power characteristics, noise characteristics, and the like of the integrated circuit. Further, the performance analyzer 220 refers to the information on the requirements of the integrated circuit included in the input data D010, and generates result data D200 including the result of determining whether the performance of the integrated circuit satisfies the requirement You may. Thus, the performance analyzer 220 can calculate (S310) the physical characteristics of the first instance (C01, FIG. 2A) and thereby determine the second instance (C02 (FIG. 2A) can be verified (S320) whether or not the local layout effect has occurred according to the purpose.

The implementation group 100 can access the result data D200 including information on the performance of the integrated circuit generated by the analysis group 200 based on the layout data D100. The implementation group 100 determines the layout of the integrated circuit according to whether or not the performance of the integrated circuit according to the layout data D100 satisfies the requirements of the integrated circuit included in the input data D010, New layout data D100 indicating the changed layout can be generated. The result data D200 may include variations in the performance of the integrated circuit according to the local layout effect and the implementation group 100 may include new layout data D100 indicating the layout of the optimally designed integrated circuit based on the result data D200 Can be generated.

In one embodiment, if the local layout effect due to the second instance (C02, Figure 2a) placed adjacent to the first instance of the target standard cell (C01, Figure 2a) does not occur for the purpose, 100 may be arranged to replace the second instance (C02, FIG. 2A) with the third instance based on the layout data D100, or to dispose the second instance on the opposite side of the face adjacent to the first instance, (S320). The step S320 may be performed similarly to the step S260 or S265 of FIG.

12 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Referring to FIG. 12, a manufacturing method of a semiconductor device can be classified into a design of an integrated circuit and a manufacturing process of an integrated circuit. The design of the integrated circuit includes steps S10 and S20, the manufacturing process of the integrated circuit includes steps S30 and S40, and the step of manufacturing the semiconductor device according to the integrated circuit based on the layout data, .

In step S10, a physical-aware compositing operation is performed. For example, step S10 may be performed by a processor using a synthesis tool. "Synthesis" may be referred to as "logic synthesis" as an operation to generate a netlist by converting input data for an integrated circuit into a hardware form of logic gates. The input data may be an abstract form for the behavior of the integrated circuit, for example, data defined in Register Transfer Level (RTL). The netlist may be generated from the RTL code using a standard cell library and may be a netlist at the gate level.

In step S20, placement and routing operations are performed. For example, step S20 may be performed by the processor using the P & R tool. Specifically, layout data for an integrated circuit can be generated by placing standard cells defining the integrated circuit according to the netlist, and then routing the nets included in the standard cells disposed.

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure can manufacture a semiconductor device by performing the method of designing the integrated circuit described above with reference to Figs. Specifically, step S20 may include steps S110 to S140 of FIG. 5, steps S210 to S270 of FIG. 8, or steps S240 to S265 of FIG. 9, and redundant description is omitted do.

In step S30, a mask is generated based on the layout data. Specifically, first, an optical proximity correction (OPC) can be performed based on layout data. The OPC refers to a process of changing a layout reflecting errors due to optical proximity effects. Then, the mask can be manufactured according to the changed layout according to the result of the OPC. At this time, a mask reflecting the OPC, for example, a GDS (Graphic Data System) II in which OPC is reflected can be used.

In step S40, a semiconductor device in which an integrated circuit is implemented is manufactured using a mask. Specifically, various semiconductor processes are performed on a semiconductor substrate such as a wafer using a plurality of masks to form a semiconductor device in which an integrated circuit is implemented. For example, a process using a mask may refer to a patterning process through a lithography process. Through this patterning process, a desired pattern can be formed on a semiconductor substrate or a material layer. Meanwhile, the semiconductor process may include a deposition process, an etching process, an ion process, a cleaning process, and the like. In addition, the semiconductor process may include a packaging process for mounting the semiconductor device on the PCB and sealing it with a sealing material, and may include a test process for testing the semiconductor device or package.

As described above, exemplary embodiments have been disclosed in the drawings and specification. Although the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for the purpose of describing the technical idea of the present disclosure and not for limiting the scope of the present disclosure as defined in the claims . Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

Claims (10)

CLAIMS What is claimed is: 1. A method of fabricating an integrated circuit comprising instances of standard cells,
Placing a first instance; And
Placing a second instance having a front-end-layer pattern coinciding with a context group of the first instance adjacent to the first instance; Lt; / RTI >
Wherein the context group includes information about a front-end-layer pattern of instances, which generates a local layout effect in the first instance and is disposed adjacent to the first instance. A method for fabricating an integrated circuit. The method according to claim 1,
Wherein the context group includes information on a pattern of a front-end-layer generating a local layout effect in which a delay time of the first instance is reduced,
Wherein the first instance and the second instance comprise an active region in which an N-type FinFET is formed,
Wherein the number of fins included in the active area of the first instance on the side where the first instance and the second instance are adjacent to each other is greater than the number of fins included in the active area of the second instance. How to. The method according to claim 1,
Wherein the context group includes information about a pattern of a front-end-layer generating a local layout effect in which power consumption of the first instance is reduced,
Wherein the first instance comprises an active region in which the second instance is formed with a P-type FinFET,
Wherein the number of fins included in the active area of the first instance on the side where the first instance and the second instance are adjacent to each other is greater than the number of fins included in the active area of the second instance. How to. The method according to claim 1,
Wherein the context group includes information about a shape of an active area formed at an interface of the first instance. A method of manufacturing a semiconductor device including an integrated circuit,
Designing the integrated circuit to generate layout data including instances of a standard cell; And
And fabricating the integrated circuit based on the layout data,
Wherein designing the integrated circuit comprises:
Placing a first instance and placing a second instance adjacent to the first instance in a first direction; And
Determining if a front-end-layer pattern of the second instance matches a context group of the first instance; Lt; / RTI >
Wherein the context group comprises information about a front-end-layer pattern of instances, which generates the same local layout effect on the first instance and is disposed adjacent to the first instance. 6. The method of claim 5,
Wherein designing the integrated circuit comprises:
Further comprising determining whether a pattern symmetric about an axis parallel to the front-end-layer pattern of the second instance and the second direction matches the context group,
And wherein the second direction is perpendicular to the first direction. The method according to claim 6,
If a pattern symmetric to the front-end-layer pattern of the second instance matches the context group,
And rearranging the second instance by symmetrically transforming the second instance around an axis parallel to the second direction. 6. The method of claim 5,
And if the front-end-layer pattern of the second instance does not match the context group,
And placing a third instance on behalf of the second instance,
Wherein the third instance performs the same function as the second instance and the front-end-layer pattern matches the context group. CLAIMS What is claimed is: 1. A computing system for manufacturing an integrated circuit comprising instances of standard cells,
A memory for storing information including procedures; And
A processor accessible to the memory and executing the procedures,
The procedures include:
An instance placement unit for arranging a first instance and arranging a second instance in which a shape of an active area and a context group of the first instance coincide with each other; And
And a router for generating layout data of the integrated circuit by routing the instances,
Wherein the context group comprises information about an active region of instances, wherein the context group generates the same local layout effect on the first instance and is disposed adjacent to the first instance. 10. The method of claim 9,
The procedures include:
Further comprising a performance analyzer for calculating a physical property of the first instance according to the arrangement of the second instance and for verifying whether a local layout effect according to the purpose has occurred based on the calculated physical property,
If the local layout effect does not occur for the purpose,
The instance placeer arranges a third instance on behalf of the second instance,
Wherein the third instance performs the same function as the second instance and the shape of the active area adjacent to the first instance is different from the second instance.

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