KR20180075233A - Symbol Interference Cancellation Circuit - Google Patents

Abstract

Provided is an inter-symbol interference cancellation circuit which cancels inter-symbol interference, thereby accurately transmitting and receiving a signal. The inter-symbol interference cancellation circuit comprises: a continuous time linear equalizer (CTLE) removing a first post cursor component of an input signal according to a first weighted value-applied signal to generate a preliminary interference cancellation signal; an interference cancellation circuit removing a second post cursor component, a third post cursor component and a fourth post cursor component of the preliminary interference cancellation signal according to a second weighted value-applied signal, a third weighted value-applied signal, a fourth weighted value-applied signal, a sampling signal and an output signal of shift registers to generate an interference cancellation signal; a sampling circuit sampling the interference cancellation signal in response to a clock, and outputting the sampled interference cancellation signal as the sampling signal; and the shift registers shifting the sampling signal by a predetermined period of a clock bar having an opposite phase to the clock, and shifting the sampling signal by a predetermined period of the clock to provide the interference cancellation circuit with the shifted signals.

Description

[0001] Symbol Interference Cancellation Circuit [

The present invention relates to a semiconductor integrated circuit, and more particularly, to a symbol interference cancellation circuit.

A semiconductor integrated circuit is a circuit for transmitting and receiving an electrical signal.

As the speed of a semiconductor integrated circuit increases, the speed at which signals are transmitted and received is also increasing.

As the transmission and reception speed of a signal increases, interference between signal symbols increases, and such an increase in interference is problematic for accurate and fast signal transmission and reception.

The present invention is intended to provide a symbol interference cancellation circuit capable of correctly transmitting and receiving a signal by eliminating intersymbol interference.

The symbol interference cancellation circuit according to an embodiment of the present invention includes a continuous time linear equalizer (CTLE) for generating a preliminary interference cancellation signal by removing a first post-cursor component of an input signal according to a first weighted signal; The second postcursor component of the preliminary interference cancellation signal, the third postcursor component, and the fourth postcursor component of the preliminary interference cancellation signal in accordance with the second weighted signal, the third weighted signal, the fourth weighted signal, the sampling signal, An interference cancellation circuit for removing the component to generate an interference cancellation signal; A sampling circuit for sampling the interference cancellation signal in response to a clock and outputting the sampled interference cancellation signal as the sampling signal; And shift registers for shifting the sampling signal by a predetermined period of a clock bar whose phase is opposite to the clock and shifting the sampling signal by a predetermined period of the clock to provide shifted signals to the interference eliminating circuit .

The symbol interference cancellation circuit according to an embodiment of the present invention includes a continuous time linear equalizer (CTLE) for generating a preliminary interference cancellation signal by removing a first post-cursor component of an input signal according to a first weighted signal; The second weighting applied signal, the fourth weighted signal, the first weighted signal, the second weighted signal, the third weighted signal, the fourth weighted signal, the first sampled signal, the first shift register, A first interference cancellation circuit for generating a first interference cancellation signal by removing a post-cursor component, a third post-cursor component, and a fourth post-cursor component; In accordance with the output signals of the first weight application signal, the second weight application signal, the third weight application signal, the fourth weight application signal, the second sampling signal, the 1-2 shift register, and the 2-1 shift register, A second interference cancellation circuit for generating a second interference cancellation signal by removing a second post-cursor component, a third post-cursor component, and a fourth post-cursor component of the second interference cancellation signal; A first sampling circuit for sampling the first interference cancellation signal in response to a clock and outputting the sampled first interference cancellation signal as the first sampling signal; A sampling circuit for sampling the second interference cancellation signal in response to the clock and outputting the sampled second interference cancellation signal as the second sampling signal; A first shift register for shifting the first sampling signal by a predetermined period of the clock and outputting the shifted first sampling signal; A first 1-2 shift register for shifting the first sampling signal by a set period of a clock bar whose phase is opposite to the clock and outputting the shifted first sampling signal; A second-1 shift register for shifting the second sampling signal by a predetermined period of the clock and outputting the shifted second sampling signal; And the second-2 shift register shifting the second sampling signal by a predetermined period of the clock bar and outputting the shifted second sampling signal.

The symbol interference cancellation circuit according to the present invention can operate at a higher operation speed than the existing symbol interference cancellation circuit.

1 is a timing diagram for explaining the operation of a symbol interference cancellation circuit according to an embodiment of the present invention;
2 is a configuration diagram of a symbol interference cancellation circuit according to an embodiment of the present invention,
3 is a configuration diagram of the first interference cancellation circuit of FIG. 2,
4 is a configuration diagram of a symbol interference cancellation circuit according to an embodiment of the present invention,
5 is a block diagram of a symbol interference cancellation circuit according to an embodiment of the present invention.

The present invention is a technique capable of eliminating the intersymbol interference shown in FIG.

The symbol interference cancellation circuit according to the embodiment of the present invention can receive the input signal D_in shown in FIG.

The main cursor component of the input signal D_in shown in FIG. 1 is a significant component of the input signal D_in. In addition, the first through fourth post cursors (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) are nonsensical components of the input signal (D_in) The cursor properties (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) can be generated by inter-symbol interference of the input signal (D_in).

Remove symbol interference according to an embodiment of the invention the circuit may be the first through fourth post-cursor ^{(1 st post cursor, 2 nd} post cursor, 3 rd post cursor, 4 th post cursor) technology for the removal of components .

As shown in FIG. 2, the symbol interference cancellation circuit according to the embodiment of the present invention includes first and second interference cancellation circuits 110 and 120, first and second sampling circuits 210 and 220, Second shift registers 310 and 320, and a weight control circuit 400. [

The first interference cancellation circuit 110 receives the first through fourth weighted signals W1, W2, W3 and W4, the first and second sampling signals D_sA and D_sB and the first and second output signals D_outA (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4) of the input signal (D_in) input to the first interference elimination circuit (110) the first interference cancellation circuit 110 may generate the first interference cancellation signal D_icA by removing the ^th post cursor component from the first interference cancellation circuit 110. For example, in D_sB) and said first weighted signal (in response to W1) of the first post-cursor (1 ^st post cursor) can be removed component. the first interference cancellation circuit 110 is the second input terminal (2) (2 ^nd post cursor) component in response to the first sampled signal (D_sA) and the second weighted signal (W2) There The first interference cancellation circuit 110 in response to a third input terminal (3) the second output signal (D_outB) and said third weighted signal (W3) that is input to the third post-cursor (3 ^rd The first interference cancellation circuit 110 may remove the post-cursor component from the first interference cancellation circuit 110. The first interference cancellation circuit 110 may be configured to receive the first output signal D_outA and the fourth weighted application signal W4, (4 ^th post cursor) component of the first interference canceling circuit 110. The first and second input terminals 1 to 4 of the first interference cancellation circuit 110 are connected to the first and second input terminals 1 to 4, The sampling signals D_sA and D_sB and the first and second output signals D_outA and D_outB include timing for removing a cursor component and the first through fourth weighted signals W1, W2, W3 and W4 May include the amount of cursor component to be removed.

The first sampling circuit 210 may sample the first interference cancellation signal D_icA in response to the clock CLK and output a result of the sampling as the first sampling signal D_sA. The first sampling circuit 210 may be implemented as a latch type sense amplifier.

The first shift register 310 may shift the first sampling signal D_sA by a predetermined period of the clock signal CLK and output the shifted first sampling signal D_sA as the first output signal D_outA. At this time, the first shift register 310 may be implemented as a flip-flop.

The second interference cancellation circuit 120 receives the first to fourth weighted signals W1, W2, W3 and W4, the first and second sampling signals D_sA and D_sB and the first and second output signals D_outA (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4) of the input signal (D_in) input to the second interference elimination circuit (120) the second interference cancellation circuit 120 may generate the second interference cancellation signal D_icB by removing the ^th post cursor component from the second interference cancellation circuit 120. For example, in D_sA) and said first weighted signal (in response to W1) of the first post-cursor (1 ^st post cursor) can be removed component. the second interference cancellation circuit 120 is the second input terminal (2) It is input and the second sampling signal (D_sB) and to remove the second in response to the weighted signal (W2) and the second post-cursor (2 ^nd post cursor) component There The second interference cancellation circuit 120 is the response to the first output signal (D_outA) and said third weighted signal (W3) that is input to the third input terminal (3) and the third post-cursor (3 ^rd The second interference cancellation circuit 120 may remove the post-cursor component from the second interference canceling circuit 120. The second interference cancellation circuit 120 may be configured to receive the second output signal D_outB and the fourth weighted application signal W4, to the fourth post-cursor (4 ^th post cursor) can be removed component. in addition, the second of the first and inputted to the first to fourth input terminals (14) of the interference removing circuit 120, the second The sampling signals D_sA and D_sB and the first and second output signals D_outA and D_outB include timing for removing a cursor component and the first through fourth weighted signals W1, W2, W3 and W4 May include the amount of cursor component to be removed. The first interference cancellation circuit 110 and the second interference cancellation circuit 120 receive the input signal D_in while the input signal D_in may be a differential signal and the first interference cancellation circuit The second interference cancellation circuit 120, the first and second sampling circuits 210 and 220 and the first and second shift registers 310 and 320 may be implemented as differential circuits.

The second sampling circuit 220 may sample the second interference cancellation signal D_icB in response to the clock CLK and output the sampled result as the second sampling signal D_sB. The second sampling circuit 220 may be implemented as a latch type sense amplifier.

The second shift register 320 may shift the second sampling signal D_sB by a predetermined period of the clock CLK and output the shifted second output signal D_outB. At this time, the second shift register 320 may be implemented as a flip-flop.

The weight control circuit 400 may store information on each of the first to fourth weighted signals W1, W2, W3 and W4. The first to fourth weighted signals W1 and W2 , W3, and W4, and outputs the determined voltage level.

The first interference cancellation circuit 110 may include a buffer 111 and first to fourth cursor component removal circuits 112, 113, 114 and 115 as shown in FIG. At this time, the input signal D_in may be a differential signal including a positive input signal D_inp and a negative input signal D_inn.

The buffer 111 buffers the positive input signal D_inp and the negative input signal D_inn and the first through fourth cursor component removal circuits 112, 113, 114, (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, and 4 ^th post cursor) components of the signal output from the first and second processors. For example, the first removal circuit cursor components 112 may remove the first post-cursor (1 ^st post cursor) component. The second cancellation circuit cursor components 113 can be removed and the second post-cursor (2 ^nd post cursor) component. The third cursor component removing circuit 114 may be removed and the third post-cursor (3 ^rd post cursor) component. The fourth cursor component removing circuit 115 can remove the post-cursor and the fourth (4 ^th post cursor) component.

The buffer 111 may include first and second resistors R1 and R2 and first through third transistors N1, N2 and N3. The first resistance element R1 receives an external voltage VDD at one end. The second resistance element R2 receives an external voltage VDD at one end. The first transistor (N1) receives the positive input signal (D_inp) at its gate and the other end of the first resistor (R1) is connected to a drain of the first transistor (N1). The second transistor N2 has the gate receiving the negative input signal D_inn and the drain connected to the other end of the second resistive element R2. The third transistor N3 receives an enable signal EN_s at its gate and a node connected to the source of the first and second transistors N1 and N2 is connected to the drain thereof. do. At this time, a first interference cancellation signal D_icAp is output at a node where the first resistance element Rl and the first transistor N1 are connected, and the second resistance element R2 and the second transistor N2 The first interference cancellation signal D_icAn is output from the node to which the first interference cancellation signal D_icAn is connected. The first interference cancellation signal D_ic may be a differential signal and the first interference cancellation signal D_ic which is a differential signal may be the first interference cancellation signal D_icAp and the first interference cancellation signal D_icAn .

The first cursor component removal circuit 112 may include fourth to sixth transistors N4, N5 and N6. The fourth transistor N4 receives a second sampling positive signal D_sBp at its gate and is connected to a node at which the first interference cancellation signal D_icAp is output to the drain thereof. The fifth transistor N5 receives a second sampling signal D_sBn at its gate and a node at which the first interference canceller signal D_icAn is output to the drain thereof. The sixth transistor N6 receives the first weight application signal W1 at its gate and the sources of the fourth and fifth transistors N4 and N5 are connected to the drain of the sixth transistor N6. do. At this time, the second sampling signal D_sB may be a differential signal, and the second sampling signal D_sB, which is a differential signal, may include the first sampling positive signal D_sBp and the second sampling signal D_sBn .

The second to fourth cursor component removal circuits 113, 114, and 115 may be configured similarly to the first cursor component removal circuit 112. At this time, the first sampling signal D_sA may be a differential signal, and the first sampling signal D_sA, which is a differential signal, may include a first sampling positive signal D_sAp and a first sampling signal D_sAn . The first output signal D_outA may be a differential signal and the first output signal D_outA which is a differential signal may include a first output definite signal D_outAp and a first output signal D_outAn. The second output signal D_outB may be a differential signal and the second output signal D_outB which is a differential signal may include a second output definite signal D_outBp and a second output signal D_outBn.

Each of the first to fourth cursor component removal circuits 112, 113, 114, and 115 configured as described above is connected to the ground terminal VSS according to the voltage levels of the input weighted signals W1, W2, W3, The amount of the sink current flowing into the capacitor can be determined. The first to fourth cursor component removal circuits 112, 113, 114, and 115 may output the first and second sampling signals D_sA and D_sB and the first and second output signals D_outA and D_outB, (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) is determined by flowing the sink current to the ground terminal (VSS) .

The symbol interference cancellation circuit according to the embodiment of the present invention configured as described above can operate as follows.

The input signal D_in is input to the first and second interference elimination circuits 110 and 120.

The first and second interference cancellation circuits 110 and 120 generate the first and second sampling signals D_sA and D_sB and the first and second output signals D_outA and D_outB and the first to fourth weighted signals W1, W2, W3, and W4, and can generate first and second interference cancellation signals D_icA and D_icB, from which the interference is canceled, by eliminating inter-symbol interference of the input signal D_in.

For example, the first interference cancellation circuit 110 may receive the first interference cancellation signal 110 input to the first interference cancellation circuit 110 in response to the second sampling signal D_sB and the first weighted application signal W1, It can be removed first post-cursor (1 ^st post cursor) component of (D_in). The first interference cancellation circuit 110 receives the input signal D_in input to the first interference cancellation circuit 110 in response to the first sampling signal D_sA and the second weight application signal W2, it is possible to remove the two post cursor (2 ^nd post cursor) component. The first interference cancellation circuit 110 receives the input signal D_in inputted to the first interference cancellation circuit 110 in response to the second output signal D_outB and the third weighted application signal W3, it is possible to eliminate the post-cursor 3 (3 ^rd post cursor) component. The first interference cancellation circuit 110 receives the input signal D_in input to the first interference elimination circuit 110 in response to the first output signal D_outA and the fourth weight application signal W4, it is possible to remove the post 4, the cursor (4 ^th post cursor) component. The second interference cancellation circuit 120 receives the input signal D_in input to the second interference cancellation circuit 120 in response to the first sampling signal D_sA and the first weighted application signal W1, it is possible to remove the first post-cursor (1 ^st post cursor) component. The second interference cancellation circuit 120 receives the second input signal D_in input to the second interference cancellation circuit 120 in response to the second sampling signal D_sB and the second weighted application signal W2, it is possible to remove the two post cursor (2 ^nd post cursor) component. The second interference cancellation circuit 120 receives the input signal D_in input to the second interference cancellation circuit 120 in response to the first output signal D_outA and the third weighted application signal W3, it is possible to eliminate the post-cursor 3 (3 ^rd post cursor) component. The second interference cancellation circuit 120 receives the second input signal D_in input to the second interference cancellation circuit 120 in response to the second output signal D_outB and the fourth weighted application signal W4, it is possible to remove the post 4, the cursor (4 ^th post cursor) component. At this time, the weight control circuit 400 may output the first through fourth weighted signals W1, W2, W3, and W4 whose voltage levels are determined according to the inter-symbol interference information. The weight control circuit 400 includes the first through fourth post-cursor ^{(1 st post cursor, 2 nd} post cursor, 3 rd post cursor, 4 th post cursor) of the first to fourth weighting according to the interference amount of the component W2, W3 and W4 of the determined voltage level and the first to fourth weighted signals W1, W2, W3 and W4 of the determined voltage level.

The first sampling circuit 210 may sample the first interference cancellation signal D_icA in response to the clock CLK and output the sampled signal as the first sampling signal D_sA.

The second sampling circuit 220 may sample the second interference cancellation signal D_icB in response to the clock CLK and output the sampled signal as the second sampling signal D_sB.

The first shift register 310 may shift the first sampling signal D_sA by a predetermined period (for example, one cycle) of the clock CLK and output the shifted first sampling signal D_sA as the first output signal D_outA .

The second shift register 320 may shift the second sampling signal D_sB by a predetermined period (for example, one cycle) of the clock CLK and output the shifted second output signal D_outB .

The symbol interference cancellation circuit according to the embodiment of the present invention includes a weighted signal having information of magnitude of symbol interference and a symbol interference signal in response to a feedback signal (sampling signal and output signal) having timing information of symbol interference, Interference can be eliminated. At this time, during which a feedback signal in response to an output signal which is finally output to the third post-cursor (3 ^rd post cursor) may cause a problem that the timing margin is insufficient to remove the component.

As shown in FIG. 4, the symbol interference cancellation circuit according to the embodiment of the present invention includes first and second interference elimination circuits 110 and 120, first and second sampling circuits 210 and 220, 1 shift register 311, a 1-2 shift register 312, a 2-1 shift register 321, a 2-2 shift register 322, and a weight control circuit 400.

The first interference cancellation circuit 110 includes first through fourth weighted signals W1, W2, W3 and W4, first and second sampling signals D_sA and D_sB, shift registers 311, 312 and 321 , 322) in response to the output signal wherein the first to the input signal (D_in) input to a first interference cancellation circuit 110, the fourth post-cursor of ((1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) may generate a first interference removal removal of the component signal (D_icA). the first input, for example, on the first interference cancellation circuit 110 has a first input terminal (1) 2 may be in response to the sampling signal (D_sB) and said first weighted signal (W1) to remove the first post-cursor (1 ^st post cursor) components. the first interference cancellation circuit 110 is the second input the input to the (2) the first sampled signal (D_sA) and the second in response to the weighted signal (W2) and the second post-cursor (2 ^nd post cursor) component The first interference cancellation circuit 110 receives the output signal of the second-2 shift register 322 and the third weight application signal W3 input to the third input terminal 3, to the third post-cursor (3 ^rd post cursor) can be removed component. the first interference cancellation circuit 110 is an output of the first-first shift register 311 is input to the fourth input terminal (4) The 4 ^th post cursor component may be removed in response to the first output signal D_outA and the fourth weighted application signal W4. The output signals of the first and second sampling signals D_sA and D_sB and the shift registers 311, 312, 321 and 322, which are input to the first to fourth input terminals 1 to 4, (W1, W2, W3, W4) includes the amount of the cursor component to be removed It can be included.

The first sampling circuit 210 may sample the first interference cancellation signal D_icA in response to the clock CLK and output a result of the sampling as the first sampling signal D_sA. The first sampling circuit 210 may be implemented as a latch type sense amplifier.

The first shift register 311 may shift the first sampling signal D_sA by a predetermined period of the clock signal CLK and output the shifted first sampling signal D_sA as the first output signal D_outA. At this time, the first shift register 310 may be implemented as a flip-flop.

The 1-2 shift register 312 may shift and output the first sampling signal D_sA by a predetermined period of the clock bar CLK_b having the opposite phase of the clock CLK. At this time, the 1-2 shift register 312 may be implemented as a flip-flop.

The second interference cancellation circuit 120 receives the first through fourth weighted signals W1, W2, W3 and W4, the first and second sampling signals D_sA and D_sB and the shift registers 311 and 312 and 321 , 322) in response to the output signal and the second first to the interference removing the input signal (D_in) input to the circuit 120, the fourth post-cursor of ((1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post it is possible to produce a second interference cancellation signal (D_icB) removing the cursor, 4 ^th post cursor) component. for example, the second interference cancellation circuit 120 is the first input to the first input (1) sampling signal (D_sA) and the first in response to the weighted signal (W1) of the first post-cursor (1 ^st post cursor) can be removed component. the second interference cancellation circuit 120 is the second input terminal ( 2) the input to the second sampling signal (D_sB) and the second in response to the weighted signal (W2) and the second post-cursor (2 ^nd post cursor) component The second interference cancellation circuit 120 receives the output signal of the first-second shift register 312 and the third weight application signal W3 input to the third input terminal 3 the output of the third post-cursor (3 ^rd post cursor) can be removed component. the second interference cancellation circuit 120 is the second-first shift register 321 is input to the fourth input terminal (4) 4 ^th post cursor component in response to the second output signal D_outB and the fourth weighted application signal W4, The output signals of the first and second sampling signals D_sA and D_sB and the shift registers 311, 312, 321 and 322, which are input to the first to fourth input terminals 1 to 4, And the first to fourth weighted signals W1, W2, W3 and W4 include the amount of the cursor component to be removed . The first interference cancellation circuit 110 and the second interference cancellation circuit 120 receive the input signal D_in while the input signal D_in may be a differential signal and the first interference cancellation circuit The second interference cancellation circuit 120, the first and second sampling circuits 210 and 220 and the first and second shift registers 310 and 320 may be realized as a differential circuit .

The second sampling circuit 220 may sample the second interference cancellation signal D_icB in response to the clock CLK and output the sampled result as the second sampling signal D_sB. The second sampling circuit 220 may be implemented as a latch type sense amplifier.

The second -1 shift register 321 may shift the second sampling signal D_sB by a predetermined period of the clock CLK and output the shifted second sampling signal D_sB as the second output signal D_outB. At this time, the second shift register 320 may be implemented as a flip-flop.

The second-second shift register 322 may shift the second sampling signal D_sB by a predetermined period of the clock bar CLK_b having an opposite phase to the clock CLK. At this time, the second-second shift register 322 may be implemented as a flip-flop.

The weight control circuit 400 may store information on each of the first to fourth weighted signals W1, W2, W3 and W4. The first to fourth weighted signals W1 and W2 , W3, and W4, and outputs the determined voltage level.

The first interference cancellation circuit 110 may include a buffer 111 and first to fourth cursor component removal circuits 112, 113, 114 and 115 as shown in FIG. The detailed configuration of the buffer 111 and the first to fourth cursor component removal circuits 112, 113, 114, and 115 has been described above, and therefore will not be described.

Each of the first to fourth cursor component removal circuits 112, 113, 114 and 115 is connected to a sink terminal VSS according to the voltage level of each of the weighted signals W1, W2, W3 and W4 inputted thereto. The amount of current can be determined. The first to fourth cursor component removing circuits 112, 113, 114, and 115 are configured to remove the first and second sampling signals D_sA and D_sB and the shift registers 311, 312, 321, and 322, (1 ^st post cursor, 2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) is determined by flowing the sink current to the ground terminal (VSS) .

The symbol interference cancellation circuit according to the embodiment of the present invention configured as described above can operate as follows.

The input signal D_in is input to the first and second interference elimination circuits 110 and 120.

The first and second interference cancellation circuits 110 and 120 receive the output signals of the first and second sampling signals D_sA and D_sB, the shift registers 311, 312, 321 and 322, It is possible to remove the inter-symbol interference of the input signal D_in in response to the applied signals W1, W2, W3 and W4 and generate the first and second interference cancellation signals D_icA and D_icB, .

The first interference cancellation circuit 110 receives the input signal D_in inputted to the first interference elimination circuit 110 in response to the second sampling signal D_sB and the first weighted signal W1, it is possible to remove the first post-cursor (1 ^st post cursor) component. The first interference cancellation circuit 110 receives the input signal D_in input to the first interference cancellation circuit 110 in response to the first sampling signal D_sA and the second weight application signal W2, it is possible to remove the two post cursor (2 ^nd post cursor) component. The first interference cancellation circuit 110 is responsive to the output signal of the second-second shift register 322 and the third weight application signal W3 to receive the input it is possible to eliminate the post-cursor 3 (3 ^rd post cursor) component of the signal (D_in). The first interference cancellation circuit 110 is responsive to the output signals of the first-shift register 311, i.e., the first output signal D_outA and the fourth weight application signal W4, The 4 ^th post cursor component of the input signal D_in input to the elimination circuit 110 may be removed. The second interference cancellation circuit 120 receives the input signal D_in input to the second interference cancellation circuit 120 in response to the first sampling signal D_sA and the first weighted application signal W1, it is possible to remove the first post-cursor (1 ^st post cursor) component. The second interference cancellation circuit 120 receives the second input signal D_in input to the second interference cancellation circuit 120 in response to the second sampling signal D_sB and the second weighted application signal W2, it is possible to remove the two post cursor (2 ^nd post cursor) component. The second interference cancellation circuit 120 is responsive to the output signal of the first-second shift register 312 and the third weight application signal W3 to generate the second interference cancellation signal it is possible to eliminate the post-cursor 3 (3 ^rd post cursor) component of the signal (D_in). The second interference cancellation circuit 120 is responsive to the output signal of the 2-1 shift register 321, i.e., the second output signal D_outB and the fourth weighted application signal W4, The 4 ^th post cursor component of the input signal D_in input to the elimination circuit 120 may be removed. At this time, the weight control circuit 400 may output the first through fourth weighted signals W1, W2, W3, and W4 whose voltage levels are determined according to the inter-symbol interference information. The weight control circuit 400 includes the first through fourth post-cursor ^{(1 st post cursor, 2 nd} post cursor, 3 rd post cursor, 4 th post cursor) of the first to fourth weighting according to the interference amount of the component W2, W3 and W4 of the determined voltage level and the first to fourth weighted signals W1, W2, W3 and W4 of the determined voltage level.

The first sampling circuit 210 may sample the first interference cancellation signal D_icA in response to the clock CLK and output the sampled signal as the first sampling signal D_sA.

The second sampling circuit 220 may sample the second interference cancellation signal D_icB in response to the clock CLK and output the sampled signal as the second sampling signal D_sB.

The first shift register 311 shifts the first sampling signal D_sA by a predetermined period (for example, one period) of the clock CLK and outputs the shifted first sampling signal D_sA as the first output signal D_outA .

The first-second shift register 312 may shift the first sampling signal D_sA by a predetermined period (for example, one period) of the clock bar CLK_b and output the shifted first sampling signal D_sA.

The second -1 shift register 321 shifts the second sampling signal D_sB by a predetermined period (for example, one cycle) of the clock CLK and outputs the shifted second sampling signal D_sB as the second output signal D_outB .

The second-second shift register 322 may shift the second sampling signal D_sB by a predetermined period (for example, one period) of the clock bar CLK_b.

Removing the other symbol interference to the embodiment of the present invention shown in Figure 4 the circuit is in the removed-symbol interference according to an embodiment of the invention the circuit differs from the third post-cursor (3 ^rd post cursor) components shown in Figure 3 Removal timing. Shifting the first and second sampling signals D_sA and D_sB using the clock bar CLK_b which is half the period of the clock CLK and shifting the shifted first and second sampling signals D_sA and D_sB the third post-cursor (3 ^rd post cursor) is used to remove component. Therefore, the removal-symbol interference according to an embodiment of the invention shown in Figure 4 circuit is compared with the symbol interference cancellation circuit in accordance with an embodiment of the invention shown in Figure 2, the third post-cursor component (3 ^rd post cursor) Can be made earlier by a half period of the clock (CLK), so that the response speed of the symbol interference elimination circuit can be increased.

5, the symbol interference elimination circuit according to the embodiment of the present invention includes first and second interference elimination circuits 110-1 and 120-1, first and second sampling circuits 210 and 220, A first-second shift register 311, a first-second shift register 312, a second-first shift register 321, a second-second shift register 322, a weight control circuit 400, (500, continuous time linear equalizer, continuous time linear equalizer).

The first said CTLE (500) removes the first post-cursor (1 ^st post cursor) of the input signal (D_in) by receiving the input signal (D_in), in response to the first weighted signal (CW), and a post-cursor (1 ^st post cursor) is removed the input signal (D_in) ingredients can be output as a preliminary interference cancellation signal (D_icp).

The first interference cancellation circuit 110-1 is responsive to the output signals of the second through fourth weighted signals W2, W3 and W4, the first sampling signal D_sA and the shift registers 311 and 322 (2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) components of the preliminary interference cancellation signal (D_icp) input to the first interference cancellation circuit (110 - 1) It is possible to generate the first interference cancellation signal D_icA. For example, the first interference cancellation circuit 110-1 may include a first interference elimination circuit 110-1 responsive to the first sampling signal D_sA and the second weight application signal W2 input to the second input 2, cursor (2 ^nd post cursor) can be removed component. The first interference cancellation circuit 110-1 is responsive to the output signal of the second-second shift register 322 and the third weight application signal W3 input to the third input terminal 3, You can remove the post cursor (3 ^rd post cursor) component. The first interference cancellation circuit 110-1 receives the output signal of the first-first shift register 311 input to the fourth input terminal 4, that is, the first output signal D_outA, in response to the applied signal (W4) and the fourth post-cursor may be removed (4 ^th post cursor) component. The output signals of the first sampling signal D_sA and the shift registers 311 and 322 inputted to the second to fourth input terminals 2 to 4 of the first interference cancellation circuit 110-1 are connected to the output terminal And the second to fourth weighted signals W2, W3, W4 may include the amount of the cursor component to be removed.

The first sampling circuit 210 may sample the first interference cancellation signal D_icA in response to the clock CLK and output a result of the sampling as the first sampling signal D_sA. The first sampling circuit 210 may be implemented as a latch type sense amplifier.

The first shift register 311 may shift the first sampling signal D_sA by a predetermined period of the clock signal CLK and output the shifted first sampling signal D_sA as the first output signal D_outA. At this time, the first shift register 310 may be implemented as a flip-flop.

The 1-2 shift register 312 may shift and output the first sampling signal D_sA by a predetermined period of the clock bar CLK_b having the opposite phase of the clock CLK. At this time, the 1-2 shift register 312 may be implemented as a flip-flop.

The second interference cancellation circuit 120-1 is responsive to the output signals of the second through fourth weighted signals W2, W3 and W4, the second sampling signal D_sB and the shift registers 312 and 321 (2 ^nd post cursor, 3 ^rd post cursor, 4 ^th post cursor) components of the preliminary interference cancellation signal (D_icp) input to the second interference cancellation circuit 2 interference cancellation signal D_icB. For example, the second interference cancellation circuit 120-1 may receive the second sampling signal D_sB and the second weight application signal W2, which are input to the second input 2, cursor (2 ^nd post cursor) can be removed component. The second interference cancellation circuit 120-1 is responsive to the output signal of the first-second shift register 312 and the third weight application signal W3 input to the third input terminal 3, You can remove the post cursor (3 ^rd post cursor) component. The second interference cancellation circuit 120 receives the output signal of the 2-1 shift register 321 input to the fourth input terminal 4, that is, the second output signal D_outB and the fourth weighted application signal in response to (W4) and the fourth post-cursor may be removed (4 ^th post cursor) component. The first and second sampling signals D_sA and D_sB and the shift registers 311 and 312 and 321 input to the second to fourth input terminals 2 to 4 of the second interference cancellation circuit 120 The output signal includes the timing of removing the cursor component, and the second through fourth weighted signals W2, W3, W4 may include the amount of the cursor component to be removed. The first interference cancellation circuit 110-1 and the second interference cancellation circuit 120-1 receive the preliminary interference cancellation signal D_icp while the preliminary interference cancellation signal D_icp may be a differential signal The first interference cancellation circuit 110-1, the second interference cancellation circuit 120-1, the first and second sampling circuits 210 and 220, and the 1-1, 1-2, and 2-1 , And 2-2 shift registers 311, 312, 321, and 322 may be implemented as differential circuits.

The second sampling circuit 220 may sample the second interference cancellation signal D_icB in response to the clock CLK and output the sampled result as the second sampling signal D_sB. The second sampling circuit 220 may be implemented as a latch type sense amplifier.

The second -1 shift register 321 may shift the second sampling signal D_sB by a predetermined period of the clock CLK and output the shifted second sampling signal D_sB as the second output signal D_outB. At this time, the second shift register 320 may be implemented as a flip-flop.

The second-second shift register 322 may shift the second sampling signal D_sB by a predetermined period of the clock bar CLK_b having an opposite phase to the clock CLK. At this time, the second-second shift register 322 may be implemented as a flip-flop.

The weight control circuit 400 may store information on each of the first to fourth weighted signals W1, W2, W3 and W4. The first to fourth weighted signals W1 and W2 , W3, and W4, and outputs the determined voltage level.

The first interference cancellation circuit 110-1 includes components constituting the first interference cancellation circuit 100 shown in FIG. 3, that is, a buffer 111 and first to fourth cursor component removal circuits 112, 113, 114, and 115. In this case, the first cursor component removal circuit 112 may be omitted. The detailed configuration of the buffer 111 and the second to fourth cursor component removal circuits 113, 114 and 115 has been described above, and therefore will not be described.

Each of the second to fourth cursor component removal circuits 113, 114 and 115 detects the amount of the sink current flowing to the ground terminal VSS according to the voltage level of each of the weighted signals W2, W3 and W4 inputted thereto You can decide. The second to fourth cursor component removal circuits 113, 114, and 115 may also be configured to ground the sink current in response to the first sampled signal D_sA and the output signals of the shift registers 311 and 322, However as the shedding (VSS), the first may determine the removing timing of the second to fourth post-cursor ^{(2 nd post cursor, 3 rd} post cursor, 4 th post cursor).

The symbol interference cancellation circuit according to the embodiment of the present invention configured as described above can operate as follows.

Input signal (D_in) is inputted to CTLE (500) of claim 1, the post-cursor (1 ^st post cursor) component is removed, is output as the interference pre-cancellation signal (D_icp). The preliminary interference cancellation signal D_icp is input to the first and second interference cancellation circuits 110-1 and 120-1.

The first and second interference cancellation circuits 110-1 and 120-1 receive the output signals of the first and second sampling signals D_sA and D_sB, the shift registers 311, 312, 321 and 322, (D_icB) and the second interference cancellation signal (D_icA, D_icB) from which the interference has been removed in response to the first to fourth weighted signals (W2, W3, W4) Can be generated.

The first interference cancellation circuit 110-1 receives the first interference signal D_sA and the second weight application signal W2 in response to the first interference cancellation circuit 110-1, it is possible to remove the two post cursor (2 ^nd post cursor) component of the canceling signal (D_icp). The first interference cancellation circuit 110-1 is connected to the first interference cancellation circuit 110-1 in response to the output signal of the second -2 shift register 322 and the third weight application signal W3, the removal of the inputted the pre-interference signal (D_icp) 3 post-cursor (3 ^rd post cursor) can be removed component. The first interference cancellation circuit 110-1 receives the output signal of the first-order shift register 311, that is, the first output signal D_outA and the fourth weight application signal W4, The 4 ^th post cursor component of the preliminary interference cancellation signal D_icp input to the 1 interference elimination circuit 110-1 can be removed. The second interference cancellation circuit 120-1 receives the second interference cancellation signal 120-1 in response to the second sampling signal D_sB and the second weight application signal W2, it is possible to remove the two post cursor (2 ^nd post cursor) component of the canceling signal (D_icp). The second interference cancellation circuit 120-1 is connected to the second interference cancellation circuit 120-1 in response to the output signal of the first-second shift register 312 and the third weight application signal W3. the removal of the inputted the pre-interference signal (D_icp) 3 post-cursor (3 ^rd post cursor) can be removed component. The second interference cancellation circuit 120-1 is responsive to the output signal of the 2-1 shift register 321, that is, the second output signal D_outB and the fourth weight application signal W4, 2, interference cancellation circuit of claim 4 wherein the pre-post of the interference cancellation signal (D_icp) input to the (120-1), the cursor can be removed (4 ^th post cursor) component. At this time, the weight control circuit 400 may output the first through fourth weighted signals CW, W2, W3, and W4 whose voltage levels are determined according to the inter-symbol interference information. The weight control circuit 400 includes the first through fourth post-cursor ^{(1 st post cursor, 2 nd} post cursor, 3 rd post cursor, 4 th post cursor) of the first to fourth weighting according to the interference amount of the component W2, W3 and W4 of the determined voltage level and the voltage levels of the applied signals CW, W2, W3 and W4, and store the first to fourth weighted signals W1, W2, W3 and W4 of the determined voltage level.

The first sampling circuit 210 may sample the first interference cancellation signal D_icA in response to the clock CLK and output the sampled signal as the first sampling signal D_sA.

The second sampling circuit 220 may sample the second interference cancellation signal D_icB in response to the clock CLK and output the sampled signal as the second sampling signal D_sB.

The first shift register 311 shifts the first sampling signal D_sA by a predetermined period (for example, one period) of the clock CLK and outputs the shifted first sampling signal D_sA as the first output signal D_outA .

The first-second shift register 312 may shift the first sampling signal D_sA by a predetermined period (for example, one period) of the clock bar CLK_b and output the shifted first sampling signal D_sA.

The second -1 shift register 321 shifts the second sampling signal D_sB by a predetermined period (for example, one cycle) of the clock CLK and outputs the shifted second sampling signal D_sB as the second output signal D_outB .

The second-second shift register 322 may shift the second sampling signal D_sB by a predetermined period (for example, one period) of the clock bar CLK_b.

Removing the other symbol interference to the embodiment of the present invention shown in Figure 5 the circuit is in the removed exemplary symbol interference according to an embodiment of the present invention, the circuit differs from the third post-cursor (3 ^rd post cursor) components shown in Fig. Removal timing. Shifting the first and second sampling signals D_sA and D_sB using the clock bar CLK_b which is half the period of the clock CLK and shifting the shifted first and second sampling signals D_sA and D_sB the third post-cursor (3 ^rd post cursor) is used to remove component. Therefore, the removed-symbol interference according to an embodiment of the invention the circuit is compared with the symbol interference cancellation circuit in accordance with an embodiment of the invention shown in Figure 3, the third post-cursor component shown in Figure 5 (3 ^rd post cursor) Can be made earlier by a half period of the clock (CLK), so that the response speed of the symbol interference elimination circuit can be increased.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (10)

A continuous time linear equalizer (CTLE) for generating a pre-interference cancellation signal by removing a first post-cursor component of the input signal according to the first weighted signal;
The second postcursor component of the preliminary interference cancellation signal, the third postcursor component, and the fourth postcursor component of the preliminary interference cancellation signal in accordance with the second weighted signal, the third weighted signal, the fourth weighted signal, the sampling signal, An interference cancellation circuit for removing the component to generate an interference cancellation signal;
A sampling circuit for sampling the interference cancellation signal in response to a clock and outputting the sampled interference cancellation signal as the sampling signal; And
Shifting the sampling signal by a predetermined period of a clock bar whose phase is opposite to that of the clock and shifting the sampling signal by a predetermined period of the clock to provide shifted signals to the interference eliminating circuit Symbol interference cancellation circuit. The method according to claim 1,
And a weight control circuit for storing and outputting the first to fourth weighted signals. The method according to claim 1,
The shift registers
At least one first shift register for shifting the sampling signal by a predetermined period of the clock and outputting the sampled signal in response to the clock,
And at least one second shift register for shifting the sampling signal by a predetermined period of the clock bar in response to the clock bar and outputting the sampled signal. The method according to claim 1,
The interference cancellation circuit
A buffer for receiving the preliminary interference cancellation signal input to the interference cancellation circuit,
And cursor removing circuits connected to an output terminal of the buffer for removing the second through fourth post-cursor components in response to the output signals of the second through fourth weighted signals, the sampling signal, and the shift registers A symbol interference cancellation circuit. 5. The method of claim 4,
Each of the cursor component removal circuits
At least one first transistor to which an output terminal of the buffer is connected to a drain and to which an output signal of a shift register corresponding to a gate or the sampling signal is input;
And a second transistor having a drain connected to the source of the first transistor, a gate to which a weighting signal corresponding to the gate is input, and a ground terminal connected to the source. A continuous time linear equalizer (CTLE) for generating a pre-interference cancellation signal by removing a first post-cursor component of the input signal according to the first weighted signal;
The second weighting applied signal, the fourth weighted signal, the first weighted signal, the second weighted signal, the third weighted signal, the fourth weighted signal, the first sampled signal, the first shift register, A first interference cancellation circuit for generating a first interference cancellation signal by removing a post-cursor component, a third post-cursor component, and a fourth post-cursor component;
In accordance with the output signals of the first weight application signal, the second weight application signal, the third weight application signal, the fourth weight application signal, the second sampling signal, the 1-2 shift register, and the 2-1 shift register, The second post-cursor component, and the fourth post-cursor component of the second interference cancellation signal to generate a second interference cancellation signal,
A first sampling circuit for sampling the first interference cancellation signal in response to a clock and outputting the sampled first interference cancellation signal as the first sampling signal;
A sampling circuit for sampling the second interference cancellation signal in response to the clock and outputting the sampled second interference cancellation signal as the second sampling signal;
A first shift register for shifting the first sampling signal by a predetermined period of the clock and outputting the shifted first sampling signal;
A first 1-2 shift register for shifting the first sampling signal by a set period of a clock bar whose phase is opposite to the clock and outputting the shifted first sampling signal;
A second-1 shift register for shifting the second sampling signal by a predetermined period of the clock and outputting the shifted second sampling signal; And
And the 2 < nd > -signal shift register for shifting and outputting the second sampling signal by a predetermined period of the clock bar. The method according to claim 6,
And a weight control circuit for storing and outputting the first to fourth weighted signals. The method according to claim 6,
And the preliminary interference cancellation signal is a differential signal. The method according to claim 6,
The first interference cancellation circuit
A buffer for buffering the preliminary interference cancellation signal,
A second cursor component removal circuit for removing the second post cursor component in response to the first sampling signal and the second weight application signal,
A third cursor component removal circuit for removing the third post-cursor component in response to the output signal of the second-2 shift register and the third weighted application signal, and
And a fourth cursor component removal circuit for removing the fourth postcursor component in response to the output signal of the first-first shift register and the fourth weighted application signal. The method according to claim 6,
The second interference cancellation circuit
A buffer for buffering the preliminary interference cancellation signal,
A second cursor component removal circuit for removing the second post-cursor component in response to the second sampling signal and the second weighted signal,
A third cursor component removal circuit for removing the third post-cursor component in response to the output signal of the first-second shift register and the third weighted signal, and
And a fourth cursor component removal circuit for removing the fourth postcursor component in response to the output signal of the 2-1 shift register and the fourth weighted application signal.

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