KR20180064274A - Can controller and method for transmission of data using the same - Google Patents

Abstract

The present invention relates to a CAN controller and a data transmission method using the same. A CAN controller according to an embodiment of the present invention includes a receiver, a reception FIFO memory, a transmission FIFO memory, and a transmitter. The receiver analyzes reception information received from a CAN bus according to a set protocol. The reception FIFO memory stores the reception information to be overwritten with previously stored reception information on the basis of a bus load and identification data of the reception information. The transmission FIFO memory stores transmission information to be overwritten on previously stored transmission information on the basis of a processor load and identification data of the transmission information. The transmitter sets a protocol and transmits transmission information stored in the transmission FIFO memory to the CAN bus according to a set protocol. According to the present invention, various CAN protocols are supported, and rapidness of CAN communications is secured.

Description

CAN CONTROLLER AND METHOD FOR TRANSMISSION OF DATA USING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an architecture supporting a CAN (Controller Area Network) as a network standard for vehicles, and more particularly, to a CAN controller and a data transmission method using the same.

A CAN (Controller Area Network) is used as a standard communication standard as a vehicle network protocol for communication between ECU (Electronic Control Unit) or peripheral electronic equipments in a vehicle system. Since the number of electronic control devices included in the conventional vehicle system is limited, each electronic control device is connected by a point-to-point connection method. However, the point-to-point wiring scheme can increase the complexity, cost, weight, and the like of the connection as the number of electronic control devices increases. Since CAN communication uses a serial bus network scheme, communication between various electronic control devices is easy.

CAN communication is designed so that electronic control devices communicate with each other via a CAN bus without a host. To this end, the electronic control device may comprise a CAN controller connected to the CAN bus. The CAN controller controls the communication between the electronic control unit and the CAN bus. The vehicle system requires rapid data communication in order to secure the safety of the occupant. Accordingly, there is a demand for a CAN controller capable of minimizing the delay of data communication and securing the speed of CAN communication.

CAN 2.0 A and CAN 2.0 B are used as protocols for CAN communication. In addition, CAN 2.0 A FD and CAN 2.0 B FD have been recently developed. The structures of the data frames of CAN 2.0 A, CAN 2.0 B, CAN 2.0 FD, and CAN 2.0 B FD are different. Thus, there is a need for a CAN controller that is easily configurable to accommodate this type of protocol.

The present invention provides a CAN controller capable of supporting both CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD and securing the speed of CAN communication, and a data transmission method using the CAN controller.

A CAN controller according to an embodiment of the present invention includes an interface, a transmitter, a receiver, a receiving first-in-first-out memory, and a transmission first-in-first-out memory. The interface provides reception information stored in the reception first-in-first-out memory to the processor or receives transmission information from the processor.

The transmitter sets the protocol and transmits the transmission information stored in the transmission first-in-first-out memory to the CAN bus according to the protocol. The transmitter includes a protocol generator. The protocol generator may set the protocol by selecting target bit states of a data frame corresponding to the protocol among a plurality of bit states. The protocol generator may sequentially transition the respective target bit states to determine the data frame of the transmission information. The protocol generator may select one of the CAN 2.0 A protocol, the CAN 2.0 B protocol, the CAN 2.0 A FD protocol, and the CAN 2.0 B FD protocol, and may select target bit states based on the selected protocol.

The receiver analyzes the received information received from the CAN bus according to the established protocol. The receiver may include a protocol analyzer, a masking filter register, a baud rate adjuster, and an error detector. The protocol analyzer can analyze the received information by sequentially transitioning the target bit states. The masking filter register can filter the received information based on the identification data of the received information. The baud rate adjuster can adjust the baud rate of the data frame of the received information according to the established protocol. The error detector may detect an error in the reception information and determine whether to provide the reception information in the reception first-in-first-out memory.

The reception first-in-first-out memory stores the reception information so as to be overwritten with the reception information previously stored based on the identification data of the reception information and the bus load of the CAN bus. The transmission first-in-first-out memory stores the transmission information so as to be overwritten with the transmission information previously stored based on the identification data of the transmission information and the processor load.

The CAN controller further includes an identification data scanner, a bus load detector, and a processor load detector. For example, when the bus load is higher than the processor load, the identification data scanner can overwrite the reception information in the memory block of the reception first-in-first-out memory storing the information having the same identification data as the identification data of the reception information. For example, when the processor load is higher than the bus load, the identification data scanner can overwrite the transmission information in the memory block of the transmission first-in-first-out memory storing the information having the same identification data as the identification data of the transmission information. The bus load detector detects the bus load, and the processor load detector can detect the processor load.

A method of transmitting data in a CAN controller according to an embodiment of the present invention includes receiving data information, sensing an amount of data to be received, storing information having the same identification data as the identification data of the data information, Retrieving a memory block of the memory, and overwriting the data information in the memory block based on the amount of data information to be received.

In one example, the data information may be transmission information provided from the processor. At this time, sensing the amount of data information may include sensing a processor load, comparing the processor load and the bus load. In the step of overwriting the data information, if the processor load is greater than the bus load or the set reference load value, the transmission information can be overwritten. The data transfer method of the CAN controller may further include sequentially outputting the information stored in the first-in first-out memory to the CAN bus.

In one example, the data information may be received information provided from the CAN bus. At this time, sensing the amount of data information may include sensing a bus load of the CAN bus, comparing the processor load and the bus load. In the step of overwriting the data information, if the bus load is larger than the processor load or the set reference load value, the received information can be overwritten. The data transfer method of the CAN controller may further include sequentially outputting the information stored in the first-in first-out memory to the processor.

The CAN controller and the data transmission method using the CAN controller according to the embodiment of the present invention can support various CAN protocols by setting the order of state transition and can overwrite the data in the first-in first-out memory according to the bus load and the processor load, It is possible to secure the promptness of the user.

1 is a block diagram of a CAN system according to an embodiment of the present invention.
2 is a block diagram of the CAN controller included in FIG.
Figure 3 is a block diagram embodying the protocol engine of Figure 2;
4 is a diagram showing the structure of a data frame for the CAN 2.0 A protocol.
5 is a diagram showing the structure of a data frame for the CAN 2.0 B protocol.
6 is a diagram showing the structure of a data frame for the CAN 2.0 A FD protocol.
7 is a diagram showing the structure of a data frame for the CAN 2.0 B FD protocol.
FIG. 8 is a block diagram embodying the data buffer unit of FIG. 2 or FIG. 3. FIG.
9 is a flowchart illustrating a method of transmitting received information according to an embodiment of the present invention.
10 is a flowchart illustrating a method of transmitting transmission information according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention. In the following, a CAN controller for CAN (Controller Area Network) communication carries transmission information or reception information. The transmission information and the reception information can be formally changed in part by various causes such as protocol setting of the CAN controller, baud rate adjustment, bit stuffing, or clock synchronization. If the meaning of the data included in each of the transmission information and the reception information is maintained, it is referred to as transmission information and reception information without changing the term, even if the format of the transmission information and the reception information change from the viewpoint of efficiency of data communication or minimization of errors will be.

1 is a block diagram of a CAN system according to an embodiment of the present invention. The CAN system 100 may be a system that performs communication by any of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols described below. Referring to FIG. 1, the CAN system 100 may include first to third electronic control devices 110 to 130 and a CAN bus 140. Although three electronic control devices have been illustrated illustratively, there is no limit to the number of electronic control devices. The CAN system 100 can be applied to various fields using the CAN protocol. For example, the CAN system 100 may be a vehicle system.

The first electronic control device 110 includes a first processor 112 and a first CAN controller 114. The second electronic control device 120 includes a second processor 122 and a second CAN controller 124. The third electronic control device 130 includes a third processor 132 and a third CAN controller 134. Each of the first to third electronic control devices 110 to 130 is connected to the CAN bus 140 to perform communication. For example, when the CAN system 100 is a vehicle system, each of the first to third electronic control devices 110 to 130 may be an apparatus for electronically controlling various vehicle devices such as an engine, a handle, and a brake .

The first to third processors 112 to 132 may perform a function of a central processing unit (CPU) for the corresponding electronic control unit. For example, when the first electronic control device 110 is an ECU for controlling the engine, the first processor 112 may perform the control operation and the arithmetic operation required to control the engine. The first processor 112 may provide information generated by these control operations and operation operations to the first CAN controller 114 as a transmit signal. In addition, the first processor 112 may receive information generated from the second processor 122 or the third processor 132 from the first CAN controller 114. Thus, the electronic control device can interact with other electronic control devices, and through this interaction complex functions such as autonomous driving can be performed.

The first to third CAN controllers 114 to 134 control transmission / reception of information to / from the corresponding electronic control unit. Each of the first to third CAN controllers 114 to 134 provides the CAN bus 140 with information including identification data. Each of the first to third CAN controllers 114 to 134 analyzes the identification data of the information provided on the CAN bus 140 to determine whether to receive the information. The identification data indicates the attribute of the corresponding information, and each of the first to third CAN controllers 114 to 134 can determine through the identification data whether the information is necessary for driving the corresponding electronic control unit.

Each of the first to third CAN controllers 114 to 134 can integrally support various CAN protocols. Each of the first to third CAN controllers 114 to 134 senses a load of a corresponding one of the first to third processors 112 to 132 or a load of the CAN bus 140, Information or reception information can be overwritten. Therefore, the efficiency of the CAN system 100 can be ensured, delay in transmission of information due to the load can be prevented, and stability can be secured. The specific contents of overwriting the transmission information or the reception information will be described later.

The CAN bus 140 may provide a communication path between the first to third electronic control devices 110 to 130 of the CAN system 100. The first to third electronic control devices 110 to 130 can exchange information with each other via the CAN bus 140. [ In the case of using the CAN bus 140, since information is exchanged without directly connecting each of the electronic control devices, efficiency can be secured in terms of the complexity, cost, and weight of the connection between the electronic control devices.

2 is a block diagram of the CAN controller included in FIG. On the aspect of the explanation, referring to the reference numerals of Fig. 1, the configurations of Fig. 2 will be described. The CAN controller 200 can be regarded as the first to third CAN controllers 114 to 134 of FIG. Hereinafter, the CAN bus will be described with reference to the reference numerals of the CAN bus 140 in Fig. 1, and the following processor will be described with reference to the reference numerals of the first processor 112 in Fig.

Referring to FIG. 2, the CAN controller 200 includes a synchronizer 210 and a protocol engine 220. The protocol engine 220 includes an interface 221, a data buffer 222, and a transceiver 223. The CAN controller 200 may be included in the first to third electronic control devices 110 to 130. The CAN controller 200 receives data information from the processor 112 and can output the data information to the CAN bus 140. Alternatively, the CAN controller 200 may receive the data information from the CAN bus 140 and output the data information to the processor 112.

The synchronizer 210 may be coupled to the processor 112 to perform data communication. The synchronizer 210 may be coupled to the processor 112 via a peripheral bus. For example, the peripheral bus may be an Advanced Peripheral Bus (APB). The clock frequency and phase of the peripheral bus may differ from the clock frequency and phase of the CAN controller 200. In this case, CDC (Clock Domain Crossing) may be generated. The synchronizer 210 can synchronize the clock of the peripheral bus and the clock of the CAN controller 200.

Protocol engine 220 controls data communication between processor 112 and CAN bus 140. For this purpose, the protocol engine 220 may generate a protocol for data communication with the CAN bus 140. The protocol engine 220 may receive the transmission information of the processor 112 provided through the synchronizer 210. The protocol engine 220 may send the transmission information to the CAN bus 140. The transmission information provided to the CAN bus 140 may be provided to a CAN controller included in another electronic control unit. The protocol engine 220 may receive the received information provided via the CAN bus 140. The protocol engine 220 may send the received information to the synchronizer 210. The synchronizer 210 may provide the received information to the processor 112.

The interface 221 may be implemented as a circuit that performs data communication between the protocol engine 220 and the processor 112. The interface 221 may provide the data buffer 222 with the transmission information received from the synchronizer 210. The interface 221 may receive the received signal from the data buffer 222 and provide it to the synchronizer 210. The received signal may be provided to the peripheral bus via the synchronizer 210 and provided to the processor 112.

The data buffer unit 222 may store the transmission information provided from the transceiver 223. The data buffer unit 222 may sequentially store the transmission information according to the flow of time, and may provide the transmission information to the interface 221 in the stored order. For this, the data buffer unit 222 may include a first-in first-out (FIFO) memory. In addition, the data buffer unit 222 may store reception information provided from the interface 221. The data buffer unit 222 may sequentially store reception information according to the flow of time, and may provide reception information to the transceiver 223 in a stored order. For this, the data buffer unit 222 may include a first-in-first-out memory.

The data buffer unit 222 can output data in the order in which data is input in a normal state. However, when the amount of data to be processed by the processor 112 is large or the amount of data provided to the CAN bus 140 is large, it may take time for the data buffer unit 222 to output all the data. Particularly, in a vehicle system in which the CAN communication method is frequently used, the delay of data output can be directly related to the safety of the passenger. In addition, it may be inefficient to delay the data output in order to output all data due to the characteristics of the vehicle system in which the surrounding situation changes rapidly in real time and the latest data is more important than the previous data. Therefore, when the amount of data information to be provided to the data buffer unit 222 is large, new data information can be overwritten on already stored data information. Details of this will be described later.

The transceiver 223 receives the transmission information from the data buffer unit 222 and transmits it to the CAN bus 140. The transceiver 223 receives the reception information from the CAN bus 140 and transmits it to the data buffer unit 222. The transceiver 223 can preset the protocol. The transceiver 223 may transmit the transmission information to the CAN bus 140 and receive the reception information from the CAN bus 140 according to the established protocol. The protocol may be either CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, or CAN 2.0 B FD. The transceiver 223 can support both CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD, and the protocol determined by the vehicle system can be selected. Details of this will be described later.

Figure 3 is a block diagram embodying the protocol engine of Figure 2; Referring to FIG. 3, the protocol engine 300 includes an interface 310, a data buffer 320, a receiver 330, and a transmitter 340. The interface 310 of FIG. 3 is substantially the same as the interface 221 of FIG. 2, so a detailed description is omitted. The data buffer unit 320 of FIG. 3 corresponds to the data buffer unit 222 of FIG. The receiver 330 and the transmitter 340 of FIG. 3 can be seen in the configuration included in the transceiver 223 of FIG.

The data buffer 320 includes a first-in first-out (FIFO) memory 322 and a transmission first-in-first-out memory 324. The reception first-in-first-out memory 322 and the transmission-first-in-first-out memory 324 in principle store data information in the order received and output the data information in the stored order. The reception first-in-first-out memory 322 stores reception information in the order received from the receiver 330. The first-in first-out memory 322 outputs the received information to the interface 310 in the stored order. The transmission first-in-first-out memory 324 stores transmission information in the order received from the interface 310. The transmission first-in-first-out memory 324 outputs transmission information to the transmitter 340 in the stored order. The reception first-in-first-out memory 322 and the transmission first-in-first-out memory 324 can be implemented by memos of the same kind.

The reception first-in-first-out memory 322 can store the reception information in place of the previously stored information according to the bus load of the CAN bus 140. The bus load is determined by the amount of data provided to the CAN bus 140. If the amount of data provided to the CAN bus is large, the bus load increases. If the bus load is large, the reception information to be stored in the reception first-in-first-out memory 322 may increase. In this case, the newly received received information can be overwritten on the received information having the same attribute. At this time, the reception information stored in the reception first-in-first-out memory 322 may be output to the interface 310 in the output order of the reception information deleted by overwriting.

The transmission first-in-first-out memory 324 may store the transmission information in place of the previously stored information according to the processor load of the processor 112. The processor load is determined by the amount by which processor 112 processes the data. If the amount of data processed in the processor 112 is large, the processor load increases. If the processor load is large, the transmission information to be stored in the transmission first-in-first-out memory 324 may increase. In this case, the newly received transmission information can be overwritten on the transmission information having the same attribute. At this time, the transmission information stored in the transmission first-in-first-out memory 324 can be output to the transmitter 340 in the output order of the transmission information deleted by overwriting.

The receiver 330 may receive the received information from the CAN bus 140. The receiver 330 may provide the received information to the data buffer 320. [ The reception information provided to the data buffer unit 320 may be stored in the reception first-in-first-out memory 322. The receiver 330 includes an error detector 331, a receive beam-rate adjuster 333, a masking filter register 334, and a protocol analyzer 335. The error detector 331 includes a counter 332.

The error detector 331 detects an error in the received information. For example, the error detector 331 may detect a bit error, a stuff error, a form error, a cyclic redundancy check (CRC) error, and an acknowledgment bit error. Bit errors occur when information sent from one node is not represented on the CAN bus. A stuff error occurs when six consecutive bit values in the CAN protocol can not appear in principle. A form error occurs when the bit value specified by 0 or 1 appears differently. The CRC error occurs when it is confirmed that some bits have been changed through the CRC calculation of the CRC area of the received information. The acknowledgment bit error is generated when the acknowledgment bit having a bit value of 0 has a different value when the receiver 330 receives the acknowledgment information without error. The counter 332 may count the number of errors detected by the error detector 331. [ If the number of detected errors is equal to or greater than a specific number, the error detector 331 can control the receiver 330 not to receive the reception information and provide it to the reception first-in-first-out memory 322.

The receive baud rate adjuster 333 adjusts the baud rate of the received information. The receive-rate-adjuster 333 adjusts the baud rate of the data area included in the received information according to the set protocol. For example, the receive-rate adjuster 333 may adjust the clock so that the data area is transmitted at a maximum of 1 Mbps when the protocol is set to CAN 2.0 A or CAN 2.0 B. The receive baud rate adjuster 333 can adjust the clock so that the data area is transmitted at a maximum of 8 Mbps when the protocol is set to CAN 2.0 A FD or CAN 2.0 B FD. The receive beam-rate adjuster 333 may not adjust the baud rate of other areas except the data area regardless of the set protocol. For example, the receive-rate adjuster 333 may maintain the baud rate of the intervening area, the control area, the CRC area, and the acknowledgment area to be described later at 1 Mbps. In addition, the receive beam-rate adjuster 333 can additionally change the sampling position of the received information.

The masking filter register 334 may filter the received information based on the identification data of the received information. The identification data may be provided in an arbitration area included in the data frame of the received information. The masking filter register 334 can set the identification data of the reception information to be received by the receiver 330 and provided to the reception first-in-first-out memory 322. For example, if the identification data of the received information matches the value of the set identification data, the receiver 330 may provide the received information to the receive first-in-first-out memory 322. [ If the identification data of the received information is different from the value of the set identification data, the receiver 330 may not provide the received information to the first-in-first-out memory 322. [ Conversely, the masking filter register 334 can set the identification data of the reception information that is not to be provided to the reception first-in-first-out memory 322.

The protocol analyzer 335 is connected to the CAN bus 140 to receive the received information. The protocol analyzer 335 analyzes the received information according to the set protocol. The protocol analyzer 335 can analyze the data frame of the reception information sequentially according to the structure of the data frame by the set protocol. The structures of the bits contained in the data frames of each of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 FD, and CAN 2.0 B FD protocols are different. Therefore, the state transitions for analyzing the received information may be different according to the set protocol. A concrete example of such state transition will be described later.

Based on the received information analyzed by the protocol analyzer 335, the error detector 331 can recognize the position of the bit required for error detection and detect an error. Based on the analyzed received information, the receive beam-rate adjuster 333 can recognize the position of the data area and adjust the baud rate of the data area according to the set protocol. Based on the analyzed reception information, the masking filter register 334 can recognize the position of the arbitration area and the identification data, and can determine whether to provide the reception information.

The protocol analyzer 335 may remove the stuff bits of the data frames of the received information. As described above, six consecutive bit values can not appear in the CAN protocol. To this end, the reception information provided to the receiver 330 includes a stuff bit having a bit value opposite to the consecutive bit value at the sixth bit when five consecutive bit values are present. The protocol analyzer 335 may remove such stuff bits. In addition, the protocol analyzer 335 can adjust the received information so that the acknowledgment bit has a value of 0 to 1 when receiving information is received without error.

The transmitter 340 may receive the transmission information from the data buffer 320. Transmitter 340 may provide transmit information to CAN bus 140. The transmitter 340 includes a transmit beam-rate adjuster 343 and a protocol generator 345. The transmit beam-rate adjuster 343 adjusts the baud rate of the data area included in the transmit information, similar to the receive beam-rate adjuster 333 included in the receiver 330. [ That is, the transmit beam-rate adjuster 343 can adjust the clock so that the data area is transmitted at a maximum of 1 Mbps when the protocol is set to CAN 2.0 A or CAN 2.0 B. The transmit beam-rate adjuster 343 can adjust the clock so that the data area is transmitted at a maximum of 8 Mbps when the protocol is set to CAN 2.0 A FD or CAN 2.0 B FD.

The protocol generator 345 is connected to the CAN bus 140 to transmit the transmission information. The protocol generator 345 sets the protocol. The protocol generator 345 can integrate CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. The protocol generator 345 may select the protocol to match the type of protocol for that vehicle system. For example, if the system containing the CAN controller supports the CAN 2.0 A protocol, the protocol generator 345 may set the protocol to have a data frame corresponding to CAN 2.0 A.

The protocol generator 345 may determine each of the bits of the transmission information according to the established protocol. In order to determine the bits of such transmission information, the protocol generator 345 may determine all bit states of the data frames included in the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. The protocol generator 345 may select the target bit states according to the protocol set among all the bit states. The protocol generator 345 may sequentially transition the selected target bit states to determine a data frame of transmission information. Table 1 shows the state transitions of these data frames.

domain Bit state CAN 2.0 A CAN 2.0 B CAN 2.0 A FD CAN 2.0 B FD SOF SOF O O O O Mediation area




ID1 O O O O SRR X O X O IDE X O X O ID2 X O X O RTR O O X X R1 X X O O Control area





IDE O X O X R1 X O X X EDL X X O O R0 O O O O BRS X X O O ESI X X O O DLC O O O O Data area DATA O O O O CRC area

SC X X O O CRC O O O O CRC_D O O O O Confirmation area
ACK O O O O ACK_D O O O O EOF EOF O O O O

Referring to Table 1, a data frame includes a start of frame, an arbitration field, a control field, a data field, a CRC field, an Acknowledge Field ), And end frame (End of frame). The arbitration area includes a first identification data ID1, a Substitute Remote Request (SRR) bit, an IDE (Identifier extension) bit, a second identification data ID2, a Remote Transmission Request (RTR) Or the like. The control area includes an IDE bit, a first control area spare bit R1, an extended data length (EDL) bit, a second control area spare bit R0, a bit rate switch (BRS) bit, an error state indicator (ESI) And a data length code (DLC) bit. The CRC region may include at least one of an SC bit, a CRC bit, and a CRC Delimiter bit (CRC_D). The acknowledgment area may comprise acknowledgment bits (ACK) and acknowledgment bits (ACK_D).

The data frame of each of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols includes bits corresponding to the bit states marked 'O', and corresponding to bit states marked 'X' It does not contain any bits. The protocol generator 245 sequentially shifts the target bit states, which are the bit states indicated by 'O' in the set protocol, to determine the data frame of the transmission information. For example, when the CAN 2.0 A protocol is set, the protocol generator 245 generates a start frame (SOF), a first identification data ID1, a RTR bit, an IDE bit, a second control area spare bit R0, And the like to sequentially determine a data frame. At this time, the protocol generator 245 may determine the data frame by selecting the first identification data ID1, then skipping the SRR bit, the IDE bit of the arbitration area, and the second identification data and transiting to the RTR bit. A description of the bits corresponding to each bit state will be described later.

The protocol generator 345 may use a dedicated circuit such as an application specific integrated circuit (ASIC) to implement the state transition of Table 1. [ For example, a plurality of decision circuits for determining respective bit states can be connected in series, and a decision circuit corresponding to a bit state indicated by 'O' according to a set protocol is passed, and a bit state indicated by 'X' The corresponding decision circuit can be implemented to be bypassed. In addition, the protocol generator 345 may be implemented with software or firmware, and may be programmed to sequentially determine and analyze data frames by sequentially transitioning target bit states denoted by 'O'. The protocol analyzer 335 can also be implemented as a dedicated circuit, software or firmware to analyze data frames.

When the protocol generator 345 sends the transmission information to the CAN bus 140, it can transmit the transmission information to the CAN bus 140 simultaneously from other transmitters. In this case, the protocol generator 345 may arbitrate to transmit the transmission information to the CAN bus first in a high priority transmitter. The priority order can be determined based on the identification data of the transmission information. Protocol generator 345 may additionally add stuff bits. In the CAN protocol, the protocol generator 345 may add a stuff bit having a bit value opposite to the consecutive bit value at the sixth bit if five consecutive bit values appear.

The reception information or transmission information by the CAN protocol may include a remote frame, an error frame, and an overload frame as well as the above-described data frame. The remote frame may be used by the receiver 330 to request the transmission of information to the transmitter of another node. An error frame may be used to notify other nodes of an error detected when an error is detected in the received information. The overload frame may be used when the receiver 330 is not ready for receiving information. The data frames of each of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols may have different bit structures, but the remote frame, the error frame, and the overload frame have the same bit structure . Accordingly, the protocol generator 345 can determine the data frame by selecting the target bit states only for the data frame.

4 is a diagram showing the structure of a data frame for the CAN 2.0 A protocol. Referring to FIG. 4, a data frame for the CAN 2.0 A protocol is divided into a start frame, an arbitration area, a control area, a data area, a CRC area, a confirmation area, and an end frame (End). The data frame may have a length of 52 bits or more and 108 bits or less.

The arbitration area may include 11-bit identification data (ID) and 1-bit RTR bit. The identification data (ID) may indicate the attribute of the data frame. The priority of the data frame can be determined based on the identification data (ID). The RTR bit is used to determine the data frame and the remote frame, and may have a bit value of 0 in the data frame.

The control area may include a 1-bit IDE bit, a 1-bit reserved bit, and a 4-bit DLC bit. The IDE bit can be used to indicate that it is a CAN 2.0 A protocol with 11 bits of identification data (ID) and can have a bit value of zero. The DLC bit can be used to indicate the length of the data area. In the CAN 2.0 A protocol, the data area can have a length of 8 bits or more and 64 bits or less. Further, as described above, in the CAN 2.0 A protocol, the data area can be transmitted at a maximum of 1 Mbps.

The CRC area may include a 15-bit CRC bit and a 1-bit CRC partition bit. The CRC bits can be used to detect errors through a cyclic redundancy check. The CRC partition bit may be provided to distinguish the CRC region from the acknowledgment region and may have a bit value of one. The acknowledgment region may comprise a 1-bit acknowledgment bit and a 1-bit acknowledgment segment bit. The confirmation bit may be set to have a bit value of 1 in the transmission information and be provided to the CAN bus 140. The acknowledgment bit may be set to have a bit value of 0 if the received information is received without error. The confirmation partition bit may be provided to distinguish the confirmation frame from the end frame, and may have a bit value of 1.

5 is a diagram showing the structure of a data frame for the CAN 2.0 B protocol. Referring to FIG. 5, a data frame for the CAN 2.0 B protocol is divided into a start frame, an arbitration region, a control region, a data region, a CRC region, a confirmation region, and an end frame (End). The data frame may have a length of 72 bits or more and 128 bits or less.

The arbitration area may include 11-bit first identification data (ID1), 1-bit SRR bit, 1-bit IDE bit, 18-bit second identification data (ID2), and 1-bit RTR bit. The first identification data ID1 and the RTR bit perform the same function as the identification data (ID) and the RTR bit in Fig. The SRR bit and the IDE bit can be provided for distinction from the CAN 2.0 A protocol and can have a bit value of one. The protocol generator 345 or the protocol analyzer 335 of FIG. 2 can recognize the presence of the second identification data ID2 by analyzing the SRR bit and the IDE bit. The CAN 2.0 B protocol can present more diverse attributes and priorities of the data frame since the second identification data (ID2) is provided.

The control area may include a 2-bit reserved bit and a 4-bit DCL bit. The DLC bit can be used to indicate the length of the data area. In the CAN 2.0 B protocol, the data area can have a length of 8 bits or more and 64 bits or less. Also, as described above, in the CAN 2.0 B protocol, the data area can be transmitted at a maximum of 1 Mbps. The CRC region may include a 15-bit CRC bit and a 1-bit CRC segment bit, such as the CAN 2.0 A protocol of FIG. The acknowledgment region may comprise a 1-bit acknowledgment bit and a 1-bit acknowledgment segment bit, such as the CAN 2.0 A protocol of FIG.

6 is a diagram showing the structure of a data frame for the CAN 2.0 A FD protocol. Referring to FIG. 6, a data frame for the CAN 2.0 A FD protocol is divided into a start frame, an arbitration area, a control area, a data area, a CRC area, a confirmation area, and an end frame (End). The arbitration area may include 11-bit identification data (ID) and 1-bit RTR bit, as in the CAN 2.0 A protocol of FIG.

The control area may include a 1-bit IDE bit, a 1-bit EDL bit, a 1-bit reserved bit, a 1-bit BRS bit, a 1-bit ESI bit, and 4-bit DLC bits. The IDE bit can be used to indicate that it is a CAN 2.0 A series protocol with 11 bits of identification data (ID), and can have a bit value of 0. The EDL bit may be used to indicate that it is an FD protocol having a length of an extended data area, and may have a bit value of 1 when the data area has a length of 8 bytes or more. The BRS bit can be used to switch to a fast baud rate during transmission of the data area and can have a bit value of one. The ESI bit can be used to identify errors in the transmission of information in the CAN 2.0 A FD protocol. The DLC area can be used to indicate the length of the data area in bytes. In the CAN 2.0 A FD protocol, the data area can have a length of 8 bytes or more and 64 bytes or less. As described above, in the CAN 2.0 A FD protocol, the data area can be transmitted at a maximum of 8 Mbps.

The CRC region may contain 17 or 21 bits of CRC bits and 1 bit of CRC partition bits. Depending on the length of the increased data area compared to the CAN 2.0 A protocol, the length of the CRC bits for cyclic redundancy check (CRC) calculation is also increased. The CRC partition bit may be provided to distinguish the CRC region from the acknowledgment region and may have a bit value of one. Although not shown, the CRC region may further include a Stuff Count (SC) bit for reflecting the stuff bits in the cyclic redundancy check (CRC) calculation. The acknowledgment region may comprise a 1-bit acknowledgment bit and a 1-bit acknowledgment segment bit, such as the CAN 2.0 A protocol of FIG.

7 is a diagram showing the structure of a data frame for the CAN 2.0 B FD protocol. Referring to FIG. 7, a data frame for the CAN 2.0 B FD protocol is divided into a start frame, an arbitration region, a control region, a data region, a CRC region, a confirmation region, and an end frame (End). The intervening area is composed of 11-bit first identification data (ID1), 1-bit SRR bit, 1-bit IDE bit, 18-bit second identification data (ID2) Lt; RTI ID = 0.0 > RTR < / RTI >

The control area may include a 1-bit EDL bit, a 1-bit reserved bit, a 1-bit BRS bit, a 1-bit ESI bit, and 4-bit DLC bits. The functions of the EDL bit, spare bit, BRS bit, ESI bit, and DLC bit are the same as the EDL bit, spare bit, BRS bit, ESI bit, and DLC bit in the CAN 2.0 A FD protocol of FIG. In the CAN 2.0 B FD protocol, the data area may have a length of 8 bytes or more and 64 bytes or less. As described above, in the CAN 2.0 B FD protocol, the data area can be transmitted at a maximum of 8 Mbps. The CRC region may include 17 or 21 bits of CRC bits and 1 bit of CRC partition bits as in the CAN 2.0 A FD protocol of FIG. The confirmation area may include a 1-bit acknowledgment bit and a 1-bit acknowledgment bit, as in the protocols of FIGS. 4-6.

4 through 7, each of the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols can have a structure of different data frames. The bit states selected in each protocol may be different. However, as shown in Table 1, the target bit states selected in the CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols exist in a total of 21 bit states.

The protocol generator 345 of FIG. 2 may set one of CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. In this case, the protocol generator 345 and the protocol analyzer 335 can sequentially determine and analyze a data frame by sequentially transitioning target bit states selected in the protocol. Therefore, the CAN controller of the present invention can integrally support CAN 2.0 A, CAN 2.0 B, CAN 2.0 A FD, and CAN 2.0 B FD protocols. That is, the use of other CAN controllers is not required to support different protocols, and as many modules as the number of protocols supported in the CAN controller are not required.

FIG. 8 is a block diagram embodying the data buffer unit of FIG. 2 or FIG. 3. FIG. Referring to FIG. 8, the data buffer unit 400 includes an identification data scanner 410, a bus load detector 420, a processor load detector 430, and a first-in first-out memory 440. The first-in-first-out memory 440 includes a plurality of memory blocks 441 to 44n. The first-in-first-out memory 440 can be seen as the first-in first-out memory 322 of FIG. Alternatively, the first-in first-out memory 440 can be viewed as the transmission first-in-first-out memory 324 of FIG. On the aspect of the explanation, referring to the reference numerals of Fig. 3, the configurations of Fig. 8 will be described. Further, the CAN bus is described with reference to the reference numerals of the CAN bus 140 in FIG. 1, and the processor described below is described with reference to the reference numerals of the first processor 112 in FIG.

The data buffer unit 400 may receive the transmission information Td from the interface 310 or receive the reception information Rd from the receiver 330. [ In other words, although the identification data scanner 410, the bus load detector 420, the processor load detector 430, and the first-in first-out memory 440 are shown as one configuration, the actual data buffer 400 stores the transmission information Td ) And a configuration for processing the reception information Rd. That is, the identification data scanner 410, the bus load detector 420, the processor load detector 430, and the first-in first-out memory 440 may each be composed of two. Alternatively, only the first-in first-out memory 440 may be composed of two, and the identification data scanner 410, the bus load detector 420, and the processor load detector 430 may be configured as one to process both the transmission information and the reception information .

The identification data scanner 410 receives the transmission information Td or the reception information Rd. The identification data scanner 410 scans the identification information of the transmission information Td or the reception information Rd. As described above, the identification data exists in the arbitration area in the data frame of the transmission information Td or the reception information Rd. The identification data scanner 410 can search the memory block in which the information having the same identification data as the scanned identification data is stored. The identification data scanner 410 can overwrite the transmission information Td or the reception information Rd in the retrieved memory block when the output delay of the received transmission information Td or reception information Rd is expected.

The identification data scanner 410 can overwrite the transmission information Td on the memory block based on the processor load. The identification data scanner 410 can overwrite the transmission information Td with the memory block if the processor load is larger than the reference load. The reference load may be a predetermined value. In this case, the value of the reference load may not change, and the value of the reference load may be determined in consideration of the stability and promptness of the system. Alternatively, the reference load may be a processor load. If the processor load is greater than the bus load, the transmission of the transmission information Td to the CAN bus may be delayed. Therefore, the identification data scanner 410 can overwrite the transmission information Td in the memory block in order to transmit the transmission information Td quickly.

The identification data scanner 410 can overwrite the received information Rd on the memory block based on the bus load. The identification data scanner 410 can overwrite the received information Rd on the memory block if the bus load is greater than the reference load. The reference load may be a predetermined value. In this case, the value of the reference load may not change, and the value of the reference load may be determined in consideration of the stability and promptness of the vehicle system. Alternatively, the reference load may be a processor load. If the bus load is greater than the processor load, the transmission of the received information Rd to the processor may be delayed. Therefore, the identification data scanner 410 can overwrite the reception information Rd in the memory block for the transmission of the reception information Rd quickly.

The bus load detector 420 senses the bus load of the CAN bus 140. The bus load detector 420 may sense the amount of data provided to the CAN bus 140. The bus load detector 420 may generate bus load information based on the sensed bus load. The bus load detector 420 may provide bus load information to the identification data scanner 410. The identification data scanner 410 can determine whether to overwrite the reception information Rd or the transmission information Td based on the bus load information.

The processor load detector 430 detects the processor load. The processor load detector 430 may sense the amount of data processed at the processor 112. [ The processor load detector 430 may generate processor load information based on the sensed processor load. The processor load detector 430 may provide processor load information to the identification data scanner 410. The identification data scanner 410 can determine whether to overwrite the transmission information Td or the reception information Rd based on the processor load information.

The first-in first-out memory 440 can store transmission information (Td) or reception information (Rd) provided in accordance with the passage of time in the received order. Also, the first-in first-out memory 440 can output the transmission information Td or the reception information Rd in the stored order. For example, the first transmission information T1d provided first in the first memory block 441 may be stored, and the second transmission information T2d provided next may be stored in the second memory block 442 . Thereafter, the transmission information may be sequentially stored in the nth first-in-first-out memory 44n. In this case, the first transmission information T1d, the second transmission information T2d, and the nth transmission information Tnd may be sequentially output to the transmitter 340 in this case.

The third memory block 443 may store the third transmission information provided after the second transmission information T2d. However, the identification data scanner 410 can determine that the processor load is larger than the reference load (bus load) and can overwrite the transmission information Td in the first-in first-out memory 440. At this time, the identification information of the third transmission information and the transmission information Td may be the same. The identification data indicates the attribute of the transmission information. Since the latest information among the information having the same attribute in the vehicle system is most important, the transmission information Td is stored in the third memory block 443. That is, the third transmission information is deleted.

The transmission information Td 'is output to the transmitter 340 after the second transmission information T2d is output. That is, by overwriting the transmission information Td, information input later can be output more quickly. In this case, the output order of the next transmission information to be received can be pulled one by one. Therefore, even when the processor load is large, the latest transmission information can be output to the CAN bus quickly. Similarly, even when the bus load is large, the latest received information can be quickly output to the processor. The transmission process of the transmission information Td described above is also applied to the process in which the reception information Rd is overwritten and outputted in the first-in first-out memory 440.

9 is a flowchart illustrating a method of transmitting received information according to an embodiment of the present invention. The steps of FIG. 9 may be performed in the data buffer unit 400 of FIG. On the basis of the explanation, referring to the reference numerals of Fig. 8, the steps of Fig. 8 are explained.

In step S110, the data buffer unit 400 detects the bus load and the processor load. The bus load may be sensed at the bus load detector 420. The processor load may be sensed at the processor load detector 430.

In step S120, the data buffer unit 400 compares the sensed bus load with the processor load. The identification data scanner 410 may receive bus load information from the bus load detector 420 and receive processor load information from the processor load detector 430. [ The identification data scanner 410 can compare the bus load information and the processor load information to determine the load information having a larger value. If the bus load is larger than the processor load, step S130 is performed. If the bus load is not greater than the processor load, step S150 is performed. Alternatively, as noted in FIG. 8, the identification data scanner 410 may compare the bus load with a predetermined reference load.

In step S130, the data buffer unit 400 determines whether the reception information having the same identification data is already stored. The identification data scanner 410 can analyze the data frame of the received information Rd to extract the identification data. The identification data scanner 410 can retrieve reception information having the same identification data as the reception information Rd among the memory blocks of the first-in first-out memory 440. [ If the reception information having the same identification data as the reception information Rd is stored in the specific memory block, step S140 is performed. If the reception information having the same identification data as the reception information Rd is not stored in all the memory blocks of the first-in first-out memory 440, step S150 is performed.

In step S140, the data buffer unit 400 overwrites the reception information Rd in the memory block storing the reception information having the same identification data. Thus, the previously stored reception information is deleted, and the newly provided reception information Rd is stored in the memory block. In step S150, the first-in first-out memory 440 stores reception information Rd. Since the bus load is sufficient in step S150, all the received information can be sufficiently transferred to the processor by the first-in first-out method. Therefore, the received information Rd is stored in an empty memory block. After step S140 or step S150, step S160 is performed.

In step S160, the data buffer unit 400 provides the stored reception information Rd to the interface 310. [ The first-in first-out memory 440 outputs the reception information Rd to the interface 310 according to the output order of the stored information. If the received information Rd is overwritten in step S140, the received information Rd is output to the interface 310 according to the output order of the deleted received information. In step S150, if the received information Rd is stored in the empty memory block, the received information Rd may be output to the interface 310 after all of the previously stored received information is output. However, if the received information provided to the data buffer unit 400 is overwritten with the received information of the previous rank, the overwritten received information may be output to the interface 310 before the received information Rd.

10 is a flowchart illustrating a method of transmitting transmission information according to an embodiment of the present invention. The steps of FIG. 10 may be performed in the data buffer unit 400 of FIG. On the basis of the explanation, referring to the reference numerals of Fig. 8, the steps of Fig. 10 are explained. In step S210, the data buffer unit 400 detects the bus load and the processor load. The bus load may be sensed at the bus load detector 420. The processor load may be sensed at the processor load detector 430.

In step S220, the data buffer unit 400 compares the detected bus load with the processor load. The identification data scanner 410 may receive bus load information from the bus load detector 420 and receive processor load information from the processor load detector 430. [ The identification data scanner 410 can compare the bus load information and the processor load information to determine the load information having a larger value. If the bus load is smaller than the processor load, step S230 is performed. If the bus load is not smaller than the processor load, step S250 is performed. Alternatively, as noted in FIG. 8, the identification data scanner 410 may compare the processor load information with a predetermined reference load.

In step S230, the data buffer unit 400 determines whether transmission information having the same identification data is already stored. The identification data scanner 410 can analyze the data frame of the received information Td to extract the identification data. The identification data scanner 410 can retrieve transmission information having the same identification data as the transmission information Td among the memory blocks of the first-in first-out memory 440. [ If the transmission information having the same identification data as the transmission information Td is stored in the specific memory block, step S240 is performed. If the transmission information having the same identification data as the transmission information Td is not stored in all the memory blocks of the first-in first-out memory 440, step S250 is performed.

In step S240, the data buffer unit 400 overwrites the transmission information Td with the memory block in which the transmission information having the same identification data is stored. Thus, the previously stored transmission information is deleted, and the newly provided transmission information Td is stored in the memory block. In step S250, the first-in first-out memory 440 stores the transmission information Td. Since the processor load is sufficient in step S250, all transmission information can be sufficiently transmitted to the CAN bus 140 in a first-in first-out manner. Therefore, the transmission information Td is stored in an empty memory block. After step S240 or step S250, step S260 is performed.

In step S260, the data buffer unit 400 provides the stored transmission information Td to the transmitter 340. [ The first-in first-out memory 440 outputs the transmission information Td to the transmitter 340 according to the output order of the stored information. In step S240, when the transmission information Td is overwritten, the transmission information Td is output to the transmitter 340 in accordance with the output order of the deleted transmission information. In step S250, if the transmission information Td is stored in the empty memory block, the transmission information Td may be output to the transmitter 340 after all of the previously stored transmission information is output. However, if the transmission information provided to the data buffer unit 400 is overwritten with the transmission information of the previous rank, the transmission information that is overwritten thereafter may be output to the transmitter 340 before the transmission information Td.

The above description is a concrete example for carrying out the present invention. The present invention includes not only the above-described embodiments, but also embodiments that can be simply modified or easily changed. In addition, the present invention includes techniques that can be easily modified by using the above-described embodiments.

100: CAN system 200: CAN controller
220, 300: protocol engine 221, 310: interface
222, 320, 400: Data buffer unit 330: Receiver
335: Protocol Analyzer 340: Transmitter
345: Protocol Generator 410: Identification Data Scanner
440: first in first out memory

Claims (18)

A receiver for analyzing the received information received from the CAN bus according to the established protocol;
A received first-in-first-out memory for storing the received information so as to be overwritten with previously stored received information based on the identification data of the received information and the bus load of the CAN bus;
An interface for providing reception information stored in the reception first-in-first-out memory to the processor or receiving transmission information from the processor;
A transmission first-in-first-out memory for storing the transmission information so as to be overwritten with previously stored transmission information based on the identification data of the transmission information and the processor load of the processor; And
And a transmitter for setting the protocol and transmitting the transmission information stored in the transmission first-in-first-out memory according to the protocol to the CAN bus. The method according to claim 1,
The transmitter comprising:
And a protocol generator for selecting the target bit states of a data frame corresponding to the protocol among a plurality of bit states to set the protocol. 3. The method of claim 2,
The protocol generator comprises:
And sequentially shifts each of the target bit states to determine a data frame of the transmission information. 3. The method of claim 2,
The protocol generator comprises:
A CAN controller for selecting one of a CAN 2.0 A protocol, a CAN 2.0 B protocol, a CAN 2.0 A FD protocol, and a CAN 2.0 B FD protocol, and selecting the target bit states based on the selected protocol. 3. The method of claim 2,
The receiver comprising:
And a protocol analyzer to analyze the received information by sequentially transitioning the target bit states. The method according to claim 1,
The receiver comprising:
A masking filter register for determining whether to provide the reception information to the reception first-in-first-out memory based on the identification data of the reception information;
A baud rate adjuster for adjusting a baud rate of a data frame of the received information according to the set protocol; And
And an error detector for detecting an error of the reception information and determining whether to provide the reception information to the reception first-in-first-out memory. The method according to claim 1,
Further comprising an identification data scanner for overwriting the received information in a memory block of the receive first-in-first-out memory where information having the same identification data as the identification data of the received information is stored when the bus load is higher than the processor load, . 8. The method of claim 7,
A bus load detector for sensing the bus load and providing bus load information to the identification data scanner; And
Further comprising a processor load detector for sensing the processor load and providing processor load information to the identification data scanner. The method according to claim 1,
Further comprising an identification data scanner for overwriting the transmission information in a memory block of the transmission first-in-first-out memory where information having the same identification data as identification data of the transmission information is stored when the processor load is higher than the bus load, . Receiving data information by the CAN controller;
Sensing the amount of data information the CAN controller is scheduled to receive;
Searching for a memory block of the first-in-first-out memory in which the CAN controller stores information having the same identification data as the identification data of the data information; And
And the CAN controller overwriting the data information in the memory block based on the amount of data information scheduled to be received. 11. The method of claim 10,
Wherein the data information is transmission information provided from a processor,
Wherein the sensing the amount of data information comprises:
And the CAN controller detecting a processor load of the processor. 12. The method of claim 11,
And the CAN controller sequentially outputs information stored in the first-in-first-out memory to the CAN bus. 12. The method of claim 11,
Wherein the sensing the amount of data information comprises:
The CAN controller further comprising comparing the bus load of the CAN bus with the processor load,
Wherein the step of overwriting the data information overwrites the transmission information when the processor load is larger than the bus load. 12. The method of claim 11,
Wherein the step of overwriting the data information overwrites the transmission information when the load of the processor is larger than the set reference load value. 11. The method of claim 10,
The data information is reception information provided from the CAN bus,
Wherein the sensing the amount of data information comprises:
And the CAN controller detecting a bus load of the CAN bus. 16. The method of claim 15,
And the CAN controller sequentially outputs information stored in the first-in-first-out memory to the processor. 16. The method of claim 15,
Wherein the sensing the amount of data information comprises:
The CAN controller further comprising comparing the bus load with a load of the processor,
Wherein the step of overwriting the data information overwrites the received information if the bus load is greater than the processor load. 16. The method of claim 15,
And overwriting the received information if the bus load is greater than the set reference load value in the step of overwriting the data information.

Images