KR20180063956A - Non-volatile memory apparatus - Google Patents

Abstract

A non-volatile memory device may include a memory cell connected to a global bit line. A write driver may supply a drift current to the global bit line. A voltage clamping circuit can limit the voltage level of the global bit line to the clamp voltage so as to turn on only a specific memory cell. It is possible to prevent a disturb phenomenon.

Description

[0001] NON-VOLATILE MEMORY APPARATUS [0002]

The present invention relates to semiconductor technology, and more particularly, to a non-volatile memory device having a non-volatile memory cell.

Electronic devices include many electronic components, and may include many electronic components comprised of computer system semiconductors. The computer system may include a memory device. DRAMs are widely used as general memory devices because they can input / output data at high speed and have random access capability. However, since the DRAM has a memory cell made up of a capacitor, it has a volatile characteristic of losing stored data when the power supply is interrupted. A flash memory device has been developed to overcome the disadvantages of the DRAM. The flash memory device may include a memory cell comprised of a floating gate and may have a nonvolatile characteristic that can maintain stored data even if the power supply is interrupted. However, there is a disadvantage in that data input / output operations are performed at a significantly slower rate than DRAM, and random access is difficult.

In recent years, next generation memory devices such as Phase change RAM, Magnetic RAM, Resistive RAM and Ferroelectric RAM have been developed with fast operating speed and nonvolatile characteristics. The next generation memory devices have the advantage of being able to operate at a high speed while having nonvolatile characteristics. In particular, the PRAM includes a memory cell comprised of a chalcogenide and can store data by varying the resistance value of the memory cell.

Embodiments of the present invention can provide a nonvolatile memory device capable of performing a selective drift recovery operation by limiting voltage levels of a write memory cell and a global bit line and improving a disturb phenomenon.

A nonvolatile memory device according to an embodiment of the present invention includes: a memory cell connected to a global bit line; A write driver for supplying a drift current to the global bit line; And a voltage clamping circuit for limiting the voltage level of the global bit line to a clamp voltage.

A nonvolatile memory device according to an embodiment of the present invention includes a plurality of memory cells for storing set data or reset data; A write driver for supplying a drift current to the plurality of memory cells; And a voltage clamping circuit for limiting the voltage applied to the plurality of memory cells to turn on the memory cells storing the set data and not turning on the memory cells storing the reset data.

A nonvolatile memory device according to an embodiment of the present invention includes: a memory cell connected to a global bit line; A write driver for providing one of a program current and a drift current to the global bit line in accordance with an operation mode; And a voltage clamping circuit for limiting the voltage level of the global bit line to one of a first clamp voltage and a second clamp voltage in accordance with the operation mode.

Embodiments of the present invention can improve operational reliability of a nonvolatile memory device.

FIG. 1 is a diagram illustrating a configuration of a nonvolatile memory device according to an embodiment of the present invention; FIG.
FIG. 2 is a graph showing current and voltage characteristics of the switching device shown in FIG. 1,
FIG. 3 is a view showing a resistance distribution of a memory cell, showing a resistance change due to a drift phenomenon and a resistance change due to a drift recovery operation,
4 is a schematic view showing a configuration of a memory cell array of a nonvolatile memory device according to an embodiment of the present invention;
5 is a diagram illustrating a configuration of a nonvolatile memory device according to an embodiment of the present invention.
6 is a diagram illustrating levels of first and second clamp voltages according to an embodiment of the present invention;
Figure 7 is a schematic diagram of a memory card having a non-volatile memory device according to various embodiments of the inventive concept,
8 is a block diagram illustrating an electronic device having a non-volatile memory device according to various embodiments of the inventive concept,
Figure 9 is a block diagram illustrating a data storage device having a non-volatile memory device in accordance with various embodiments of the inventive concepts;
10 is a block diagram of an electronic system with a non-volatile memory device in accordance with various embodiments of the inventive concepts.

FIG. 1 is a diagram illustrating a configuration of a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 1, the non-volatile memory device 1 may include a memory cell 110 capable of storing data. The memory cell 110 may include a variable resistive element 111 and a switching element 112. The variable resistive element 111 may be formed of a variable resistive material to store data. For example, the variable resistive element 111 can be programmed and / or written into a high resistance state or a low resistance state. The high resistance state may be defined as reset data, and the low resistance state may be defined as set data. The switching element 112 can cause a current to flow in a specific direction like a diode. The switching element 112 may be an Ovonic Threshold Switch (OTS). The ovonic threshold switch may be configured such that when a current greater than a threshold current is applied or when a voltage level of both ends of the ovonic threshold switch exceeds a level of a threshold voltage, Current can flow

2 is a graph showing the current and voltage characteristics of the switching element 112 shown in FIG. In FIG. 2, the horizontal axis of the graph may be a voltage, and the vertical axis may be a magnitude of a current in logarithmic scale. The switching device 112 may be turned off when a current equal to or lower than the threshold current value Ith flows or when a voltage difference between both ends of the switching device 112 is equal to or less than a set threshold voltage VthSET. Only a very small amount of current can flow through the memory cell 110 when the switch element 112 is turned off. When the amount of current applied to the switching element 112 increases and becomes equal to or greater than the threshold current Ith or the voltage difference across the switching element 112 becomes equal to or greater than the set threshold voltage VthSET, ) May be turned on. When the switching element 112 is turned on, an unlimited amount of current can flow through the memory cell 110. The switching device 112 is controlled by the threshold voltage of the switching device 112 when the memory cell 110 is in a low-resistance state and / or when the memory cell 110 is storing SET data. And may correspond to a threshold voltage VthSET and may correspond to a threshold of the switching element 112 when the memory cell 110 is in a high resistance state and / or when the memory cell 110 is storing reset data RESET. The voltage may correspond to the reset threshold voltage VthRST. As will be described later, the read reference voltage VREAD used to read the data stored in the memory cell 110 may have a level between the set threshold voltage VthSET and the reset threshold voltage VthRST.

In FIG. 1, the memory cell 110 may be connected to a global bit line (GBL). The non-volatile memory device 1 may include a write driver 120 and a voltage clamping circuit 130. The write driver 120 may supply the drift current IDR to the global bit line GBL. The write driver 120 may supply the drift current IDR to the memory cell 110 through the global bit line GBL. The write driver 120 may supply the drift current IDR in a drift recovery operation. The write driver may supply the drift current (IDR) based on an operation mode signal RDR associated with a drift recovery operation. The write driver 120 may supply the programming current IPR to the global bit line GBL and the memory cell 110 in a write operation. The programming current IPR may be a current for setting the memory cell 110 to a low-impedance state or a high-resistance state, and may be a current for storing set data or reset data in the memory cell 110. [ The write driver 120 may generate a programming current IPR for storing set data based on a set signal SET during a write operation and supply the program current IPR to the global bit line GBL. When the write driver 120 receives the reset signal RESET during the write operation, the write driver 120 may generate the program current IPR for storing the reset data and supply the program current IPR to the global bit line GBL.

The voltage clamping circuit 120 may limit the voltage level of the global bit line GBL. The voltage clamping circuit 130 may limit the voltage level of the memory cell 110 by limiting the voltage level of the global bit line GBL. The voltage clamping circuit 130 may limit the voltage level of the global bit line GBL to the level of the clamp voltage VCL. The level of the clamp voltage VCL may be higher than the lead reference voltage VREAD and lower than the level of the reset threshold voltage VthRST.

The voltage clamping circuit 130 turns on the memory cell storing the low resistance state or the set data by limiting the voltage level of the global bit line GBL to the clamp voltage VCL, The memory cell storing the reset data may not be turned on. Therefore, when the drift current IDR is supplied from the write driver 120 to the global bit line GBL, the drift recovery operation for the memory cell storing the high-resistance state memory or the reset data is not performed . That is, the drift recovery operation can be performed only for a memory cell having a low resistance state or a memory cell storing set data.

The nonvolatile memory device 1 may further include a column switch 140, a row switch 150, and a read sense amplifier 160. The non-volatile memory device 1 may have a hierarchical bit line and a hierarchical word line structure. One end of the memory cell 110 may be connected to the bit line BL. The column switch 140 may be coupled between the global bit line GBL and the bit line BL and may connect the global bit line GBL and the bit line BL based on the column select signal YS. . As is well known, the global bit line GBL can be connected to a plurality of bit lines through a plurality of column switches, and when a specific column switch is turned on, a specific bit line and a memory cell connected to the specific bit line can be connected . The other end of the memory cell 110 may be connected to the word line WL. The row switch 150 may be connected between the word line WL and the global word line GWL and may be connected to the word line WL and the global word line GWL based on the row select signal XS. You can connect. Similarly, the global word line GWL may be coupled to a plurality of word lines via a plurality of row switches, and may be coupled to a specific word line and a memory cell coupled to the particular word line when a particular row switch is turned on. The global word line GWL may be coupled to a low voltage (VL) stage. The low voltage VL may be a ground voltage or a negative voltage having a level lower than the ground voltage. For example, the negative voltage may be a bulk bias or a back bias voltage. For example, when the nonvolatile memory device 1 is in the standby mode, the ground voltage may be supplied to the low voltage VL, and when the nonvolatile memory device 1 is in the active mode, Can be supplied to the low voltage (VL).

The read sense amplifier 160 may read data stored in the memory cell 110 during a read operation. The read sense amplifier 160 may be connected to the global bit line GBL and may be connected to the memory cell 110 through the global bit line GBL. The read sense amplifier 160 may supply the lead reference voltage VREAD to the global bit line GBL during a read operation. The read sense amplifier 160 senses the voltage of the memory cell 110 or the current flowing through the memory cell 110 when the read reference voltage VREAD is supplied to the memory cell 110, It is possible to generate the signal OUT.

In FIG. 1, the voltage clamping circuit 130 may include a comparator 131 and a driver 132. The comparator 131 receives the clamp voltage VCL and may compare the voltage level of the global bit line GBL with the clamp voltage VCL. The driver 132 may change the voltage level of the global bit line GBL based on the output of the comparator 131. [ The driver 132 may include a transistor T1. The transistor T1 has a gate connected to the output of the comparator 131, a drain connected to the write driver 120, and a source connected to the global bit line GBL. The driver 132 may maintain the voltage level of the global bit line GBL at substantially the same level as the clamp voltage VCL.

FIG. 3 is a view showing a resistance distribution of a memory cell, showing a resistance change due to the drift phenomenon and a resistance change due to the drift recovery operation. FIG. Referring to FIG. 1, if the set data and the reset data are written into the memory cell 110 through the write driver 120, the resistance distribution can have the same two resistances as the solid line. The left solid line may represent the set data (SET) or the low resistance distribution, and the right solid line may represent the reset data (RESET) or the high resistance distribution. Thereafter, over time, the data stored in the memory cell, i.e., the resistance state of the memory cell, may be changed by a drift phenomenon. Generally, the drift phenomenon may occur in a direction in which the resistance value increases. By the drift phenomenon, the set data or the low resistance distribution and the reset data or the high resistance distribution can be shifted all the rightward than the solid line as shown by the dotted line. If the drift recovery operation is not performed, the sensing margin capable of distinguishing the set data (SET) from the reset data (RESET) may be A. When a drift recovery operation is performed on all the memory cells storing the set data (SET) and the reset data (RESET), the resistance distribution shifted to the right due to the drift phenomenon is represented by a solid line Can be restored to the left as shown in Fig. At this time, the sensing margin for distinguishing the set data (SET) from the reset data (RESET) may be B. Since the sensing margin B has a value similar to the sensing margin A, an effect of expanding the sensing margin through the drift recovery operation can not be obtained. The nonvolatile memory device 1 according to the embodiment of the present invention can selectively perform the drift recovery operation only on the memory cell storing the set data SET. That is, the voltage clamping circuit 130 turns on only the memory cell storing the set data (SET) by limiting the voltage level of the global bit line GBL to the clamp voltage VCL, The drift recovery operation can be performed only for the cell. Therefore, although the SET distribution can be shifted to the left as indicated by the solid line, the reset data (RESET) distribution can maintain the same position as the dotted line. The sensing margin that can distinguish the set data (SET) from the reset data (RESET) may be C. The sensing margin C may be much larger than the sensing margins A and B and the sensing margin capable of distinguishing the set data SET from the reset data RESET may be significantly enlarged.

4 is a diagram schematically showing a configuration of a memory cell array 400 of a nonvolatile memory device according to an embodiment of the present invention. 4, the memory cell array 400 has nine memory cells in an area where three bit lines and three word lines intersect. However, the memory cell array 400 may include a larger number of bits Lines, word lines, and memory cells. One end of the first memory cell MC11 may be connected to the first bit line BL1 and the other end may be connected to the first word line WL1. One end of the second memory cell MC12 may be connected to the first bit line BL1 and the other end may be connected to the second word line WL2. One end of the third memory cell MC13 may be connected to the first bit line BL1 and the other end may be connected to the third word line WL3. One end of the fourth memory cell MC21 may be connected to the second bit line BL2 and the other end may be connected to the first word line WL1. One end of the fifth memory cell MC22 may be connected to the second bit line BL2 and the other end may be connected to the second word line WL2. One end of the sixth memory cell MC23 may be connected to the second bit line BL2 and the other end may be connected to the third word line WL3. One end of the seventh memory cell MC31 may be connected to the first bit line BL1 and the other end may be connected to the first word line WL1. One end of the eighth memory cell MC32 may be connected to the second bit line BL2 and the other end may be connected to the second word line WL2. One end of the ninth memory cell MC33 may be connected to the third bit line BL3 and the other end may be connected to the third word line WL3. Although not shown, the first to third bit lines BL1, BL2, and BL3 may be connected to the global bit line through a column switch, respectively, and the first to third word lines WL1, WL2, And may be coupled to the global word lines through respective row switches. Assume that the first memory cell MC11 stores the set data as a low resistance state and the second and third memory cells MC12 and MC13 store the reset data as a high resistance state. When the drift recovery operation is performed, for example, the first bit line BL1 is connected to the global bit line via a column switch, and the first to third word lines WL1, WL2, And may be coupled to the global word line via a switch. For the drift recovery operation, the write driver 120 may supply a drift current (IDR) to the global bit line GBL. At this time, when the drift current IDR exceeds the reset threshold current value, the drift phenomenon generated by turning on the first to third memory cells MC11, MC12, and MC13 can be compensated. At this time, the voltage clamping circuit 130 according to the embodiment of the present invention may limit the voltage level of the global bit line GBL to the clamp voltage VCL. Therefore, although the first and second memory cells MC11 and MC13 are turned on, the drift recovery operation is performed only on the first memory cell MC11. .

5 is a diagram showing a configuration of a nonvolatile memory device 5 according to an embodiment of the present invention. In FIG. 5, the non-volatile memory device 5 may include a memory cell 510, a write driver 520, and a voltage clamping circuit 530. The memory cell 510 may include a variable resistance element 511 and a switching element 512. One end of the memory cell 510 is connected to the bit line BL and the column switch 540 connects the bit line BL and the global bit line GBL based on the column switch signal YS . The other end of the memory cell 510 is connected to the word line WL and the row switch 550 connects the word line WL and the global word line GWL based on the row select signal XS. . The global word line GWL may be coupled to a low voltage (VL) stage.

The write driver 520 may provide one of the recovery current IDR and the programming current IPR to the global bit line GBL according to the operation mode of the nonvolatile memory device 5. [ The write driver 520 may provide a drift current (IDR) to the global bit line GBL during a drift recovery operation. The write driver 520 may provide the drift current based on the drift recovery signal RDR. The write driver 520 may provide a program current (IPR) to the global bit line GBL in a write operation. The write driver 520 may provide a programming current (IPR) for writing set data to the memory cell 510 based on a set signal SET, (IPR) for writing the reset data to the reset transistor 510.

The voltage clamping unit 530 may limit the global bit line GBL to one of the first clamp voltage VCL1 and the second clamp voltage VCL2 according to the operation mode of the nonvolatile memory device 5 . The voltage clamping circuit 530 may limit the voltage level of the global bit line GBL to the first clamp voltage VCL1 in a drift recovery operation. The voltage clamping circuit 530 may limit the voltage level of the global bit line GBL to the second clamp voltage VCL2 in the write operation.

6 is a diagram showing the levels of the first and second clamp voltages VCL1 and VCL2 according to the embodiment of the present invention. 6 shows the resistance distribution of the memory cell storing the set data SET and the resistance distribution of the memory cell storing the reset data RESET. The lowest threshold voltage among the resistance distributions of the memory cells storing the set data SET may be the minimum set threshold voltage VthSET_min and the highest threshold voltage may be the maximum set threshold voltage VthSET_max. The set threshold voltage VthSET may correspond to an intermediate value between the minimum set threshold voltage VthSET_min and the maximum set threshold voltage VthSET_max. The lowest threshold voltage among the resistance distributions of the memory cells storing the reset data RESET may be the minimum reset threshold voltage VthRST_min and the highest threshold voltage may be the maximum reset threshold voltage VthRST_max. The reset threshold voltage VthRST may correspond to an intermediate value between the minimum reset threshold voltage VthRST_min and the maximum reset threshold voltage VthRST_max. The read reference voltage VREAD may have any value between the maximum set threshold voltage VthSET_max and the minimum reset threshold voltage VthRST_min. For example, the read voltage VREAD may correspond to an average value of the set threshold voltage VthSET and the reset threshold voltage VthRST. The first clamp voltage VCL1 may have substantially the same level as the clamp voltage VCL described in Figs. The first clamp voltage VCL1 has a level higher than the read reference voltage VREAD and may have a level lower than the minimum reset threshold voltage VthRST_min. That is, the first clamp voltage VCL1 may have a value between the read reference voltage VREAD and the minimum reset threshold voltage VthRST_min. The second clamp voltage VCL2 may have a level lower than the first clamp voltage VCL1. The second clamp voltage VCL2 may have a level lower than the minimum set threshold voltage VthSET_min, for example.

The voltage clamping circuit 530 may include a voltage generator 533, a comparator 531, and a driver 532. The voltage generator 533 may output one of the first clamp voltage VCL1 and the second clamp voltage VCL2 to the comparator 531 based on the operation mode signal. The operation mode signal may include a drift recovery signal RDR and a write signal WT. The drift recovery signal RDR may be generated when the drift recovery operation of the nonvolatile memory device 5 is performed and the write signal WT may be generated when the write operation of the nonvolatile memory device 5 is performed Can be generated. The voltage generator 533 outputs the first clamp voltage VCL1 to the comparator 531 based on the drift recovery signal RDR and outputs the second clamp voltage VCL1 to the comparator 531 based on the write signal WT. VCL2 to the comparator 531. [

The comparator 531 may receive the first clamp voltage VCL1 or the second clamp voltage VCL2 from the voltage generator 533. The comparator 531 may compare the voltage level of the global bit line GBL with the output of the voltage generator 533. [ The driver 532 may change the voltage level of the global bit line GBL based on the comparison result of the comparator 531. [ The driver 532 may maintain the voltage level of the global bit line GBL at the level of the first clamp voltage VCL1 or the second clamp voltage VCL2, respectively. The driver 532 may include a transistor T2. The transistor T2 has a gate connected to the output of the comparator 531, a drain connected to the write driver 520, and a source connected to the global bit line GBL.

The nonvolatile memory device 5 may further include a read sense amplifier 560. The read sense amplifier 560 may read data stored in the memory cell 510 during a read operation. The read sense amplifier 560 may be connected to the global bit line GBL and may be connected to the memory cell 510 via the global bit line GBL. The read sense amplifier 560 can supply the lead reference voltage VREAD to the global bit line GBL during a read operation. The read sense amplifier 560 detects the voltage of the memory cell 510 or the current flowing through the memory cell 510 when the read reference voltage VREAD is supplied to the memory cell 510, It is possible to generate the signal OUT.

The voltage clamping circuit 530 restricts the voltage level of the global bit line GBL to the first clamp voltage VCL1 in the drift recovery operation so that only the memory cell 510 storing the set data is subjected to drift recovery So that the operation is performed. Therefore, the nonvolatile memory device 5 can obtain the same effect as the nonvolatile memory device 1 shown in FIG. In a write operation, the voltage clamping circuit 530 may limit the voltage level of the global bit line GBL to the second clamp voltage VCL2. Referring to FIG. 4, when the first bit line BL1 and the first word line WL1 are selected and a write operation is performed to the first memory cell MC11, the second and third word lines WL2, The voltage level of the memory cell increases due to off leakage due to a disturb phenomenon in the second and third memory cells MC12 and MC13, can do. If a memory cell having a threshold voltage, particularly a set threshold voltage, is present among the second and third memory cells M12 and M13, the memory cell having a low threshold voltage can be turned on first, The write operation may fail. In addition, data stored in a memory cell having a low threshold voltage may be lost. The voltage clamping circuit 530 may limit the voltage level of the global bit line GBL to the second clamp voltage VCL2 in order to prevent the voltage level of the global bit line GBL from rising excessively And the disturb phenomenon that can occur thereby can be improved. The voltage clamping circuit 530 may limit the voltage level of the global bit line GBL for the entire time during which a write operation is performed, but in one embodiment, the voltage clamping circuit 530 may, The voltage level of the global bit line GBL can be limited only for a predetermined time. For example, the predetermined time may be a time until the memory cell 510 is turned on by the programming current (IPR) after the write operation starts. When the memory cell 510 is turned on, the voltage clamping circuit 530 may not limit the voltage level of the global bit line GBL, and accordingly, the memory cell 510, which is relatively far from the write driver 520, The current driving force for supplying the program current (IPR) to the cell can be improved.

7 is a schematic diagram illustrating a memory card having a non-volatile memory device according to various embodiments of the inventive concepts. 7, the memory card system 4100 may include a controller 4110, a memory 4120, and an interface member 4130. [ The controller 4110 and the memory 4120 can be configured to exchange commands and / or data. The memory 4120 may be used to store, for example, instructions executed by the controller 4110, and / or user data.

The memory card system 4100 can store data in the memory 4120 or output data from the memory 4120 to the outside. The memory 4120 may include nonvolatile memory devices 1 and 5 according to the above-described embodiments of the present invention.

The interface member 4130 can take charge of data input / output with the outside. The memory card system 4100 may be a multimedia card (MMC), a secure digital card (SD), or a portable data storage device.

8 is a block diagram illustrating an electronic device having a nonvolatile memory device according to various embodiments of the inventive concepts. 8, the electronic device 4200 may include a processor 4210, a memory 4220, and an input / output device (I / O) 4230. The processor 4210, the memory 4220, and the input / output device 4230 may be connected via a bus 4246.

The memory 4220 may receive a control signal from the processor 4210. The memory 4220 may store code and data for operation of the processor 4210. [ The memory 4220 may be used to store data accessed via bus 4246. [ The memory 4220 may include nonvolatile memory devices 1 and 5 according to the above-described embodiments of the present invention. Additional circuit and control signals may be provided for specific realization and modification of the invention.

The electronic device 4200 may configure various electronic control devices that require the memory 4220. For example, the electronic device 4200 may be a computer system, a wireless communication device such as a PDA, a laptop computer, a portable computer, a web tablet, a cordless telephone, a mobile phone, a digital music player player, an MP3 player, navigation, a solid state disk (SSD), a household appliance, or any device capable of transmitting and receiving information in a wireless environment.

More specific implementations and modified examples of the electronic device 4200 will be described with reference to Figs. 9 and 10. Fig.

Figure 9 is a block diagram illustrating a data storage device having a non-volatile memory device in accordance with various embodiments of the inventive concepts. 9, a data storage device such as a solid state disk (SSD) 4311 may be provided. The solid state disk (SSD) 4311 may include an interface 4313, a controller 4315, a nonvolatile memory 4318, and a buffer memory 4319.

The solid state disk 4311 is a device for storing information by using a semiconductor device. The solid state disk 4311 has a speed faster than a hard disk drive (HDD), has a mechanical delay, failure rate, heat generation and noise, and can be miniaturized and lightened. The solid state disk 4311 may be widely used in a notebook PC, a netbook, a desktop PC, an MP3 player, or a portable storage device.

The controller 4315 may be formed adjacent to the interface 4313 and electrically connected thereto. The controller 4315 may be a microprocessor including a memory controller and a buffer controller. The non-volatile memory 4318 may be formed adjacent to the controller 4315 and may be electrically connected to the controller 4315 via a connection terminal T. The data storage capacity of the solid state disk 4311 may correspond to the nonvolatile memory 4318. The buffer memory 4319 may be formed adjacent to the controller 4315 and electrically connected thereto.

The interface 4313 can be connected to the host 4302 and can transmit and receive electric signals such as data. For example, the interface 4313 may be a device using standards such as SATA, IDE, SCSI, and / or a combination thereof. The non-volatile memory 4318 may be connected to the interface 4313 via the controller 4315. [

The non-volatile memory 4318 may store data received through the interface 4313. [ The non-volatile memory 4318 may include non-volatile memory devices 1 and 5 according to the above-described embodiments of the present invention. The data stored in the nonvolatile memory 4318 is preserved even if the power supply to the solid state disk 4311 is interrupted.

The buffer memory 4319 may include a volatile memory. The volatile memory may be DRAM (DRAM), and / or SRAM (SRAM). The buffer memory 4319 has a relatively fast operation speed as compared with the nonvolatile memory 4318.

The data processing speed of the interface 4313 may be relatively faster than the operation speed of the nonvolatile memory 4318. Here, the buffer memory 4319 may serve to temporarily store data. The data received via the interface 4313 is temporarily stored in the buffer memory 4319 via the controller 4315 and is temporarily stored in the nonvolatile memory 4318 in accordance with the data recording speed of the nonvolatile memory 4318. [ Lt; / RTI >

In addition, frequently used data among the data stored in the nonvolatile memory 4318 may be read in advance and temporarily stored in the buffer memory 4319. [ That is, the buffer memory 4319 can increase the effective operation speed of the solid state disk 4311 and reduce the error occurrence rate.

10 is a block diagram of an electronic system with a non-volatile memory device in accordance with various embodiments of the inventive concepts. 10, the electronic system 4400 may include a body 4410, a microprocessor unit 4420, a power unit 4430, a functional unit 4440, and a display controller unit 4450.

The body 4410 may be a motherboard formed of a printed circuit board (PCB). The microprocessor unit 4420, the power unit 4430, the functional unit 4440, and the display controller unit 4450 may be mounted to the body 4410. A display unit 4460 may be disposed within the body 4410 or outside the body 4410. For example, the display unit 4460 may be disposed on the surface of the body 4410 to display an image processed by the display controller unit 4450.

The power unit 4430 supplies a predetermined voltage from an external battery or the like to a required voltage level and supplies the voltage to the microprocessor unit 4420, the functional unit 4440, the display controller unit 4450, Can play a role. The microprocessor unit 4420 can receive the voltage from the power unit 4430 and control the functional unit 4440 and the display unit 4460. The functional unit 4440 may perform the functions of various electronic systems 4400. For example, when the electronic system 4400 is a cellular phone, the functional unit 4440 may be operable to perform various functions, such as dialing or communicating with an external device 4470, such as video output to the display unit 4460, It can include several components that can perform cell phone functions, and can act as a camera image processor if the camera is attached together.

When the electronic system 4400 is connected to a memory card or the like for capacity expansion, the functional unit 4440 may be a memory card controller. The functional unit 4440 can exchange signals with the external device 4470 through a wired or wireless communication unit 4480. When the electronic system 4400 requires USB or the like for function expansion, the functional unit 4440 may serve as an interface controller. The nonvolatile memory devices 1 and 5 according to the embodiments of the present invention may be applied to at least one of the microprocessor unit 4420 and the functional unit 4440. [

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (19)

A memory cell coupled to a global bit line;
A write driver for supplying a drift current to the global bit line; And
And a voltage clamping circuit for limiting the voltage level of the global bit line to a clamp voltage. The method according to claim 1,
Wherein the clamping voltage has a voltage level that turns on the memory cells in the set state and does not turn on the memory cells in the reset state. The method according to claim 1,
Wherein the clamping voltage is higher than the lead reference voltage and lower than the reset threshold voltage. A plurality of memory cells for storing set data or reset data;
A write driver for supplying a drift current to the plurality of memory cells; And
And a voltage clamping circuit which limits a voltage applied to the plurality of memory cells to turn on the memory cell storing the set data and does not turn on the memory cell storing the reset data. 5. The method of claim 4,
Wherein the plurality of memory cells are coupled to a global bit line, and wherein the voltage clamping circuit limits the voltage level of the global bit line to a clamp voltage. 6. The method of claim 5,
Wherein the clamp voltage is higher than the lead reference voltage and lower than the reset threshold voltage. A memory cell coupled to a global bit line;
A write driver for providing one of a program current and a drift current to the global bit line in accordance with an operation mode; And
And a voltage clamping circuit for limiting the voltage level of the global bit line to one of a first clamp voltage and a second clamp voltage in accordance with the operation mode. 8. The method of claim 7,
Wherein the write driver provides the drift current to the global bit line in a drift recovery operation and provides a programming current to the global bit line in a write operation. 9. The method of claim 8,
Wherein the voltage clamping circuit limits the voltage level of the global bit line to the first clamp voltage in the drift recovery operation and limits the voltage level of the global bit line to the second clamp voltage in the write operation, Device. 10. The method of claim 9,
Wherein the voltage clamping circuit limits the voltage level of the global bit line only for a predetermined time after the write operation is started. 11. The method of claim 10,
Wherein the predetermined time is a time after the write operation is started until the memory cell is turned on. 8. The method of claim 7,
Wherein the first clamp voltage has a level higher than the read voltage and lower than the reset threshold voltage. 8. The method of claim 7,
And the second clamp voltage has a level lower than the first clamp voltage. 13. The method of claim 12,
And the second clamp voltage has a level lower than a set threshold voltage. 8. The method of claim 7,
The voltage clamping circuit comprising: a voltage generator for outputting one of the first clamp voltage and the second clamp voltage based on an operation mode signal;
A comparator for comparing an output of the voltage generator with a voltage level of the global bit line; And
And a driver for varying the voltage level of the global bit line based on the comparison result of the comparator. 8. The method of claim 7,
Wherein the non-volatile memory device further includes a column switch that is turned on based on a column select signal, one end of the memory cell is connected to a bit line, and the bit line is connected to the global bit line via the column switch Volatile memory device. 17. The method of claim 16,
The nonvolatile memory device further includes a row switch that is turned on based on a row select signal, the other end of the memory cell is connected to a word line, and the word line is connected to a global word line via the row switch. Volatile memory device. 18. The method of claim 17,
Wherein the global word line is connected to a low voltage terminal, and the low voltage is a negative voltage lower than a ground voltage or a ground voltage. 8. The method of claim 7,
And a read sense amplifier that compares the level of the read voltage with the voltage level of the global bit line in a read operation to generate an output signal.

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