KR20180050860A - Data processing system and operation method for the same - Google Patents

Abstract

The present invention relates to a data processing system for processing data between a host and a memory system, and an operating method thereof. The data processing system comprises: the host including a host memory which includes a system region and a memory region, and including in the memory region characteristic information of write data managed in the system region; and the memory system checking the characteristic information of the write data stored in the memory region at the time of receiving a write command corresponding to the write data from the host, and adjusting a storage manner of the write data applied from the host based on the checked result.

Description

Technical Field [0001] The present invention relates to a data processing system and a data processing system,

The present invention relates to a memory system, and more particularly, to a data processing system for processing data between a host and a memory system and a method of operating the data processing system.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use memory systems that use memory devices, i. E., Data storage devices. The data storage device is used as a main storage device or an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because there is no mechanical driving part, and the access speed of information is very fast and power consumption is low. As an example of a memory system having such advantages, a data storage device includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

Embodiments of the present invention provide a data processing system and an operation method of a data processing system capable of adjusting a storage method of a write data generated by a host by reflecting the characteristic information of write data when the memory system stores the write data in the memory system do.

A data processing system according to an embodiment of the present invention includes a host that includes a host memory including a system area and a memory area and includes characteristic information of write data managed in the system area in the memory area; And a control unit for checking the property information of the write data stored in the memory area at the time of receiving the write command corresponding to the write data from the host and controlling the storing method of the write data applied from the host A memory system that is capable of storing data.

Also, the host may distinguish hot data or cold data based on an update frequency of the write data managed in the system area, and then write the write data separated by the hot data And copying or moving the write data to the first subspace of the memory area from the system area and copying or moving the write data separated by the cold data from the system area to the second subspace of the memory area.

Also, the memory system may include a non-volatile memory device including a plurality of first memory blocks and a plurality of second memory blocks, and determining that the write data is stored in the first sub- Program the write data to the first memory blocks and if the write data is confirmed to be stored in the second subspace through the check result, can do.

In addition, the host may store information for distinguishing hot data or cold data based on an update frequency of the write data managed in the system area in the memory area.

Also, the memory system may include a non-volatile memory device including a plurality of first memory blocks and a plurality of second memory blocks, and when the write data is identified as hot data through the check result, 1 memory blocks, and when the write data is confirmed as cold data through the check result, the second memory blocks can be programmed.

In addition, the host may store, in the memory area, information indicating whether or not it is large data based on a size of the write data managed in the system area, as characteristic information of the write data.

Also, the memory system may include a non-volatile memory device including a plurality of memory blocks. When the write data is identified as large data through the check result, The preparatory operation can be performed so that the number of blocks can be secured to a predetermined number or more.

Also, the host may store, in the memory area, information indicative of meta data or user data based on the logical address of the write data as characteristic information of the write data.

In addition, the on-board memory system includes a non-volatile memory device including a plurality of memory blocks and a cache memory for temporarily storing data to be input / output to / from the host, If it is determined that the metadata is the metadata, it is stored and managed in the cache memory, and if it is confirmed that the write data is user data, the memory blocks can be programmed.

The mall-state memory system may program the write data stored as meta data in the cache memory to the memory blocks at a set time.

According to another aspect of the present invention, there is provided a method of operating a data processing system including a host including a host memory including a system area and a memory area, and a memory system including a memory system receiving and storing write data from the host A method of operating a system, the method comprising: managing the write data in the system area by the host, and including characteristic information of the write data in the memory area; Transmitting the write command corresponding to the write data from the host to the memory system and confirming the property information of the write data stored in the memory area in the memory system; And adjusting the manner in which the write data is stored internally in the memory system based on the result of the verifying step.

In addition, the step of embedding may include: generating the write data at the host and storing the generated write data in the system area; And hot data or cold data on the basis of a frequency of update of the write data stored in the system area, Copying or moving the data into the first subspace of the area, and copying or moving the write data separated by the cold data from the system area to the second subspace of the memory area.

The memory system may also include a non-volatile memory device including a plurality of first memory blocks and a plurality of second memory blocks, wherein the adjusting comprises: Programming the write data identified to be stored in the first memory blocks in the memory system; And programming the write data identified to be stored in the second subspace through the verifying step into the second memory blocks in the memory system.

In addition, the step of embedding may include: generating the write data at the host and storing the generated write data in the system area; And storing information for distinguishing hot data or cold data based on an update frequency of the write data stored in the system area in the memory area.

The memory system may also include a non-volatile memory device including a plurality of first memory blocks and a plurality of second memory blocks, wherein the adjusting comprises, through the verifying step, Programming in the first memory blocks in the memory system, if it is determined to be; And programming the second memory blocks in the memory system when the write data is identified as cold data through the verifying step.

In addition, the step of embedding may include: generating the write data at the host and storing the generated write data in the system area; And storing information indicating whether the data is large data based on a size of the write data stored in the system area in the memory area as characteristic information of the write data.

The memory system may also include a non-volatile memory device including a plurality of memory blocks, wherein the adjusting comprises: if the write data is identified as large data through the verifying step, The number of free memory blocks among the memory blocks can be secured by a predetermined number or more.

In addition, the step of embedding may include: generating the write data at the host and storing the generated write data in the system area; And storing information indicative of meta data or user data on the basis of the logical address of the write data stored in the system area as characteristic information of the write data in the memory area .

The memory system may further include a nonvolatile memory device including a plurality of memory blocks and a cache memory for temporarily storing data to be input / output to / from the host, Storing and managing the write data in the cache memory in the memory system when the write data is confirmed as metadata; And programming the memory blocks in the memory system if the write data is determined to be user data through the verifying step.

The adjusting may further include programming the write data stored as meta data in the cache memory in the memory system to the memory blocks at a predetermined time point.

In this technique, a part of the host memory included in the host is set as an integrated area accessible from the memory system, and the characteristic information of the write data to be stored in the memory system is stored in the integrated area, When the data is stored in the memory system, the memory system can reflect the property information of the write data and adjust the storage method.

1 schematically illustrates an example of a data processing system including a memory system in accordance with an embodiment of the present invention;
Figure 2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention;
3 schematically shows a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention.
Figure 4 schematically illustrates a memory device structure in a memory system according to an embodiment of the present invention;
5 and 6A to 6D are diagrams for explaining characteristic data processing operations of the present invention in a data processing system including a memory system according to an embodiment of the present invention.
Figures 7 to 15 schematically illustrate other examples of a data processing system including a memory system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, it is to be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, Is provided to fully inform the user.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 1, a data processing system 100 includes a host 102 and a memory system 110.

And the host 102 includes electronic devices such as portable electronic devices such as mobile phones, MP3 players, laptop computers, or the like, or electronic devices such as desktop computers, game machines, TVs, projectors and the like, i.e. wired and wireless electronic devices.

The host 102 also includes at least one operating system (OS), which generally manages and controls the functionality and operation of the host 102, And provides interoperability between the user using the memory system 110 and the host 102. [ Here, the operating system supports functions and operations corresponding to the purpose and use of the user, and can be classified into a general operating system and a mobile operating system according to the mobility of the host 102, for example. In addition, the general operating system in the operating system may be classified into a personal operating system and an enterprise operating system according to the user's use environment. For example, the personal operating system may include a service providing function System, including windows and chrome, and enterprise operating systems are specialized systems for securing and supporting high performance, including Windows servers, linux, and unix . ≪ / RTI > In addition, the mobile operating system in the operating system may be a system characterized by supporting mobility service providing functions and a power saving function of the system for users, and may include android, iOS, windows mobile, and the like . At this time, the host 102 may include a plurality of operating systems, and also executes the operating system to perform operations with the memory system 110 corresponding to the user's request.

The memory system 110 also operates in response to requests from the host 102, and in particular stores data accessed by the host 102. In other words, the memory system 110 may be used as the main memory or auxiliary memory of the host 102. [ Here, the memory system 110 may be implemented in any one of various types of storage devices according to a host interface protocol connected to the host 102. For example, the memory system 110 may be a solid state drive (SSD), an MMC, an embedded MMC, an RS-MMC (Reduced Size MMC), a micro- (Universal Flash Storage) device, a Compact Flash (CF) card, a Compact Flash (CF) card, a Compact Flash A memory card, a smart media card, a memory stick, or the like.

In addition, the storage devices implementing the memory system 110 may include a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, a read only memory (ROM), a magnetic random access memory (MROM) Volatile memory device such as a ROM, an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a ferromagnetic ROM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM) Can be implemented.

The memory system 110 also includes a memory device 150 that stores data accessed by the host 102 and a controller 130 that controls data storage in the memory device 150. [

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. In one example, controller 130 and memory device 150 may be integrated into a single semiconductor device to configure an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be further improved. In addition, the controller 130 and the memory device 150 may be integrated into a single semiconductor device to form a memory card. For example, a PC card (PCMCIA), a compact flash card (CF) , Memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash memory can do.

In another example, memory system 110 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet ), A tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a 3-dimensional television, a smart television, a digital audio a recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a data center, Constitute Storage, an apparatus capable of transmitting and receiving information in a wireless environment, one of various electronic apparatuses constituting a home network, one of various electronic apparatuses constituting a computer network, one of various electronic apparatuses constituting a telematics network, (radio frequency identification) device, or one of various components that constitute a computing system.

Meanwhile, the memory device 150 in the memory system 110 can maintain the stored data even when no power is supplied, and in particular, can store data provided from the host 102 through a write operation, ) Operation to the host 102. Here, the memory device 150 includes a plurality of memory blocks 152,154 and 156, each memory block 152,154, 156 including a plurality of pages, Includes a plurality of memory cells to which a plurality of word lines (WL) are connected. The memory device 150 also includes a plurality of memory dies including a plurality of planes, each of which includes a plurality of memory blocks 152, 154, 156, respectively, Lt; / RTI > In addition, the memory device 150 may be a non-volatile memory device, e.g., a flash memory, wherein the flash memory may be a three dimensional stack structure.

Here, the structure of the memory device 150 and the three-dimensional solid stack structure of the memory device 150 will be described in more detail below with reference to FIGS. 2 to 4, and a plurality of memory blocks 150, A plurality of memory dies each including a plurality of planes, and a memory device 150 including a plurality of memory dies will now be described in more detail in FIG. 5, A detailed description thereof will be omitted.

The controller 130 in the memory system 110 controls the memory device 150 in response to a request from the host 102. [ For example, the controller 130 provides data read from the memory device 150 to the host 102 and stores data provided from the host 102 in the memory device 150, Write, program, erase, and the like of the memory device 150 in accordance with an instruction from the control unit 150. [

More specifically, the controller 130 includes a host interface (Host I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, A power management unit (PMU) 140, a NAND flash controller (NFC) 142, and a memory 144.

In addition, the host interface unit 132 processes commands and data of the host 102, and may be a USB (Universal Serial Bus), a Multi-Media Card (MMC), a Peripheral Component Interconnect- , Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE) A Mobile Industry Processor Interface), and the like.

In addition, when reading data stored in the memory device 150, the ECC unit 138 detects and corrects errors contained in the data read from the memory device 150. [ In other words, after the ECC unit 138 performs error correction decoding on the data read from the memory device 150, it determines whether or not the error correction decoding has succeeded, and outputs an instruction signal, for example, an error correction success and outputs a success / fail signal and corrects the error bit of the read data using the parity bit generated in the ECC encoding process. At this time, when the number of error bits exceeds the correctable error bit threshold value, the ECC unit 138 can output an error correction failure signal that can not correct the error bit and can not correct the error bit.

Herein, the ECC unit 138 includes a low density parity check (LDPC) code, a Bose (Chaudhri, Hocquenghem) code, a turbo code, a Reed-Solomon code, a convolution code, ), Coded modulation such as trellis-coded modulation (TCM), block coded modulation (BCM), or the like, may be used to perform error correction, but the present invention is not limited thereto. In addition, the ECC unit 138 may include all of the circuits, modules, systems, or devices for error correction.

The PMU 140 provides and manages the power of the controller 130, that is, the power of the components included in the controller 130. [

The NFC 142 also includes a memory / memory controller 150 that performs interfacing between the controller 130 and the memory device 150 to control the memory device 150 in response to a request from the host 102. [ As a storage interface, the control signal of the memory device 150, in accordance with the control of the processor 134, when the memory device 150 is a flash memory, in particular when the memory device 150 is a NAND flash memory, And processes the data. The NFC 142 performs and performs operations of an interface, for example, a NAND flash interface, for processing commands and data between the controller 130 and the memory device 150. In particular, the controller 130 and the memory device 150 ) Data input / output.

The memory 144 is an operation memory of the memory system 110 and the controller 130 and stores data for driving the memory system 110 and the controller 130. [ The memory 144 controls the memory device 150 in response to a request from the host 102 such that the controller 130 is able to control the operation of the memory device 150, The controller 130 provides data to the host 102 and stores the data provided from the host 102 in the memory device 150 for which the controller 130 is responsible for reading, erase, etc., this operation is stored in the memory system 110, that is, data necessary for the controller 130 and the memory device 150 to perform operations.

The memory 144 may be implemented as a volatile memory, for example, a static random access memory (SRAM), or a dynamic random access memory (DRAM). In addition, the memory 144 may be internal to the controller 130 or external to the controller 130, as shown in FIG. 1, wherein data from the controller 130 via the memory interface And may be implemented as an external volatile memory that is input and output.

The memory 144 also stores data necessary for performing operations such as data writing and reading between the host 102 and the memory device 150 and data for performing operations such as data writing and reading as described above And includes a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a map buffer / cache, and the like for storing data.

The processor 134 controls the overall operation of the memory system 110 and controls the write operation or the read operation for the memory device 150 in response to a write request or a read request from the host 102 do. Here, the processor 134 drives firmware called a Flash Translation Layer (FTL) to control all operations of the memory system 110. The processor 134 may also be implemented as a microprocessor or a central processing unit (CPU).

The controller 130 performs the requested operation from the host 102 through the processor 134 implemented in a microprocessor or central processing unit (CPU) or the like in the memory device 150, 102 to the memory device 150. The memory device 150 is a memory device. Here, the controller 130 performs a foreground operation by a command operation corresponding to a command received from the host 102, for example, performs a program operation corresponding to a write command, a read operation corresponding to a read command, An erase operation corresponding to an erase command and a parameter set operation corresponding to a set parameter command or a set feature command with a set command.

The controller 130 may then perform a background operation on the memory device 150 via a processor 134 implemented as a microprocessor or a central processing unit (CPU). Here, the background operation for the memory device 150 is an operation for copying and storing the data stored in an arbitrary memory block in the memory blocks 152, 154 and 156 of the memory device 150 to another arbitrary memory block, For example, a garbage collection (GC) operation, an operation of swapping data between memory blocks 152, 154, 156 of memory device 150 or between data stored in memory blocks 152, 154, 156, WL, Wear Leveling) operation, storing the map data stored in the controller 130 in the memory blocks 152, 154, 156 of the memory device 150, such as a map flush operation, A bad block management operation for checking bad blocks in a plurality of memory blocks 152, 154 and 156 included in the memory device 150 and for processing the bad blocks, And the like.

Particularly, in the memory system according to the embodiment of the present invention, for example, the controller 130 performs a command operation corresponding to a command received from the host 102, for example, a program operation corresponding to a write command or a read operation The memory device 150 and the memory device 150, that is, whether or not the command operation is completed in the memory device 150. [

In addition, the processor 134 of the controller 130 may include a management unit (not shown) for performing bad management of the memory device 150, and the management unit may include a plurality The bad blocks are checked in the memory blocks 152, 154, and 156 of the bad blocks, and bad block management is performed to bad check the bad blocks. Bad management can be used to prevent a data light, for example, a program failure in a data program, due to a characteristic of the NAND when the memory device 150 is a flash memory, for example, a NAND flash memory, This means that the failed memory block is bad-processed and the program failed data is written to the new memory block, that is, programmed. In addition, when the memory device 150 has a three-dimensional solid stack structure as described above, if the block is processed as a bad block in response to a program failure, the utilization efficiency of the memory device 150 and the memory system 100 ), The reliability of the bad block management needs to be more reliably managed. Hereinafter, the memory device in the memory system according to the embodiment of the present invention will be described in more detail with reference to FIG. 2 to FIG.

Figure 2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention, Figure 3 schematically illustrates a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention. FIG. 4 is a view schematically showing a memory device structure in a memory system according to an embodiment of the present invention, and schematically shows a structure when the memory device is implemented as a three-dimensional nonvolatile memory device .

2, the memory device 150 includes a plurality of memory blocks, such as BLK 0 (Block 0) 210, BLK 1 220, BLK 2 230, and a block N-1 (BLKN-1) 240. Each block 210, 220, 230, 240 includes a plurality of pages, e.g., 2M pages (2MPages). Here, for convenience of explanation, it is assumed that a plurality of memory blocks each include 2M pages, but the plurality of memories may each include M pages. Each of the pages includes a plurality of memory cells to which a plurality of word lines (WL) are connected.

In addition, the memory device 150 may include a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, a plurality of memory blocks, Multi Level Cell) memory block or the like. Here, the SLC memory block includes a plurality of pages implemented by memory cells storing one bit of data in one memory cell, and has high data operation performance and high durability. And, the MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (e.g., two bits or more) in one memory cell, Space, in other words, can be highly integrated. In particular, the memory device 150 may be an MLC memory block, as well as an MLC memory block including a plurality of pages implemented by memory cells capable of storing 2-bit data in one memory cell, A triple level cell (TLC) memory block including a plurality of pages implemented by memory cells capable of storing bit data, a plurality of memory cells that are implemented by memory cells capable of storing 4-bit data in one memory cell, A Quadruple Level Cell (QLC) memory block containing pages of memory cells, or a plurality of pages implemented by memory cells capable of storing 5 bits or more of bit data in one memory cell A multiple level cell memory block, and the like.

Each of the blocks 210, 220, 230 and 240 stores the data provided from the host 102 through the write operation and provides the stored data to the host 102 through the read operation.

3, each memory block 330 in the plurality of memory blocks 152, 154, 156 included in the memory device 150 of the memory system 110 is implemented as a memory cell array, and bit lines BL0 to BLm-1, respectively. The cell string 340 of each column may include at least one drain select transistor DST and at least one source select transistor SST. Between the selection transistors DST and SST, a plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series. Each of the memory cells MC0 to MCn-1 may be configured as an MLC that stores data information of a plurality of bits per cell. Cell strings 340 may be electrically connected to corresponding bit lines BL0 to BLm-1, respectively.

3 illustrates each memory block 330 configured as a NAND flash memory cell. However, a plurality of memory blocks 152, 154, and 156 included in the memory device 150 according to the embodiment of the present invention may include NAND flash memory NOR-type flash memory, a hybrid flash memory in which two or more kinds of memory cells are mixed, and a one-NAND flash memory in which a controller is embedded in a memory chip, can be realized. In addition, the memory device 150 according to the embodiment of the present invention may include a flash memory device in which the charge storage layer is composed of a conductive floating gate, a Charge Trap Flash (CTF) memory Device, or the like.

The voltage supply unit 310 of the memory device 150 may supply the word line voltages (e.g., program voltage, read voltage, pass voltage, etc.) to be supplied to the respective word lines in accordance with the operation mode, (For example, a well region) in which the voltage supply circuit 310 is formed, and the voltage generation operation of the voltage supply circuit 310 may be performed under the control of a control circuit (not shown). In addition, the voltage supplier 310 may generate a plurality of variable lead voltages to generate a plurality of lead data, and may supply one of the memory blocks (or sectors) of the memory cell array in response to the control of the control circuit Select one of the word lines of the selected memory block, and provide the word line voltage to the selected word line and unselected word lines, respectively.

In addition, the read / write circuit 320 of the memory device 150 is controlled by a control circuit and operates as a sense amplifier or as a write driver depending on the mode of operation . For example, in the case of a verify / normal read operation, the read / write circuit 320 may operate as a sense amplifier for reading data from the memory cell array. In addition, in the case of a program operation, the read / write circuit 320 can operate as a write driver that drives bit lines according to data to be stored in the memory cell array. The read / write circuit 320 may receive data to be written into the cell array from a buffer (not shown) during a program operation, and may drive the bit lines according to the input data. To this end, the read / write circuit 320 includes a plurality of page buffers (PB) 322, 324 and 326, respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs) And each page buffer 322, 324, 326 may include a plurality of latches (not shown).

In addition, the memory device 150 may be implemented as a two-dimensional or three-dimensional memory device, and may be implemented as a non-volatile memory device of a three-dimensional solid stack structure, Structure, it may include a plurality of memory blocks BLK0 to BLKN-1. 4 is a block diagram showing memory blocks 152, 154 and 156 of the memory device 150 shown in FIG. 1, wherein each of the memory blocks 152, 154 and 156 is implemented as a three-dimensional structure (or vertical structure) . For example, each of the memory blocks 152,154, 156 may include structures extending along first to third directions, e.g., x-axis, y-axis, and z- . ≪ / RTI >

Each memory block 330 included in the memory device 150 may include a plurality of NAND strings NS extending along a second direction and may include a plurality of NAND strings arranged along the first and third directions. NAND strings NS may be provided. Here, each NAND string NS includes a bit line BL, at least one string select line SSL, at least one ground select line GSL, a plurality of word lines WL, at least one dummy word Line DWL, and a common source line CSL, and may include a plurality of transistor structures TS.

That is, in the plurality of memory blocks 152, 154, 156 of the memory device 150, each memory block 330 includes a plurality of bit lines BL, a plurality of string select lines SSL, May be coupled to a plurality of NAND strings GSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a plurality of common source lines CSL, . In addition, in each memory block 330, a plurality of NAND strings NS may be connected to one bit line BL, and a plurality of transistors may be implemented in one NAND string NS. The string selection transistor SST of each NAND string NS may be connected to the corresponding bit line BL and the ground selection transistor GST of each NAND string NS may be connected to the common source line CSL, Lt; / RTI > Here, memory cells MC are provided between the string selection transistor SST and the ground selection transistor GST of each NAND string NS, that is, a plurality of memory blocks 152, 154 and 156 of the memory device 150 are provided, In block 330, a plurality of memory cells may be implemented.

5 and 6A to 6D are diagrams for explaining characteristic data processing operations of the present invention in a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 5, there is shown a data processing system 100 including a characteristic configuration of the present invention referring to a data processing system 100 according to an embodiment of the present invention with reference to FIG. have.

Specifically, the data processing system 100 shown in FIG. 5 includes a host 102 and a memory system 110. Here, the host 102 includes a host memory 510. At this time, the host memory 144 includes a system area 514 and a memory area 512. The memory system 110 includes a controller 130 and a plurality of memory blocks 151 <1, 2, 3, ..., 153 <1, 2, 3,. At this time, the controller 130 includes a cache memory 520.

5, the cache memory 520 included in the controller 130 is a component corresponding to the memory 144 described as being included in the controller 130 in FIG. 5, the function of temporarily storing the write data (WRITE_DATA <x>) among the various functions of the memory 144 and managing the mapping information (not shown in FIG. 5) Another reference numeral '520' is used. 1, a host interface (I / F) unit 132, a processor 134, an error correction code (ECC) unit 138 ), A power management unit (PMU) 140, and a NAND flash controller (NFC) 142 are shown as being not included in the controller 130 in FIG. 5, But it will be actually included in the controller 130, which is omitted from the drawings for convenience of explanation.

As described above, the host memory 510 included in the host 102 includes a system area 514 and a memory area 512. At this time, the host memory 510 is a component for temporarily storing information that is required to be stored in the process of performing operations in the host 102, and is implemented as a volatile memory. For example, it may be implemented as a static random access memory (SRAM) or a dynamic random access memory (DRAM).

And, the memory system 110 and the host 102 can be configured according to an unified memory architecture (UMA). That is, a portion of the storage space of the host memory 510 may be allocated to an area accessible in the memory system 110 and used by the memory system 110. The system area 514 of the host memory 510 exemplified in the embodiment of the present invention is an area used exclusively by the host 102 and means an area in which the memory system 110 can not be accessed. The memory area 512 of the host memory 510 may be accessed by the host 102 but may also be accessed and used by the memory system 110. [

The host 102 stores the characteristic information WD_INFO <1, 2, 3> of the write data (WRITE_DATA <1, 2, 3>) managed in the system area 514 of the host memory 510 as host Is included in the memory area 512 of the memory 510.

The memory system 110 receives the write commands WRITE COMMAND <1, 2, 3> corresponding to the write data (WRITE_DATA <1, 2, 3>) from the host 102 (WD_INFO <1, 2, 3>) corresponding to the write data (WRITE_DATA <1, 2, 3>) stored in the memory area 512 of the host memory 510. In this way, the memory system 110 controls the manner in which each of the write data (WRITE_DATA <1, 2, 3>) applied from the host 102 is stored.

5A and 5B together with FIG. 5, the host 102 reads the write data WRITE_DATA <1, 2, 3> managed in the system area 514 of the host memory 510, (WRITE_DATA <1, 2, 3>) is hot data or cold data based on the update frequency of the data (WRITE_DATA <1, 2, 3>). After dividing each of the write data (WRITE_DATA <1, 2, 3>) into hot data or cold data, the host 102 reads the write data (WRITE_DATA < The second write data WRITE_DATA <2> and the third write data WRITE_DATA <3> separated by the cold data are stored in the first partial space 5121 of the memory area 512, In the second subspace 5122 of the memory area 512. [

In other words, the host 102 generates the write data (WRITE_DATA <1, 2, 3>) and manages it in the system area 514 before it is programmed in the memory system 110 The write data WRITE_DATA < 1, 2, 3 > may be copied or moved to the memory area 512. [

In this case, since the write data WRITE_DATA <1, 2, 3> is copied or moved from the system area 514 to the memory area 512, the write data WRITE_DATA < (WRITE_DATA <1, 2, 3>) corresponding to each of the memory areas (WD_INFO <1, 2, 3> 512).

After the write data WRITE_DATA <1, 2, 3> is copied or moved to the memory area 512, the host 102 writes the write data WRITE_DATA <1, 2, 3> (WRITE COMMAND < 1, 2, 3 >) to the memory system 110 in order to program the program.

The memory system 110 stores the write data WRITE_DATA (1, 2, 3) corresponding to the write commands WRITE COMMAND <1, 2, 3> at the time when the write commands WRITE COMMAND <1, 2, 3> are stored in the first subspace 5121 or the second subspace 5122 of the memory area 512, respectively. This checking operation is performed when the memory system 110 described in FIG. 5 accesses the memory area 512 at the time when each of the write commands (WRITE COMMAND <1, 2, 3>) is received and the write data WRITE_DATA < 1, 2, 3 >) of characteristic information WD_INFO < 1, 2, 3 >.

For example, when the host 102 generates and sends the first write command WRITE_COMMAND <1> to the memory system 110 to program the first write data WRITE_DATA <1> to the memory system 110, The memory system 110 stores the first write data WRITE_DATA <1> corresponding to the first write command WRITE_COMMAND <1> at the time when the first write command WRITE_COMMAND <1> Whether it is stored in the first subspace 5121 or in the second subspace 5122 of FIG. As a result, it is confirmed that the first write data (WRITE_DATA <1>) is stored in the first subspace 5121, so that it can be confirmed that the first write data (WRITE_DATA <1>) is hot data.

When the host 102 generates and sends the second write command WRITE_COMMAND <2> to the memory system 110 to program the second write data WRITE_DATA <2> to the memory system 110, The memory system 110 stores the second write data WRITE_DATA <2> corresponding to the second write command WRITE_COMMAND <2> at the time when the second write command WRITE_COMMAND <2> Whether it is stored in the first subspace 5121 or in the second subspace 5122 of FIG. As a result, it is confirmed that the second write data (WRITE_DATA <2>) is stored in the second subspace 5122, so that it can be confirmed that the second write data (WRITE_DATA <2>) is the cold data.

Similarly, when the host 102 generates and transmits the third write command WRITE_COMMAND <3> to the memory system 110 to program the third write data WRITE_DATA <3> to the memory system 110, The memory system 110 stores the third write data WRITE_DATA <3> corresponding to the third write command WRITE_COMMAND <3> at the time when the third write command WRITE_COMMAND <3> Whether it is stored in the first subspace 5121 or in the second subspace 5122 of FIG. As a result, it is confirmed that the third write data (WRITE_DATA <3>) is stored in the second subspace 5122, so that it can be confirmed that the third write data (WRITE_DATA <3>) is the cold data.

When the memory system 110 confirms the characteristic information WD_INFO <1, 2, 3> of each of the write data WRITE_DATA <1, 2, 3> through the above-described method, And controls the manner in which the write data (WRITE_DATA <1, 2, 3>) is stored based on the check result.

For example, in the case of the first write data (WRITE_DATA < 1 >), which is stored in the first subspace 5121 of the memory area 512 and confirmed as hot data through the confirmation result, 1, 2, 3, ...> among the first memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, .

In the case of the second write data (WRITE_DATA < 2 >), which is stored in the second partial space 5122 of the memory area 512 and confirmed as the cold data through the confirmation result, 1, 2, 3, ...> among the first memory blocks 153 <1, 2, 3, ...> 153 <1, 2, 3, ...> .

Similarly, in the case of the third write data (WRITE_DATA < 3 >), which is stored in the second subspace 5122 of the memory area 512 and confirmed as the cold data through the confirmation result, 1, 2, 3, ...> among the first memory blocks 153 <1, 2, 3, ...> 153 <1, 2, 3, ...> .

The first memory blocks 151 <1, 2, 3, ...> among the memory blocks 151 <1, 2, 3, ...>) can be managed as a hot memory block, and the second memory blocks 153 <1, 2, 3, ...> can be managed as a cold memory block. Separating and managing the memory blocks 151 <1, 2, 3, ...>, 153 <1, 2, 3, ...> into hot memory blocks and cold memory blocks, ) Reliability and service life.

Referring to FIG. 6B together with FIG. 5 for explaining another embodiment, the host 102 reads the write data WRITE_DATA < 1, 2, 3 > managed in the system area 514 of the host memory 510, (WRITE_DATA <1, 2, 3>) is hot data or cold data based on the update frequency of the data (WRITE_DATA <1, 2, 3>). After dividing each of the write data (WRITE_DATA <1, 2, 3>) into hot data or cold data, the host 102 sets hot data of the write data (WRITE_DATA < The first write data WRITE_DATA <1> is included in the first characteristic information WD_INFO <1> corresponding to the distinguished first write data WRITE_DATA <1>. In addition, a value indicating that the second write data (WRITE_DATA <2>) is cold data is included in the second characteristic information (WD_INFO <2>) corresponding to the second write data (WRITE_DATA <2> . In addition, a value indicating that the third write data (WRITE_DATA <3>) is cold data is included in the third characteristic information (WD_INFO <3>) corresponding to the third write data (WRITE_DATA <3> . After generating the characteristic information WD_INFO <1, 2, 3> corresponding to each of the write data WRITE_DATA <1, 2, 3>, the generated characteristic information WD_INFO < &Gt;) in the memory area 512.

In other words, the host 102 generates the write data (WRITE_DATA <1, 2, 3>) and manages it in the system area 514 before it is programmed in the memory system 110 (WD_INFO < 1, 2, 3 >) of the write data (WRITE_DATA <1, 2, 3>) is stored in the memory area 512.

In this case, the write data (WRITE_DATA <1, 2, 3>) is continuously managed in the system area 514 and the characteristic information corresponding to each of the write data (WRITE_DATA < 1, 2, 3>) corresponding to the write data WRITE_DATA <1, 2, 3> described in FIG. 5 are stored in the memory area 512, 2, 3>) exist as separate data.

After the characteristic information WD_INFO <1, 2, 3> corresponding to each of the write data WRITE_DATA <1, 2, 3> is stored in the memory area 512, (WRITE COMMAND < 1, 2, 3 >) to program the memory system 110 to the memory system 110 and to transmit the write commands WRITE COMMAND <1, 2, 3>

The memory system 110 stores the write data WRITE_DATA (1, 2, 3) corresponding to the write commands WRITE COMMAND <1, 2, 3> at the time when the write commands WRITE COMMAND (1, 2, 3 &gt;) in the memory area 512. In this case,

For example, when the host 102 generates and sends the first write command WRITE_COMMAND <1> to the memory system 110 to program the first write data WRITE_DATA <1> to the memory system 110, The memory system 110 stores the first characteristic information WD_INFO < 1 > corresponding to the first write command WRITE_COMMAND <1> at the time when the first write command WRITE_COMMAND <1> ). As a result, it is confirmed that the first write data (WRITE_DATA <1>) contains a value of hot data in the first characteristic information (WD_INFO <1>), .

When the host 102 generates and sends the second write command WRITE_COMMAND <2> to the memory system 110 to program the second write data WRITE_DATA <2> to the memory system 110, The memory system 110 stores the second characteristic information WD_INFO <2> corresponding to the second write command WRITE_COMMAND <2> at the time when the second write command WRITE_COMMAND <2> ). As a result, it is confirmed that the second write data (WRITE_DATA <2>) contains the value of the cold data in the second characteristic information (WD_INFO <2>). .

Similarly, when the host 102 generates and transmits the third write command WRITE_COMMAND <3> to the memory system 110 to program the third write data WRITE_DATA <3> to the memory system 110, The memory system 110 stores the third characteristic information WD_INFO <3> corresponding to the third write command WRITE_COMMAND <3> at the time when the third write command WRITE_COMMAND <3> ). As a result, it is confirmed that the third write data (WRITE_DATA <3>) contains the value of the cold data in the third characteristic information (WD_INFO <3>). .

When the memory system 110 confirms the characteristic information WD_INFO <1, 2, 3> of each of the write data WRITE_DATA <1, 2, 3> through the above-described method, And controls the manner in which the write data (WRITE_DATA <1, 2, 3>) is stored based on the check result.

For example, in the case of the first write data (WRITE_DATA < 1 >) identified as hot data including a value indicating hot data in the first characteristic information (WD_INFO < 1 & The first memory blocks 151 <1, 2, 3, ...> among the memory blocks 151 <1, 2, 3, Lt; / RTI >

In the case of the second write data (WRITE_DATA < 2 >) identified by the cold data including the value indicating the cold data in the second characteristic information (WD_INFO <2>) through the check result, The second memory blocks 153 <1, 2, 3, ...> among the memory blocks 151 <1, 2, 3, Lt; / RTI >

Similarly, in the case of the third write data (WRITE_DATA < 3 >) identified as the cold data including the value indicative of the cold data in the third characteristic information (WD_INFO <3> The second memory blocks 153 <1, 2, 3, ...> among the memory blocks 151 <1, 2, 3, Lt; / RTI >

The first memory blocks 151 <1, 2, 3, ...> among the memory blocks 151 <1, 2, 3, ...>) can be managed as a hot memory block, and the second memory blocks 153 <1, 2, 3, ...> can be managed as a cold memory block. Separating and managing the memory blocks 151 <1, 2, 3, ...>, 153 <1, 2, 3, ...> into hot memory blocks and cold memory blocks, ) Reliability and service life.

In summary, in the memory system 110, the characteristic information WD_INFO <1, 2, 3> of each of the write data (WRITE_DATA <1, 2, 3>) is stored in the memory area 512 of the host memory 510 (WRITE_DATA < 1, 2, 3 >) according to the check result, it is possible to confirm whether each of the write data (WRITE_DATA < Each of which can be programmed into memory blocks managed with hot data blocks or with memory blocks managed with cold data blocks.

Since the write data (WRITE_DATA <1, 2, 3>) managed in the system area 514 of the host memory 510 are data generated and managed by the host 102, The operation of grasping whether each of the data WRITE_DATA <1, 2, 3> is hot data or cold data is performed when each of the write data WRITE_DATA <1, 2, 3> is transferred to the memory system 110 Is much more accurate than checking whether each of the write data (WRITE_DATA < 1, 2, 3 >) in the controller 130 in the post-memory system 110 is hot data or cold data.

Referring to FIG. 6C together with FIG. 5 for explaining another embodiment, the host 102 stores write data WRITE_DATA <1, 2, 3> managed in the system area 514 of the host memory 510, (WRITE_DATA <1, 2, 3>) is large data, based on the size of the write data (WRITE_DATA <1, 2, 3>). After distinguishing whether or not each of the write data WRITE_DATA <1, 2, 3> is large data, the host 102 determines whether the write data WRITE_DATA <1, 2, 3> A value indicating that the first write data WRITE_DATA < 1 > is not large data in the first characteristic information WD_INFO <1> corresponding to the first write data WRITE_DATA <1> . In addition, a value indicating that the second write data (WRITE_DATA < 2 >) is large data is included in the second characteristic information (WD_INFO <2>) corresponding to the second write data (WRITE_DATA <2> . In addition, a value indicating that the third write data (WRITE_DATA <3>) is large data is included in the third characteristic information (WD_INFO <3>) corresponding to the third write data (WRITE_DATA <3> . After generating the characteristic information WD_INFO <1, 2, 3> corresponding to each of the write data WRITE_DATA <1, 2, 3>, the generated characteristic information WD_INFO < &Gt;) in the memory area 512.

In other words, the host 102 generates the write data (WRITE_DATA <1, 2, 3>) and manages it in the system area 514 before it is programmed in the memory system 110 (WD_INFO < 1, 2, 3 >) of the write data (WRITE_DATA <1, 2, 3>) is stored in the memory area 512.

In this case, the write data (WRITE_DATA <1, 2, 3>) is continuously managed in the system area 514 and the characteristic information corresponding to each of the write data (WRITE_DATA < 1, 2, 3>) corresponding to the write data WRITE_DATA <1, 2, 3> described in FIG. 5 are stored in the memory area 512, 2, 3>) exist as separate data.

After the characteristic information WD_INFO <1, 2, 3> corresponding to each of the write data WRITE_DATA <1, 2, 3> is stored in the memory area 512, (WRITE COMMAND < 1, 2, 3 >) to program the memory system 110 to the memory system 110 and to transmit the write commands WRITE COMMAND <1, 2, 3>

The memory system 110 stores the write data WRITE_DATA (1, 2, 3) corresponding to the write commands WRITE COMMAND <1, 2, 3> at the time when the write commands WRITE COMMAND (1, 2, 3 &gt;) in the memory area 512. In this case,

For example, when the host 102 generates and sends the first write command WRITE_COMMAND <1> to the memory system 110 to program the first write data WRITE_DATA <1> to the memory system 110, The memory system 110 stores the first characteristic information WD_INFO < 1 > corresponding to the first write command WRITE_COMMAND <1> at the time when the first write command WRITE_COMMAND <1> ). As a result, it is confirmed that the first write data WRITE_DATA < 1 > is included in the first characteristic information WD_INFO < 1 & .

When the host 102 generates and sends the second write command WRITE_COMMAND <2> to the memory system 110 to program the second write data WRITE_DATA <2> to the memory system 110, The memory system 110 stores the second characteristic information WD_INFO <2> corresponding to the second write command WRITE_COMMAND <2> at the time when the second write command WRITE_COMMAND <2> ). As a result, it is confirmed that the second write data (WRITE_DATA < 2 >) includes the value of the large data in the second characteristic information WD_INFO <2> .

Similarly, when the host 102 generates and transmits the third write command WRITE_COMMAND <3> to the memory system 110 to program the third write data WRITE_DATA <3> to the memory system 110, The memory system 110 stores the third characteristic information WD_INFO <3> corresponding to the third write command WRITE_COMMAND <3> at the time when the third write command WRITE_COMMAND <3> ). As a result, it is confirmed that the third write data (WRITE_DATA <3>) contains a value of large data in the third characteristic information (WD_INFO <3>). .

When the memory system 110 confirms the characteristic information WD_INFO <1, 2, 3> of each of the write data WRITE_DATA <1, 2, 3> through the above-described method, And controls the manner in which the write data (WRITE_DATA <1, 2, 3>) is stored based on the check result.

For example, the memory system 110 stores the first write data (WRITE_DATA < 1 >) having a value indicating that the first characteristic information WD_INFO < 1 & 1, 2, 3, ..., 153) when the first write data (WRITE_DATA <1>) is received from the host 102 without performing another preparatory operation, &Lt; 1, 2, 3, ... >).

In the case of the second write data (WRITE_DATA < 2 >) identified as large data including a value indicating large data in the second characteristic information (WD_INFO <2>) through the confirmation result, A preparation operation of securing a set number of free memory blocks among the memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, 1, 2, 3,...>, 153 <1, 2, 3, ...> received from the host 102 to the second write data (WRITE_DATA < Lt; / RTI >

That is, the memory system 110 can confirm that the second write data (WRITE_DATA <2>) is large data before receiving the second write data (WRITE_DATA <2>), It is possible to perform a preparation operation for reserving a predetermined number or more of free memory blocks sufficient to program the data (WRITE_DATA <2>).

If there is only a predetermined number or less of free memory blocks among the memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, Memory block 520 in a state where only the second write data WRITE_DATA <2> received from the host 102 is stored in the cache memory 520, and the number of free memory blocks is equal to or greater than the set number It is also possible to operate so as to become

Likewise, in the case of the third write data (WRITE_DATA <3>) identified by the large data including the value indicating the large data in the third characteristic information (WD_INFO <3>) through the check result, A preparation operation of securing a set number of free memory blocks among the memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, 1, 2, 3,...>, 153 <1, 2, 3, ...> received from the host 102 to the third write data (WRITE_DATA < Lt; / RTI >

That is, the memory system 110 can confirm that the third write data (WRITE_DATA <3>) is the large data before receiving the third write data (WRITE_DATA <3>), It is possible to perform a preparation operation for reserving a predetermined number or more of free memory blocks sufficient to program the data (WRITE_DATA <3>).

If there is only a predetermined number or less of free memory blocks among the memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, The memory controller 520 performs an operation such as garbage collection in a state where only the third write data WRITE_DATA <3> received from the host 102 is stored in the cache memory 520, It is also possible to operate so as to become

6A and FIG. 6B, the first memory blocks 151 <1, 2, 3,... In the case of the first write data (WRITE_DATA <1>) other than the large data >, And in the case of the second write data WRITE_DATA <2> and the third write data WRITE_DATA <3> which are the large data, the second memory blocks 153 <1, 2, 3, It is possible that the memory system 110 operates in a form in which only the memory system 110 is stored.

It is possible to reserve a predetermined number of free memory blocks before storing the large data in the memory system 110 through the above-described operation. This operation is very important in that the efficiency of the program operation of the memory system 110 can be maximized.

Referring to FIG. 6D together with FIG. 5 for explaining another embodiment, the host 102 stores write data WRITE_DATA < 1, 2, 3 > managed in the system area 514 of the host memory 510 (WRITE_DATA <1, 2, 3>) is meta data or user data, based on the logical address of the data area WRITE_DATA <1, 2, 3> After dividing each of the write data (WRITE_DATA <1, 2, 3>) into metadata or user data, the host 102 writes the write data WRITE_DATA <1, 2, 3> A value indicating that the first write data WRITE_DATA <1> is metadata is included in the first characteristic information WD_INFO <1> corresponding to the distinguished first write data WRITE_DATA <1>. In addition, a value indicating that the second write data (WRITE_DATA <2>) is user data is included in the second characteristic information (WD_INFO <2>) corresponding to the second write data (WRITE_DATA <2> . In addition, a value indicating that the third write data (WRITE_DATA <3>) is user data is included in the third characteristic information (WD_INFO <3>) corresponding to the third write data (WRITE_DATA <3> . After generating the characteristic information WD_INFO <1, 2, 3> corresponding to each of the write data WRITE_DATA <1, 2, 3>, the generated characteristic information WD_INFO < &Gt;) in the memory area 512.

In other words, the host 102 generates the write data (WRITE_DATA <1, 2, 3>) and manages it in the system area 514 before it is programmed in the memory system 110 (WD_INFO < 1, 2, 3 >) of the write data (WRITE_DATA <1, 2, 3>) is stored in the memory area 512.

In this case, the write data (WRITE_DATA <1, 2, 3>) is continuously managed in the system area 514 and the characteristic information corresponding to each of the write data (WRITE_DATA < 1, 2, 3>) corresponding to the write data WRITE_DATA <1, 2, 3> described in FIG. 5 are stored in the memory area 512, 2, 3>) exist as separate data.

After the characteristic information WD_INFO <1, 2, 3> corresponding to each of the write data WRITE_DATA <1, 2, 3> is stored in the memory area 512, (WRITE COMMAND < 1, 2, 3 >) to program the memory system 110 to the memory system 110 and to transmit the write commands WRITE COMMAND <1, 2, 3>

The memory system 110 stores the write data WRITE_DATA (1, 2, 3) corresponding to the write commands WRITE COMMAND <1, 2, 3> at the time when the write commands WRITE COMMAND (1, 2, 3 &gt;) in the memory area 512. In this case,

For example, when the host 102 generates and sends the first write command WRITE_COMMAND <1> to the memory system 110 to program the first write data WRITE_DATA <1> to the memory system 110, The memory system 110 stores the first characteristic information WD_INFO < 1 > corresponding to the first write command WRITE_COMMAND <1> at the time when the first write command WRITE_COMMAND <1> ). As a result, it is confirmed that the first write data WRITE_DATA < 1 > is included in the first characteristic information WD_INFO < 1 & .

When the host 102 generates and sends the second write command WRITE_COMMAND <2> to the memory system 110 to program the second write data WRITE_DATA <2> to the memory system 110, The memory system 110 stores the second characteristic information WD_INFO <2> corresponding to the second write command WRITE_COMMAND <2> at the time when the second write command WRITE_COMMAND <2> ). As a result, it is confirmed that the second write data (WRITE_DATA <2>) contains a value of user data in the second characteristic information (WD_INFO <2>). .

Similarly, when the host 102 generates and transmits the third write command WRITE_COMMAND <3> to the memory system 110 to program the third write data WRITE_DATA <3> to the memory system 110, The memory system 110 stores the third characteristic information WD_INFO <3> corresponding to the third write command WRITE_COMMAND <3> at the time when the third write command WRITE_COMMAND <3> ). As a result of checking, it is confirmed that the third write data (WRITE_DATA <3>) contains a value of user data in the third characteristic information (WD_INFO <3>). .

When the memory system 110 confirms the characteristic information WD_INFO <1, 2, 3> of each of the write data WRITE_DATA <1, 2, 3> through the above-described method, And controls the manner in which the write data (WRITE_DATA <1, 2, 3>) is stored based on the check result.

For example, in the case of the first write data (WRITE_DATA < 1 >) identified by the metadata including the value indicating the meta data in the first characteristic information (WD_INFO < 1 >) through the check result, And stores it in the cache memory 520 for management. The first write data WRITE_DATA <1> stored in the cache memory 520 is temporarily stored in the memory blocks 151 <1, 2, 3, and 4 for backup at a set point such as a check point, ..., 153 &lt; 1, 2, 3, ... &gt;, and is always stored in the cache memory 520. [

Also, in the case of the second write data (WRITE_DATA <2>) including the value indicating the user data in the second characteristic information (WD_INFO <2>) and confirmed by the user data through the confirmation result, the memory system (110) The memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, ...> That is, in the case of the second write data (WRITE_DATA <2>) which is the user data, the memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, But may be deleted from the cache memory 520 after the program is completed.

Likewise, in the case of the third write data (WRITE_DATA <3>) identified by the user data including the value indicating the user data in the third characteristic information (WD_INFO <3>) through the check result, The memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, ...> That is, in the case of the third write data (WRITE_DATA <3>) which is the user data, the memory blocks 151 <1, 2, 3, ...> 153 <1, 2, 3, But may be deleted from the cache memory 520 after the program is completed.

The first write data (WRITE_DATA < 1 >) identified as metadata having a relatively high probability of accessing from the host 102 relatively among the write data (WRITE_DATA <1, 2, 3> , It can be stored and managed in the cache memory 520 which operates relatively quickly. On the other hand, the second write data (WRITE_DATA < 2 >) identified as user data with a low probability of repeatedly accessing from the host 102 among the write data (WRITE_DATA < In the case of the write data (WRITE_DATA <3>), it can be programmed in the memory device 150 that operates relatively slowly. In this way, managing the write data (WRITE_DATA &lt; 1, 2, 3 &gt;) separately by metadata and user data is very important because it greatly affects the operation speed of the entire memory system 110.

In summary, in the memory system 110, the characteristic information WD_INFO <1, 2, 3> of each of the write data (WRITE_DATA <1, 2, 3>) is stored in the memory area 512 of the host memory 510 (WRITE_DATA < 1, 2, 3 >) according to the confirmation result, it is possible to confirm whether each of the write data (WRITE_DATA < To be programmed into memory blocks 151 <1, 2, 3, ..., 153 <1, 2, 3, ...> .

Since the write data (WRITE_DATA <1, 2, 3>) managed in the system area 514 of the host memory 510 are data generated and managed by the host 102, The operation of recognizing whether each of the data WRITE_DATA <1, 2, 3> is a meta data or a user data is performed when each write data WRITE_DATA <1, 2, 3> is transferred to the memory system 110 Is much more accurate than checking whether each of the write data (WRITE_DATA <1, 2, 3>) in the controller 130 in the post-memory system 110 is metadata or user data.

7-15, a memory system 110 (not shown) including the memory device 150 and the controller 130 described in FIGS. 1-5 and 6A-6D in accordance with an embodiment of the present invention will now be described, ) Will be described in more detail.

7 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 7 is a schematic view of a memory card system to which a memory system according to an embodiment of the present invention is applied.

Referring to Fig. 7, the memory card system 6100 includes a memory controller 6120, a memory device 6130, and a connector 6110. Fig.

More specifically, the memory controller 6120 is coupled to a memory device 6130 implemented as a non-volatile memory, and is implemented to access the memory device 6130. For example, the memory controller 6120 is implemented to control the read, write, erase, and background operations of the memory device 6130, and the like. The memory controller 6120 is then implemented to provide an interface between the memory device 6130 and the host and is configured to drive firmware to control the memory device 6130. That is, the memory controller 6120 corresponds to the controller 130 in the memory system 110 described in FIG. 1, and the memory device 6130 corresponds to the memory device 150 in the memory system 110 described in FIG. ). &Lt; / RTI &gt;

Accordingly, the memory controller 6120 includes components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit .

In addition, the memory controller 6120 can communicate with an external device, such as the host 102 described in Fig. 1, via the connector 6110. [ For example, the memory controller 6120 may be connected to an external device such as a USB (Universal Serial Bus), an MMC (multimedia card), an eMMC (embeded MMC), a peripheral component interconnection (PCI) Advanced Technology Attachment), Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS) , Bluetooth, and the like, thereby enabling the memory system and the data processing system according to embodiments of the present invention to be used in wired / wireless electronic devices, particularly mobile electronic devices, Can be applied.

The memory device 6130 may be implemented as a nonvolatile memory such as an EPROM (Electrically Erasable and Programmable ROM), a NAND flash memory, a NOR flash memory, a PRAM (Phase-change RAM), a ReRAM RAM), an STT-MRAM (Spin-Torque Magnetic RAM), and the like.

In addition, the memory controller 6120 and the memory device 6130 may be integrated into one semiconductor device, and may be integrated into one semiconductor device to form a solid state drive (SSD) SD card (SD, miniSD, microSD, SDHC), PC card (PCMCIA), compact flash card (CF), smart media card (SM, SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro, eMMC) , A universal flash memory device (UFS), and the like.

8 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention.

8, data processing system 6200 includes a memory device 6230 implemented with at least one non-volatile memory, and a memory controller 6220 that controls memory device 6230. [ The data processing system 6200 shown in FIG. 8 may be a storage medium such as a memory card (CF, SD, microSD, etc.), a USB storage device, Corresponds to the memory device 150 in the memory system 110 described in Figure 1 and the memory controller 6220 can correspond to the controller 130 in the memory system 110 described in Figure 1 .

The memory controller 6220 controls read, write, erase operations and the like for the memory device 6230 in response to a request from the host 6210. The memory controller 6220 includes at least one CPU 6221, A buffer memory such as RAM 6222, an ECC circuit 6223, a host interface 6224, and a memory interface, such as an NVM interface 6225.

Here, the CPU 6221 can control the overall operation of the memory device 6230, e.g., read, write, file system management, bad page management, etc.). The RAM 6222 operates under the control of the CPU 6221 and can be used as a work memory, a buffer memory, a cache memory, and the like. When the RAM 6222 is used as a work memory, the data processed in the CPU 6221 is temporarily stored. When the RAM 6222 is used as a buffer memory, 6230 or to the host 6210 from the memory device 6230 and when the RAM 6222 is used as cache memory the low speed memory device 6230 will be used to operate at high speed .

The ECC circuit 6223 corresponds to the ECC unit 138 of the controller 130 described with reference to FIG. 1 and includes a fail bit of data received from the memory device 6230, Or an error correction code (ECC: Error Correction Code) for correcting an error bit. In addition, the ECC circuit 6223 performs error correction encoding of data provided to the memory device 6230 to form data with a parity bit added thereto. Here, the parity bit may be stored in the memory device 6230. Also, the ECC circuit 6223 can perform error correction decoding on the data output from the memory device 6230, at which time the ECC circuit 6223 can correct the error using parity. For example, the ECC circuit 6223 uses various coded modulation such as LDPC code, BCH code, turbo code, Reed-Solomon code, convolution code, RSC, TCM and BCM as described in FIG. So that the error can be corrected.

The memory controller 6220 transmits and receives data and the like with the host 6210 via the host interface 6224 and transmits and receives data and the like with the memory device 6230 via the NVM interface 6225. Here, the host interface 6224 can be connected to the host 6210 through a PATA bus, a SATA bus, a SCSI, a USB, a PCIe, a NAND interface, and the like. The memory controller 6220 is connected to an external device such as a host 6210 or an external device other than the host 6210 by implementing a wireless communication function, WiFi or Long Term Evolution (LTE) Data, and the like, and is configured to communicate with an external device through at least one of various communication standards, it is possible to use a memory system according to an embodiment of the present invention in wired / wireless electronic devices, And a data processing system can be applied.

9 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 9 is a schematic view of a solid state drive (SSD) to which a memory system according to an embodiment of the present invention is applied.

Referring to FIG. 9, the SSD 6300 includes a memory device 6340 and a controller 6320, which includes a plurality of non-volatile memories. The controller 6320 corresponds to the controller 130 in the memory system 110 described in FIG. 1 and the memory device 6340 corresponds to the memory device 150 in the memory system 110 described in FIG. Lt; / RTI &gt;

More specifically, the controller 6320 is connected to the memory device 6340 through a plurality of channels CH1, CH2, CH3, ..., CHi. The controller 6320 includes at least one processor 6321, a buffer memory 6325, an ECC circuit 6322, a host interface 6324, and a memory interface, for example, a nonvolatile memory interface 6326.

Here, the buffer memory 6325 temporarily stores data received from the host 6310 or data received from a plurality of flash memories NVMs included in the memory device 6340, or a plurality of flash memories (NVMs) ), For example, a map table. The buffer memory 6325 may be implemented as a volatile memory such as a DRAM, an SDRAM, a DDR SDRAM, an LPDDR SDRAM, or a GRAM or a nonvolatile memory such as a FRAM, a ReRAM, a STT-MRAM or a PRAM. But may also be external to the controller 6320. The controller 6320 of FIG.

The ECC circuit 6322 calculates the error correction code value of the data to be programmed in the memory device 6340 in the program operation and outputs the data read from the memory device 6340 in the read operation to the memory device 6340 based on the error correction code value And performs an error correction operation of the recovered data from the memory device 6340 in the recovery operation of the failed data.

The host interface 6324 also provides an interface function with an external device such as a host 6310 and a nonvolatile memory interface 6326 provides an interface function with a memory device 6340 connected via a plurality of channels do.

A plurality of SSDs 6300 to which the memory system 110 described with reference to FIG. 1 is applied may implement a data processing system such as a Redundant Array of Independent Disks (RAID) system. In this case, A plurality of SSDs 6300, and a RAID controller for controlling the plurality of SSDs 6300. When the RAID controller receives the write command from the host 6310 and performs the program operation, the RAID controller reads data corresponding to the write command from the plurality of RAID levels, that is, from the plurality of SSDs 6300 to the host 6310 (I.e., SSD 6300) in accordance with the RAID level information of the write command received from the SSD 6300, and then output the selected SSD 6300 to the selected SSD 6300. When the RAID controller receives the read command from the host 6310 and performs the read operation, the RAID controller reads the RAID level of the read command received from the host 6310 in the plurality of RAID levels, that is, the plurality of SSDs 6300 In response to the information, at least one memory system, i.e., SSD 6300, may be selected and then provided to the host 6310 from the selected SSD 6300.

10 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 10 is a view schematically showing an embedded multimedia card (eMMC) to which a memory system according to an embodiment of the present invention is applied.

Referring to FIG. 10, the eMMC 6400 includes a memory device 6440 implemented with at least one NAND flash memory, and a controller 6430. The controller 6430 corresponds to the controller 130 in the memory system 110 described in Fig. 1 and the memory device 6440 corresponds to the memory device 150 in the memory system 110 described in Fig. Lt; / RTI &gt;

More specifically, the controller 6430 is connected to the memory device 2100 through a plurality of channels. The controller 6430 includes at least one core 6432, a host interface 6431, and a memory interface, e.g., a NAND interface 6433.

Here, the core 6432 controls the overall operation of the eMMC 6400, the host interface 6431 provides the interface function between the controller 6430 and the host 6410, and the NAND interface 6433 is a memory And provides an interface function between the device 6440 and the controller 6430. For example, the host interface 6431 may be a parallel interface, e.g., an MMC interface, as described in FIG. 1, and may also include a serial interface, such as a UHS (Ultra High Speed) .

11 through 14 are diagrams schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIGS. 11 to 14 are views schematically showing a UFS (Universal Flash Storage) to which a memory system according to an embodiment of the present invention is applied.

11 through 14, each of the UFS systems 6500, 6600, 6700, and 6800 includes hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, And UFS cards 6530, 6630, 6730, and 6830, respectively. Here, each of the hosts 6510, 6610, 6710, and 6810 may be an application processor such as a wired / wireless electronic device, particularly a mobile electronic device, and each UFS device 6520,6620,6720,6820 ) Are embedded UFS (Embedded UFS) devices. In addition, each of the UFS cards 6530, 6630, 6730, 6830 includes an external embedded UFS device or a removable UFS card .

Also, in each of the UFS systems 6500, 6600, 6700, and 6800, each of the hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530 , 6630, 6730, 6830) can communicate with external devices, such as wired / wireless electronic devices, especially mobile electronic devices, etc., via the UFS protocol, and UFS devices 6520, And UFS cards 6530, 6630, 6730, and 6830 may be implemented in the memory system 110 described with reference to FIG. For example, in each of the UFS systems 6500, 6600, 6700, and 6800, the UFS devices 6520, 6620, 6720, and 6820 are connected to the data processing system 6200, the SSD 6300, Or eMMC 6400, and the UFS cards 6530, 6630, 6730, and 6830 may be implemented in the form of the memory card system 6100 described in FIG.

In addition, in each of the UFS systems 6500, 6600, 6700, and 6800, each of the hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530 , 6630, 6730, and 6830 can perform communication through a Universal Flash Storage (UFS) interface, for example, a MIPI M-PHY and a MIPI UniPro (Unified Protocol) in a Mobile Industry Processor Interface (MIPI) The devices 6520, 6620, 6720, 6820 and the UFS cards 6530, 6630, 6730, 6830 can communicate via protocols other than the UFS protocol, for example, various card protocols such as UFDs, MMC , Secure digital (SD), mini SD, and micro SD.

UniPro is present in each of the host 6510, the UFS 6520 and the UFS card 6530 in the UFS system 6500 shown in Fig. 11. The host 6510 is connected to the UFS 6520, The host 6510 performs a swtiching operation in order to perform communication with the UFS card 6530 and the UFS card 6530, 6520 or performs communication with the UFS card 6530. [ At this time, communication between the UFS unit 6520 and the UFS card 6530 can be performed through link layer switching in the UniPro of the host 6510. In the embodiment of the present invention, for convenience of description, one UFS device 6520 and a UFS card 6530 are connected to the host 6510, respectively. However, a plurality of UFS devices The UFS cards may be connected to the host 6410 in a parallel form or a star form, and a plurality of UFS cards may be connected to the UFS unit 6520 in a parallel form or a star form, or in a serial form or a chain form .

In the UFS system 6600 shown in Fig. 12, UniPro is present in the host 6610, the UFS device 6620, and the UFS card 6630, respectively, and includes a switching module 6640, In particular, the host 6610 communicates with the UFS device 6620 or communicates with the UFS card 6630 via a switching module 6640 that performs link layer switching, e.g., L3 switching operation, in UniPro . At this time, the communication between the UFS unit 6520 and the UFS card 6530 may be performed through link layer switching in the UniPro of the switching module 6640. In the embodiment of the present invention, for convenience of description, one UFS device 6620 and a UFS card 6630 are connected to the switching module 6640, respectively. However, a plurality of UFS devices And UFS cards may be connected to the switching module 6640 in a parallel form or in a star form and a plurality of UFS cards may be connected to the UFS unit 6620 in a parallel form or in a star form or in a serial form or a chain form It is possible.

In addition, in the UFS system 6700 shown in FIG. 13, UniPro exists in the host 6710, the UFS device 6720, and the UFS card 6730, respectively, and includes a switching module 6740 for performing a switching operation, The host 6710 communicates with the UFS device 6720 or communicates with the UFS card 6730 via a switching module 6740 that performs link layer switching, e.g., L3 switching operation, in UniPro . At this time, the UFS device 6720 and the UFS card 6730 may perform communication through link layer switching in the UniPro of the switching module 6740, and the switching module 6740 may perform communication through the UFS 6720 And may be implemented as a single module with the UFS device 6720, either internally or externally. Although one UFS unit 6620 and one UFS card 6630 are connected to the switching module 6740 for convenience of explanation in the embodiment of the present invention, And the UFS device 6720 may be connected to the host 6710 in a parallel form or in a star form, or the respective modules may be connected in a serial form or chain form, and a plurality of UFS cards May be connected to the switching module 6740 in a parallel form or in a star form.

In the UFS system 6800 shown in Fig. 14, M-PHY and UniPro are respectively present in the host 6810, the UFS device 6820, and the UFS card 6830, and the UFS device 6820, The UFS device 6820 performs a switching operation to perform communication with the host 6810 and the UFS card 6830 respectively and in particular the UFS device 6820 includes an M-PHY and UniPro module for communication with the host 6810, Communicates with the host 6810 or communicates with the UFS card 6830 through switching, e.g., Target ID, switching between the M-PHY and UniPro modules for communication with the host 6810 . At this time, the host 6810 and the UFS card 6530 may perform the communication through the target ID switching between the M-PHY and UniPro modules of the UFS unit 6820. In this embodiment of the present invention, for convenience of description, one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to one UFS device 6820 However, a plurality of UFS devices may be connected to the host 6810 in a parallel form or a star form, or may be connected in a serial form or a chain form. In a UFS device 6820, a plurality of UFS cards may be connected in parallel Or may be connected in star form, or in series form or chain form.

15 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 15 is a view schematically showing a user system to which the memory system according to the present invention is applied.

15, the user system 6900 includes an application processor 6930, a memory module 6920, a network module 6940, a storage module 6950, and a user interface 6910.

More specifically, the application processor 6930 drives the components included in the user system 6900, an operating system (OS), and for example, the components included in the user system 6900 Controllers, interfaces, graphics engines, and so on. Here, the application processor 6930 may be provided as a system-on-chip (SoC).

The memory module 6920 can be operated as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 6900. The memory module 6920 may be a volatile random access memory such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDRAM, an LPDDR3 SDRAM, an LPDDR3 SDRAM, or a nonvolatile random access memory such as a PRAM, a ReRAM, Memory. For example, the application processor 6930 and the memory module 6920 may be packaged and implemented based on a POP (Package on Package).

Also, the network module 6940 can communicate with external devices. For example, the network module 6940 may support not only wired communication but also other services such as Code Division Multiple Access (CDMA), Global System for Mobile communications (GSM), Wideband CDMA (WCDMA), CDMA- The present invention can perform communication with wired / wireless electronic devices, particularly mobile electronic devices, by supporting various wireless communications such as Access, Long Term Evolution (LTE), Wimax, WLAN, UWB, Bluetooth and WI-DI. Accordingly, the memory system and the data processing system according to the embodiment of the present invention can be applied to wired / wireless electronic devices. Here, the network module 6940 may be included in the application processor 6930.

In addition, the storage module 6950 may store data, e.g., store data received from the application processor 6930, and then transfer the data stored in the storage module 6950 to the application processor 6930. [ The storage module 6950 may be implemented as a nonvolatile semiconductor memory device such as a PRAM (Phase Change RAM), an MRAM (Magnetic RAM), an RRAM (Resistive RAM), a NAND flash, a NOR flash, And may also be provided as a removable drive, such as a memory card, an external drive, etc., of the user system 6900. That is, the storage module 6950 may correspond to the memory system 110 described with reference to FIG. 1, and may also be implemented with the SSD, eMMC, and UFS described in FIGS.

The user interface 6910 may include interfaces for inputting data or instructions to the application processor 6930 or outputting data to an external device. For example, the user interface 6910 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, , And a user output interface such as an LCD (Liquid Crystal Display), an OLED (Organic Light Emitting Diode) display device, an AMOLED (Active Matrix OLED) display device, an LED, a speaker and a motor.

1 is applied to a mobile electronic device of a user system 6900, the application processor 6930 controls the overall operation of the mobile electronic device, The network module 6940 is a communication module that controls wired / wireless communication with an external device as described above. In addition, the user interface 6910 supports displaying data processed by the application processor 6930 as a display / touch module of the mobile electronic device, or receiving data from the touch panel.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

510: host memory 512: memory area
514: system area 520: cache memory
151 <1, 2, 3, ...>: The first memory blocks
153 <1, 2, 3, ...>: the second memory blocks

Claims (20)

A host including a host memory including a system area and a memory area, the host including characteristics information of write data managed in the system area in the memory area; And
After receiving the write command corresponding to the write data from the host, checks the characteristic information of the write data stored in the memory area and adjusts the storage method of the write data applied from the host on the basis of the confirmation result Memory system
And the data processing system.
The method according to claim 1,
The host,
Hot data or cold data on the basis of the update frequency of the write data managed in the system area and stores the write data classified into hot data in the system area in the memory And copying or moving the read data into the first subspace of the area and copying or moving the write data separated by the cold data from the system area to the second subspace of the memory area. 3. The method of claim 2,
The memory system comprising:
A nonvolatile memory device comprising a plurality of first memory blocks and a plurality of second memory blocks,
Program the write data to the first memory blocks when it is confirmed that the write data is stored in the first subspace through the check result,
And program the write data in the second memory blocks when it is confirmed that the write data is stored in the second subspace through the check result.
The method according to claim 1,
The host,
And storing information for distinguishing hot data or cold data based on an update frequency of the write data managed in the system area in the memory area.
5. The method of claim 4,
The memory system comprising:
A nonvolatile memory device comprising a plurality of first memory blocks and a plurality of second memory blocks,
And programming the first memory blocks when the write data is confirmed as hot data through the check result,
And if the write data is identified as cold data through the check result, programs the second memory blocks.
The method according to claim 1,
The host,
Wherein information indicating whether or not the data is large is stored in the memory area as characteristic information of the write data based on a size of the write data managed in the system area.
The method according to claim 6,
The memory system comprising:
A non-volatile memory device comprising a plurality of memory blocks,
And performs a preparation operation so as to secure a predetermined number or more of the number of free memory blocks among the memory blocks when the write data is identified as large data through the confirmation result.
The method according to claim 1,
The host,
And stores information indicating that the data is meta data or user data based on a logical address of the write data in the memory area as characteristic information of the write data.
9. The method of claim 8,
In a commercial memory system,
A non-volatile memory device including a plurality of memory blocks, and a cache memory for temporarily storing data input / output between the host and the host,
If the write data is found to be metadata in the check result, the write data is stored and managed in the cache memory,
And if the write data is determined to be user data in the checking result, programs the memory blocks. 10. The method of claim 9,
In a commercial memory system,
And program the write data stored as meta data in the cache memory to the memory blocks at a set time.
A method of operating a data processing system including a host including a host memory including a system area and a memory area, and a memory system receiving and storing write data from the host,
Managing the write data in the system area by the host and including characteristic information of the write data in the memory area;
Transmitting the write command corresponding to the write data from the host to the memory system and confirming the property information of the write data stored in the memory area in the memory system; And
And adjusting the manner in which the write data is stored internally in the memory system based on a result of the verifying step.
12. The method of claim 11,
Wherein the step of including,
Generating the write data at the host and storing the generated write data in the system area; And
Hot data or cold data on the basis of a frequency of update of the write data stored in the system area and then writing the write data divided into hot data in the system area to the memory area And copying or moving the write data into the first subspace of the memory area, and copying or moving the write data separated by the cold data from the system area to the second subspace of the memory area, Way.
13. The method of claim 12,
The memory system includes a non-volatile memory device including a plurality of first memory blocks and a plurality of second memory blocks,
Wherein the adjusting comprises:
Programming the write data identified in the first subspace to the first memory blocks in the memory system through the verifying step; And
And programming the write data identified in the second subspace to the second memory blocks in the memory system via the verifying step.
12. The method of claim 11,
Wherein the step of including,
Generating the write data at the host and storing the generated write data in the system area; And
Storing information for distinguishing hot data or cold data based on an update frequency of the write data stored in the system area in the memory area; Way.
15. The method of claim 14,
The memory system includes a non-volatile memory device including a plurality of first memory blocks and a plurality of second memory blocks,
Wherein the adjusting comprises:
Programming the first memory blocks in the memory system if the write data is identified as hot data through the verifying step; And
And programming the second memory blocks in the memory system when the write data is identified as cold data through the verifying step.
12. The method of claim 11,
Wherein the step of including,
Generating the write data at the host and storing the generated write data in the system area; And
And storing information indicating whether the data is large data in the memory area as characteristic information of the write data based on a size of the write data stored in the system area .
17. The method of claim 16,
The memory system includes a non-volatile memory device including a plurality of memory blocks,
Wherein the adjusting comprises:
A data processing system for performing a preparation operation in the memory system to secure a predetermined number or more of the memory blocks in a free state among the memory blocks when the write data is identified as large data, Lt; / RTI &gt;
12. The method of claim 11,
Wherein the step of including,
Generating the write data at the host and storing the generated write data in the system area; And
And storing information indicating that the data is meta data or user data based on a logical address of the write data stored in the system area as characteristic information of the write data in the memory area, Lt; / RTI &gt;
19. The method of claim 18,
The memory system includes a nonvolatile memory device including a plurality of memory blocks, and a cache memory for temporarily storing data to be input / output to / from the host,
Wherein the adjusting comprises:
Storing and managing the write data in the cache memory in the memory system when the write data is confirmed as metadata; And
And programming the memory blocks in the memory system if the write data is determined to be user data through the verifying step.
20. The method of claim 19,
Wherein the adjusting comprises:
Further comprising programming the write data stored as metadata in the cache memory in the memory system to the memory blocks at a set point.

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