KR20180038211A - Fuse circuit, repair control circuit and semiconductor apparatus including the same - Google Patents

Abstract

The technique includes a fuse array including a plurality of first fuse sets shared by a plurality of first redundant word lines and a plurality of second fuse sets corresponding one-to-one to a plurality of second redundant word lines; a fuse latch set array configured to generate a plurality of sets of flag signals indicating a match between defective addresses read from the fuse array and externally inputted addresses during the push-up operation of a semiconductor device; and a repair determination part configured to generate a plurality of repair determination signals according to the plurality of flag signal sets and to block the activation of a part of the plurality of repair determination signals in accordance with a normal repair interruption signal. It is possible to improve the efficiency of a post package repair operation.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a fuse circuit, a repair control circuit, and a semiconductor device including the fuse circuit,

The present invention relates to a semiconductor circuit, and more particularly, to a fuse circuit, a repair control circuit, and a semiconductor device including the same.

Semiconductor Circuits Semiconductor circuits having a data storage area, such as a semiconductor memory, for example, may experience defective memory cells in a unit data storage area, such as in a manufacturing process or a packaging process.

Therefore, the semiconductor circuit may include a repair circuit for performing a repair operation for replacing the defective memory cell with a spare memory cell.

In addition, the semiconductor circuit may include a post package repair (PPR) function for repairing defective memory cells even after packaging is completed.

Embodiments of the present invention provide a fuse circuit, a repair control circuit, and a semiconductor device including the fuse circuit, the repair control circuit, and the like, capable of improving the efficiency of the post package repair operation.

An embodiment of the present invention includes a plurality of first fuse sets for programming a detected defective address before packaging of a semiconductor device is performed; And a plurality of second fuse sets for programming a defective address detected after the packaging, wherein the plurality of first fuse sets are shared by a plurality of first redundant word lines, and the plurality of second fuses The sets may correspond one-to-one to a plurality of second redundant word lines.

An embodiment of the present invention is a fuse array including a plurality of first fuse sets shared by a plurality of first redundant word lines and a plurality of second fuse sets corresponding one-to-one to a plurality of second redundant word lines; A fuse latch set array configured to generate a plurality of sets of flag signals indicating a match of defective addresses read from the fuse array and externally input addresses during a push-up operation of a semiconductor device; And a repair determination unit configured to generate a plurality of repair determination signals in accordance with the plurality of flag signal sets and to block activation of a part of the plurality of repair determination signals in accordance with the normal repair interruption signal.

An embodiment of the present invention includes a memory cell array including a plurality of normal word lines and a plurality of redundant word lines for replacing the plurality of normal word lines; And a plurality of first fuse sets shared by a plurality of first redundant word lines and a plurality of second fuse sets corresponding one-to-one to a plurality of second redundant word lines among the plurality of redundant word lines. Wherein the repair control circuit includes a plurality of first fuse sets and a plurality of first fuse sets, wherein the repair control circuit includes a plurality of first fuse sets, May be configured to block repair operations by the fuse sets.

This technique can improve the efficiency of the post package repair operation in a semiconductor device.

1 is a diagram illustrating a configuration of a memory system 100 according to an embodiment of the present invention,
FIG. 2 is a diagram showing the configuration of the semiconductor memory of FIG. 1,
3 is a diagram showing a configuration of the memory cell array 103 of FIG. 2,
Fig. 4 is a diagram showing the configuration of the fuse array 106 of Fig. 2,
5 is a diagram showing a configuration of the repair control unit 107 of FIG. 2,
FIG. 6 is a diagram showing a configuration of a fuse latch set (FUSE LATCH SET - 31, FUSE LATCH SET - 0)
FIG. 7 is a diagram showing the configuration of the latch 400 of FIG. 6,
8 to 10 are diagrams showing the configuration of the comparators CMP_31, CMP_0 and CMP_7 in FIG. 5,
11 is a diagram showing a configuration of the normal repair cutoff signal generator 900 of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The memory system 100 according to an exemplary embodiment of the present invention may be implemented as a system in package, a multi-chip package, a system on chip, (Package On Package) including a package of a package.

1, a memory system 100 according to an embodiment of the present invention includes a semiconductor memory 101, that is, a stacked semiconductor memory 101 in which a plurality of dies are stacked, a memory controller (CPU or GPU) An interposer, and a package substrate (Package Substrate).

The semiconductor memory 101 may be configured as a HBM (High Bandwidth Memory) type in which a plurality of dies are stacked and electrically connected through a penetrating electrode to increase the number of input / output units to increase the bandwidth. have.

An interposer may be connected to the top of the package substrate.

The semiconductor memory 101 and the memory controller (CPU or GPU) can be connected to the upper portion of the interposer.

The semiconductor memory 101 and the memory controller (CPU or GPU) can be connected to each physical area (PHY) through an interposer.

The semiconductor memory 101 may be constructed by stacking a plurality of dies.

The plurality of dies may include a base die and a plurality of core dies.

The base die and the plurality of core dies may be electrically connected through a plurality of through electrodes (for example, TSV: Through Silicon Via).

2, one or both of the base die and the plurality of core dies of FIG. 1, for example, includes a memory cell array 103, a decoder 104, a command / address processing unit (not shown) 105, a fuse array 106, and a repair control unit 107.

The decoder 104 may decode the row address and column address to select the word line and bit line of the memory cell array 103.

The command / address processing unit 105 receives and decodes the command / address signal C / A externally and outputs a command related to the normal operation such as a read command / write command or signals related to the push-up operation and the repair operation, And may provide a row address and a column address associated with the normal operation / repair operation to the decoder 104 or the repair control unit 107. The decoder 104 or the repair control unit 107 may generate the bank operation information BK0_ACT and the bank active information BK0_ACT and BK1_ACT.

The boot-up mode signal (Boot) is a signal defining the boot-up mode, which can be activated during the boot-up mode operation.

The bank active information BK0_ACT and BK1_ACT includes the first bank active information BK0_ACT capable of defining the activation of the first memory bank BK0 and the second bank active BK0_ACT capable of defining the activation of the second memory bank BK1. Information (BK1_ACT).

The fuse array 106 may include a plurality of fuses and may store defective addresses, that is, addresses corresponding to defective memory cells among the memory cells of the memory cell array 103, in units of fuses.

The fuse array 106 can use a plurality of electronic fuses (e-fuses) capable of recording information through program operation after packaging as well as in a wafer state.

The repair control unit 107 can program the defective address detected before or after the packaging in the fuse array 106 according to a command generated by the command / address processing unit 105, for example, a repair instruction.

The repair control unit 107 can read and internally store defective addresses programmed into the fuse array 106 in response to a command generated by the command / address processing unit 105, for example, a push-up command.

The repair control unit 107 may perform a repair operation to select a redundant word line instead of the normal word line of the memory cell array 103 when the externally input address matches an internally stored defective address.

As shown in FIG. 3, the memory cell array 103 may include a plurality of unit memory blocks, for example, a plurality of memory banks BK0, BK1, ....

The plurality of memory banks BK0, BK1, ... may be configured identically.

For example, the first memory bank BK0 may include a plurality of word lines WL and RWL, a plurality of bit lines BL, and a plurality of memory cells MC connected to the plurality of word lines WL and RWL.

At this time, WL among the plurality of word lines (WL, RWL) may represent a normal word line, and RWL may represent a redundant word line for replacing WL corresponding to a defect address among WLs.

As shown in FIG. 4, the fuse array 106 may include a plurality of fuse sets (FUSE SET_O to FUSE SET_31).

At this time, a plurality of fuse sets (FUSE SET_O to FUSE SET_31) are examples of fuse sets allocated to some areas of the memory cell array 103.

A plurality of fuse sets (FUSE SET_O to FUSE SET_31) can be programmed with different defect addresses.

The plurality of fuse sets FUSE SET_O to FUSE SET_31 includes first fuse sets FUSE SET_8 to FUSE SET_31 and second fuse sets FUSE SET_0 to FUSE SET_7).

The normal repair fuse sets FUSE SET_8 to FUSE SET_31 may be a configuration for programming an address corresponding to a memory cell determined to be defective in the wafer test process before the packaging is performed, for example.

At this time, the program operation may be performed by rupture the fuses of the fuse set to the addresses.

The post package repair fuse sets FUSE SET_0 to FUSE SET_7 may be a configuration for programming an address corresponding to a memory cell in which a failure has occurred since packaging.

The normal repair fuse sets FUSE SET_8 to FUSE SET_31 may be shared by the first memory banks BK0 and the second memory bank BK1, respectively. That is, each of the normal repair fuse sets (FUSE SET_8 to FUSE SET_31) may be shared with a plurality of (for example, four) redundant word lines for replacing a plurality of normal word lines corresponding to different addresses.

For example, four redundant word lines (RWL0 - RWL3 for convenience) may be assigned to FUSE SET_31.

The fuse set (FUSE SET_31) may store an enable signal EN and an address signal A <1: n> which define whether the fuse is used or not.

At this time, since the fuse sets FUSE SET_8 to FUSE SET_31 are shared by the plurality of normal word lines, it is necessary to program the least significant address bit A0 for distinguishing a plurality of normal word lines from the entire address bits A <0: n> none.

In the normal operation, the defect address programmed in the FUSE SET_31 is any of the row addresses corresponding to the four normal word lines (WL0 to WL3 for convenience), the externally input row address is the defective address programmed in the FUSE SET_31 If they match, all of WL0-WL3 can be replaced by four redundant word lines (RWL0-RWL3) corresponding to them.

On the other hand, the post package repair fuse sets FUSE SET_0 to FUSE SET_7 may correspond to the redundant word lines on a one-to-one basis, respectively.

The post package repair fuse sets FUSE SET_0 to FUSE SET_7 may be divided into first post package repair fuse sets FUSE SET_0 to FUSE SET_3 and second post package repair fuse sets FUSE SET_4 to FUSE SET_7.

The redundant word lines (for convenience, RWLa-RWLd) for the first memory bank BK0 may be corresponded one-to-one to the first post-package repair fuse sets FUSE SET_0 to FUSE SET_3.

The redundant word lines RWLe-RWLh for the second memory bank BK1 may be corresponded one-to-one to the second post-package repair fuse sets FUSE SET_4 to FUSE SET_7.

The fuse set FUSE SET_0 may store an enable signal EN and an address signal A < 0: n > that define whether the fuse is used or not.

At this time, since the fuse sets (FUSE SET_0 to FUSE SET_7) correspond to the redundant word lines on a one-to-one basis, as described above, the lowest address bit A0 for distinguishing each of the redundant word lines can be programmed.

If the defective address programmed in FUSE SET_0 is a row address corresponding to the normal word line (for convenience, WL4) of the first memory bank BK0 and the externally input row address matches the defective address programmed in FUSE SET_0, WL4 May be replaced with a corresponding redundant word line (RWLa).

If the defective address programmed in FUSE SET_4 is a row address corresponding to the normal word line (for convenience, WL8096) of the second memory bank BK1 and the externally input row address matches the defective address programmed in FUSE SET_4, then WL8096 May be replaced by a corresponding redundant word line (RWLe).

As shown in FIG. 5, the repair control unit 107 of FIG. 2 may include a fuse latch set array 300, a repair determination unit 500, and a normal repair cutoff signal generation unit 900.

The fuse latch set array 300 may store defective addresses read from a plurality of fuse sets (FUSE SET_O to FUSE SET_31) during a push-up operation.

The fuse latch set array 300 includes a plurality of flag signal sets (Hit <8: 31> <1: n> / EN, Hit <4>) for notifying whether stored defective addresses match an externally input address : 7> <0: n> / EN, Hit <0: 3> <0: n> / EN).

The fuse latch set array 300 may include a plurality of fuse latch sets FUSE LATCH SET_O to FUSE LATCH SET_31.

A plurality of fuse latch sets (FUSE LATCH SET_O to FUSE LATCH SET_31) may correspond one-to-one with a plurality of fuse sets (FUSE SET_O to FUSE SET_31) of FIG.

FUSE LATCH SET_8 to FUSE LATCH SET_31 among the plurality of fuse latch sets FUSE LATCH SET_O to FUSE LATCH SET_31 may correspond to normal repair fuse sets FUSE SET_8 to FUSE SET_31, (FUSE SET_0 to FUSE SET_3), and FUSE LATCH SET_4 to FUSE LATCH SET_7 may correspond to second post package repair fuse sets (FUSE SET_4 to FUSE SET_7).

In a push-up operation, a plurality of fuse latch sets (FUSE LATCH SET_O to FUSE LATCH SET_31) may store defect addresses read from a plurality of fuse sets (FUSE SET_O to FUSE SET_31).

The repair judgment unit 500 judges whether or not the boot mode signal Boot, the first bank active information BK0_ACT, the second bank active information BK1_ACT and the plurality of flag signal sets Hit <8:31> <1: n> / (Hitb <0:31>) according to EN, Hit <4: 7> <0: n> / EN, Hit <0: 3> <0: n> / EN have.

The repair determining unit 500 may block activation of some of the plurality of repair determination signals (Hitb <0:31>), for example, Hitb <8: 31> when the normal repair shutoff signal (Hitb_dis) is activated.

The repair determination unit 500 may include a plurality of comparators CMP_0 to CMP_31.

The plurality of first comparators CMP_8 to CMP_31 among the plurality of comparators CMP_0 to CMP_31 includes a plurality of flag signal sets Hit <8:31> <1: n> / EN, Hit <4: 7> (Hit <8:31> <1: n> / EN) among a plurality of first flag signal sets (Hit <8: 31> <1: n> / EN) (Hitb < 8:31 >) among the first repair determination signals (Hitb <0:31>).

The plurality of first comparators CMP_8 to CMP_31 may be configured to be identical to each other.

The plurality of first comparators CMP_8 to CMP_31 among the plurality of comparators CMP_0 to CMP_31 block the activation of the first repair determination signals Hitb <8:31> when the normal repair blocking signal Hitb_dis is activated .

The normal repair shutoff signal Hitb_dis is generated by FUSE LATCH SET_0 to FUSE LATCH SET_7 which stores defect addresses of post package repair fuse sets FUSE SET_0 to FUSE SET_7, that is, post package repair fuse sets FUSE SET_0 to FUSE SET_7. Is a signal for allowing the repair operation to be performed preferentially in comparison with the FUSE LATCH SET_8 to FUSE LATCH SET_31 storing defective addresses of the normal repair fuse sets (FUSE SET_8 to FUSE SET_31).

For example, when a defect of a redundant word line corresponding to a row address stored in any one of FUSE LATCH SET_8 to FUSE LATCH SET_31 is detected, the corresponding address is set to any one of the post-package repair fuse sets (FUSE SET_0 to FUSE SET_7) Can be programmed.

In this case, Hitb < 8 > and Hitb < 0 > can be activated simultaneously by a fuse latch set, e.g., FUSE LATCH SET_8 and FUSE LATCH SET_0, in which the same row address is stored.

Therefore, Hitb <0> can be activated preferentially by blocking the activation of Hitb <8> by FUSE LATCH SET_8 using the normal repair blocking signal (Hitb_dis).

The plurality of second comparators CMP_0 to CMP_3 among the plurality of comparators CMP_0 to CMP_31 are provided with a plurality of flag signal sets Hit <8:31> <1: n> / EN, Hit <4: 7> (Hit <0: 3> <1: n> / EN) and the boot-up mode signal Boot from among the plurality of second flag signal sets (Hit <0: 3> <1: n> / EN) (Hitb < 0: 3 >) out of a plurality of repair decision signals (Hitb <0:31>) according to the first bank active information BK0_ACT.

The plurality of second comparators CMP_0 to CMP_3 may be configured to be identical to each other.

The plurality of third comparators CMP_4 to CMP_7 among the plurality of comparators CMP_0 to CMP_31 are provided with a plurality of flag signal sets Hit <8:31> <1: n> / EN, Hit <4: 7> (Hit <4: 7> <1: n> / EN) and the boot-up mode signal (Boot) among the plurality of third flag signal sets (Hit <4: 7> <1: n> / EN) (Hitb <4: 7>) among the plurality of repair determination signals (Hitb <0:31>) according to the first bank active information (BK1_ACT) and the second bank active information (BK1_ACT).

The plurality of third comparators CMP_4 to CMP_7 may be configured to be identical to each other.

The normal repair shutoff signal generating unit 900 generates a normal repair shutoff signal Hitb_dis according to Hitb <0: 7> and the bootup mode signal Boot among a plurality of repair determination signals (Hitb <0:31>) .

6, the fuse latch sets FUSE LATCH SET_8 to FUSE LATCH SET_31 may be configured identically, for example, the fuse latch set_31 may include a plurality of latches 400, . &Lt; / RTI &gt;

The plurality of latches 400 of the fuse latch set_31 may store the enable signal EN and the address signal A <1: n> output from the fuse set FUSE SET_31 separately for each bit.

As described above, since the fuse latch sets FUSE LATCH SET_8 to FUSE LATCH SET_31 correspond one-to-one to the normal repair fuse sets FUSE SET_8 to FUSE SET_31 shared by the plurality of normal word lines, It is not necessary to store the least significant bit A0 for distinguishing the line.

The fuse latch sets FUSE LATCH SET_0 to FUSE LATCH SET_7 may be configured identically. For example, the fuse latch set FO may include a plurality of latches 401.

The plurality of latches 401 of the fuse latch set_0 can store the enable signal EN and the address signal A <0: n> output from the fuse set FUSE SET_0, respectively.

Since the fuse latch sets FUSE LATCH SET_0 to FUSE LATCH SET_7 correspond to one-to-one correspondence to the post-package repair fuse sets FUSE SET_0 to FUSE SET_7 allocated one-to-one to the redundant word line of the memory bank, The lowest address bit A0 for distinguishing each line can be stored.

The plurality of latches 400 and 401 may be configured identically to each other.

As shown in FIG. 7, the latch 400 may include a plurality of logic gates 411 - 419.

The latch 400 latches the enable signal EN and the address signal A <1: n> output from the fuse set FUSE SET_31 in accordance with the fuse selection signal FSEL <i> May be received as the input signal IN < i > and stored in the node Node_A.

Thereafter, in the normal operation, one of the row addresses input from the outside is accepted as the input signal IN < i >, and when the level of one bit among the signal level and the row address stored in the node Node_A coincide, < i >) to a high level.

For example, in a push-up operation, the fuse selection signal FSEL < i > is at a high level so that the logic gate 412 can be turned on. When the input signal IN < i > is at a high level, a high level can be stored in the node Node_A via the logic gate 412. [

Thereafter, the logic gate 412 can be turned off since the fuse selection signal FSEL < i > is low level in the normal operation. The logic gate 417 can be turned on because the node Node A is at a high level. If the input signal IN < i > is at the high level, the flag signal (Hit < i >) can be activated to the high level via the logic gates 416 and 417.

On the other hand, since the high level is stored in the node Node_A through the push-up operation, the logic gate 417 can be maintained in the turn-on state. Thereafter, the logic gates 412 and 415 may be turned off since the fuse selection signal FSEL < i > is low level in the normal operation. If the input signal IN < i > is low level, the flag signal (Hit < i >) can be deactivated to low level through the logic gates 416 and 417.

As another example, the logic gate 412 may be turned on because the fuse selection signal FSEL < i > is high during the push-up operation. A low level can be stored in the node Node_A via the logic gate 412 when the input signal IN < i > is low level.

Thereafter, the logic gate 412 can be turned off since the fuse selection signal FSEL < i > is low level in the normal operation. Because node Node A is at a low level, logic gate 417 is turned off and logic gate 418 can be turned on. The flag signal (Hit < i >) can be activated to a high level through the logic gates 416 and 418 if the input signal IN < i >

On the other hand, since the low level is stored in the node (Node_A) through the push-up operation, the logic gate 418 can be kept turned on. Thereafter, the logic gates 412 and 415 may be turned off since the fuse selection signal FSEL < i > is low level in the normal operation. If the input signal IN < i > is at a high level, the flag signal (Hit < i >) can be deactivated to low level through the logic gates 416 and 418.

As shown in FIG. 8, the comparator CMP_31 of FIG. 4 may include a plurality of logic gates 511, 513, 515, and 517.

Logic gates 511 may output the flag signal set (Hit < 31 &lt; 1: n &gt;) by negative logical multiplication.

Logic gates 511 may generate a low level output when the flag signal set (Hit <31> < 1: n >) is all activated to a high level.

Logic gates 513 are coupled between the power supply stage and the ground stage and can bring node (Node_B) high if the outputs of logic gates 511 are all low.

The logic gates 515 may make the node Node_B low if any of the outputs of the logic gates 511 are at a high level.

The logic gate 517 may output the result of the negative logical multiplication of the level of the node Node_B, the enable signal EN and the normal repair blocking signal Hitb_dis as a repair judgment signal Hitb <31>.

The comparator CMP_31 is turned on when all of the flag signal sets (Hit <31> <1: n>) are activated to the high level, the enable signal EN is activated to the high level and the normal repair blocking signal (Hitb_dis) The repair determination signal Hitb <31> can be activated to the low level only when it is inactivated to the low level.

The comparator CMP_31 can deactivate the repair determination signal (Hitb <31>) to a high level regardless of the remaining input signals when the normal repair shutoff signal (Hitb_dis) is activated to the low level.

As shown in FIG. 9, the comparator CMP_0 of FIG. 4 may include a plurality of logic gates 521, 523, 525, 527, 528, 529.

Logic gates 521 may output the flag signal set (Hit <0> < 0: n >) negatively and logically multiplied.

Logic gates 521 may produce a low level output when the flag signal set (Hit <0> < 0: n >) is all activated to a high level.

Logic gates 523 are coupled between the power stage and the ground stage, and can make node Node_C high if the outputs of logic gates 521 are all low.

The logic gates 525 may make the node Node_C low if any of the outputs of the logic gates 521 are at a high level.

The logic gates 527 and 528 may output the boolean mode signal Boot and the first bank active information BK0_ACT together.

Logic gate 529 may output the result of the negative logical multiplication of the level of node Node_C, the enable signal EN, and the output of logic gate 528 as a repair decision signal (Hitb < 0 >).

The comparator CMP_0 is turned on when all of the flag signal sets (Hit <0> <0: n>) are activated to the high level, the enable signal EN is activated to the high level, The repair determination signal Hitb < 0 > can be activated to a low level only when any one of the active information BK0_ACT is activated.

The comparator CMP_31 changes the repair judgment signal Hitb <0> to the high level regardless of the remaining input signals when both the boot-up mode signal Boot and the first bank active information BK0_ACT are inactivated to the low level Can be deactivated.

In other words, the comparator CMP_31 is not in the current boot-up mode and may block activation of the repair determination signal (Hitb <0>) to a low level when the first memory bank BK0 is not activated.

As shown in FIG. 10, the comparator CMP_7 of FIG. 4 may include a plurality of logic gates 531, 533, 535, 537, 538, 539.

Logic gates 531 may negatively logically multiply the flag signal set (Hit <7> <0: n>) and output.

Logic gates 531 may generate a low level output when the flag signal set (Hit <7> <0: n>) is all activated high.

The logic gates 533 are connected between the power supply terminal and the ground terminal, and can make the node Node_D high level when the outputs of the logic gates 531 are all low level.

The logic gates 535 may make the node Node_D low if any of the outputs of the logic gates 531 are at a high level.

Logic gates 537 and 538 can output the boolean mode signal Boot and the second bank active information BK1_ACT by performing a logical sum.

Logic gate 539 may output the result of the negative logical multiplication of the level of node Node_D, the enable signal EN, and the output of logic gate 538 as a repair decision signal (Hitb <7>).

The comparator CMP_7 is turned on when all of the flag signal sets (Hit <7> <0: n>) are activated to the high level, the enable signal EN is activated to the high level, The repair determination signal Hitb < 7 > can be activated to a low level only when any one of the active information BK1_ACT is activated.

The comparator CMP_7 changes the repair judgment signal Hitb <7> to the high level regardless of the remaining input signals when both the boot-up mode signal Boot and the second bank active information BK1_ACT are inactivated to the low level Can be deactivated.

That is, the comparator CMP_7 is not in the current break-up mode and can block activation of the repair determination signal (Hitb <7>) to the low level when the second memory bank BK1 is not activated.

11, the normal repair shutdown signal generator 900 may include a plurality of logic gates 911, 913, 915, and 917. [

The logic gates 911 can output the repair decision signals (Hitb < 0: 7 >) negatively and logically.

The logic gate 913 can perform the NOR operation on the output of the logic gates 911.

Logic gates 915 and 917 can output the normal repair shutoff signal Hitb_dis by logically combining the output of the logic gate 913 and the boot-up mode signal Boot.

The normal repair cutoff signal generating unit 900 generates repair repair signal fsets_0 to fuse_set_7 generated by the fuse latch sets FUSE_LATCH_SET_0 to FUSE_LATCH_SET7 storing the defect addresses of the post package repair fuse sets FUSE_SET_0 to FUSE_SET_7. <0: 7>), the normal repair shutoff signal (Hitb_dis) can be activated.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (20)

A plurality of first fuse sets for programming a detected defective address before the packaging of the semiconductor device is performed; And
A plurality of second fuse sets for programming a defective address detected after said packaging,
Wherein the plurality of first fuse sets are shared by a plurality of first redundant word lines and the plurality of second fuse sets are one to one correspond to a plurality of second redundant word lines. The method according to claim 1,
The plurality of first fuse sets
Wherein the remaining signal bits except for the least significant bit among all the signal bits of the defect address are programmed. The method according to claim 1,
The plurality of second fuse sets
Wherein a total signal bit of the defective address is programmed. The method according to claim 1,
Some of the plurality of second fuse sets
One-to-one correspondence to the plurality of first redundant word lines located in the first memory area among the memory areas of the semiconductor device,
The remaining of the plurality of second fuse sets
One to one correspondence to the plurality of second redundant word lines located in the second memory area of the memory area of the semiconductor device. A fuse array including a plurality of first fuse sets shared by a plurality of first redundant word lines and a plurality of second fuse sets corresponding one-to-one to a plurality of second redundant word lines;
A fuse latch set array configured to generate a plurality of sets of flag signals indicating a match of defective addresses read from the fuse array and externally input addresses during a push-up operation of a semiconductor device; And
And a repair determination unit configured to generate a plurality of repair determination signals in accordance with the plurality of flag signal sets and to block activation of a part of the plurality of repair determination signals in accordance with the normal repair interruption signal. 6. The method of claim 5,
And a normal repair shutoff signal generator configured to generate the normal repair shutoff signal according to the plurality of repair determination signals. 6. The method of claim 5,
The plurality of first fuse sets
And the remaining signal bits except for the least significant bit among the entire signal bits of the defect address are programmed. 6. The method of claim 5,
The plurality of second fuse sets
And the entire signal bit of the defect address is programmed. 6. The method of claim 5,
Some of the plurality of second fuse sets
One-to-one correspondence to the plurality of first redundant word lines located in the first memory area among the memory areas of the semiconductor device,
The remaining of the plurality of second fuse sets
One correspondence to the plurality of second redundant word lines located in the second memory area among the memory areas of the semiconductor device. 6. The method of claim 5,
The repair determination unit
Wherein the repair control circuit is configured to generate the plurality of repair determination signals in accordance with a set of a banking mode signal, a bank active information, and a plurality of flag signal sets. 6. The method of claim 5,
The repair determination unit
When a defect address stored in any one of the plurality of second fuse sets matches any one of the plurality of first fuse sets,
And to inhibit activation of a repair determination signal corresponding to any one of the plurality of first fuse sets among the plurality of repair determination signals. 6. The method of claim 5,
The repair determination unit
Generating first repair determination signals among the plurality of repair determination signals in accordance with a plurality of first flag signal sets among the plurality of flag signal sets, and activating the first repair determination signals in accordance with the normal repair interruption signal A plurality of first comparators configured to &lt; RTI ID = 0.0 &gt;
A plurality of second comparators configured to generate second repair determination signals from the plurality of repair determination signals in accordance with a plurality of second flag signal sets, a start-up mode signal, and first bank active information among the plurality of flag signal sets, And
A plurality of third comparators configured to generate third repair determination signals among the plurality of repair determination signals in accordance with the plurality of third flag signal sets, the bump mode signal, and the second bank active information among the plurality of flag signal sets, Includes repair control circuit. The method according to claim 6,
The normal repair cutoff signal generating unit
And to activate the normal repair shutoff signal when any one of the plurality of repair determination signals generated by the second fuse set is activated. A memory cell array including a plurality of normal word lines and a plurality of redundant word lines for replacing the plurality of normal word lines; And
A plurality of first fuse sets shared by a plurality of first redundant word lines among the plurality of redundant word lines and a plurality of second fuse sets corresponding one-to-one to a plurality of second redundant word lines, And a repair control circuit,
Wherein the repair control circuit is configured to block the repair operation by the plurality of first fuse sets when a defective address stored in any one of the plurality of second fuse sets matches one of the plurality of first fuse sets . 15. The method of claim 14,
The repair control circuit
A fuse latch set array configured to generate a plurality of flag signal sets that indicate whether defect addresses read from the fuse array match an externally input address during a push-up operation of a semiconductor device, and
And a repair determination unit configured to generate a plurality of repair determination signals according to the plurality of flag signal sets and to block activation of a part of the plurality of repair determination signals in accordance with the normal repair interruption signal. 16. The method of claim 15,
Further comprising a normal repair shutoff signal generator configured to activate the normal repair shutoff signal when any signal generated by the plurality of second fuse sets is activated among the plurality of repair determination signals. 15. The method of claim 14,
The plurality of first fuse sets
The remaining signal bits excluding the least significant bit among the entire signal bits of the defect address are programmed. 15. The method of claim 14,
The plurality of second fuse sets
And the entire signal bit of the defect address is programmed. 15. The method of claim 14,
Some of the plurality of second fuse sets
One-to-one correspondence to the plurality of first redundant word lines located in a first memory bank of the memory cell array,
The remaining of the plurality of second fuse sets
One-to-one correspondence to the plurality of second redundant word lines located in a second memory bank of the memory cell array. 16. The method of claim 15,
The repair determination unit
Generating first repair determination signals among the plurality of repair determination signals in accordance with a plurality of first flag signal sets among the plurality of flag signal sets, and activating the first repair determination signals in accordance with the normal repair interruption signal A plurality of first comparators configured to &lt; RTI ID = 0.0 &gt;
A plurality of second flag signal sets among the plurality of flag signal sets,
A plurality of second comparators configured to generate second repair determination signals from the plurality of repair determination signals in accordance with a first bank active information defining a bust-up mode signal and an active of a first memory bank of the memory cell array,
And a second bank active information defining active of a second memory bank of the memory cell array and a plurality of third flag signal sets among the plurality of flag signal sets, And a third plurality of comparators configured to generate three repair determination signals.

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