KR20180028613A - Memory System and Memory Control Method - Google Patents

Abstract

The present invention provides a memory system and a memory control method capable of securing a time margin. According to one aspect of the present invention, the memory system comprises: a memory device; and a memory controller for adjusting delay of a data strobe clock, processing at least one of a read test and a write test on the memory device, detecting at least one data bit reducing at least one of a setup margin and a hold margin among a plurality of data bits, and adjusting delay of the at least one bit to increase the reduced at least one margin.

Description

[0001] DESCRIPTION [0002] MEMORY SYSTEM AND MEMORY CONTROL METHOD [

An embodiment of the present invention relates to a memory system and a memory control method.

The characteristics of the memory may change with the use environment, the number of times of use, or the use time. Accordingly, a data skew may occur in the memory interface of the system using the memory according to the voltage and the environment change. Much research is underway to reduce data skew in memory interfaces.

To reduce data skew and stably execute the data latch, the memory system can perform a calibration that positions the data strobe clock signal at the center of the timing margin of the data signal. However, the calibration for the data strobe clock signal was not performed before the read and write operations to the memory device occurred (initial training) and could not improve the reduced timing margin.

Various embodiments of the present invention can provide a memory system and a memory control method capable of securing a timing margin.

A memory system according to an aspect of the present invention includes: a memory device; And at least one of a read test and a write test for the memory device and controls at least one of a setup margin and a hold margin among a plurality of data bits, And a memory controller for detecting at least one data bit that reduces one margin and adjusting the delay of the at least one bit to increase the at least one margin that is reduced.

According to another aspect of the present invention, a method for controlling a memory by at least one processor comprises: controlling a delay of a data strobe clock; performing at least one of a read test and a write test for a memory device; Detecting at least one data bit that reduces at least one of a setup margin and a hold margin among the plurality of data bits; And adjusting the delay of the at least one bit to increase the reduced at least one margin.

According to another aspect of the present invention, there is provided a memory controller including: a storage unit for storing a setup margin and a hold margin; And at least one of a read test and a write test for a memory device and adjusts a delay of a data strobe clock and at least one of a set margin and a hold margin of the plurality of data bits, A processor for detecting one data bit and adjusting the delay of the at least one bit to increase the at least one margin that is reduced.

According to the present invention, the timing margin of the memory interface due to PI and SI effects can be improved.

1 is a block diagram illustrating a memory system according to an embodiment of the present invention.
2 and 3 are timing diagrams illustrating a data interface according to an embodiment of the present invention.
4 is a block diagram illustrating a memory controller according to an embodiment of the present invention.
5 is a timing diagram of a setup margin test process according to an embodiment of the present invention.
6 is a timing diagram of a hold margin test process according to an embodiment of the present invention.
7 is a flowchart illustrating a method of securing a timing margin of a read operation according to an embodiment of the present invention.
8 is a flowchart illustrating a method of securing a timing margin of a write operation according to an embodiment of the present invention.

Various embodiments of the invention will now be described with reference to the accompanying drawings. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments of the invention. In connection with the description of the drawings, like reference numerals may be used for similar components.

In this document, the expressions "have," "may," "include," or "include" may be used to denote the presence of a feature (eg, a numerical value, a function, Quot ;, and does not exclude the presence of additional features. In this document, the expressions "A or B," "at least one of A and / or B," or "one or more of A and / or B," etc. may include all possible combinations of the listed items . For example, "A or B," "at least one of A and B," or "at least one of A or B" includes (1) at least one A, (2) Or (3) at least one A and at least one B all together.

The expressions "first," " second, "" first, " or "second ", etc. used in this document may describe various components, It is used to distinguish the components and does not limit the components. For example, the first user equipment and the second user equipment may represent different user equipment, regardless of order or importance. For example, without departing from the scope of the rights described in this document, the first component can be named as the second component, and similarly the second component can also be named as the first component.

(Or functionally or communicatively) coupled with / to "another component (eg, a second component), or a component (eg, a second component) Quot; connected to ", it is to be understood that any such element may be directly connected to the other element or may be connected through another element (e.g., a third element). On the other hand, when it is mentioned that a component (e.g., a first component) is "directly connected" or "directly connected" to another component (e.g., a second component) It can be understood that there is no other component (e.g., a third component) between other components.

As used herein, the phrase " configured to " (or set) to be "adapted to, " To be designed to, "" adapted to, "" made to, "or" capable of ". The term " configured (or set) to "may not necessarily mean " specifically designed to" Instead, in some situations, the expression "configured to" may mean that the device can "do " with other devices or components. For example, a processor configured (or configured) to perform the phrases "A, B, and C" may be a processor dedicated to performing the operation (e.g., an embedded processor), or one or more software programs To a generic-purpose processor (e.g., a CPU or an application processor) that can perform the corresponding operations.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the other embodiments. The singular expressions may include plural expressions unless the context clearly dictates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art. The general predefined terms used in this document may be interpreted in the same or similar sense as the contextual meanings of the related art and are intended to mean either ideally or in an excessively formal sense It is not interpreted. In some cases, even the terms defined in this document can not be construed as excluding the embodiments of this document.

FIG. 1 is a configuration diagram illustrating a memory system according to an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams illustrating a data interface according to an embodiment of the present invention.

1, a memory system according to an embodiment of the present invention may include a memory device 20 and a memory controller 40. [

According to one embodiment of the present invention, the memory device 20 may store data under the control of the memory controller 40. [ For example, the memory device 20 may be various memory devices such as a DDR (Double Data Rate) memory, a Flash memory, a SSD (Single Data Rate) memory, a hard disk and the like.

According to an embodiment of the present invention, the memory device 20 may be connected to the memory controller 40 via a plurality of data input / output interfaces and control interfaces. In one embodiment, the plurality of data input / output interfaces may include a plurality of data bits (DQS) that are signals for a read operation, a write operation, and addressing of read and write operations to the memory device 20. [ For example, the plurality of data bits may be 8 bits. In one embodiment, the control interface may include at least one data strobe clock (DQS_c, DQS_t) and other control signals. For example, at least one of the data strobe clocks DQS_c and DQS_t may be a signal that provides a reference point of time for reading and writing data. In the present specification, the case where the data strobe clock is provided as two signals is shown as an example, but the present invention is not limited thereto. In one embodiment, the other control signals may be different depending on the type of memory device 20 and may include, for example, WE (write enable), RE (read enable), address addr, CS Command (CMD), and the like. WE (write enable) may be a signal indicating that the memory controller 40 is writing a plurality of data bits to the memory device 20. [ RE (read enable) may be a signal indicating that the memory controller 40 is reading from the memory device 20. The address addr may be a signal indicating whether the plurality of data bits specify the address of the memory device 20 or not. The chip select (CS) signal may be a signal indicating that the memory device 20 is in an interface with a plurality of memory devices. The command CMD may be a signal for discriminating whether data transmitted through a plurality of data bits is a command or data.

According to one embodiment of the present invention, the memory controller 40 may control the read and write operations to the memory device 20. [ The memory controller 40 may control the erase operation for the memory device 20. [ For example, the memory controller 40 may be an element that controls the read and write operations to and from the memory device 20, according to instructions from the processor, between the processor and the memory device 20. [ The memory controller 40 may be configured in the form of a system on chip (SoC). In one embodiment, the processor may include one or more of a central processing unit (CPU), an application processor (AP), or a communications processor (CP).

2 or 3, the memory controller 40 according to an exemplary embodiment of the present invention synchronizes with the synchronous edge of the data strobe clock to designate a specific address of the memory device 20 to write a plurality of data bits , And may read a plurality of data bits from the memory device (20). For example, the sync edge may be at least one of a rising edge and a falling edge.

Referring to FIG. 2 or FIG. 3, a plurality of data bits may transition from a 'to a'. The setup margin b may be a time interval between synchronization edges of the data strobe clock at a time point when the state transition of all the plurality of data bits is completed. The setup margin b may be determined by a data bit whose timing is the slowest among a plurality of data bits. The hold margin c may be an interval from the synchronous edge of the data strobe clock to the start point of the next state transition of the plurality of data bits. The hold margin c can be determined by the data bit having the highest timing. The timing margin (b + c) may be the sum of the setup margin (b) and the hold margin (c).

According to one embodiment of the present invention, the memory controller 40 adjusts the delay of the data strobe clock (see 'd' in FIGS. 2 and 3) and performs a read test and a write test on the memory device 20, It is possible to measure the timing margin of the timing belt 20. For example, the memory controller 40 may perform a read test or a write test on the memory device 20 by adjusting the synchronous edge of the data strobe clock to a specified setup margin position (e.g., the start time of the b section). The memory controller 40 can detect at least one data bit that reduces a setup margin among a plurality of data bits by performing a read or a write test in a state in which a sync edge of a data strobe clock is located at a specified setup margin position have. The memory controller 40 performs a read test or write test by adjusting the synchronous edge of the data strobe clock to a specified hold margin position (e.g., the start time of the section c), and at least a hold margin One data bit can be detected.

According to one embodiment of the present invention, the memory controller 40 adjusts the delay of the data strobe clock to a setup margin or a hold margin position when performing a read test, ) Can be read. For example, the reference pattern stored in the memory device 20 may be written to the memory device 20 before the memory controller 40 adjusts the delay of the data strobe clock or before performing the read test, Pattern. The memory controller 40 compares the read reference pattern with the stored reference pattern to check whether the reference patterns match with each other or not, and can determine a bit that does not match as a data bit that reduces a setup margin or a hold margin. In one embodiment, the reference pattern may be data capable of state transitions of a plurality of data bits at a plurality of sync edges. For example, when the plurality of data bits is 8 bits, each bit of the reference pattern may be 01010101 and 10101010.

According to an embodiment of the present invention, when performing a write test, the memory controller 40 adjusts the delay of the data strobe clock to a setup margin or a hold margin position and then stores the reference pattern stored in the internal memory in the memory device 20 Can be written. The memory controller 40 may read the pattern written to the memory device 20 after restoring the delay of the data strobe clock before the position adjustment. The memory controller 40 can detect a data bit for reducing the setup margin or the hold margin by comparing the pattern read from the memory device 20 with the reference pattern of the internal memory. For example, when the reference pattern of the internal memory and the read pattern do not coincide with each other, the memory controller 40 can determine the bits that do not match among the bits of the two patterns as data bits that reduce the setup margin or the hold margin.

According to one embodiment of the present invention, the memory controller 40 controls the delay of a plurality of data bits based on the data strobe clock in the initialization process of the memory device 20, and performs a read operation (or a read test) By performing an operation (or a write test), it is possible to set the delay in which the timing margin is maximized among all possible delays for each data bit.

According to one embodiment of the present invention, the memory controller 40 may perform a read test and a write test on the memory device 20 during use of the initialized memory device 20. For example, the memory controller 40 may periodically perform read and write tests. The memory controller 40 can wait for a moment when the read operation or the write operation is instructed from the processor during the execution of the read test or the write test. The memory controller 40 can perform an operation waiting after the completion of the read test or the write test.

According to one embodiment of the present invention, the memory controller 40 may perform a read test and a write test after the threshold time has elapsed since the initialization of the memory device 20. [ For example, the threshold time may be determined using a time point at which the PI and SI effects occur due to a time delay or the like after initialization of the memory device 20. [ The memory controller 40 may perform a read test and a write test after at least one of the read operation and the write operation is performed after the initialization of the memory device 20 for a predetermined number of times or more. For example, the threshold number of times may be determined using the number of operations in which PI and SI effects occur due to repetition of operations, etc. after the initialization of the memory device 20.

Various embodiments of the present invention can adjust the delay of the data bits that cause the timing margin to be reduced, thereby ensuring a reduced timing margin due to SI and PI effects. Various embodiments of the present invention may improve the reduced timing margin in accordance with the use of the memory device.

FIG. 4 is a configuration diagram illustrating a memory controller according to an embodiment of the present invention. FIG. 5 is a timing diagram of a setup margin test process according to an embodiment of the present invention. FIG. It is a timing diagram of the test process.

4, the memory controller 40 according to an embodiment of the present invention includes a storage module 410, a training module 420, a read controller 450, a write controller 430, a read margin test module 460 and a write margin test module 440. At least one of the training module 420, the read controller 450, the write controller 430, the read margin test module 460, and the write margin test module 440 according to the embodiment of the present invention may be omitted. Each component of the memory controller 40 according to an embodiment of the present invention may be a hardware module of at least one processor and may be a software module implemented by at least one processor. For example, each component included in the memory controller 40 may be performed by at least one processor, or each processor may be executed by a separate processor.

According to one embodiment of the present invention, the storage module 410 may store test information used in read and write tests. For example, the test information may include a reference pattern, a set-up margin position, a hold margin position, and the address of a memory device used for each test. In one embodiment, the reference pattern is data for timing margin confirmation of a plurality of data bits, and may be data that is transitioned to a plurality of operation periods. For example, when the plurality of data is 8 bits, the reference pattern may be data in which each bit of the first data is 01010101 and each bit of the second data is 10101010. According to one embodiment of the present invention, the storage module 410 may be an internal memory of the memory controller 40. [

In accordance with one embodiment of the present invention, the training module 420 adjusts the interface delay for each data bit in the initialization for the memory device 20, and performs at least one of read and write operations in the adjusted delay Timing margin can be confirmed. In one embodiment, the training module 420 may adjust the interface delays of the plurality of data bits, respectively, based on the data strobe clock. The training module 420 can identify each interface delay that can relatively increase the timing margin relatively among the adjusted delays and set each identified interface delay as the interface delay of each data bit.

According to one embodiment of the present invention, the read controller 450 may perform a read operation to the memory device 20 in accordance with the instructions of the processor. Write controller 430 may perform a read operation to the memory device 20 in accordance with an instruction of the processor.

According to one embodiment of the present invention, the read controller 450 may adjust the interface delay of the read operation of the plurality of data bits. For example, the read controller 450 may adjust an interface delay for a read operation of a plurality of data bits in response to a request of at least one of the training module 420 and the read margin test module 460.

According to one embodiment of the present invention, the write controller 430 may adjust the interface delay for a write operation of a plurality of data bits. For example, the write controller 430 may adjust an interface delay for a write operation of a plurality of data bits in response to a request of at least one of the training module 420 and the write margin test module 440. For example, each interface delay may be delayed or delayed by a specified time unit (e.g., 1 ms). For example, the designated time unit may be 1 / n times the data strobe clock.

According to one embodiment of the present invention, the read margin test module 460 may perform a read test to check the timing margin of the read operation of the memory device 20. [ For example, the read margin test module 460 may adjust the delay of the data strobe clock to a specified setup margin or hold margin position and perform a read test on the memory device 20. The read margin test module 460 may detect a bit that reduces a setup margin or a hold margin as a result of a read test.

As shown in FIG. 5, the read margin test module 460 according to an embodiment of the present invention adjusts the data strobe clock to the position of the setup margin, and reads the first pattern stored in the memory device 20. In one embodiment, the first pattern is generated by the write controller 430 or the write margin test module 440 before the read test is performed (or before the position of the data strobe clock is adjusted to the setup margin position) 20). ≪ / RTI > The read margin test module 460 according to an embodiment of the present invention checks whether each bit of the read first pattern and the reference pattern of the storage module 410 coincide with each other, The flag can be output. The read margin test module 460 according to an embodiment of the present invention may compare each bit of the reference pattern and the read pattern and detect bits that do not coincide with each other as a bit whose set margin is reduced. 5, each bit (DQ [7: 0]) of the reference pattern is 11001011, and each bit (DQ [7: 0]) of the first pattern read from the memory device 20 may be 11000011. In this case, the read margin test module 460 can detect the DQ3 bit with a data bit whose set margin is reduced. According to one embodiment of the present invention, the read margin test module 460 may pass the data information with reduced setup margin to the read controller 450. In one embodiment, the read controller 450 shifts the delay of the data bits for which the set-up margin has been reduced to the left by at least one hour (for example, shifts) based on the synchronous edge of the data strobe clock to secure the setup margin of the read operation can do.

According to one embodiment of the present invention, the read margin test module 460 may adjust the data strobe clock to the hold margin position and read the first pattern stored in the memory device 20. In one embodiment, the read margin test module 460 checks whether each bit of the first pattern read and the bits of the reference pattern of the storage module 410 coincide with each other, and outputs a hold margin failure flag can do. In one embodiment, the read margin test module 460 may compare each bit of the reference pattern with the read pattern, and detect the bit that is not the result of comparison as a bit with a reduced hold margin. In FIG. 6, each bit (DQ [7: 0]) of the reference pattern is 11001011 and each bit (DQ [7: 0]) of the read first pattern may be 11101011. In this case, the read margin test module 460 can detect the DQ5 bit with a data bit whose hold margin is reduced. According to one embodiment of the present invention, the read margin test module 460 may pass the data information with the reduced hold margin to the read controller 450. The read controller 450 moves the delay of the data bit (e.g., DQ5) in which the hold margin is reduced to the right by at least one hour on the basis of the synchronous edge of the data strobe clock to secure the hold margin of the read operation can do.

According to one embodiment of the present invention, the read margin test module 460 performs the read test again when the setup margin of the read operation or the delay of the data bit that reduces the hold margin is adjusted, thereby obtaining a setup margin or a hold margin Can be confirmed. For example, the read margin test module 460 may perform a read test immediately after the delay is adjusted. According to another embodiment of the present invention, the read margin test module 460 may check whether the setup margin or the hold margin of the read operation is increased through the next read test.

According to an embodiment of the present invention, the read margin test module 460 can confirm both the setup margin and the hold margin in one read test, and only one of them can be confirmed.

According to one embodiment of the present invention, the write margin test module 440 may adjust the data strobe clock to a setup margin position and write a reference pattern to the memory device 20 when performing a write test. The write margin test module 440 may read the pattern stored in the memory device 20 from the memory device 20 by restoring the data strobe clock to the original position after writing the reference pattern. The write margin test module 440 checks whether the bits of the read second pattern and the reference pattern stored in the storage module 410 coincide with each other. If the bits do not coincide with each other, the write margin test module 440 outputs a setup margin failure flag. The write margin test module 440 compares each bit of the reference pattern with the read pattern, and detects the bits that do not coincide with each other with the bit whose set margin is reduced. The write margin test module 440 may transmit the data bit information to the write controller 430 in which the setup margin detected through the write test is reduced. According to one embodiment of the present invention, the write controller 430 shifts the delay of a data bit (e.g., DQ5) in which the setup margin is reduced to the left by at least one hour on the basis of the data strobe clock, .

According to one embodiment of the present invention, the write margin test module 440 may adjust the data strobe clock to the hold margin position and store the reference pattern in the memory device 20 when performing the write test. The write margin test module 440 may read the pattern stored in the memory device 20 by restoring the data strobe clock before adjusting the delay. The write margin test module 440 may check whether the read second pattern and the reference pattern stored in the storage module 410 coincide with each other and output a hold margin failure flag if they do not coincide with each other. The write margin test module 440 compares each bit of the reference pattern with the read second pattern, and detects non-coincident bits with a bit whose hold margin is reduced. The write margin test module 440 may transmit the data information to the write controller 430 in which the hold margin detected through the write test is reduced. According to one embodiment of the present invention, the write controller 430 shifts the delay of the data bit (e.g., DQ5) in which the hold margin is reduced by at least one hour unit shift ) So that the hold margin of the write operation can be secured.

According to an embodiment of the present invention, the write margin test module 440 can confirm both the setup margin and the hold margin in one write test, and only one of them can be confirmed.

According to one embodiment of the present invention, the read margin test module 460 may perform a read test on the memory device 20 when there is no read operation and no write operation to the memory device 20. For example, the read margin test module 460 may periodically check whether there is a read operation and a write operation, and perform a read test when there is no read operation or write operation as a result of the check. Read margin test module 460 may perform a read test when the processor is in a particular state (e.g., sleep state) where no read and write operations occur. In accordance with an embodiment of the present invention, the write margin test module 440 may also determine whether the memory device 20 (e. G., The memory device 20) ). ≪ / RTI >

According to an embodiment of the present invention, one of the read margin test module 460 and the write margin test module 440 may have a priority so that collision does not occur during each test progress. For example, the read margin test module 460 may have a priority when the memory controller 40 stores the reference pattern in the memory device 20 in advance in the initialization process and the like. Since the read test is possible after the reference pattern is written, the write margin test module 440 may have a priority.

According to one embodiment of the present invention, the read margin test module 460 and the write margin test module 440 read after the threshold time has elapsed since the initialization of the memory device 20, or after each operation has been performed a threshold number of times Test and write tests can be performed separately. For example, the read margin test module 460 may perform a read test after a threshold time has elapsed at the time of initialization of the memory device 20, or after a read operation has been performed a threshold number of times. The write margin test module 440 may perform a write test after the threshold time elapses at the time of initialization of the memory device 20 or after the write operation has been performed a threshold number of times. According to the embodiment of the present invention, since the memory device 20 is used, the test can be efficiently performed by performing the read test and the write test from the time when the influence of SI and PI occurs.

According to an embodiment of the present invention, the writing margin test module 440 may have different addresses for writing the reference pattern for the setup margin and the hold margin in each writing test. According to another embodiment of the present invention, the write margin test module 440 may erase the reference pattern after one write test. In the embodiment of the present invention, it is possible to prevent the erroneous writing test from being performed by erroneously checking the reference pattern written in the previous test at the time of the writing test.

According to one embodiment of the present invention, the read margin test module 460 and the write margin test module 440 may use different reference patterns for the read test and the write test. At least one of the read margin test module 460 and the write margin test module 440 may use a different address for each test. For example, the write margin test module 440 may perform a write test by storing the reference pattern at the next address where the data of the memory device 20 is not stored.

According to an embodiment of the present invention, the read controller 450 and the write controller 430 may center the data strobe clock to the middle of the timing margin when the delay of the data bits is adjusted. The read controller 450 and the write controller 430 can adjust the delay of the data strobe clock in consideration of the set up margin and the hold margin, which are ensured by adjusting the delay of the data bits. For example, the read controller 450 and the write controller 430 can advance the data strobe clock by half of the delay of the preceding data bit if the delay of the data bit is advanced to secure the setup margin. The read controller 450 and the write controller 430 may delay the data strobe clock by half of the delay of the delayed data bit when the delay of the data bit is delayed in order to secure the hold margin. If the delay of the data bits is adjusted by an odd time unit, the read controller 450 and the write controller 430 can adjust the delay of the data strobe clock by a division of the adjusted delay by two.

Various embodiments of the present invention can identify whether the timing margin has been reduced due to PI or SI effects during use of the memory device in the board environment of the memory device and can improve the reduced timing margin to some extent.

7 is a flowchart illustrating a method of securing a timing margin of a read operation according to an embodiment of the present invention.

Referring to FIG. 7, at operation 710, the memory controller 40 may verify that it has arrived at a predetermined period. When the memory controller 40 arrives at a predetermined period, if there is an operation (e.g., a read operation and a write operation) instructed by the processor, the memory controller 40 can perform the read test after performing the indicated operation. Or the memory controller 40 can wait for the indicated operation until the completion of the read test. In one embodiment, the memory controller 40 may check whether a predetermined period of time has elapsed since the expiration of the threshold time after initialization or after a threshold number of read operations proceeded.

In operation 715, the memory controller 40 may adjust the delay of the data strobe clock so that the synchronous edge of the data strobe clock occurs at the setup margin position.

In operation 720, the memory controller 40 may read the reference pattern stored in the first address of the memory device 20 from the memory device 20. [ In one embodiment, the reference pattern may be stored in the initialization process of the memory device 20. [ In another embodiment, the reference pattern may be stored just prior to adjusting the delay of the data strobe clock.

At operation 725, the memory controller 40 may verify that the read pattern and the stored reference pattern match each other.

In operation 730, if the read pattern and the self-stored reference pattern do not coincide with each other, the memory controller 40 can detect bits that do not coincide with each other in a bit for reducing the setup margin.

In operation 735, the memory controller 40 may adjust the delay of the bit for decreasing the setup margin in the direction of increasing the setup margin. For example, the memory controller 40 may advance the delay of the detected data bits to secure a setup margin.

In operation 740, the memory controller 40 may adjust the delay of the data strobe clock so that the synchronous edge of the data strobe clock occurs at the hold margin position.

At operation 745, the memory controller 40 may read the reference pattern from the memory device 20 at a first address of the memory device 20.

At operation 750, the memory controller 40 can verify that the read pattern matches the self-stored reference pattern.

In operation 755, if the read pattern and the self-stored reference pattern do not coincide with each other, the memory controller 40 can detect data bits that do not coincide with each other with a bit for decreasing the hold margin.

In operation 760, the memory controller 40 may adjust the delay of the detected bit in a direction to increase the hold margin. For example, the memory controller 40 can delay the delay of the detected data bits to secure a hold margin.

At operation 765, the memory controller 40 may complete the read test and then center the delay of the data strobe clock to the center position of the timing margin.

In FIG. 7, the memory controller 40 tests the setup margin of the read operation and then tests the hold margin of the read operation. In another embodiment of the present invention, the setup margin of the read operation may be tested after the hold margin of the read operation is tested.

In FIG. 7, the case where the setup margin and the hold margin are simultaneously tested in one read test is described as an example. Alternatively, in accordance with another embodiment of the present invention, the memory controller 40 may alternately test the setup margin and the hold margin in one read test. For example, the memory controller 40 may test the setup margin of the read operation in an odd period and the hold margin of the read operation in an even period.

8 is a flowchart illustrating a method of securing a timing margin of a write operation according to an embodiment of the present invention.

Referring to FIG. 8, at operation 810, the memory controller 40 may verify that it has arrived at a predetermined period. In one embodiment, the memory controller 40 can check if there is an operation (e.g., a read operation and a write operation) indicated by the processor if the predetermined period is a predetermined period. The memory controller 40 may perform a write test after performing the indicated operation when the read operation and the write operation are instructed. The memory controller 40 can wait for the indicated operation until the completion of the write test when the read operation and the write operation are instructed.

At operation 815, the memory controller 40 may adjust the delay of the data strobe clock so that the synchronous edge of the data strobe clock occurs at the setup margin position to test the write setup margin.

At operation 820, the memory controller 40 may write a reference pattern from the memory device 20 to the first address of the memory device 20. In one embodiment, the first address may be a fixed address and may be a variable address. For example, the first address may be the first address of an area where the data of the memory device 20 is not stored.

At operation 825, the memory controller 40 may restore the data strobe clock to a previous location and perform a read operation to read the reference pattern from the first address of the memory device 20. [ For example, the memory controller 40 may adjust the delay of the data strobe clock to be opposite to the delay adjusted at operation 815. [

In operation 830, the memory controller 40 can check whether the bits of the read pattern and the internally stored reference pattern coincide with each other.

In operation 835, if the read pattern and the self-stored reference pattern do not coincide with each other, the memory controller 40 can detect bits that do not coincide with each other among the bits of the two patterns, with a bit for decreasing the setup margin.

In operation 840, the memory controller 40 may adjust the delay of the detected data bits in the direction of increasing the setup margin. For example, the memory controller 40 may advance the delay of the detected data bits to secure a setup margin.

In operation 845, the memory controller 40 may adjust the delay of the data strobe clock such that the synchronous edge of the data strobe clock occurs at the hold margin position to test the write-hold margin.

At operation 850, the memory controller 40 may write the reference pattern stored at the second address of the memory device 20 from the memory device 20. [ In one embodiment, the second address may be a fixed address and may be a variable address. For example, the second address may be the first address of an area where the data of the memory device 20 is not stored.

In operation 855, the memory controller 40 may restore the data strobe clock to its original location and read the reference pattern from the second address of the memory device 20. [ In one embodiment, memory controller 40 may adjust the delay of the data strobe clock to be opposite to the delay adjusted at operation 845. [

In operation 860, the memory controller 40 can verify whether the read pattern matches the self-stored reference pattern.

In operation 865, the memory controller 40 can detect data bits that do not coincide if the read pattern and the self-stored reference pattern do not coincide with each other.

In operation 870, the memory controller 40 may adjust the delay of the detected data bits in the direction of increasing the hold margin. For example, the memory controller 40 can delay the delay of the detected data bits to secure a hold margin.

In operation 875, the memory controller 40 may center the adjusted data strobe clock through at least one of operations 840 and 870.

In FIG. 8, the case where the memory controller 40 tests the setup margin of the write operation and then tests the hold margin of the write operation has been described as an example. In another embodiment of the present invention, the setup margin of the write operation may be tested after testing the hold margin of the write operation.

In FIG. 8, the setup margin and the hold margin are simultaneously tested in one write test. Alternatively, according to another embodiment of the present invention, the memory controller 40 may alternately test the setup margin and the hold margin in a single write test. For example, the memory controller 40 may test the setup margin of the write operation in the odd period and the hold margin of the write operation in the even period.

In one embodiment of the present invention, the address at which the memory controller 40 writes the reference pattern for verification of the setup margin and the hold margin in one write test may be different. In the embodiment of the present invention, it is possible to prevent the erroneous execution of the write test by erroneously checking the reference pattern written in the previous test process at the time of confirming the setup margin and the hold margin. In another embodiment of the present invention, after one write test, the reference pattern may be erased.

In an embodiment of the present invention, the memory controller 40 may use different reference patterns for the read test and the write test. The memory controller 40 can use different addresses for the read test and the write test.

As used herein, the term "module " includes units comprised of hardware, software, or firmware and may be used interchangeably with terms such as, for example, logic, logic blocks, components, or circuits. A "module" may be an integrally constructed component or a minimum unit or part thereof that performs one or more functions. "Module" may be implemented either mechanically or electronically, for example, by application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs) And may include programmable logic devices.

At least some of the devices (e.g., modules or functions thereof) or methods (e.g., operations) according to various embodiments may be implemented with instructions stored in a computer-readable storage medium in the form of program modules. When the instruction is executed by the processor, the processor may perform a function corresponding to the instruction. The computer-readable recording medium may be a hard disk, a floppy disk, a magnetic medium such as a magnetic tape, an optical recording medium such as a CD-ROM, a DVD, a magnetic-optical medium such as a floppy disk, The instructions may include code that is generated by the compiler or code that may be executed by the interpreter. Modules or program modules according to various embodiments may include at least one or more of the components described above Some of which may be omitted, or may further include other components.

Operations performed by modules, program modules, or other components, in accordance with various embodiments, may be performed sequentially, in parallel, repetitively, or heuristically, or at least some operations may be performed in a different order, . And the embodiments disclosed in this document are presented for the purpose of explanation and understanding of the disclosed technology and do not limit the scope of the technology described in this document. Accordingly, the scope of this document should be interpreted to include all modifications based on the technical idea of this document or various other embodiments.

Claims (20)

A memory device; And
Wherein the control circuit controls at least one of a read test and a write test for the memory device and controls at least one of a setup margin and a hold margin among a plurality of data bits, A memory controller that detects at least one data bit that reduces the margin of the at least one bit and adjusts the delay of the at least one bit to increase the at least one marginal decrease;
≪ / RTI > The memory controller according to claim 1,
Adjust the data strobe clock to a designated set-up margin position to perform the read test or the write test, and detect the at least one bit to reduce the setup margin from the plurality of data bits. The memory controller according to claim 1,
Wherein the data strobe clock is adjusted to a specified hold margin position to perform the read test or the write test and the at least one bit to reduce the hold margin from the plurality of data bits. The memory controller according to claim 1,
A reference pattern stored in an internal memory is stored in the memory device when the read test is performed, a reference pattern is read from the memory device and is compared with a reference pattern of the internal memory, And determines a bit that does not match in each bit of the reference pattern as the at least one bit. The memory controller according to claim 4,
Storing a reference pattern of the internal memory in the memory device before adjusting the delay of the data strobe clock, adjusting the data strobe clock to a specified setup margin position or a designated hold margin position, and then reading the reference pattern from the memory device . The memory controller according to claim 1,
Wherein the reference pattern of the internal memory is written to the memory device when the write test is performed, the reference pattern stored in the memory device is read and compared with the reference pattern of the internal memory, And determines the mismatched bit as the at least one bit. The memory controller according to claim 6,
The data strobe clock is wired to the memory device after the data strobe clock is adjusted to a specified setup margin position or a designated hold margin position and the data strobe clock is adjusted before the setup margin position or the hold margin position is adjusted And reads the reference pattern stored in the memory device. The memory controller according to claim 1,
And performs at least one of the read test and the write test when a read operation and a write operation to the memory device are not performed after initialization of the memory device. The memory controller according to claim 8,
And performs at least one of the read test and the write test after a read operation of a first threshold number of times or more or a write operation of a second threshold number of times or more. The memory controller according to claim 1,
And adjusts the delay of the data strobe clock to place the data strobe clock in the middle of a data margin when the delay of the at least one bit is adjusted. A memory control method by at least one processor,
Adjusting a delay of a data strobe clock and performing at least one of a read test and a write test for the memory device;
Detecting at least one data bit that reduces at least one of a setup margin and a hold margin among the plurality of data bits; And
Adjusting the delay of said at least one bit to increase said at least one margin reduced
≪ / RTI > 12. The method of claim 11,
Adjusting the sync edge of the data strobe clock to a designated setup margin position to perform the read test or the write test;
Adjusting the sync edge of the data strobe clock to a designated hold margin position to perform the read test or the write test
/ RTI > 12. The method of claim 11, wherein the act of performing the read test comprises:
An operation of reading the pattern stored in the first address of the memory device from the memory device by adjusting the synchronous edge of the data strobe clock to a designated setup margin position or a hold margin position
/ RTI > 14. The method of claim 13, wherein the act of performing the read test comprises:
Storing the reference pattern stored in the internal memory of the at least one processor at the first address of the memory device before adjusting the delay of the data strobe clock. 12. The method of claim 11, wherein the act of performing the write test comprises:
Writing the reference pattern of the processor to a first address of the memory device by adjusting a delay of the data strobe clock; And
Reading the reference pattern stored in the first address from the memory device
/ RTI > 16. The method of claim 15,
And adjusting the data strobe clock to a specified setup margin position or a specified hold margin position and then writing (wirte) the reference pattern to the memory device. 17. The method of claim 16,
And restores the data strobe clock to a state prior to the adjustment of the specified setup margin position or the specified hold margin position, thereby reading the reference pattern from the memory device. 12. The method of claim 11,
Comparing the reference pattern read from the memory device with an internally stored reference pattern through the write test or the read test; And detecting, as the comparison, a bit that does not coincide in the two patterns with the at least one bit. 12. The method of claim 11,
Wherein at least one of a read operation of a first threshold number or more or a write operation of a second threshold number or more is performed after initialization of the memory device. A storage unit for storing a setup margin and a hold margin; And
At least one of a read test and a write test for the memory device is performed, and at least one of the plurality of data bits, which reduces the margin of at least one of the setup margin and the hold margin, A processor for adjusting the delay of the at least one bit to detect a data bit of the at least one bit,
.

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