KR20180026230A - Security gateway that implements multiple communication cryptographic operation parallelism - Google Patents

Abstract

The present invention provides a security gateway to implement a multi-communication cryptographic operation parallel processing. The security gateway includes: a first communication port which enables communication using a first communication protocol from a first external communication terminal; a second communication port which enables communication using a second communication protocol from a second external communication terminal; a central processing unit (CPU) which supports many core processors (MCP), gives orders so that a hardware security module (HSM) can process encryption/decryption request data transmitted from the first communication terminal through a first interface, and gives orders so that the HSM can process encryption/decryption request data transmitted from a second communication terminal through a second interface; and the HSM which uses the MCP inside and performs data encryption/decryption of the first communication terminal ordered through the first interface and data encryption/decryption of the second communication terminal ordered through the second interface simultaneously and independently. The present invention is able to minimize time delay of internal processing.

Description

[0001] SECURITY GATEWAY THAT IMPLEMENTS [0002] MULTIPLE COMMUNICATION CRYPTOGRAPHIC OPERATION PARALLELISM [

The present invention relates to a security gateway that implements parallel communication cryptographic operation parallel processing, and more particularly, to a security gateway that uses MCP (Many Core Processor) internally and performs data encryption and decryption of a first communication terminal The data encryption / decryption of the second communication terminal instructed through the second interface is carried out independently of each other, and in consideration of the correlation between the encryption algorithms, the communication port used, and the data movement speed between the cores, The present invention provides a hardware cipher module (HSM) for deciding a cipher algorithm to be placed in a core, thereby solving a bottleneck even when communication is performed through a plurality of communication terminals. In addition, A security gateway that implements parallel communication cryptographic parallelism that can minimize internal processing time delays Relate to.

In the field of information security and authentication technology, the need for development of devices and systems for securely managing hardware authentication information such as personal authentication information and passwords for financial transactions has been raised along with the spread of the Internet.

This confidential information is a means of authenticating an individual and confirming that he or she has performed a certain act directly. Therefore, if the confidential information is exposed to another person, it is impossible to specify the actor, so that the entire financial transaction system may collapse. .

To provide such high security, the concept of a hardware cryptographic module (HSM) equipped with a hardware cryptographically secure key management system is introduced.

The HSM is a device that generates a secret master key in itself and handles generation of induction keys and encryption / decryption of data based on the generated secret master key. It can not extract data stored therein by any method, It is a device that can guarantee the security of confidential information by securing a safety device such as extinction of data by itself and by receiving the certification of the accredited institution.

FIG. 1 shows a schematic configuration of a gateway which causes a bottleneck of the hardware cipher module (HSM) according to the prior art.

1, the gateway 100a according to the related art includes a hardware security module (HSM) 110, a central processing unit (CPU) 120, an Ethernet 0 131, and an Ethernet 1 132).

In this case, data is transmitted / received between the central processing unit (CPU) 120 and the hardware cipher module (HSM) 110 through the first interface P1, which is one physical communication port, While the hardware encryption module (HSM) 110 processes the encryption / decryption request data transmitted from the first communication terminal 10a and the second encryption / decryption request data transmitted from the second communication terminal 10b, The bottleneck phenomenon occurs.

As described above, the prior art has a problem that the communication speed of the system is lowered as a whole due to the bottleneck phenomenon of the hardware cipher module (HSM) 110 that processes the cryptographic operation of two or more pieces of communication data.

Korean Patent Publication No. 10-2016-0008560

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data communication method and a data communication method using a MCP (Many Core Processor) in the inside, data encryption and decryption of a first communication terminal instructed through a first interface, A hardware cipher module for deciding a cipher algorithm to be placed in each core of the square core block in the MCP in consideration of the correlation between the encryption algorithms, the communication port used, and the data moving speed between the cores, (HSM), which not only eliminates the bottleneck even when performing communication through a plurality of communication terminals, but also minimizes the internal processing time delay due to the optimal arrangement of the protection function algorithm in each core, And to provide a security gateway that implements cryptographic computation parallel processing.

According to an aspect of the present invention, there is provided a security gateway for implementing parallel communication processing of multiple communication cryptographic operations, the security gateway including: a first communication port for enabling communication using a first communication protocol from an external first communication terminal; A second communication port for allowing communication from an external second communication terminal to be implemented using the second communication protocol; (MCP), and instructs the hardware encryption module (HSM) to process the encryption / decryption request data transmitted from the first communication terminal through a first interface, A central processing unit (CPU) for instructing the hardware cryptographic module (HSM) to process the encryption / decryption request data via a second interface; And a plurality of MCPs (Many Core Processors) are used in the first interface, and the data encryption / decryption of the first communication terminal and the data encryption / decryption of the second communication terminal, which are commanded via the second interface, And a hardware cipher module (HSM) that performs independently and simultaneously.

The present invention not only eliminates bottlenecks when performing communication through a plurality of communication terminals, but also has a technical effect of minimizing internal processing time delays due to optimal placement of a protection function algorithm in each core.

FIG. 1 shows a schematic configuration of a gateway which causes a bottleneck of the hardware cipher module (HSM) according to the prior art.
FIG. 2 shows a schematic configuration of a security gateway for implementing parallel communication cryptographic operation parallel processing using the MCP HSM according to the present invention.
FIG. 3A shows a detailed structure of an HSM having a square core block diagram of MCP 6 × 6 according to an exemplary embodiment of the present invention.
FIG. 3B is a diagram illustrating a clock for a 6 × 6 square core block, which is used for moving data from coordinates (0, 0) to coordinates (1, 1) or coordinates (5, 5) Lt; / RTI >
FIG. 4 is a diagram illustrating the relationship between cipher algorithms, the communication port used, and the speed of data movement between cores in the HSM having a square core block diagram of MCP 6 × 6 according to an embodiment of the present invention. In order to explain how to do this.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a schematic configuration of a security gateway for implementing parallel communication cryptographic operation parallel processing using the MCP HSM according to the present invention.

Referring to FIG. 2, the multiple communication cryptographic parallel processing system 200 according to the present invention includes a security gateway 200a, a first communication terminal 10a, and a second communication terminal 10b.

The security gateway 200a includes a hardware security module (HSM) 210, A central processing unit (CPU) 220, an Ethernet 0 (231), and an Ethernet 1 (232).

Here, the HSM 210 configures two or more communication ports such as USB, PCI, SPI, UART, and Ethernet by using a MCP (Many Core Processor) to process cipher operations for two or more simultaneous communications For example, two USBs, two SPIs, two UARTs, three PCIe, and four Ethernets are simultaneously supported), a structure thereof, and a method of implementing a protection function algorithm through optimal placement for each core are shown in FIGS. 3A and 4 Respectively.

The CPU 220 is a central processing unit. The processor supports cores such as 8, 16, 32, 36, 64 and 100 as MCPs (Many Core Processors) The HSM 210 can process the encryption decryption request data transmitted from the first communication terminal 10a and the encryption decryption request data transmitted from the second communication terminal 10b through the second interface P2, To be processed by the HSM 210.

That is, the present invention supports cryptographic operation processing through two simultaneous communication ports or multiple (three or more) simultaneous communication ports like the first interface (P1) and the second interface (P2) It is possible to solve the bottleneck phenomenon that occurs when the communication ports are used.

 The Ethernet 0 231 allows data to be transmitted and received between the first external communication terminal 10a and the CPU 220 via the first communication line Pa and the Ethernet 1 232 communicates with the external second communication terminal 10b And the CPU 220 through the second communication line Pb.

Here, the first communication terminal 10a and the second communication terminal 10b may be a communication device capable of performing wired or wireless communication with the security gateway 200a, such as a PC, a notebook, a PDA, a smart phone, .

FIG. 3A shows a detailed structure of an HSM having a square core block diagram of MCP 6 × 6 according to an exemplary embodiment of the present invention.

3A, the HSM 210 of the present invention has a square core block 211 of MCP 6 × 6, and is adjacent to the core block 211 and is connected to the upper communication port 212, A lower PCI port unit 214, a left memory unit 215, and a right memory unit 216. The lower memory port unit 214, the lower PCI port unit 214, the left memory unit 215,

Herein, each of the cores (0, 0) to (5, 5) constituting the core block 211 are connected through a physical communication bus so as to be able to process independent processes individually And each core has a structure capable of transmitting data to the other cores, thereby providing a parallel processing environment in cryptographic operation processing.

In this case, each core in the MCP is composed of a core of 64-bit processing and can be programmed to operate by implementing eight protection function algorithms in one core. However, since there are many available cores, It is desirable to program one core to increase the processing speed or minimize the delay.

The upper cores ((0,0), (1,0), (2,0), (3,0), (4,0), (5,0)) constitute the upper communication port unit 212 In this case, data is transferred from the upper cores to the external communication port for one clock period. However, as the clock goes to the lower core, clock) (see FIG. 3B).

The lower cores ((0,5), (1,5), (2,5), (3,5), (4,5), (5,5) (X4) or a lower PCI port (214). In this case, data is transmitted from the lower cores to the lower communication port for one clock period. (See FIG. 3B), which takes one more clock to the core.

The left cores ((0,0), (0,1), (0,2), (0,3), (0,4), (0,5) The right cores ((5,0), (5,1), (5,2), (5,3), (5,4), Directly connected.

FIG. 3B is a diagram illustrating a clock for a 6 × 6 square core block, which is used for moving data from coordinates (0, 0) to coordinates (1, 1) or coordinates (5, 5) Lt; / RTI >

Referring to FIG. 3B, clocks required for data movement from the coordinates (0, 0) to the coordinates (1, 1) in the 6 × 6 square core block are shifted one time If a clock is used and a total of two cells are moved, a total of two clocks are required.

Next, in the 6 × 6 square core block, the clock required for moving data from the coordinates (0, 0) to the coordinates (5, 5) is one clock ), And a total of 10 clocks are required.

Similarly, in the 6x6 square core block, the total clock required for data movement from arbitrary core coordinates to other core coordinates can be calculated.

FIG. 4 is a diagram illustrating the relationship between cipher algorithms, the communication port used, and the speed of data movement between cores in the HSM having a square core block diagram of MCP 6 × 6 according to an embodiment of the present invention. In order to explain how to do this.

First, the MCP HSM cipher algorithm of the security gateway 200a will be briefly described below (the minimum required eight cipher algorithms of the National Intelligence Service).

[National Information Service Regulations Minimum 8 Required Cryptographic Algorithms]

① ARIA encryption algorithm (ECB / CBC / CTR / CCM / GCM): key length 128bit, block length 128bit

      ② LEA encryption algorithm (ECB / CBC / CTR / CCM / GCM): key length 128 bits, block length

128 bit

      ③ Message authentication code: HMAC - SHA256

      ④ Hash function: SHA-256

      ⑤ Random number generator: CTR_DRBC - Block cipher (ARIA-128)

      ⑥ Digital signature ECDSA: Curve FIPS P-256, hash SHA-256

      ⑦ Digital signature EC-KCDSA: Curve FIPS P-256, hash SHA-256

⑧ Key setting method ECDH: Curve FIPS P-256

Here, the random number of the random number generator is used when a secret key is generated in the encryption algorithm, and encryption or decryption of data is performed using the generated secret key.

A hash function is a function that generates a hash value when generating an electronic signature and a message authentication code, and is characterized in that long data is generated so as not to be duplicated as a random value of a certain length.

Referring to FIG. 4, the present invention has a total of 6 × 6 square core blocks in the MCP. In this case, the A communication area cipher module C_A further includes 3 × 3 square core blocks ((0,0) to 2, 2), communication is performed using the IEC 61850 communication protocol via the upper USB0 communication port, and the B communication area cipher module C_B again transmits 3 × 3 square core blocks (3, 0) to , 2)), communication is performed using the DNP 3.0 communication protocol through the upper USB1 communication port, and the C communication area cipher module (C_C) again transmits the 3 × 3 square core blocks (0, 5)), communication is performed using the IEC 61850 communication protocol through the lower Ethernet0 communication port, and the D communication area encryption module (C_D) again transmits the 3 × 3 square core blocks (3,3 to 5,5 )), Communication is performed using the IEC 61850 communication protocol through the lower Ethernet1 communication port.

Hereinafter, a method for determining the position of the above-mentioned "minimum required eight encryption algorithm of the National Information Society Regulation" according to the correlation between the encryption algorithms, the communication port used, and the data moving speed between the cores in the HSM having a total of 6 × 6 square core blocks in the MCP .

First, it is preferable that the ARIA encryption algorithm and the LEA encryption algorithm are arranged in the closest core to the upper or lower communication port in consideration of the most frequently used communication data encryption / decryption.

For example, in the case of the A communication area cipher module C_A, the ARIA encryption algorithm is arranged in the core (1,0) closest to the upper USB0 communication port and the LEA encryption algorithm is arranged in the core (2,0).

Similarly, in the case of the B communication area cipher module C_B, the ARIA encryption algorithm is arranged in the core (4,0) closest to the upper USB1 communication port and the LEA encryption algorithm is arranged in the core (5,0) In the case of the cryptographic module C_C, the ARIA encryption algorithm and the LEA encryption algorithm are arranged in the cores 1 and 5 respectively nearest to the lower Ethernet0 communication port and the core 2 and 5, respectively, and the D communication area cipher module C_D, , The ARIA encryption algorithm is arranged in the core (4, 5) closest to the lower Ethernet 1 communication port, and the LEA encryption algorithm is arranged in the core (5, 5).

In this case, if the non-USB Ethernet and PCIe communication ports are used for the A communication area encryption module (C_A) or the B communication area encryption module (C_B), the number of added encryption algorithms can be further increased.

Next, the random number generator generates a random number to generate a random number, thereby providing a random number to the ARIA encryption algorithm, the LEA encryption algorithm, the digital signature ECDSA, the digital signature EC-KCDSA, and the key establishment ECDH function, It is desirable to provide a random number in each of them quickly.

For example, in the case of the A communication area cipher module (C_A), (5) the random number generator is disposed in the center core (1, 1) in consideration of the above situation.

Likewise, in the case of the B communication area cipher module C_B, the random number generator is arranged in the central core 4,1 in consideration of the above situation, and in the case of the C communication area cryptographic module C_C, Considering the above situation, in the case of the D communication area cipher module (C_D), (5) the random number generator is arranged in the center positioned in the core (4, 4) .

Next, it is desirable that the hash function is placed in close proximity to the electronic signature ECDSA and the electronic signature EC-KCDSA, taking into account the fact that the hash function is often used for digital signatures.

For example, in the case of the A communication domain cryptographic module (C_A), the hash function (4) takes into account the above situation, (6) the core (0,1) in which the electronic signature ECDSA is disposed, and (0, 2), which is a position close to the core (0, 0).

Similarly, in the case of the B communication domain cipher module C_B, the hash function ④ takes the above situation into account, ⑥ the core (3,1) in which the electronic signature ECDSA is placed, and ⑦ the core Can be disposed in the core (3, 2), which is a position close to the core (5,1).

Similarly, in the case of the C communication domain cryptographic module (C_C), the hash function (4) takes the above situation into account, (6) the core (0,4) in which the digital signature ECDSA is disposed, and (0, 3), which is a position close to the core (0, 5).

Similarly, in the case of the D communication area cryptographic module (C_D), (4) the hash function takes into account the above situation, (6) the core (3,4) in which the digital signature ECDSA is disposed, and (3, 3), which are in close proximity to the cores (3, 5).

Next, (3) When the IEC 61850 communication protocol is used, the message authentication code is placed at a position requiring one clock more than the ARIA encryption algorithm and the (2) LEA encryption algorithm, .

For example, in the case of the A communication area cipher module (C_A), (3) because the message authentication code uses the IEC 61850 communication protocol, it is less frequently used than other encryption algorithms. ) And (2) the core (2,1) where a clock is required for USB0 based on the core (2,0) where the LEA encryption algorithm is located.

Similarly, in the case of the C communication domain cryptographic module (C_C), considering the fact that the message authentication code uses the IEC 61850 communication protocol, the frequency of use is smaller than that of other cryptographic algorithms. ) And (2) the core (2, 4) where one clock is required for Ethernet0 based on the core (2, 5) where the LEA encryption algorithm is located.

Similarly, in the case of the D communication area cipher module (C_D), considering the fact that the message authentication code uses the IEC 61850 communication protocol, it is less frequently used than other encryption algorithms. ) And (2) the core 5, 5 at which a clock is required for the Ethernet 1 as compared to the core 5, 5 where the LEA encryption algorithm is located.

On the other hand, when the DNP 3.0 communication protocol is used, it is preferable to place the message authentication code in the upper core close to the upper USB1 port, considering that the encryption algorithm is used more frequently than other encryption algorithms. KCDSA is used for key exchange when communicating, and can be placed far away from the upper USB1 port due to its low frequency.

For example, in the case of the B communication area cipher module C_B, since the DNP 3.0 communication protocol is used, it can be allocated to the core 3, which is close to the upper USB1 port, In this case, ⑦ electronic signature EC-KCDSA is used for key exchange when communication is connected, it can be placed in core (5,1) located far away from upper USB1 port because frequency is low.

Thus, in the HSM having a total 6x6 core block diagram in the MCP, the above-mentioned [minimum required eight encryption algorithms of the National Intelligence Service] in consideration of the correlation among the encryption algorithms, the communication port used, , And 4 A communication area cryptographic modules (C_A) to D communication area cryptographic modules (C_D) each having a 3 × 3 square core block, thereby minimizing the delay time in the internal processing of the encryption algorithm .

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention.

200a: Security gateway
210: Hardware Cipher Module (HSM)
220: central processing unit (CPU)
231: Ethernet 0
232: Ethernet 1
10a: first communication terminal
10b: second communication terminal
Pa: first communication line
Pb: second communication line
P1: First interface
P2: Second interface

Claims (9)

A first communication port that enables communication using a first communication protocol from an external first communication terminal;
A second communication port for allowing communication from an external second communication terminal to be implemented using the second communication protocol;
(MCP), and instructs the hardware encryption module (HSM) to process the encryption / decryption request data transmitted from the first communication terminal through a first interface, A central processing unit (CPU) for instructing the hardware cryptographic module (HSM) to process the encryption / decryption request data via a second interface; And
Wherein the MCP (Many Core Processor) is used in the first interface and the data encryption and decryption of the first communication terminal instructed through the first interface and the data encryption and decryption of the second communication terminal instructed through the second interface are independent And a hardware cipher module (HSM) for simultaneously performing the cipher processing and the cipher processing. The system according to claim 1, wherein the hardware cipher module (HSM)
A cryptographic algorithm disposed in each core of the square core block in the MCP is determined in consideration of the correlation between the encryption algorithms, the communication port used, and the data movement speed between the cores. Gateway. 3. The MCP of claim 2,
N = N (N = 4, 6, 8) square core blocks,
And a high communication port unit, a low communication port unit, a left memory unit, and a right memory unit in four directions adjacent to the core block. 3. The method according to claim 2,
(8) minimum cryptographic algorithms of the National Intelligence Service. ≪ / RTI > 5. The method according to claim 4, wherein the above-mentioned "
(3) a message authentication code, (4) a hash function, (5) a random number generator, (6) an electronic signature ECDSA, (7) an electronic signature EC-KCDSA, and A security gateway that implements parallel communication. 6. The method of claim 5,
The (1) ARIA encryption algorithm and (2) LEA encryption algorithm,
Wherein the security gateway is disposed in a core closest to the upper communication port or the lower communication port in consideration of the most frequently used encryption / decryption. 6. The random number generator according to claim 5,
Considering that the random numbers are generated to provide the random numbers to the ARIA encryption algorithm, the LEA encryption algorithm, the digital signature ECDSA, the digital signature EC-KCDSA, and the key establishment ECDH function, Wherein the secure gateway is located in a central core that is at a location that is at least partially occupied by the security gateway. 6. The method of claim 5, wherein the hash function (4)
The electronic signature ECDSA and the digital signature EC-KCDSA are placed in a position close to the digital signature ECDSA and the digital signature EC-KCDSA. 6. The method of claim 5,
Considering that the frequency of use is less than that of other encryption algorithms when the IEC 61850 communication protocol is used, one clock is required for the higher communication port or lower communication port than the above-mentioned (1) ARIA encryption algorithm and (2) Wherein the secure gateway is located at a location where the cryptographic computation is performed.

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