KR20180023919A - Magnetroresistive random access memory and method of inspecting defect of memory cells in the same - Google Patents

Abstract

A magnetic random access memory for reading a plurality of memory cells and inspecting a defect, and a memory cell defect inspection method therefor. The magnetic random access memory includes a memory cell part including a plurality of memory cells, a reference cell part including at least one reference cell, and a detection circuit. Here, when inspecting a memory cell defect, a plurality of memory cells are selected along a plurality of word lines selected at the same time. In addition, the detection circuit detects the resistances of the selected memory cells, detects the resistance of the reference cell, and compares the detected resistances to determine whether the memory cell is defective.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoresistive memory device and a method of inspecting a memory cell,

The present invention relates to a magneto-resistive memory device for simultaneously reading a plurality of memory cells and inspecting defects of the memory cells, and a method for inspecting memory cell defects therein.

Random Access Memory (RAM) may be volatile or non-volatile. Volatile RAM loses information stored in volatile RAM each time power is removed, while non-volatile RAM can retain memory contents in non-volatile RAM even when power is removed from memory.

However, a non-volatile RAM has a read / write time that is slower than a volatile RAM, although non-volatile RAM has the advantage of being able to retain information without powering it.

Magnetoresistive random access memory (MRAM) is a non-volatile memory having read / write times comparable to volatile memory. Unlike conventional RAM technology, which stores data such as electrical charges or currents, the MRAM uses magnetic currents.

In such a magnetoresistive random access memory, the defective inspection of the memory cells sequentially reads each memory cell to check for defects. However, this method has a problem that the inspection time increases sharply as the memory is highly integrated.

KR 10-2013-0114317 A

SUMMARY OF THE INVENTION The present invention provides a magnetoresistive memory device for reading a plurality of memory cells and inspecting defects, and a method for inspecting a memory cell defect therein.

According to an aspect of the present invention, there is provided a magnetoresistive memory device including: a memory cell portion including a plurality of memory cells; A reference cell portion including at least one reference cell; And a sensing circuit. Here, when inspecting a memory cell defect, a plurality of memory cells are selected along a plurality of word lines selected at the same time. The sensing circuit senses the resistance of the selected memory cells, senses the resistance of the reference cell, and compares the sensed resistors to determine whether the memory cell is defective.

According to another aspect of the present invention, there is provided a magnetoresistive memory device including: a memory cell portion including a plurality of memory cells; A reference cell portion including at least one reference cell and an auxiliary reference cell; And a sensing circuit. Here, when inspecting a memory cell defect, a plurality of memory cells are selected along a plurality of word lines selected at the same time. The sensing circuit senses the resistance of the selected memory cells, senses the resistance of the reference cell and the auxiliary reference cell, and compares the sensed resistors to determine whether the memory cell is defective.

A method for inspecting a memory cell defect in a magnetoresistive memory device according to an embodiment of the present invention includes: simultaneously activating a plurality of word lines; Sensing a resistance of memory cells connected to the activated word lines; Comparing the resistance of the sensed memory cells with the resistance of a reference cell; And determining whether the memory cells are defective according to the comparison result.

A method for inspecting a memory cell defect in a magnetoresistive memory device according to another embodiment of the present invention includes: simultaneously activating a plurality of word lines; Sensing a resistance of memory cells connected to the activated word lines; Comparing the resistance of the sensed memory cells with the resistance of the reference cell and the auxiliary reference cell; And determining whether the memory cells are defective according to the comparison result. Here, the auxiliary reference cell records data of the opposite logic to the data written in the memory cells.

The magnetoresistive memory device according to the present invention reads a plurality of memory cells at the same time by inspecting defects, so that the inspection time can be considerably reduced.

1 is a diagram illustrating a structure of an STT-MRAM according to an embodiment of the present invention.
2 is a diagram showing a structure of a memory cell.
3 is a diagram illustrating a structure of an STT-MRAM according to another embodiment of the present invention.
4 is a diagram showing the detection margin.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising "and the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps. Also, the terms "part," " module, "and the like described in the specification mean units for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software .

The present invention relates to a magnetoresistive memory device, for example, a spin transfer torque magnetic random access memory (STT-MRAM) and a memory cell defect inspection method therefor, Lead can be inspected. As a result, inspection time can be considerably reduced.

According to one embodiment, the defect inspection method of the memory cell may simultaneously test a plurality of memory cells while considering a sensing margin. That is, the memory cell defect inspection method can shorten the inspection time while considering the detection margin.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 illustrates a structure of an STT-MRAM according to an embodiment of the present invention, and FIG. 2 illustrates a structure of a memory cell. Referring to FIG.

1, a magneto-resistive memory device, for example, STT-MRAM of the present embodiment includes a memory cell portion 100, a reference cell portion 102, a word line driver 104, a write driver 106, a control logic 108 And a sensing circuit 110. [0034]

The memory cell unit 100 includes a plurality of memory cells 120. Each memory cell 120 may include one MTJ (Magnetic Tunnel Junction) element and one transistor T as shown in FIG.

One end of the MTJ may be connected to the bit line BL and the other end may be connected to the transistor T. The gate of the transistor T may be connected to the word line WL and the other end may be connected to the source line SL.

The MTJ may include a sequentially arranged fixed layer, a tunnel barrier layer, and a free layer. The pinned layer has a constant magnetization direction, and the free layer may have a different magnetization direction depending on the direction of a current flowing to the MTJ element. The tunnel barrier layer is arranged between the fixed layer and the free layer and may be an insulating layer.

The reference cell portion 102 includes reference cells 122. The structure of the reference cell 122 is the same as that of the memory cell 120.

The word line driver 104 applies a word line driving signal to the memory cells 120 and the reference cell 122 through the word lines WL and is connected to the memory cells 120 or the reference cell 122 Word lines WL can be selected and driven. For example, the word line driver 104 may be a decoder.

Write driver 106 selects memory cell 120 or reference cell 122 through bit line BL.

Specifically, the write driver 106 may serve to drive the bit lines BL and the source lines SL, and may be, for example, a buffer.

According to one embodiment, the write driver 106 may include a column decoder for selecting a bit line and a source line voltage generator for generating a voltage on the source line SL. For example, the column decoder decodes the input column address to generate a decoded column address, and as a result the bit line BL can be selected.

In addition, the write driver 106 may control a voltage applied to the bit line BL and the source line SL for a write operation to determine the direction of a current flowing to the array of the memory cell unit 100. For example, the write driver 106 may write bit lines BL and source lines SL such that the magnetization directions of the pinned layer and the free layer of the MTJ element are the same for writing "0" data to the corresponding memory cell 120. [ Is applied to the bit line BL and the source line SL so that the magnetization direction of the fixed layer and the free layer of the MTJ element are different from each other in order to write the "1" data to the memory cell 120 The voltage can be determined.

That is, when writing "0" data, the write driver 106 sets the bit line (the bit line) so that the direction of the current flowing into the array of the memory cell unit 100 and the direction of the current flowing into the array when writing "1" BL and the source line SL can be determined.

The control logic 108 controls the operation of the word line driver 104 and the write driver 106.

The sense circuit 110 compares the resistance of the selected memory cell with the resistance of the reference cell, and determines whether the selected memory cell is defective according to the comparison result.

According to one embodiment, the word line driver 104 simultaneously selects, i.e. activates, a plurality of word lines WL unlike the prior art. For example, the word line driver 104 may simultaneously select four word lines WL. For example, the word line driver 104 may simultaneously select the first to third word lines WL0 to WL3, and then simultaneously select the fourth to sixth word lines WL3 to WL5 , And this process can be repeatedly performed to the last word line.

Since four word lines are simultaneously selected and one bit line is selected, the resistance of the four memory cells can be sensed through sense circuitry 110. [ That is, the defect inspection can proceed in units of four memory cells. Of course, the resistance of the reference cells of the reference cell part 102 is also detected when the memory cell defect inspection is performed, and the detected resistances are compared.

Hereinafter, a process of inspecting a memory cell defect in the STT-MRAM having such a structure will be described.

According to one embodiment, '1' may be written to all the memory cells 120, '1' may be written to some of the reference cells (left reference cells 122a in FIG. 1) '0' may be recorded in the reference cell (right reference cells 122b in FIG. 1). That is, the resistance of the reference cell may be an average value of a resistance corresponding to '1' and a resistance corresponding to '0'.

The sense circuit 110 then senses the resistance of the selected four memory cells in response to activation of the four word lines WL, senses the resistance of the reference cells 122, and compares the sensed resistors.

Then, the control unit connected to the sensing circuit 110 determines whether the four memory cells are defective based on the comparison result.

According to another embodiment, '0' may be written in all the memory cells 120, '1' is recorded in some reference cells (left reference cells 122a in FIG. 1) of the reference cells 122, '0' may be recorded in the reference cell (right reference cells 122b in FIG. 1). That is, the resistance of the reference cell may be an average value of a resistance corresponding to '1' and a resistance corresponding to '0'.

The sense circuit 110 then senses the resistance of the selected four memory cells in response to activation of the four word lines WL, senses the resistance of the reference cells 122, and compares the sensed resistors.

Then, the control unit connected to the sensing circuit 110 determines whether the four memory cells are defective based on the comparison result.

To summarize, the STT-MRAM of this embodiment checks whether or not it is defective in units of N (two or more integer) memory cells. Therefore, the time for inspecting the memory cell defect can be considerably shortened.

For example, when defects are detected in two specific memory cells when defective cells are checked in units of two memory cells, the defective memory cells are connected to redundant cells of a spare cell array ). ≪ / RTI >

In the conventional STT-MRAM, one defective memory cell is replaced with one redundant cell. However, in the STT-MRAM of the present embodiment, a plurality of defective memory cells can be replaced with a plurality of redundant cells at once.

FIG. 3 is a diagram illustrating a structure of an STT-MRAM according to another embodiment of the present invention, and FIG. 4 is a diagram illustrating a sensing margin.

3, the STT-MRAM of the present embodiment includes a memory cell portion 300, a reference cell portion 302, a word line driver 304, a write driver 306, a control logic 308, and a sense circuit 310 .

The remaining components except for the reference cell portion 302 are the same as those of FIG. 1, so that the description of the same components will be omitted.

The reference cell portion 302 further includes at least one auxiliary reference cell 324 in addition to the reference cells 322.

The resistance corresponding to '0', the resistance corresponding to the reference cell, and the resistance corresponding to '1' must be sufficiently separated from each other as shown in FIG. 4 (A) The resistance may overlap as shown in FIG. As a result, the detection margin can be reduced.

Therefore, the STT-MRAM of the present embodiment additionally uses the auxiliary reference cell 324 in order to secure a sufficient sensing margin, thereby improving the accuracy of the memory cell defect inspection. That is, the STT-MRAM uses the auxiliary reference cell 324 as a resistance adjustment cell.

Hereinafter, a process of inspecting a memory cell defect in the STT-MRAM having such a structure will be described.

According to one embodiment, '1' may be recorded in all the memory cells 320, '1' may be written in some of the reference cells (left reference cells 322a in FIG. 3) '0' may be written in the reference cell (right reference cells in FIG. 3, 322b), and '0' may be written in the auxiliary reference cell 324.

The sense circuit 310 then senses the resistance of the four selected memory cells in response to activation of the four word lines WL and senses the resistance of the reference cells 322 and the auxiliary reference cells 324, Compare the sensed resistors.

Then, the control unit connected to the sense circuit 310 determines whether the four memory cells are defective based on the comparison result.

According to another embodiment, '0' may be written to all the memory cells 320, '1' is written to some reference cells (left reference cells 322a in FIG. 3) of the reference cells 322, '1' may be recorded in the reference cell (right reference cells in FIG. 3, 322b), and '0' may be recorded in the auxiliary reference cell 324.

The sense circuit 310 then senses the resistance of the four selected memory cells in response to activation of the four word lines WL and senses the resistance of the reference cells 322 and the auxiliary reference cells 324, Compare the sensed resistors.

Then, the control unit connected to the sense circuit 310 determines whether the four memory cells are defective based on the comparison result.

In summary, the STT-MRAM of this embodiment inspects whether or not the memory cell is defective in units of N (two or more integer) memory cells, and further performs the memory cell defect inspection using the auxiliary reference cell 324. Therefore, it is possible to sufficiently shorten the inspection time while sufficiently securing the detection margin in the memory cell defect inspection.

According to one embodiment, the logic of the data written to the auxiliary reference cell 324 may be opposite to the logic of the data written to the memory cell. If the opposite logic is used, the area of the overlapped portions of the resistors in Fig. 4A may be reduced or eliminated. That is, a sufficient sensing margin can be secured.

However, the logic of the data written to the auxiliary reference cell 324 is not limited to the logic of the data written to the memory cell.

On the other hand, the components of the above-described embodiment can be easily grasped from a process viewpoint. That is, each component can be identified as a respective process. Further, the process of the above-described embodiment can be easily grasped from the viewpoint of the components of the apparatus.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

100: memory cell part 102: reference cell part
104: Word line driver 106: Write driver
108: control logic 110: sense circuit
120: memory cell 122: reference cell
300: memory cell part 302: reference cell part
304: Word line driver 306: Write driver
308: control logic 310: sense circuit
320: memory cell 322: reference cell
324: auxiliary reference cell

Claims (2)

A memory cell portion including a plurality of memory cells;
A reference cell portion including at least one reference cell; And
Sensing circuit,
In the memory cell defect inspection, a plurality of memory cells are selected along a plurality of word lines selected at the same time,
The sensing circuit senses a resistance of the selected memory cells, senses a resistance of the reference cell, compares the sensed resistors to determine whether the memory cell is defective, and determines N (two or more integers) The memory cell defect inspection is performed on the memory cell. Simultaneously activating a plurality of word lines;
Sensing a resistance of memory cells connected to the activated word lines;
Comparing the resistance of the sensed memory cells with the resistance of a reference cell; And
And determining whether the memory cells are defective according to the result of the comparison.

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