KR20180016680A - Storage device, test system for testing the same, and method thereof - Google Patents

Abstract

According to the present invention, a method of a test system includes: a step of issuing a command in a test program; a step of generating a plurality of commands corresponding to the command in a device driver; and a step of simultaneously transmitting the commands to a multi-port of each storage device. The storage device of the present invention can improve a data transfer rate by efficiently performing Write and Read operations using a plurality of ports and test efficiency by reducing test time when a quantitative test is performed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a storage device,

The present invention relates to a storage device and a test system and method for testing it.

Recent storage devices are being developed in the form of multi-ports in order to increase the efficiency of use. The conventional test apparatus performs testing in such a manner that the port is sequentially operated at a speed lower than the maximum transmission speed by not using the multi port of the storage device at the same time. In addition, conventional test equipment can not access multiple ports in hardware / software.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned technical problems, and it is an object of the present invention to provide a multiport storage device for increasing test efficiency and a test system and method for testing the multiport storage device.

A method of a test system including a host apparatus according to an embodiment of the present invention and storage devices connected to the host apparatus via a multiport includes issuing a command in a test program, Generating the commands, and simultaneously transmitting the plurality of commands to the multi-port of each of the storage devices.

A storage device according to an embodiment of the present invention includes a first port implemented according to a communication protocol, a second port implemented according to the communication protocol, a first at least one non-volatile memory device, a second at least one non- A first memory controller coupled to the first port and controlling the first at least one non-volatile memory device, and a second memory controller coupled to the second port and configured to control the second at least one non-volatile memory device Wherein the first port and the second port are activated during a test operation, each of the first and second memory controllers receives commands via a corresponding port, and the received commands The corresponding non-volatile memory device may be tested.

A test system according to an embodiment of the present invention includes a host device and a plurality of dots connected to the host device through a dual port, the host device including a central processing unit, And a second command can be simultaneously transmitted to a second port of the dual port while a first command is transmitted to a first port of the dual port in a test operation.

A method of testing a storage device according to an embodiment of the present invention includes receiving a first command through a first port, receiving a second command through a second port while receiving the first command, Testing the first memory in response to the command, and testing the first memory in response to the second command while testing the first memory.

A storage device according to an embodiment of the present invention and a test system for testing the same and a method thereof can improve data transmission speed by efficiently performing Write / Read using a plurality of ports and reduce test time during quantitative test The test efficiency can be improved.

1 is an exemplary illustration of a test system in accordance with an embodiment of the present invention.
Figures 2a and 2b are illustrative examples of connectors having dual ports.
3 is an exemplary illustration of a software layer of a test system according to an embodiment of the present invention.
4 is a diagram illustrating a method of generating a dual port command generated in a test program according to an embodiment of the present invention.
5 is a diagram illustrating a command structure generated in a test program according to an exemplary embodiment of the present invention.
FIG. 6 is a diagram illustrating a dual port command process according to an exemplary embodiment of the present invention. Referring to FIG.
7 is a block diagram illustrating an embodiment of a dual port SSD according to an embodiment of the present invention.
8 is a block diagram illustrating another embodiment of a dual port SSD according to an embodiment of the present invention.
9 is a diagram illustrating an exemplary method of generating a host command according to an embodiment of the present invention.
10 is a diagram illustrating a method of testing a dual port SSD according to an exemplary embodiment of the present invention.
11 is a diagram illustrating an exemplary test system according to another embodiment of the present invention.
FIG. 12 is an exemplary diagram illustrating a data server system to which a storage device according to an embodiment of the present invention is applied.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

The storage device according to the embodiment of the present invention supports the multi-port and performs the test operation through the multi-port, thereby reducing the test time and improving the test efficiency.

1 is an exemplary illustration of a test system 10 in accordance with an embodiment of the present invention. Referring to FIG. 1, a test system 10 may include a host device 100 and a plurality of dirts (DUTs) 210, 220, ..., 2N0, have.

The host device 100 may include a central processing unit (CPU) 110 and a host bus adapter (HBA) 120. For example, the host device 100 may be a computing device.

The central processing unit 110 can perform a test operation on the plurality of dots 210, 220, ..., 2N0 by controlling the hardware / software / firmware.

The host bus adapter 120 is connected to the central processing unit 110 and transmits test commands of the central processing unit 110 to the plurality of dutts 210, 220, ..., 2N0, (210, 220, ..., 2NO) to the central processing unit (110).

The host bus adapter 120 may be connected to the dual ports PT1 and PT2 at each of the plurality of dots 210, 220, ..., 2N0. In an embodiment, host bus adapter 120 may include a plurality of bus adapter units coupled to dual ports PT1 and PT2, respectively, of each of a plurality of dots 210, 220, ..., 2N0 . Where each of the bus adapter units may be implemented to process test operations for the same test command in parallel. On the other hand, in FIG. 1, one host bus adapter 120 is shown in the central processing unit 110, but the number of host bus adapters of the present invention is not limited thereto. It should be understood that a plurality of host bus adapters may be connected to the central processing unit 110. [

In an embodiment, the host device 100 sends a new test command to the dots 210, 220, ..., 2N0 before receiving a test result value corresponding to the test command from the dots 210, 220, ..., 2N0. ..., 2N0.

In an embodiment, the host device 100 may activate the dual port of the dots 210, 220, ..., 2N0 to perform a test operation.

In an embodiment, the host device 100 may transmit a test command to darts 210, 220, ..., 2N0 in a queuing manner through a dual port.

The plurality of dots 210, 220, ..., 2N0 are memory devices on which a test operation is performed. In an embodiment, each of the plurality of dots 210, 220, ..., 2N0 may include dual ports PT1, PT2. Here, each of the dual ports PT1 and PT2 may be implemented by the same communication protocol. The communication protocol may be a non-volatile memory express (NVMe), a peripheral component interconnect (PCIe), a serial at attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a universal storage bus attached SCSI, Internet Small Computer System Interface (iSCSI), Fiber Channel, Fiber Channel over Ethernet (FCoE), and the like.

In the embodiment, the dual ports PT1 and PT2 can be activated simultaneously in the test operation of the corresponding dirt. In other words, the first test operation for the dirt through the first port PT1 and the second test operation for the dirt through the second port PT2 can be performed independently.

In an embodiment, each of the plurality of dots 210, 220, ..., 2N0 may be a solid state drive (SSD). For example, the plurality of dots 210, 220, ..., 2N0 may be a serial attached SCSI (SAS) SSD.

In an embodiment, each of the plurality of dots 210, 220, ..., 2N0 may be a hard disk drive (HDD). For example, the plurality of dots 210, 220, ..., 2N0 may be a serial attached SCSI (SAS) HDD. It should be understood that each of the plurality of dots 210, 220, ..., 2N0 may be any kind of memory device configured as a dual port in addition to the SSD and the HDD.

The host device 100 is physically connected to all of the ports PT1 and PT2 of each of the dots 210, 220, ..., 2N0 and simultaneously performs access to the ports PT1 and PT2 .

On the other hand, each of the dots 210, 220, ..., 2N0 shown in FIG. 1 includes two ports PT1 and PT2. However, the dots of the present invention need not be limited thereto. It should be understood that the dirts of the present invention may include three or more ports (multiport).

The test system 10 according to the embodiment of the present invention performs the test operation on the corresponding dirt using all of the dual ports PT1 and PT2 to reduce the test time as compared with the conventional one, Performance can be expected to improve.

2A and 2B are illustrative examples of connectors 201a and 201b having a dual port. Referring to FIG. 2A, first single pins, power and control pins are disposed on a first side of the connector 201a, and first single pins are disposed on a second side opposite to the first side. Wherein the first single pins indicate a first port (Port A) and the second single pins indicate a second port (Port B).

Referring to FIG. 2B, power pins P1 to P15, PCIe sideband pins E1 to E6, and first ports S1 to S7 are disposed on a first side of the connector 201b, The PCIe lanes and the sideband pins E17 to E39, the second ports S8 to S14, and the PCIe lanes and the reference clock pins E7 to E16 may be disposed on the second side.

In an embodiment, each of connectors 201a, 201b may be implemented with an SSD Form Factor connector.

On the other hand, it should be understood that the pin arrangement of the connectors 201a and 201b shown in Figs. 2A and 2B is merely an embodiment that does not limit the present invention. The connector included in the storage device of the present invention can constitute a dual port in various forms.

Figure 3 is an exemplary illustration of a software layer of a test system 10 (Figure 1) in accordance with an embodiment of the present invention. 1 to 3, the software layer of the host device 100 for performing a test operation may include an application layer, a command layer, a transport layer, a link layer, and a physical layer. The software layer of a dirt (e.g., 210 in FIG. 1) where the test operation is performed may include an application layer, a command layer, a transport layer, a link layer, and a physical layer.

In an embodiment, the application layer of the host device 100 and the application layer of the dart 210 may be logically connected, and the transport layer of the host device 100 and the transport layer of the dart 210 may be logically connected , The link layer of the host device 100 and the link layer of the dart 210 can be logically connected.

In the embodiment, the host apparatus 100 may be implemented as a test program (software) corresponding to an application layer, and implemented as a kernel (or a "device driver") corresponding to the command layer.

Here, the test program may be stored in a memory (not shown) of the host apparatus 100. The test program may include a test sequence or test data for performing a test operation. For example, after the specific data is stored in the storage area of the dirt, the success / failure of the test operation may be determined depending on whether the read data is the same as the specific data. If a particular storage area in the dirt is determined to be bad, the test program may be implemented to transfer the specific storage area to the host device 100. [ The test program may also be implemented to replace a particular storage area with a redundancy area or to indicate that a particular storage area is bad.

In an embodiment, the test program may be implemented to generate a plurality of commands at the same time in order to improve the test efficiency of the dots supporting multi-port. Generally, to access the dirt, the program passes the command to the device driver (eg, the kernel).

In an embodiment, the physical layer of the host device 100 and the physical layer of the dart 210 may be physically connected. Here, the physical connection can utilize the dual ports PT1 and PT2. For example, the host device 100 may be implemented with hardware (e.g., PCIe ports) corresponding to the physical layer.

On the other hand, a command structure issued in a general application program may include an operation code for defining an operation, a control (feature) and a logical block address for accessing physical data, and a transmission length indicating a quantitative amount of data. The command structure generated in the test program of the present invention may further include information indicating use of a dual port and addresses added with dual port support.

4 is a diagram illustrating a method of generating a dual port command generated in a test program according to an embodiment of the present invention. 4, a command generated in a test program corresponding to an application layer includes an operation code (OP code), a first address ADDR1, a sector count corresponding to a transmission length, features, A meter (flag), and a second address ADDR2.

The commands generated in the test program can be separated and generated into two commands based on the command layer, i.e., the dual port delimiter (flag) in the device driver. In an embodiment, the first command generated in the device driver may include an operation code, a first address (ADDR1), a sector count, and features. Here, the first command may be transmitted to the first port PT1 out of the dual ports PT1 and PT2.

In an embodiment, the second command generated in the device driver may include an operation code, a second address (ADDR2), a sector count, and a feature. Here, the second command may be transmitted to the second port PT2 out of the dual ports PT1 and PT2.

Meanwhile, it should be understood that the method of generating the command shown in FIG. 4 is merely an embodiment that does not limit the present invention. The host device 100 of the present invention can generate a command corresponding to a dual port in various ways.

5 is a diagram illustrating a command structure generated in a test program according to an exemplary embodiment of the present invention. 5, the structure of the read command generated in the test program includes a 1-byte operation code, a 7-byte first address ADDR1, a group number corresponding to the transmission length, a 1-byte dual port delimiter (dual a flag indicating a port delimiter, and a second address ADDR2 of 7 bytes.

On the other hand, it should be understood that the structure of the read command shown in FIG. 5 is merely an embodiment that does not limit the present invention. For example, the size of the addresses ADDR1 and ADDR2 will not be limited to 7 bytes.

The command structure generated in the test program according to the embodiment of the present invention can be configured by concatenating a flag with an additional address in a general command in comparison with a general command structure. This configuration allows a substantial number of commands to be transmitted during the time of transmitting one command to the device driver in the test program. As a result, the test program of the present invention can minimize the overhead of command generation according to the dual port operation as compared with the general test program.

In an embodiment, the read function of the Dual Port SAS can be expressed as read (rdbuf1, rdbuf2, LBA1, LBA2, Test_SC). Here, rebuf1 and rdbuf2 can indicate the read data buffer output from each port, LBA1 indicates the first logical block address, LBA2 indicates the additional logical block address, and Test_SC indicates the sector count.

In an embodiment, in an embodiment, the write function of the Dual Port SAS may be expressed as write (wdbuf, LBA1, LBA2, Test_SC). Here, wdbuf may indicate a write buffer, LBA1 may indicate a first logical block address, LBA2 may indicate an additional logical block address, and Test_SC may indicate a sector count.

In an embodiment, the read function of the Dual Port NVMe may be expressed as readnvme (rdbuf1, rdbuf2, LBA1, LBA2, SC). Where rdbuf1 is the read buffer, rdbuf2 is the dual port enabled read buffer, LBA1 is the logical block address, LBA2 is the dual port enabled logical block address, and SC is the sector count.

In an embodiment, the write function of Dual Port NVMe may be expressed as writenvme (wdbuf, LBA1, LBA2, SC). Where wdbuf is the write buffer, LBA1 is the bits of the logical block address, LBA2 is the bits of the dual port enabled logical block address, and SC is the sector count.

On the other hand, the device driver determines whether to support the dual port operation according to the flag value of the command, and can change the command transmitted from the upper layer to the commands suitable for the dual port support when the dual port operation can be supported.

FIG. 6 is a diagram illustrating a dual port command process according to an exemplary embodiment of the present invention. Referring to FIG. 6, the CPU issues a dual port command, the first commands are sequentially transmitted to the SSD through the first port PT1, and the second commands are sequentially transmitted to the SSD through the first port PT2, Lt; / RTI > The SSD may simultaneously process the first and second commands received via the first and second ports PT1 and PT2.

In an embodiment, the first and second commands between the CPU and the SSD may be transmitted and received according to a queuing scheme.

7 is a block diagram illustrating an embodiment of a dual port SSD according to an embodiment of the present invention. 7, the dual port SSD 300 includes a first memory controller MC1 311 coupled to a first port PT1, at least one nonvolatile memory device NVM (not shown) coupled to a first memory controller 311, (NVM (s), 322 coupled to a second memory controller 312, a second memory controller (MC2, 312) coupled to a second port PT2, and at least one nonvolatile memory device can do.

The memory controller 311/312 may be coupled to the non-volatile memory device 321/322 via a plurality of channels. The memory controller 312/312 may be implemented to perform an error correction code (ECC) function, wear leveling, bad block management, signal processing, and the like. The memory controller 312/312 may include at least one processor, a buffer memory, a buffer memory controller, an error correction circuit, a host interface, a non-volatile memory interface, and the like, although not shown.

At least one processor may control the overall operation of the dual port storage device 300. The buffer memory controller may be implemented to control the buffer memory. The error correction circuit calculates the error correction code value of the data to be programmed in the write operation, error-corrects the data read in the read operation based on the error correction code value, and performs the error correction in the non-volatile memory device 321/322, It is possible to correct the error of the recovered data. The error correction circuit may be a circuit for decoding a low density parity check (LDPC) code, a BCH code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis- Block coded modulation (Coded Modulation) can be used to correct errors.

Although not shown, a code memory for storing code data necessary for operating the memory controller 321/322 can be further included. The code memory may be implemented as a non-volatile memory device.

The host interface may provide an interface function with an external host 100 (see FIG. 1). In an embodiment, the host interface may be implemented by various types of interfaces and may include non-volatile memory express (NVMe), peripheral component interconnect express (PCIe), serial at attachment (SATA), small computer system interface , SAS (serial attached SCSI), UAS (universal storage bus) attached SCSI, iSCSI (Internet Small Computer System Interface), Fiber Channel, Fiber Channel over Ethernet (FCoE), and the like.

The non-volatile memory interface may provide an interface function with the non-volatile memory device 321/322. For example, the non-volatile memory interface may be implemented as a legacy NAND interface or a vertical nand flash memory (VNAND) interface. However, it should be understood that the non-volatile memory interface is not limited thereto.

The buffer memory will temporarily store the data necessary for the operation of the memory controller 311/312. The buffer memory may include a plurality of memory lines for storing data or instructions. Wherein the plurality of memory lines may be mapped in various ways to the cache lines. The buffer memory may store page bitmap information and read count information. In an embodiment, the buffer memory may be implemented as volatile memory or non-volatile memory. For example, the buffer memory may be implemented as a dynamic random access memory (DRAM) or a phase random access memory (PRAM).

The first commands transmitted through the first port PT1 are processed in the first memory controller 311 and the second commands transmitted via the second port PT2 are processed in the second memory controller 312 ). ≪ / RTI > In an embodiment, the first memory controller 311 and the second memory controller 312 may independently process the corresponding commands.

Each of the at least one nonvolatile memory devices 321 and 322 may be a NAND flash memory, a vertical NAND flash memory (VNAND), a NOR flash memory ), A resistive random access memory (RRAM), a phase-change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM) A spin transfer random access memory (STT-RAM), or the like.

The non-volatile memory device may also be implemented as a three-dimensional array structure. As an embodiment of the present invention, a three-dimensional memory array may be monolithically connected to one or more physical levels of arrays of memory cells having active areas disposed above a circuit associated with operation of a silicon substrate and memory cells. ). The circuitry associated with the operation of the memory cells may be located within or on the substrate. The term monolithical means that layers of each level in a three-dimensional array are deposited directly on the lower-level layers of the three-dimensional array.

As an embodiment in accordance with the inventive concept, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on the other memory cell. The at least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. The at least one select transistor has the same structure as the memory cells and can be formed monolithically with the memory cells.

A three-dimensional memory array is composed of a plurality of levels and has word lines or bit lines shared between the levels. Suitable configurations for a three-dimensional memory array will be described in US 7,679,133, US 8,553,466, US 8,654,587, US 8,559,235, and US 2011/0233648, filed by Samsung Electronics and incorporated herein by reference. The nonvolatile memory device (NVM) of the present invention is applicable not only to a flash memory device in which the charge storage layer is composed of a conductive floating gate but also to a charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

Meanwhile, the dual port SSD 300 shown in FIG. 7 includes nonvolatile memory devices 321 and 322 corresponding to each of the ports PT1 and PT2. However, the dual port SSD of the present invention will not be limited thereto.

8 is a block diagram illustrating another embodiment of a dual port SSD according to an embodiment of the present invention. 8, dual port SSD 400 may include at least one non-volatile memory device 420 that is shared across bus 415 as compared to that of FIG. The first and second memory controllers 411 and 422 may be implemented to perform the same functions as those of FIG.

9 is a diagram illustrating an exemplary method of generating a host command according to an embodiment of the present invention. 1 to 9, a method of generating a command of the host apparatus 100 is as follows.

The CPU 110 may issue a dual port command for a test operation by executing a test program (S110). The device driver may receive the issued dual port command and generate a first command to be transmitted to the corresponding first port PT1 and a second command to be transmitted to the second port PT2 (S120). Here, the device driver determines the dual port delimiter including the dual port command, determines whether the dual port delimiter is supported by the dual port delimiter, and generates the commands corresponding to each port when the dual port is supported. Thereafter, the first and second commands may be simultaneously transmitted to the corresponding ports PT1 and PT2, respectively (S130).

10 is a diagram illustrating a method of testing a dual port SSD according to an exemplary embodiment of the present invention. Referring to FIGS. 1 to 10, a method of testing a dual port SSD is as follows.

First, the first and second ports PT1 and PT2 (see FIG. 1) of the dual port SSD will be activated for the test operation. Activation of the first and second ports PT1 and PT2 may be performed under the control of the host apparatus 100. [ However, the activation of the first and second ports PT1 and PT2 will not necessarily be limited thereto. The dual port SSD may simultaneously receive the first and second commands through the first and second ports PT1 and PT2 (S210). Here, the dual port SSD may store a plurality of first commands and a plurality of second commands. For example, the dual port SSD may receive and store a plurality of first commands sequentially through a first port in a queuing manner, and may sequentially receive and store a plurality of second commands through a second port.

Then, the dual port SSD may simultaneously test the first and second memories corresponding to the first and second commands, respectively (S220). The test result values may be temporarily stored in a buffer and then transmitted to the host device 100. [

On the other hand, the test system of the present invention will not be limited to a dual-port supporting dirt. The test system of the present invention is applicable to dots that support three or more multi-ports.

11 is a diagram illustrating an exemplary test system according to another embodiment of the present invention. 11, the test system 20 may include a host 100a and a plurality of dots 210a, ..., 2N0b. The host 100a can test the dots 210a, ..., 2N0a connected through four ports PT1, PT2, PT3, and PT4 in comparison with that of FIG. Each of the dots 210 ... ... 2N0a can activate all four ports PT1, PT2, PT3 and PT4, and the four activated ports PT1, PT2, PT3 and PT4 And can simultaneously process the received commands independently.

FIG. 12 is an exemplary diagram illustrating a data server system to which a storage device according to an embodiment of the present invention is applied. 12, the data server system 1000 may include a database management system (RDBMS) 1100, a cache server 1200, and an application server 1300.

The cache server 1200 may include key value storage for holding and deleting different pairs of keys and value pairs corresponding to the invalidation notification from the database management system 1100. [ The database management system 1200 may include the dual port storage device described in Figures 1-11.

Since the data server system 1000 according to the embodiment of the present invention can quickly and quickly perform the test operation through the multiport, the management cost can be greatly reduced compared with the conventional method.

The SAS device according to the embodiment of the present invention can improve the test efficiency by improving the data transfer rate by efficiently performing Write / Read using a plurality of ports and decreasing the test time during the quantitative test.

In the method of testing the SAD device according to the embodiment of the present invention, testing can be performed at the maximum performance by simultaneously using each port.

The above-described contents of the present invention are only specific examples for carrying out the invention. The present invention will include not only concrete and practical means themselves, but also technical ideas which are abstract and conceptual ideas that can be utilized as future technologies.

10, 20: Test system
100, 100a: host
110, 110a: CPU
120, 120a: HBA
210, 220, 2N0: dirt
PT1: First port
PT2: second port
201a, 201b: Connector
300, 400: Dual port SSD

Claims (20)

A method of a test system comprising a host device and storage devices connected to the host device through a multiport, the method comprising:
Issuing a command in a test program;
Generating a plurality of commands in the device driver corresponding to the command; And
And simultaneously transmitting the plurality of commands to the multi-port of each of the storage devices. The method according to claim 1,
Wherein the multiport is a dual port. The method according to claim 1,
Wherein the command comprises an operation code, a first address, a flag indicating dual port operation, and a second address. The method of claim 3,
Wherein generating the plurality of commands comprises:
And judging whether or not the flag is present from the command in the device driver. 5. The method of claim 4,
Wherein generating the plurality of commands comprises:
When the flag is present, generating a first command having the operation code and the first address, and a second command having the operation code and the second address. The method according to claim 1,
Further comprising activating all the ports of the multi-port of each of the storage devices. The method according to claim 1,
Wherein the plurality of commands are transmitted according to a peripheral component interconnect express (PCIe) interface at the physical layer. A first port implemented according to a communication protocol;
A second port implemented in accordance with the communication protocol;
A first at least one non-volatile memory device;
A second at least one non-volatile memory device;
A first memory controller coupled to the first port and controlling the first at least one non-volatile memory device; And
And a second memory controller coupled to the second port and controlling the second at least one non-volatile memory device,
During the test operation, the first port and the second port are activated,
Wherein each of the first and second memory controllers receives commands via a corresponding port and tests the corresponding non-volatile memory device in response to the received commands. 9. The method of claim 8,
And a connector having the first port and the second port. 10. The method of claim 9,
Wherein the connector comprises:
A first side having single pins, power and control pins corresponding to the first port; And
And a second side opposite the first side and having single pins corresponding to the second port. 10. The method of claim 9,
Wherein the connector comprises:
A first side having signal pins corresponding to the first port, first pins for a PCIe sideband, and power pins; And
And a second side opposite the first side and having second pins for the PCIe sideband, signal pins corresponding to the second port, and third pins for the PCIe sideband. 9. The method of claim 8,
Wherein the first at least one non-volatile memory device and the second at least one non-volatile memory device are the same,
Wherein each of the first and second memory controllers controls the same non-volatile memory device via a bus. 9. The method of claim 8,
Corresponding first and second commands are simultaneously received through the first and second ports,
Wherein tests for the corresponding at least one non-volatile memory device are performed concurrently in response to the first and second commands. 9. The method of claim 8,
Wherein the communication protocol is a protocol according to a nonvolatile memory device express (NVMe) interface. A host device; And
A plurality of dots connected to the host device through a dual port,
The host apparatus includes:
A central processing unit; And
And a host bus adapter connecting the central processing unit and the plurality of dirts,
Wherein during a test operation, a first command is transmitted to a first port of the dual port, and a second command is simultaneously transmitted to a second port of the dual port. 16. The method of claim 15,
Wherein the host bus adapter comprises a plurality of bus adapter units corresponding to the plurality of dots. 16. The method of claim 15,
Wherein the software layer of the host device comprises an application layer for issuing a dual port command and a command layer for generating the first and second commands to be transmitted to the first and second ports in response to the dual port command Test system. 18. The method of claim 17,
Wherein the dual port command comprises an operation code, a first address, a sector count, a feature, a dual port delimiter, a second address,
Wherein the first command includes the operation code, the first address, the sector count, and the feature,
Wherein the second command comprises the operation code, the second address, the sector count, and the feature. 16. The method of claim 15,
Wherein each of the plurality of dots is a SAS (serial attached small computer system interface) solid state drive (SSD). A method of testing a storage device comprising:
Receiving a first command through a first port;
Receiving a second command via a second port while receiving the first command;
Testing a first memory in response to the first command; And
Testing the first memory while testing the second memory in response to the second command.

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