KR20180013661A - System and method for designing integrated circuit by considering local layout effect - Google Patents

Abstract

Disclosed are a computing system and method for designing an integrated circuit by considering a local layout effect according to an exemplary embodiment of the present invention. The method for designing an integrated circuit according to an exemplary embodiment of the present disclosure includes the step of arranging instances of pre-arranged cells to reduce the occurrence of a local layout effect inducing structure. Also, the method for designing an integrated circuit according to an exemplary embodiment of the present disclosure can estimate the local layout effect to the arranged instance by extracting a context of the instance from a peripheral layout of the instance and can analyze the performance of the integrated circuit.

Description

[0001] SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUIT BY CONSIDERING LOCAL LAYOUT EFFECT [0002]

Technical aspects of the present disclosure relate to an integrated circuit, and more particularly, to a system and method for designing an integrated circuit in consideration of local layout effects.

An integrated circuit for processing digital signals can be designed based on standard cells. The integrated circuit may include instances of standard cells, and instances corresponding to one standard cell may have the same structure, i.e., a layout. Instances are placed and interconnects electrically connecting the instances are created so that the integrated circuit implements the desired functionality, so that a layout of the integrated circuit can be created.

Due to the miniaturization of the semiconductor manufacturing process, standard cells including patterns formed in a plurality of layers not only include patterns of reduced size, but also can reduce the size of standard cells. Thus, an instance of a standard cell included in an integrated circuit may have a greater influence from its surrounding structure (i.e., layout), and the effect of such a peripheral layout may be affected by a local layout effect (LLE) may be referred to as a layout dependent effect (LDE).

The technical idea of the present disclosure relates to a method of designing an integrated circuit in consideration of the local layout effect and a system for generating a layout of the integrated circuit so as to reduce the local layout effect and analyzing the performance of the integrated circuit by reflecting the local layout effect And methods.

To achieve these and other advantages and in accordance with one aspect of the present disclosure, a computing system for designing an integrated circuit including instances of standard cells includes a memory for storing information including procedures, And may include a processor that is accessible to memory and executes the procedures. The procedures include pre-arrangers that arrange the first instances of pre-arranged cells such that the occurrence of a local layout effect (LLE) inducing structure by placement of second instances of logical cells is reduced, An instance deployer that places the second instances in an un-deployed area, and a router that generates layout data for the integrated circuit by routing connections of the deployed first and second instances.

According to an aspect of the present disclosure, a method of designing an integrated circuit can be performed by a computing system, the method comprising: placing first instances of pre-arranged cells, Placing the second instances in an area in which the first instances are not arranged, and routing the connections of the first and second instances to the first instance and the second instance in order to reduce the occurrence of a local layout effect (LLE) Thereby generating layout data of the integrated circuit.

A computing system for designing an integrated circuit including instances of standard cells in accordance with an aspect of the teachings of the present disclosure includes a memory that stores information including procedures and a memory accessible to the memory, Lt; / RTI > Procedures refer to Local Layout Effect (LLE) data that includes information about the physical characteristics of standard cells that depend on the peripheral layout, and refer to the context of the deployed instance on the peripheral layout of the instance deployed in the integrated circuit. An instance characterizer for calculating the physical characteristics of the deployed instance based on the context data including the performance information of the deployed instance, and generating result data including performance information of the integrated circuit based on the calculated physical characteristics of the deployed instance And a performance analyzer.

A method of designing an integrated circuit, in accordance with an aspect of the teachings of the present disclosure, may be performed by a computing system, and the method includes the steps of: generating LLE data comprising information about physical characteristics of a standard cell Accessing context data that includes the context of the deployed instance with respect to a peripheral layout of the instance disposed in the integrated circuit, computing physical properties of the deployed instance based on the LLE data and context data And generating result data comprising performance information of the integrated circuit based on the calculated physical characteristics of the deployed instance.

According to the system and method for designing an integrated circuit according to an exemplary embodiment of the present disclosure, the local layout effect in an integrated circuit can be eliminated or reduced, and an integrated circuit with reduced performance variations due to local layout effects is designed .

In addition, with the system and method for designing an integrated circuit according to an exemplary embodiment of the present disclosure, the actual performance of the integrated circuit can be analyzed to reflect the local layout effects, and thus the integrated circuit can be optimally designed .

1 shows a block diagram of a computing system including a memory for storing a program according to an exemplary embodiment.
Figure 2 shows a schematic plan view of an integrated circuit in accordance with an exemplary embodiment.
Figure 3 shows a block diagram of the program of Figure 1 in accordance with an illustrative embodiment.
Figure 4 shows a block diagram of the deployer of Figure 3 in accordance with an exemplary embodiment.
Figures 5-8 are diagrams illustrating exemplary operations of the pre-deployer of Figure 4 in accordance with the illustrative embodiments.
Figures 9A and 9B illustrate examples of the implementation group of Figure 3.
10A and 10B are diagrams illustrating exemplary operations of the instance shifter of FIG. 9A or FIG. 9B in accordance with exemplary embodiments.
Figure 11 shows a block diagram of the analysis group of Figure 3 in accordance with an exemplary embodiment.
12 shows a block diagram of an LLE data generator in accordance with an exemplary embodiment.
Figures 13A and 13B illustrate exemplary operations in which the cell context generator of Figure 12 generates the context of a standard cell in accordance with exemplary embodiments.
14 illustrates an example of LLE data according to an exemplary embodiment.
15 is a block diagram of a context data generator according to an exemplary embodiment.
16 illustrates an exemplary operation of the instance context extractor of FIG.
17 is a flow diagram illustrating an integrated circuit design method in accordance with an exemplary embodiment.
18 is a flowchart showing an example of step S120 in Fig.
19 is a flowchart illustrating a method for moving an instance to remove an LLE triggered structure in accordance with an exemplary embodiment.
20 is a flow diagram illustrating an integrated circuit design method in accordance with an exemplary embodiment.

1 shows a block diagram of a computing system 10 including a memory for storing a program according to an exemplary embodiment of the present disclosure. The operation of designing the integrated circuit in accordance with the exemplary embodiment of the present disclosure may be performed in the computing system 10.

The computing system 10 may be a fixed computing system, such as a desktop computer, a workstation, a server, or the like, or a portable computing system, such as a laptop computer. 1, the computer system 10 includes a central processing unit (CPU) 11, input / output devices 12, a network interface 13, a random access memory (RAM) 14, only memory < / RTI > (15) and a storage device (16). The CPU 11, the input / output devices 12, the network interface 13, the RAM 14, the ROM 15 and the storage device 16 may be connected to the bus 17, Communication can be performed.

CPU 11 may be referred to as a processing unit and may be any unit of instruction such as a microprocessor, an application processor, a digital signal processor (DSP), a graphics processing unit (GPU) A core capable of executing IA-32 (Intel Architecture-32), 64-bit extension IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.) The processor 11 may access the memory via the bus 17 or RAM 14 or ROM 15 and may execute instructions stored in the RAM 14 or the ROM 15. [ The RAM 14 may store the program 20 or at least a portion thereof in accordance with the illustrative embodiment of the present disclosure and the program 20 may cause the CPU 11 to perform operations for designing the integrated circuit The program 20 may include a plurality of instructions executable by the CPU 11, A plurality of commands are included in 20, can be to perform the operations for designing an integrated circuit in accordance with an exemplary embodiment of the disclosure allows the CPU (11) present.

The storage device 16 may not lose the stored data even if the power supplied to the computing system 10 is interrupted. For example, the storage device 16 may be a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory ), Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM) Or may include a storage medium such as a magnetic disk. In addition, the storage device 16 may be removable from the computing system 10. The storage device 16 may store the program 20 in accordance with the illustrative embodiment of the present disclosure and may store the program 20 or the program 20 from the storage device 16 prior to being executed by the CPU 11. [ At least a portion of it may be loaded into the RAM 14. The storage device 16 may store a file written in a programming language and the program 20 or at least a part thereof generated by a compiler or the like may be loaded into the RAM 14. [

The storage device 16 may store data to be processed by the CPU 11 or data processed by the CPU 11. [ That is, the CPU 11 can generate new data by processing the data stored in the storage device 16 according to the program 20, and store the generated data in the storage device 16. [ For example, the storage device 16 may store the input data D010 of FIG. 3 processed by the program 20 and / or the layout data D100 of FIG. 3 generated by the program 20 and / And store result data D200.

Input / output devices 12 may include input devices such as keyboards, pointing devices, and the like, and may include output devices such as display devices, printers, and the like. For example, the user may trigger the execution of the program 20 by the CPU 11 or input the input data D010 of Fig. 3 via the input / output devices 12, D100, result data D200, and / or an error message.

The network interface 13 may provide access to a network outside the computing system 10. For example, a network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links. The input data D010 of Figure 3 may be provided to the computing system 10 via the network interface 13 and the layout data D100 and / May be provided to the system.

2 shows a schematic plan view of an integrated circuit 5 according to an exemplary embodiment of the present disclosure. In Fig. 2, each component included in the integrated circuit 5 may not be scaled for explanatory convenience, and may be exaggerated or reduced.

Referring to FIG. 2, the integrated circuit 5 may include instances of standard cells (C01 through C06). Instances corresponding to the same standard cell (e.g., C02, C03, C04, C05) may have the same layout, and instances corresponding to different standard cells may have different layouts, respectively. The instances C01 to C06 may be arranged in a plurality of rows R01 to R04. The instances C01 to C06 may have a length H (i.e., height) defined in a direction perpendicular to the plurality of rows R01 to R04 extending in the X direction (i.e., the Y direction) (I.e., width) in the direction parallel to the rows (i.e., the X direction). Each of the plurality of rows R01 through R04 in which the instances C01 through C06 are aligned may have a height corresponding to a minimum height of the standard cell. The standard cell of instances having a height that coincides with the row height H, such as the instances (C01 through C05 and C07) of FIG. 2, may be referred to as a single height cell, A standard cell of an instance having a height that coincides with a multiple of the row height H, such as C06, may be referred to as a multi-height cell.

A standard cell to be included in an integrated circuit may be selected from a cell library (for example, D310 in FIG. 3) including information on a plurality of standard cells based on physical characteristics of standard cells such as functions, timing characteristics, The layout of the integrated circuit 5 can be created by placing an instance of the standard cell. An instance may have physical characteristics that differ from the physical characteristics of a standard cell (i. E. Intrinsic physical characteristics of a standard cell) depending on its surrounding layout. For example, the threshold voltage (Vth) and the saturation current (Idsat) of the transistors included in the instance may vary according to the layout around the instance, so that the physical characteristics of the instance included in the integrated circuit 5, May be different from the intrinsic physical properties of a standard cell defined in < RTI ID = 0.0 > In this way, the impact of the peripheral layout of the instance may be referred to as a local layout effect (LLE) or a layout dependent effect (LDE), and the local layout effect on the instance may be referred to as instance & It may be difficult to know exactly until it is decided.

The physical characteristics of the transistor, such as the threshold voltage Vth and the saturation current Idsat, may be determined by a front-end-layer or front-end-of-layer pattern formed around the transistor Lt; / RTI > For example, the physical properties of the transistor can be varied by the length of the pattern of the front-end-layer aligned in the Y direction and the distance between the patterns of the front-end-layer spaced in the X direction. The front-end-layer may refer to a layer formed by a front-end-of-line (FEOL) that forms elements such as transistors, capacitors, resistors, etc. in a semiconductor manufacturing process. For example, as shown in FIG. 2, the instances of the standard cell (C01 through C06) may comprise patterns of front-end-layers formed on or inside the edges.

According to an exemplary embodiment of the present disclosure, a method of designing an integrated circuit that may be performed in the computing system 10 of FIG. 1 may consider local layout effects based on the front-end-layer. For example, as described below with reference to Figures 4 to 10B, the instances may be arranged such that the occurrence of local layout effects by the front-end-layer is reduced, and thus local layout effects and local layout effects The performance fluctuation of the integrated circuit due to the power consumption can be eliminated or reduced. In addition, as will be described later with reference to Figures 11-16, the instance can be calculated on the basis of the front-end-layer around it, and thus, The actual performance can be analyzed and the integrated circuit can be optimally designed with the unnecessary performance margin eliminated.

FIG. 3 shows a block diagram of program 20 of FIG. 1 in accordance with an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1, program 20 may include a plurality of instructions, and the plurality of instructions contained in program 20 may cause CPU 11 to execute instructions, So that an operation of designing an integrated circuit can be performed. All of the components of the program 20 shown in Figure 3 may be stored in the RAM 14 of Figure 1 and at least some of the components are stored in the RAM 14 of Figure 1, 1 < / RTI >

3, program 20 may include an implementation group 100 and an analysis group 200, and the implementation group 100 and analysis group 200 may include a plurality of procedures 120, 140, 220, and 240, respectively. A procedure may refer to a set of instructions for performing a particular task. A procedure may also be referred to as a function, a routine, a subroutine, a subprogram, or the like. Each of the procedures may process externally provided data (e.g., D010) or data (e.g., D180) generated by another procedure. Herein, the CPU 11 of FIG. 1 performs operations by executing a procedure (e.g., 120, 140, 220 or 240) until a procedure (e.g., 120, 140, 220 or 240) . ≪ / RTI >

Cell library D310, design rules D320 and LLE data D330 may be stored in storage medium 30 and storage medium 30 may be storage device 16 in FIG. The cell library D310 may include at least one of information on physical characteristics of a plurality of standard cells, for example, function information, timing information, layout information, and power information. Design rule D320 may include rules that an integrated circuit must conform to in order for the integrated circuit to be fabricated by a semiconductor process and / or to prevent degradation of the performance of the integrated circuit. Further, as described later, the design rule D320 may further include information for detecting a structure causing a local layout effect. The LLE data D330 may include information on the physical property variation of the standard cell due to the local layout effect. LLE data D330 may be generated by the LLE data generator 300 and may be generated prior to the implementation group 100 and analysis group 200 of Figure 3 being executed, as described below with reference to Figures 12-14. Can be prepared.

The implementation group 100 may refer to the data D310, D320 and D330 stored in the storage medium 30 and may generate the layout data D100 from the input data D010. The input data D010 may include data defining the integrated circuit, e.g., a netlist containing information about the instances of standard cells and the electrical connections of the instances. Further, the input data D010 may further include information on the requirements of the integrated circuit, such as timing conditions, power conditions, area conditions, and the like. The implementation group 100 references the data D310, D320, and D330 stored in the storage medium 30 to generate layout data D100 including the physical information of the layout of the integrated circuit from the input data D101 defining the integrated circuit Can be generated.

The implementation group 100 may also access result data D200 that includes information about the performance of the integrated circuit generated by the analysis group 200 based on the layout data D100. The implementation group 100 determines the layout of the integrated circuit according to whether or not the performance of the integrated circuit according to the layout data D100 satisfies the requirements of the integrated circuit included in the input data D010, New layout data D100 indicating the changed layout can be generated. For example, the result data D200 may include performance degradation or performance margins of the integrated circuit depending on the local layout effect, and the implementation group 100 may include a layout of the optimally designed integrated circuit based on the result data D200 Lt; RTI ID = 0.0 > D100 < / RTI >

The deployer 120 of the implementation group 100 can refer to the cell library D310 and arrange the instances defined in the input data D010. The deployer 120 can obtain the layout of the instances defined in the input data D010 by referring to the cell library D310 and can obtain information about the requirements of the integrated circuit included in the input data D010 and the design rule D320 (I. E., Layouts of instances) based on the < / RTI > As will be described below, according to an exemplary embodiment of the present disclosure, the deployer 120 may deploy instances to reduce the occurrence of a structure that causes a local layout effect. Details regarding the placement machine 120 will be described later with reference to Figs.

Router 140 may create interconnections that electrically connect instances disposed by deployer 120. For example, the router 140 may use a routing resource, i. E., A plurality of interconnect layers and vias, to create an interconnect that includes patterns and / or vias formed in the interconnect layer. The router 140 can generate the interconnections based on the design rule D320 and information about the connection relationship of the instances defined in the input data D010. In addition, the router 140 may generate interconnections based on information regarding the requirements of the integrated circuit included in the input data D010.

The analysis group 200 can refer to the data D310, D320 and D330 stored in the storage medium 30 and generate the result data D200 from the layout data D100. The layout data D100 may include physical information related to the layout of the integrated circuit, and may include data having a GDSII format, for example. Although the analysis group 200 in FIG. 3 is shown as accessing the layout data D100 generated by the implementation group 100, the layout data D100 may be different from the computing system in which the analysis group 200 is performed, May be generated by the system and provided to the analysis group 200. The analysis group 200 can analyze the performance of the integrated circuit based on the layout data D100 and generate the result data D200 that includes information on the performance of the integrated circuit. As described below, the analysis group 200 can estimate the local layout effects that occur in the layout of the integrated circuit, and thus the result data D200 can reflect the performance of the actual integrated circuit.

The instance characterizer 220 of the analysis group 200 can calculate the physical characteristics of the instance included in the layout data D100 by referring to the LLE data D330. That is, the instance characterizer 220 can calculate the physical characteristics of the instance by estimating the local layout effect on the instance by the peripheral layout of the instance, that is, the context. For example, even though they are instances of the same standard cell, the physical characteristics of those instances extracted by the instance characterizer 220 may be different. As described below with reference to FIGS. 15 and 16, the instance characterizer 220 determines the physical characteristics of the instance based on the pattern of the front-end-layer included in the instance and the pattern of the front- Can be calculated.

The performance analyzer 240 can generate the result data D200 by analyzing the performance of the integrated circuit based on the physical characteristics of the instance extracted by the instance characterizer 220. [ For example, the performance analyzer 240 can analyze timing characteristics, power characteristics, noise characteristics, and the like of the integrated circuit. The performance analyzer 240 also refers to the information about the requirements of the integrated circuit included in the input data D010 and generates result data D200 including the result of determining whether the performance of the integrated circuit satisfies the requirement You may.

Figure 4 shows a block diagram of the deployer 120 of Figure 3 in accordance with an exemplary embodiment of the present disclosure. As described above with reference to FIG. 3, deployer 120 may deploy the instances defined in input data D010. 4, deployer 120 may include pre-deployer 122 and instance deployer 124 and may access input data D010, cell library D310, and design rules D320 .

The pre-deployer 122 may deploy instances of pre-deployed cells. The pre-layout cell may correspond to instances (referred to as first instances) that are disposed before the instances of logic cells included in the integrated circuit (hereinafter referred to as second instances) are deployed, A well-edge cell, a well-bias cell, a decap cell, or the like. The cell library D310 may include information about the pre-layout cell, the input data D010 may define some of the instances of the pre-layout cell, and the pre-layout 122 may include It is possible to create and arrange the instances of the pre-arranged cells with reference to the cell library D310.

The preprocessor 122 is configured to generate a local layout effect inducing structure (hereinafter referred to as an LLE inducing structure) by placement of second instances (i.e., instances of logic cells) (I. E., Instances of pre-arranged cells). As shown in FIG. 4, the design rule D320 may include the LLE rule D322, and the LLE rule D322 may include information about the LLE inducement structure. For example, the LLE rule D322 may include information defining a structure in which the patterns formed in the front-end-layer are arranged, and the pre-layout 122 may refer to the LLE rule D322, As described below with reference to FIG. 8, the first instances may be arranged such that the pattern of the front-end-layer included in the second instances decreases. The LLE rule D322 may also include information about the spacing and / or the opposing length between adjacent patterns formed in the front-end-layer.

The instance deployer 124 may place the second instances in an area where the first instances are not deployed. By limiting the area in which the second instances are arranged by the first instances arranged by the preprocessor 122, the LLE inducing structure formed by the second instances can be reduced or eliminated. Thus, the second instances may have physical characteristics that approximate the physical characteristics (i.e., intrinsic physical characteristics) of the standard cell defined in the cell library D310 and may include physical characteristics of the second instances that have been deployed and input data D010) may be reduced (e.g., during logical synthesis), the gap between the physical characteristics of the expected second instances may decrease. The cell library D310 may include information defining the physical characteristics of the standard cell when no local layout effect has occurred in the standard cell or when an average local layout effect occurs in the standard cell and input data D010 ) May be generated based on the cell library D310. As a result, the gap between the performance of the integrated circuit according to the layout data D100 and the performance of the integrated circuit expected when the input data D010 is generated can be reduced, and accordingly, . ≪ / RTI >

5 through 8 are diagrams illustrating exemplary operations of the preprocessor 122 of FIG. 4 in accordance with an exemplary embodiment of the present disclosure. As described above with reference to FIG. 4, the preprocessor 122 may arrange the first instances of the pre-deployed cell such that the occurrence of the local layout effect inducing structure by placement of the second instances is reduced. 5-8 illustrate examples of instances deployed by the preprocessor 122, and it will be understood that the operation of the preprocessor 122 is not limited to the examples shown in FIGS. 5-8. 5 to 8 will be described with reference to Fig.

In the examples of FIGS. 5-8, the LLE rule 322 of FIG. 4 is assumed to contain information defining the structure in which the patterns of the front-end-layer are aligned as an LLE inducing structure, It is assumed, at least in part, to include front-end-layer patterns formed on opposing edges as shown in FIG. Accordingly, the preprocessor 122 may place the first instances such that the edges of the area in which the second instances are arranged are not aligned in a series of rows. That is, the preprocessor 122 may reduce the alignment of the edges of the second instances by properly arranging the first instances so that the edges of the regions disposed in the second instances are not aligned in a plurality of rows . As a result, the alignment of the front-end-layer patterns formed at the edges of the second instances can be reduced.

Referring to Figures 5 and 6, according to an exemplary embodiment of the present disclosure, the pre-arranger 122 is configured to align the edges of the first instances closest to each other in a direction perpendicular to a plurality of rows (e.g., R11 through R19 in Figure 5) Lt; RTI ID = 0.0 > 1 < / RTI > For example, as shown in FIG. 5, the preprocessor 122 may arrange the first instances such that the edges of the first instances disposed in adjacent rows are not aligned. 6, the pre-arranger 122 may also be arranged in an odd numbered row (e.g., due to the design rule D320 of FIG. 4) The first instances may be arranged so that the edges of one instance are not aligned.

Referring to FIG. 5A, the pre-arranger 122 is arranged at the left edge of the first instances C11a, C13a, C15a, C17a, C19a disposed in odd rows R11, R13, R15, R17, And right edges of the first instances C12a, C14a, C16a, and C18a arranged in the even rows R12, R14, R16, and R18 are respectively aligned at Y10 and Y12, and Y11 and Y13 The first instances C11a through C19a may be arranged so that the first instances C11a through C19a are respectively aligned with the first instances C11a through C19a. 5B, the preprocessor 122 determines that the left edges of the first instances (e.g., C11b through C13b) that are sequentially placed in a series of rows (e.g., R11 through R13) , The first instances C11b through C19b may be arranged such that the right edges are respectively aligned with Y17, Y18 and Y19, respectively, and the right edges are respectively aligned with Y17, Y18 and Y19.

6 (a), the preprocessor 122 determines that the left edges of the first instances (e.g., C21a, C22a) that are sequentially disposed in odd rows (e.g., R21, R23) And the first instances C21a through C25a may be arranged such that the right edges are aligned with Y22 and Y23, respectively. Similarly, referring to FIG. 6B, the pre-arranger 122 includes left edges of first instances C21b to C25b sequentially disposed in odd rows R21, R23, R25, R27, and R29 The first instances C21b to C25b may be arranged such that the right edges are respectively aligned in order with Y27, Y25, Y26, Y25, and Y24, and the right edges are respectively aligned with Y27, Y28, Y29, Y28, and Y27.

Referring to Figures 7 and 8, the preprocessor 122 may place instances of dummy cells adjacent to the first instances such that the occurrence of the local layout effect inducing structure by placement of the second instances is reduced. The dummy cell is a cell independent of the function of the integrated circuit, and may include a pre-arranged cell or a filler cell. The cell library D310 of FIG. 4 may contain information about dummy cells, and the preprocessor 122 may place instances of dummy cells by referring to the cell library D310.

Advanceer 122 may place instances of different dummy cells (e.g., dummy cells having different widths) adjacent an edge of at least one first instance having an edge perpendicular to the series of rows. 7, the pre-layout cell may be a multi-height cell (i.e., 4x multi-height cell) corresponding to the height of four rows, and the pre-layout 122 may be a multi- Two or more dummy cells having different widths adjacent to the edge of the instance of the first layer may be alternately arranged.

7A, a first instance C31a of a pre-positioned cell, which is a 4x multi-height cell, can be placed by the preprocessor 122, and the preprocessor 122 can be arranged in a first instance C31a, (D31a to D34a, D36a to D39a) adjacent to the edge of the first instance C31a in the series of rows R32 to R35 in which the first instance C31a is arranged. For example, instances of dummy cells D31a, D34a having left edges aligned with Y30 may be placed in even rows R32, R34, respectively, and instances of dummy cells having left edges aligned in Y31 (D32a, D34a) may be arranged in the odd-numbered rows R33, R35, respectively. Similarly, instances (D36a, D38a) of dummy cells having the right edge aligned with Y32 can be placed in odd rows (R35, R33), respectively, and instances of dummy cells D37a, and D39a may be disposed in the even rows R34 and R32, respectively. Dummy cell instances D30a and D35a may also be arranged in the series of rows R32 to R35 in which the first instance C31a is arranged and in the adjacent rows R31 and R36 respectively.

7B, instances of different dummy cells D31b-D34b, D31b-D34b adjacent to the edge of the first instance C31b in the series of rows R32-R35 in which the first instance C31b is disposed, D36b to D39b may be alternately arranged. For example, an instance D32b of a dummy cell having a left edge aligned in Y34 may be placed in row R33, and instances of a dummy cell D31b, D34b having a left edge aligned in Y35 may be arranged in rows (R32, R35), and an instance (D33b) of the dummy cell having the left edge aligned to Y36 may be placed in row R34. Similarly an instance D38b of the dummy cell with the right edge aligned to Y37 may be placed in row R33 and instances of the dummy cell D36b and D39b with the right edge aligned to Y38 may be placed in rows R35, and R32, respectively, and an instance D37b of the dummy cell having the right edge aligned to Y39 may be disposed in the row R34. Dummy cell instances D30b and D35b may also be arranged in the series of rows R32 to R35 in which the first instance C31b is arranged and in the adjacent rows R31 and R36, respectively.

8A, a plurality of first instances C41a-C49a of a pre-placement cell C41a-C49a are arranged by a preprocessor 122, for example, by a design rule D320 of FIG. 4, R41 to R49). The preprocessor 122 is operable to provide different instances of dummy cells D41a-D49a, D41a'-D49a 'adjacent to the edges of the first instances C41a-C49a aligned in the series of rows R41- They can be arranged alternately. For example, the instances D42a, D44a, D46a, and D48a of the dummy cell having the left edge aligned in Y40 may be disposed in the even rows R42, R44, R46, and R48, respectively, The instances D41a, D43a, D45a, D47a, and D49a of the dummy cell having edges can be disposed in the odd rows R41, R43, R45, R47, and R49, respectively. Similarly, instances of a dummy cell D41a'-D49a 'having a right edge aligned to Y42 or Y43, adjacent to the right edges of the first instances C41a-C49a, may be alternatively arranged .

Referring to Figure 8B, the pre-arranger 122 is configured to create instances of different dummy cells D41b-C49b adjacent to the edges of the first instances C41b-C49b aligned in a series of rows R41-R49 To D49b, D41b 'to D49b') can be arranged alternately. For example, instances of dummy cells D43b, D46b, and D49b having left edges aligned at Y44 may be disposed in rows R43, R46, and R49, respectively, and dummy cells having left edges aligned at Y45 The instances D41b, D45b and D48b of the dummy cell having the left edge aligned at Y46 can be arranged in the rows R42, R45 and R48, respectively, , R44, and R47, respectively. Similarly, instances of dummy cells D41b 'to D49b' having the right edge aligned to Y47, Y48 or Y49 adjacent to the right edges of the first instances C41b to C49b are alternately arranged .

Figures 9A and 9B illustrate examples 100a and 100b of the implementation group 100 of Figure 3 in accordance with an exemplary embodiment of the present disclosure. As shown in FIGS. 9A and 9B, the implementation group 100a or 100b may include an instance shifter 126a or 166b.

In accordance with an exemplary embodiment of the present disclosure, instance shifters 126a and / or 166b, as described below with reference to FIGS. 10A and 10B, are arranged by preprocessor 122a and instance arranger 124a or 124b, respectively It is possible to remove the LEE induced structure in the layout of the integrated circuit or reduce the local layout effect by the LLE induced structure by moving at least one first or second instance related to the LLE induced structure among the first and second instances. FIG. 9A shows an example in which the instance shifter 126a is included in the placement machine 120a, and FIG. 9B shows an example in which the instance shifter 166b is included in an engineering change order (ECO) 160b. In accordance with an exemplary embodiment of the present disclosure, deployer 120b of Figure 9b may also include an instance shifter, as shown in Figure 9a. Hereinafter, among the descriptions of Figs. 9A and 9B, the description overlapping with the description of Fig. 4 will be omitted.

9A, an implementation group 100a may include a deployer 120a and a router 140a, and the deployer 120a may include a pre-deployer 122a, an instance deployer 124a, and an instance shifter 126a . 4, pre-deployer 122a may deploy instances of pre-deployed cells (first instances), and instance deployer 124a may deploy instances of logical cells (second instances < RTI ID = 0.0 > ) In an area where the first instances are not arranged.

The instance shifter 126a can refer to the LLE rule D322 included in the design rule D32 to move at least one first or second instance of the first and second instances related to the LLE inducing structure . For example, the LLE rule D322 may include information defining at least one LLE inducing structure, and the instance shifter 126a may include information about the first and / In the layout of the integrated circuit including the second instances, the LLE induced structure can be detected based on the LLE rule D322. The instance shifter 126a may remove the LLE induced structure or reduce the local layout effect by the LLE induced structure by moving at least one first or second instance associated with the detected LLE induced structure.

The router 140a may generate the layout data D100 by creating interconnections that connect the first and second instances of the integrated circuit including the first or second instance moved by the instance shifter 126a have.

9B, the implementation group 100b may include a deployer 120b, a router 140b, and an ECO 160b, and the ECO 160b may include an instance shifter 166b. The ECO 160b may refer to the process of replacing a deployed instance or adding a new instance as needed after the instances of the standard cell are deployed and interconnects connecting the instances are created. The ECO 160b may perform the routing operation locally with respect to the replaced or added instance. Thus, while the processes for designing the integrated circuit, such as logic synthesis, placement, routing, timing analysis, and the like are omitted, limited changes can be reflected in the integrated circuit by the ECO 160b.

In accordance with an exemplary embodiment of the present disclosure, instance shifter 166b may be included in ECO 160b and similar to instance shifter 126a of Figure 9a, the LLE rule D322 included in design rule D320, To move at least one first or second instance associated with the LLE triggering structure. The instance shifter 166b may generate layout data D100 of the integrated circuit including the moved first or second instance.

10A and 10B are diagrams illustrating exemplary operations of instance shifter 126a or 166b of FIG. 9A or FIG. 9B in accordance with an exemplary embodiment of the present disclosure. As described above with reference to Figures 9A and 9B, the instance shifter 126a or 166b may detect the LLE induced structure based on the LLE rule D322 and may detect at least one first Or by moving the second instance to remove the LLE induced structure or reduce the local layout effect by the LLE induced structure. 10A and 10B illustrate examples of moving an instance by instance shifter 126a or 166b, and the operation of instance shifter 126a or 166b is not limited to the examples shown in FIGS. 10A and 10B It will be understood. Hereinafter, Figs. 10A and 10B will be described with reference to Fig. 9A.

Referring to FIG. 10A, the instance shifter 126a may detect the LLE induced structure. For example, the LLE rule D322 of FIG. 9A may define front-end-layer patterns arranged above a certain length as the instances of the standard cell are arranged, and the instance shifter 126a may define The patterns of the front-end layer aligned in the series of four rows R51 to R54 as shown in Fig. 10A can be detected as the LLE inducing structure LLE1. 10A, the instance shifter 126a may move the instance C51 in the left direction (i.e., the -X direction) to remove the LLE induced structure LLE1, (That is, in the + X direction). In addition, to remove the LLE induced structure LLE1, the instance shifter 126a may include at least one instance that includes a pattern of the front-end layer contributing to the LLE induced structure LLE1 as well as the left- (I.e., the + Y direction) or the downward direction (i.e., the -Y direction), move to a specific distance or other area, and exchange other instances and positions with each other. Accordingly, the LLE inducing structure LLE1 can be eliminated by the instances C51 'and C52' moved by the instance shifter 126a, as shown in FIG. 10A, (b).

Referring to FIG. 10B, according to an exemplary embodiment of the present disclosure, instance shifter 126a may move two or more instances adjacent to each other in the same row. For example, as shown in FIG. 10B (a), the instance shifter 126a includes an LLE inducing structure LLE2 including patterns of front-end layers arranged in a series of four rows R61 through R64 The two or more instances C61 and C62 adjacent to each other in the row R61 can be moved in the same direction (i.e., the leftward direction or the -X direction). In addition, the instance shifter 126a can move two or more instances C63 and C64 adjacent to each other in the row R63 in opposite directions. In addition, to remove the LLE induced structure LLE2, the instance shifter 126a may include at least one instance including a pattern of the front-end layer contributing to the LLE induced structure LLE2 as well as the left- Direction (i.e., the + Y direction) or the downward direction (i.e., the -Y direction), and can be moved to a specific distance or to an area other than the specified distance, and can exchange positions with other instances. Hence, the LLE inducing structure LLE2 can be eliminated by the instances C61 'to C64' moved by the instance shifter 126a, as shown in FIG. 10B, (b).

The implementation group 100 of FIG. 3 according to an exemplary embodiment of the present disclosure has been described above with reference to FIGS. 4 through 10B, and with reference to FIGS. 11 through 16, the analysis group 200 of FIG. Will be explained.

FIG. 11 shows a block diagram of an analysis group 200 of FIG. 3 in accordance with an exemplary embodiment of the present disclosure. 3, the analysis group 200 may include an instance characterizer 220 and a performance analyzer 240 and may refer to the cell library D310 and the LLE data D330, The result data D200 can be generated from the data D100. The result data D200 generated by the analysis group 200 may include information on the actual performance of the integrated circuit in which the local layout effect is reflected.

Referring to FIG. 11, the instance characterizer 220 may access the LLE data D330 and the context data D150. The LLE data D330 may include information on the physical characteristic variation of the standard cell due to the local layout effect and the context data D150 may include information on the peripheral layout of the instance extracted from the layout data D010 . The instance characterizer 220 can calculate the physical characteristics according to the local layout effect of the instances included in the integrated circuit by referring to the LLE data D330 and the context data D150. The details of the LLE data D330 will be described later with reference to Figs. 12 to 14, and the details of the context data D150 will be described later with reference to Figs. 15 and 16. Fig.

The performance analyzer 240 can access the cell library D310 and the layout data D010. The performance analyzer 240 analyzes the information on the physical characteristics of the standard cell included in the cell library D310 and on the basis of the information on the physical characteristics of the instance provided by the instance characterizer 220, The performance of the integrated circuit can be analyzed and the result data D200 including the actual performance information of the integrated circuit reflecting the local layout effect can be generated.

12 shows a block diagram of an LLE data generator 300 that generates LLE data D330 in accordance with an exemplary embodiment of the present disclosure. LLE data generator 300 may include a procedure including a series of instructions and may be performed by a processor (e.g., CPU 11 of FIG. 1) executing the instructions to perform operations of LLE data generator 300 . The LLE data generator 300 may generate LLE data D330 from the cell library D310 and may include a cell context generator 320 and an LLE estimator 340, as shown in FIG.

The cell context generator 320 may generate a plurality of contexts of the first standard cell by arranging various layouts around the layout of standard cells included in the cell library D310. For example, as described below with reference to FIG. 13A, the cell context generator 320 generates a context of an object standard cell by placing standard cells including a pattern of a front-end-layer around the object standard cell . In addition, as described later with reference to FIG. 13B, the cell context generator 320 may generate the context of the standard cell by arranging arbitrary patterns formed in the front-end-layer around the standard cell. The various contexts of the standard cell generated by the cell context generator 320 may be used by the LLE estimator 340 to estimate the local layout effect corresponding to each of the contexts.

The LLE estimator 340 may receive information about the contexts of the standard cell from the cell context generator 320 and may estimate the local layout effect caused by each context and may determine the physical It is possible to generate LLE data D330 including information on the variation of the characteristic. For example, the cell library D310 may include a property function that computes a value representing the physical characteristics of a standard cell, and the LLE estimator 340 may include a property function that, based on the context provided by the cell context generator 320, Parameters can be determined. The LLE data 340 may generate LLE data D330 containing the results of the characteristic function by the parameters determined by the LLE estimator 340 or the determined parameters.

Figures 13A and 13B illustrate exemplary operations in which the cell context generator 320 of Figure 12 generates the context of a standard cell in accordance with an exemplary embodiment of the present disclosure.

Referring to FIG. 13A, in accordance with an exemplary embodiment of the present disclosure, the cell context generator 320 generates standard cells C70 included in the cell library D310 (C71 through C74) To generate various contexts of the standard cell C70. For example, the cell context generator 320 may generate a context of an object standard cell (e.g., C70) that includes a pattern of the front-end-layer and may generate a context- (For example, C71 to C74) including a pattern of the end-layer is randomly arranged around the target standard cell (e.g., C70).

Referring to FIG. 13B, according to an exemplary embodiment of the present disclosure, a cell context generator 320 generates a context of a standard cell C80 by arranging a polygon of a layer having various shapes around a standard cell C80 can do. For example, as shown in FIG. 13B, the cell context generator 320 generates a plurality of patterns P11 to P16, each including a different pattern of the front-end-layer, So as to generate the contexts of the standard cell C80.

14 illustrates an example of LLE data D330 in accordance with an exemplary embodiment of the present disclosure. 12, the LLE estimator 340 of the LLE data generator 300 estimates the LLE data D330 by estimating the local layout effect corresponding to the various contexts generated by the cell context generator 320 Can be generated. Fig. 14 shows a part of the LLE data D330 showing the variation of the physical characteristics of the inverter INV, which is a standard cell corresponding to the local layout effect.

According to an exemplary embodiment of the present disclosure, LLE estimator 340 may generate LLE data D330 based on parameters of a characteristic function determined based on context and context. For example, the LLE estimator 340 may generate LLE data (D330) containing parameters of a characteristic function determined based on the context and context, and may generate LLE data (D330) that includes the values of the characteristic functions corresponding to the context and context Data D330 may be generated. 14, instead of the value of the characteristic function corresponding to the context, the LLE data including the ratio or ratio between the value of the characteristic function corresponding to the context and the value of the characteristic function based on the intrinsic parameter of the standard cell (D330). The intrinsic parameters of the standard cell include a characteristic function for calculating a value representing the intrinsic physical property of the standard cell, such as when the local layout effect does not occur in the standard cell or when an average local layout effect occurs in the standard cell Parameter.

14, the rows of the table represent the intervals in the X direction between the patterns of the front-end-layer, and the rows of the table represent the lengths of the patterns of the front-end-layer aligned in the Y direction. Depending on the context of the inverter INV, the X-directional spacing between the front-end-layer patterns is '2x' (i.e., a distance corresponding to twice the reference distance) and the patterns of the front- The physical property of the inverter INV may be the value of the characteristic function by the intrinsic parameter of the inverter INV when the length aligned with the input INV is '1y' (i.e., the length of the polygon drawn in a specific layer or a multiple of the reference length) have.

As shown in FIG. 14, the table may include variations of physical characteristics corresponding to the various contexts of the inverter INV as items, for example, each of the items may correspond to a delay time of the inverter INV . For example, according to the context of the inverter INV, the X-directional interval between the patterns of the front-end-layer is '8x', the length of the patterns of the front- The delay time of the inverter INV is 7.37% degradation (i.e., 7.37%) than the delay time (REF) due to the intrinsic parameter, due to the local layout effect due to the front- Extended). The delay time REF of the inverter INV by the intrinsic parameter can be calculated from the characteristic function included in the cell library D310 or included in the cell library D310 and the intrinsic parameter. As described above with reference to FIG. 11, the LLE data D330 including the table of FIG. 14 may be used by the instance characterizer 220 to characterize the layout of the integrated circuit.

FIG. 15 shows a block diagram of context data generator 400 in accordance with an exemplary embodiment of the present disclosure. Context data generator 400 may include a procedure including a series of instructions and may be executed by a processor (e.g., CPU 11 of FIG. 1) executing the instructions to perform operations of context data generator 400 . In one embodiment, the context data generator 400 may be included in the implementation group 100 of FIG. 2, and thus the context data D150 may be generated along with the layout data D100. In addition, in one embodiment, the context data generator 400 may be included in the analysis group 200 of FIG. 2, and thus the context data D150 may be generated from the layout data D100. As shown in FIG. 15, the context data generator 400 may include an instance selector 420 and an instance context extractor 440.

The instance selector 420 may, in the layout of the integrated circuit, select an instance to create the context. For example, the instance selector 420 may provide all of the instances included in the integrated circuit to the instance context selector 440, select some of the instances included in the integrated circuit and send it to the instance context extractor 440 . In one embodiment, the instance selector 420 can recognize the instances included in the critical path of the integrated circuit by referring to the input data D010 or the layout data D100, and the instances included in the critical path And provide them to the instance context extractor 440. In addition, in one embodiment, the instance selector 420 may select instances included in the clock tree of the integrated circuit and provide them to the instance context extractor 440. The instance selector 420 may select instances of the integrated circuit that are highly relevant to the performance of the integrated circuit to be analyzed and provide selected instances to the instance context extractor 440. [

The instance context extractor 440 may generate from the layout data D100 the context data D150 that includes information (i.e., context) about the peripheral layout of the instances selected by the instance selector 420. [ For example, the instance context extractor 440 extracts the context data D150 including the context of the instance based on the pattern of the front-end-layer included in the instance and the pattern of the front- Lt; / RTI > The cell context generator 320 of FIG. 12 generates various contexts of the standard cell by arranging various various layouts around the standard cell for generation of the LLE data D330, while the instance context extractor 440 of FIG. In order to generate the context data D150, the context of the instance can be extracted from the actual peripheral layout of the instance arranged in the layout of the contact circuit based on the layout data D100.

16 is a diagram illustrating an exemplary operation of the instance context extractor 440 of FIG. 16 is a plan view showing a part of the layout of the integrated circuit, and the instance context extractor 440 can generate the context of the instance INV_1 of the inverter INV. That is, the instance INV_1 may be provided to the instance context extractor 440 as an instance selected by the instance selector 420 of FIG.

As described above with reference to Fig. 15, the instance context extractor 440 extracts the context of the instance based on the pattern of the front-end-layer included in the instance and the pattern of the front- can do. 15, the instance context extractor 440 extracts the instance context extractor 440 from the length (DY) of the front-end-layer aligned patterns included in the LLE inducing structure LLE3 related to the instance INV_1, The distance DX in the X direction between the aligned patterns and the pattern of the adjacent front-end-layer can be extracted as the context of the instance INV_1. That is, in the example of FIG. 15, the instance context extractor 440 can extract '3y' and '8x' as the context of the instance INV_1. Accordingly, the instance characterizer 220 of FIG. 11 extracts the context data D150 including the LLE data D330 including the table of FIG. 14 and the context data D150 including the context of the instance INV_1, Time can be '3.06%' degraded (ie, '3.06%' extended).

17 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure; Specifically, FIG. 17 shows a method of generating layout of an integrated circuit in consideration of a local layout effect, and the method shown in FIG. 17 can be performed by the implementation group 100 of FIG. As shown in FIG. 17, a method for designing an integrated circuit may include a plurality of steps S120, S140, S160.

In step S120, an operation of placing first instances of pre-arranged cells may be performed such that the occurrence of the LLE inducing structure by the second instances of logic cells is reduced. For example, the LLE inducing structure may include front-end-layer patterns, and the occurrence of the LLE inducing structure may be reduced by patterns of the front-end-layer included in the second instances, Can be pre-arranged. The first instances may be defined in the input data D010 as instances of the pre-configured cell or added by rule D320. In addition, the LLE rule D322 included in the design rule D320 may include information on the LLE trigger structure, and the first instances are arranged such that the occurrence of the LLE trigger structure is reduced based on the LLE rule D322 .

In step S140, an operation of arranging the second instances in the area where the first instances are not disposed may be performed. The second instances may start to be placed adjacent to the first instances already arranged to comply with design rule D320 as instances of the logical cell. Due to the placement of the first instances by step S120, the occurrence of the LLE inducing structure by the second instances may be reduced.

In step S160, an operation of routing connections of the first and second instances may be performed. For example, interconnections may be created to connect the first and second instances, and layout data D100 including physical information about interconnections and information about the placement of the first and second instances may be generated .

Figure 18 is a flow chart illustrating an example of step S120 of Figure 17 in accordance with an exemplary embodiment of the present disclosure. As described above with reference to FIG. 17, in step S120, the operation of placing the first instances of pre-arranged cells may be performed such that the occurrence of the LLE inducing structure by the second instances of logic cells is reduced. 18 illustrates an example in which step S120 includes both steps S122 and S124, but step S120 may include only one of the two steps, and two steps S122 and S124 may be performed in parallel May be performed either sequentially or sequentially.

In step S122, an operation may be performed to arrange that the edges of the first instances are not aligned. For example, as described above with reference to Figures 5 and 6, the first instances may be arranged so that the edges of the first instances closest to each other are not aligned. Thus, the LLE inducing structure by the second instances including the pattern of the front-end-layer formed at the edge can be reduced.

In step S124, an operation of alternately arranging instances of dummy cells having different widths may be performed. For example, as described above with reference to FIG. 7, a pre-positioned cell may include a multi-height cell disposed in a series of rows, and an instance corresponding to a multi-height cell may include an edge perpendicular to the series of rows Lt; / RTI > Also, as described above with reference to Fig. 8, due to design rule D320, a plurality of instances of pre-layout cells may be arranged and arranged such that an edge of the first instances perpendicular to the series of rows . Instances of dummy cells having different widths adjacent to the edges of at least one first instance perpendicular to the series of rows are alternately arranged so that the second instances including the pattern of the front- Induced LLE induction can be reduced.

19 is a flow diagram illustrating a method for moving an instance to remove an LLE triggered structure in accordance with an exemplary embodiment of the present disclosure. According to an exemplary embodiment of the present disclosure, steps S182 and S184 shown in FIG. 19 may be included in step S140 of FIG. 17 and may be performed after step S160 of FIG. 17 is performed .

In step S182, an operation of detecting the LLE induced structure may be performed. That is, the LLE rule D322 included in the design rule D320 may include information on the LLE induction structure and may include information on instances (e.g., in steps S120 and S140 of FIG. 17, Lt; RTI ID = 0.0 > and / or < / RTI > deployed first and second instances). For example, the LLE rule D322 may define patterns of the front-end-layer aligned over a certain length as the LLE inducing structure, and the front-end-layer arrangements aligned over a certain length based on such LLE rule D322, The patterns of the layer can be detected.

In step S184, an operation of moving at least one instance related to the LLE inducing structure may be performed. That is, to remove the detected LLE inducing structure, at least one of the instances (e.g., the first and second instances of FIG. 17) associated with the patterns of the front-end-layer included in the LLE inducing structure . For example, one instance may be moved in one row, as shown in FIG. 10A, or two or more instances in a row, as shown in FIG. 10B.

20 is a flow diagram illustrating a method of designing an integrated circuit in accordance with an exemplary embodiment of the present disclosure; Specifically, Fig. 20 shows a method for analyzing the performance of an integrated circuit in consideration of the local layout effect. As shown in Fig. 20, the method includes a plurality of steps S220, S240, S260, S280 .

In step S220, an operation of calculating the physical characteristics of the instance based on the LLE data D330 and the context data D150 may be performed. The physical properties of an instance may refer to physical properties that have changed or remained due to local layout effects caused by the peripheral layout (i.e., context) of the instance, from the intrinsic physical properties of the standard cell corresponding to the instance. The LLE data D330 may include information about variations of the physical characteristics of the standard cell corresponding to the various contexts and the context data D150 may include information about the context of the instance extracted from the layout data D100 . ≪ / RTI > As shown in Fig. 20, the LLE data D330 and the context data D150 can be generated by steps S260 and S280, respectively.

In step S240, an operation of analyzing the performance of the integrated circuit based on the physical characteristics of the instance may be performed. For example, the netlist of the integrated circuit can be extracted from the layout data D100 based on the cell library D310 and the physical characteristics of the calculated instance, and the extracted netlist can be extracted from actual And may include information about elements (e.g., resistors and / or capacitors) for reflecting operation. The performance of the integrated circuit, such as timing characteristics, power characteristics, noise characteristics, etc., can be analyzed based on the extracted netlist, and result data D200 including information on the performance of the integrated circuit can be generated.

In step S260, an operation of generating LLE data D330 from the cell library D310 may be performed. Step S260 may be performed before steps S220 and S240 are performed, and step S260 may include steps S262 and S264.

In step S262, an operation of generating a plurality of contexts of the standard cell may be performed. For example, as described above with reference to FIG. 13A, by arranging different standard cells included in the cell library D310 around the standard cell, for example, the same or different standard cells, a plurality of contexts of the standard cell Lt; / RTI > In addition, as described above with reference to FIG. 13B, a plurality of contexts of the standard cell can be generated by arranging patterns of various shapes formed in the front-end-layer around the standard cell.

In step S264, the physical characteristics of the standard cell corresponding to the plurality of contexts may be calculated. For example, the cell library D310 may include a characteristic function of a standard cell, and parameters of a characteristic function corresponding to each of the contexts may be determined. Accordingly, a plurality of physical characteristics according to a plurality of contexts can be calculated for one standard cell, and LLE data D330 including information about such physical characteristics can be generated. For example, the LLE data D330 may generate LLE data D330 that includes the difference or ratio between the value of the characteristic function by the intrinsic parameter of the standard cell and the value of the characteristic function by the parameter determined by the context .

In step S280, an operation of generating the context data D150 from the layout data D100 may be performed. Step S280 may be performed before steps S220 and S240 are performed, and step S280 may include steps S282 and S284.

In step S282, an operation of selecting instances to create a context may be performed. In other words, all or a part of the instances included in the integrated circuit can be selected by referring to the input data D010 or the layout data D100. For example, instances included in the critical path of the integrated circuit may be selected, and instances included in the clock tree may be selected.

In step S284, an operation of extracting the contexts of the selected instances may be performed. That is, in step S282, context data D150 including information on the peripheral layout of the selected instances (i.e., context) may be generated from the layout data D100. For example, the context of the selected instance may be extracted based on the pattern of the front-end-layer included in the selected instance and the pattern of the front-end-layer included in the selected instance surrounding layout.

As described above, exemplary embodiments have been disclosed in the drawings and specification. Although the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for the purpose of describing the technical idea of the present disclosure and not for limiting the scope of the present disclosure as defined in the claims . Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

Claims (20)

CLAIMS What is claimed is: 1. A computing system for designing an integrated circuit comprising instances of standard cells,
A memory for storing information including procedures; And
A processor accessible to the memory and executing the procedures,
The procedures include:
Arranges first instances of pre-arranged cells such that the occurrence of a local layout effect (LLE) inducing structure by placement of second instances of logical cells is reduced;
An instance deployer for deploying the second instances in an area where the first instances are not disposed; And
And a router for generating layout data of the integrated circuit by routing connections of the first and second instances disposed therein. The method according to claim 1,
Wherein the pre-arranged cells comprise at least one of a well-edge cell, a well-bias cell and a decap cell. The method according to claim 1,
Wherein the LLE inducing structure is formed by front-end-layer patterns included in two or more adjacent second instances. The method of claim 3,
Wherein the first and second instances are arranged on a plurality of equally spaced parallel rows,
Wherein the predeployer places the first instances so that the patterns of the front-end-layer included in the second instances are not aligned in a direction perpendicular to the plurality of rows. The method of claim 4,
Wherein the predeployer places the first instances such that the edges of the first instances closest to each other are not aligned in a direction perpendicular to the plurality of rows. The method of claim 4,
The first instances comprising at least one first instance forming an edge perpendicular to a series of rows of the plurality of rows,
Wherein the pre-arranger alternately places instances of two or more dummy cells having different widths adjacent edges perpendicular to the series of rows. The method of claim 6,
The edge perpendicular to the series of rows is formed by a first instance of a pre-arranged cell that is a multi-height cell or two or more first instances adjacent to each other aligned in a direction perpendicular to the rows Lt; / RTI > The method according to claim 1,
The procedures comprising: detecting the LLE triggering structure in a layout in which the first and second instances are located; and detecting at least one first or second instance of the first and second instances associated with the LLE triggering structure And removing the LLE-induced structure by moving the LLE-induced structure. CLAIMS What is claimed is: 1. A computing system for designing an integrated circuit comprising instances of standard cells,
A memory for storing information including procedures; And
A processor accessible to the memory and executing the procedures,
The procedures include:
Refers to LLE (Local Layout Effect) data including information about the physical characteristics of standard cells that depend on the peripheral layout, and includes the context of the deployed instance regarding the peripheral layout of the instance disposed in the integrated circuit An instance characterizer for calculating a physical property of the deployed instance based on the context data; And
And a performance analyzer for generating result data including performance information of the integrated circuit based on the calculated physical characteristics of the deployed instance. The method of claim 9,
The LLE data may include information on physical characteristics of the standard cell dependent on a pattern formed on at least one front-end-layer included in the layout of the standard cell and the peripheral layout of the standard cell Lt; / RTI >
Wherein the context of the deployed instance comprises information about a pattern formed in at least one front-end-layer included in a peripheral layout of the deployed instance. The method of claim 9,
The procedures further comprise an LLE data generator for generating the LLE data,
Wherein the LLE data generator comprises:
A cell context generator for generating a plurality of contexts of the first standard cell by arranging various layouts around the layout of the first standard cell; And
And an LLE estimator for generating the LLE data by calculating physical characteristics of the first standard cell corresponding to the plurality of contexts, respectively. The method of claim 11,
Wherein the cell context generator generates the plurality of contexts by placing a layout of at least one standard cell included in the cell library around the layout of the first standard cell. The method of claim 11,
Wherein the cell context generator generates the plurality of contexts by arranging patterns of different shapes formed in at least one layer affecting the physical characteristics of the first standard cell, around the layout of the first standard cell Lt; / RTI > The method of claim 11,
Wherein the LLE estimator determines parameters of a characteristic function of the first standard cell corresponding to the plurality of contexts. 15. The method of claim 14,
Wherein the LLE estimator comprises generating the LLE data comprising ratios or differences between values of the characteristic function by the determined parameters and the value of the characteristic function by intrinsic parameters of the first standard cell A computing system characterized by. The method of claim 9,
Wherein the procedures are executed by extracting the context of the deployed instance based on a first pattern included in the layout of the deployed instance and a second pattern included in a peripheral layout of the deployed instance, Further comprising a context extractor. 18. The method of claim 16,
Wherein the first and second patterns are each formed in one of the front-end-layers in the layout of the integrated circuit. 18. The method of claim 16,
Wherein the instance context extractor extracts at least one of a distance between the first and second patterns, an arrangement of the first and second patterns, a length, and an area as a context of the disposed instance. The method of claim 9,
Wherein the procedure further comprises an instance selector for providing an instance characterizer with instances included in the critical path of the integrated circuit among the instances included in the integrated circuit,
Wherein the performance analyzer generates the result data including the timing information of the critical path. The method of claim 9,
Wherein the result data comprises information about at least one of timing, noise and power of the integrated circuit.

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