KR20180013629A - Multi-layered magnetic thin film stack and data storage device having the same - Google Patents

Abstract

The present invention relates to a multi-layered magnetic thin film stack with improved element reliability, and a data storage device having the same. According to an embodiment of the present invention, the electronic device comprises: a tunneling barrier layer including a metal oxide layer as an information storage element; a magnetic fixed layer on a first surface of the tunneling barrier layer; and a magnetic free layer on a second surface opposite to the first surface of the tunneling barrier layer. At least one of the magnetic fixed layer and the magnetic free layer includes a double magnetic layer structure including: an Fe layer having a first surface being in contact with the metal oxide layer; and a Co layer being in contact with a second surface opposite to the first surface of the Fe layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-layer magnetic thin film stack and a data storage device including the multi-

The present invention relates to a magnetic structure, and more particularly, to a multi-layer magnetic thin film stack and a data storage device including the same.

A magnetic random access memory (MRAM or MRAM) is a nonvolatile magnetic memory device that utilizes a giant magnetoresistance effect or a tunneling magnetoresistance effect based on a spin-dependent conduction phenomenon peculiar to a nano-magnetic material. The MRAM is faster than the phase-change memory (PcRAM) or the resistive memory (ReRAM), which is another non-volatile memory device, and has excellent durability against repeated use, and has recently attracted attention as a next generation memory.

In order to realize the MRAM device, spin transfer torque magnetic random access memory (STT-MRAM), which is most actively studied, is regarded as a candidate candidate device of a next generation memory device because of its high speed operation, excellent power efficiency, and high integration. The STT-MRAM generally has a magnetic tunnel junction (MTJ) structure having a structure in which one tunneling barrier layer is interposed between two magnetic thin films. In the MTJ structure, perpendicular magnetic anisotropy (PMA) has a lower switching current density for magnetization inversion than in in-plane magnetic anisotropy, and has a small influence on volume change It is advantageous not only in terms of scale but also in terms of thermal stability since the uniformity between cells is small. Therefore, the implementation of stable PMA is important for the realization of MRAM devices.

In the conventional MTJ structure, a magnetic thin film such as Co, CoFe or NiFe is applied. In the case of the Co, the interfacial anisotropy induced at the interface with the nonmagnetic metal thin film such as platinum or palladium is used to form the multi- However, it is difficult to obtain uniform magnetic characteristics. In the case of CoFe, a large magnetic anisotropy can be obtained at the interface with MgO, but the magnetic moment per unit volume is increased due to the alloying of Co and Fe, thereby increasing the write current. Recently, soft magnetic materials such as CoFeB have been studied to solve this problem. However, due to the decrease of spin polarization due to the addition of boron, loss of tunneling magnetoresistance is lower than that of magnetic thin films such as Co, CoFe and NiFe having a crystal structure Occurs. In addition, at the interface of the MTJ to which the CoFeB magnetic thin film is applied, there is a problem that the surface anisotropic energy decreases due to the addition of boron. This disadvantage leads to a decrease in device reliability when a memory cell is manufactured with a size of several tens nm or less.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer magnetic thin film stack having a large vertical magnetic anisotropy and a reduced write current and improved device erosion.

Another problem to be solved by the present invention is to provide an electronic device that realizes a memory operation with reduced consumption power with reliability from the above-mentioned advantages.

According to an aspect of the present invention, there is provided a multi-layer magnetic thin film stack including: a metal oxide layer; An iron (Fe) layer having a first surface in contact with the metal oxide layer; And a cobalt (Co) layer in contact with a second surface opposite to the first surface of the iron layer. The metal oxide layer has a magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), titanium oxide (TiO _2), aluminum nitride (AlN), ruthenium oxide (RuO _2), strontium oxide (SrO), calcium oxide ( CaO _2), may comprise hafnium oxide (HfO _2), tantalum oxide (Ta ₂ O _5), zirconium oxide (ZrO _2), and silicon oxide one, mixtures thereof, or a layered thin film of the (SiO _2).

On the one surface of the iron layer, a hybrid bonding between the 3d orbit of iron and the 2p orbital of oxygen in the metal oxide layer can be achieved. The iron layer may have a single crystal or polycrystalline crystal structure crystallized so as to have a texture in a Miller index (001) direction or a preferential oriented surface. In addition, the cobalt layer may have a single crystal or polycrystalline crystal structure crystallized so as to have a texture or a preferential oriented surface in a Miller index (001) direction along the iron layer.

The total thickness of the iron layer and the cobalt layer may be in the range of 0.88 nm to 1.14 nm. In one embodiment, the thickness of the iron layer is at least 0.52 nm, and the thickness of the cobalt layer may be at most 0.6 nm. The thickness t ₁ of the iron layer is larger than the thickness t ₂ of the cobalt layer and the thickness of the iron layer with respect to the total thickness t ₁ + t ₂ of the iron layer and the cobalt layer ratio (t1 / (t1 + t2) of t ₁₎₎ can range from less than 0.69.

In one embodiment, the multi-layer magnetic thin film stack may further include a seed layer at the bottom of the cobalt layer. The seed layer may include a layered structure of a sequentially formed tantalum layer / ruthenium layer / tantalum layer.

According to another aspect of the present invention, there is provided an electronic device including a tunneling barrier layer including a metal oxide layer as an information storage element, a magnetoresistance layer on a first surface of the tunneling barrier layer, And a magnetic free layer on a second surface opposite to the first surface of the magnetic tunneling junction.

In one embodiment, at least one of the magnetically fixed layer and the magnetic free layer includes: an iron (Fe) layer having a first surface in contact with the metal oxide layer; And a cobalt (Co) layer in contact with a second surface opposite to the first surface of the iron layer. The metal oxide layer has a magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), titanium oxide (TiO _2), aluminum nitride (AlN), ruthenium oxide (RuO _2), strontium oxide (SrO), calcium oxide ( CaO _2), may comprise hafnium oxide (HfO _2), tantalum oxide (Ta ₂ O _5), zirconium oxide (ZrO _2), and silicon oxide one, mixtures thereof, or a layered thin film of the (SiO _2).

On the one surface of the iron layer, a hybrid bonding between the 3d orbit of iron and the 2p orbital of oxygen in the metal oxide layer can be achieved. The iron layer may have a single crystal or polycrystalline crystal structure crystallized so as to have a texture in a Miller index (001) direction or a preferential oriented surface.

The cobalt layer may have a single crystal or polycrystalline crystal structure crystallized so as to have a texture or a preferential oriented surface in a Miller index (001) direction along the iron layer. The total thickness of the iron layer and the cobalt layer may be in the range of 0.88 nm to 1.14 nm. The thickness of the iron layer may be 0.52 nm or more, and the thickness of the cobalt layer may be 0.6 nm or less.

The thickness of the Fe layer (t ₁₎ is the thickness of the steel layer to the larger, the total thickness (t ₁ + t ₂₎ of said iron layer and the cobalt layer than the thickness (t ₂₎ of the cobalt layer (t ₁ ) (T1 / (t1 + t2)) may be within a range of 0.69 or less. The electronic device may further include a seed layer on the bottom of the cobalt layer. The seed layer may include a layered structure of a sequentially formed tantalum layer / ruthenium layer / tantalum layer.

According to the embodiment of the present invention, the metal oxide layer and the iron layer are directly in contact with each other, and the cobalt layer 21 is further laminated on the iron layer to provide the magnetic layer with a double magnetic layer structure of a layer structure differentiated from each other, It is possible to provide a multilayer magnetic thin film stack in which the surface magnetic anisotropy due to the oxide layer is maximized and an excessive increase in magnetic moment due to alloying of iron and cobalt is suppressed while relaxing bulk anisotropy of iron is suppressed to realize optimum vertical magnetic anisotropy have.

Further, according to another embodiment of the present invention, by using the magnetic tunneling junction including the above-described dual magnetic layer structure, an electronic device can be provided that realizes a memory operation reliably and consumed at a reduced power.

1 is a block diagram of a magnetic memory device according to an embodiment of the present invention.
2 is a circuit diagram of a memory cell array of a magnetic memory device according to an embodiment of the present invention.
Figures 3a and 3b are cross-sectional views illustrating a multilayer magnetic thin film stack according to various embodiments of the present invention.
4A and 4B are cross-sectional views showing the structure of memory cells of a non-volatile memory device according to various embodiments of the present invention.
5 is a graph showing the magnetic properties of a double magnetic layer structure (20 in FIG. 1, Fe layer (thickness t1 = 0.65 nm) / Co layer (thickness t2 = 0.36 nm)) according to an embodiment of the present invention admit.
6 is a graph showing the relationship between the total thickness t1 + t2 and the total thickness t1 + t2 of the double magnetic layer structure (iron layer (thickness t1) / Co layer (thickness t2) (T1 / (t1 + t2)) of the thickness (t1) of the iron layer with respect to the thickness (t1)
FIG. 7 is a graph illustrating MH loop changes according to an annealing temperature of a dual magnetic layer structure according to an embodiment of the present invention. FIG.
8A and 8B are graphs showing changes in magnetic anisotropy energy and surface magnetic anisotropy energy according to the thickness of a double magnetic layer structure in an embodiment of the present invention, respectively.
9 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.
10 is a block diagram illustrating an information storage device including a solid-state disk according to an embodiment of the present invention.
11 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.
12 is a block diagram illustrating a data storage device according to another embodiment of the present invention.
13 is a block diagram illustrating a magnetic memory device and a computing system including the same according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings, the thickness and size of each layer are exaggerated for convenience and clarity of description, and the same reference numerals refer to the same elements in the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. It is self-evident. These terms are only used to distinguish one member, component, region or portion from another region or portion. Accordingly, the first member, component, region or portion described below may refer to a second member, component, region or portion without departing from the teachings of the present invention.

Further, in the case where some layers are formed or arranged on another layer, an intermediate layer may be formed or arranged between these layers. Similarly, even if some materials are adjacent to another material, there may be an intermediate material between these materials. Conversely, when a layer or material is referred to as being "directly" or "directly" formed or disposed on another layer or material, or "directly" It should be understood that there is no intermediate material or layer between the layers.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing ideal embodiments of the present invention. In the drawings, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein.

As used herein, the term "substrate" is not limited to a bulk based substrate such as silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), but may be a layered structure, a doped or undoped layered structure, It may be a strained layer structure. Further, the "substrate" is not limited to a semiconductor material but may also be referred to as a non-semiconductor layer. The term semiconductor is not limited to a silicon-based material but may be a III-V semiconductor material such as carbon-based, polymer or silicon-germanium, germanium and gallium-gallium-based compound materials, a II- Material, and refers to a multi-component material of two-component system or higher without limitation. Similarly, the term non-semiconductor may also refer to an insulating ceramic material, a metal material, or a polymer material, and is not limited to these examples.

The magnetic memory element of the following disclosure may have different layers. Magnetic tunneling junctions typically include a magnetic tunneling barrier layer sandwiched between a magnetically pinned layer and a magnetic free layer. The magnetic finned layer may be referred to as a reference layer, a hard magnetic layer or a magnetic fixed layer, and a magnetic free layer may be referred to as an information storage layer information storage layer, which may be referred to as a magnetic pinning layer or a soft magnetic layer.

1 is a block diagram of a magnetic memory device according to an embodiment of the present invention.

1, a magnetic memory device may include a memory cell array 1, a row decoder 2, a column selection circuit 3, a read / write circuit 4, and a control logic 5. The memory cell array 1 includes a plurality of word lines and a plurality of bit lines, and the memory cells may be coupled to the points where the word lines and the bit lines intersect. The configuration of the memory cell array 1 will be described later in detail with reference to FIG.

The row decoder 2 may be connected to the memory cell array 1 via the word lines. The row decoder 2 may decode an externally input address to select one of a plurality of word lines. The column selection circuit 3 is connected to the memory cell array 1 through bit lines and can decode an address input from the outside to select one of a plurality of bit lines. The bit line selected in the column selection circuit 3 may be connected to the read / write circuit 4.

The read / write circuit 4 may apply a bias signal to the bit line to access the selected memory cell under the control of the control logic 5. [ For example, the read / write circuit 4 may apply the bit line voltage to the selected bit line to write or read the input data to the memory cell.

The control logic 5 may output control signals for controlling the magnetic memory sound according to a command signal received from an external circuit. The control signals output from the control logic 5 can control the read / write circuit 4. [

2 is a circuit diagram of a memory cell array 1 of a magnetic memory device according to an embodiment of the present invention.

Referring to FIG. 2, the memory cell array 1 may include a plurality of first conductive lines, second conductive lines, and memory cells MC. The first conductive lines may be word lines (WL), and the second conductive lines may be bit lines (BL). The memory cells MC can be arranged two-dimensionally or three-dimensionally. The memory cells MC may be connected between the word lines WL and the bit lines BL, which intersect each other. Each of the word lines WL may connect a plurality of unit memory cells MC. Each of the bit lines BL may be connected to each of the memory cells MC connected by one word line WL. Thus, each of the memory cells MC connected by one word line WL can be connected to the read / write circuit 4, described with reference to Fig. 1, by each of the bit lines BL .

Each of the memory cells MC may include a memory element ME and a selection element SE. The memory cell ME may be connected between the bit line BL and the selection device SE and the selection device SE may be connected between the memory cell ME and the word line WL. The memory element ME can operate as a variable resistive element which can be switched into two resistance states by an applied electrical pulse.

According to one embodiment, the memory cells ME may be formed with a multi-layer magnetic thin film stack whose electrical resistance can be varied using a spin transfer process by an electric current passing through each memory cell. The unit memory cell ME exhibits a magnetoresistance characteristic. The memory cells ME may comprise at least one ferromagnetic material and / or at least one antiferromagnetic material.

The selection element SE may be configured to selectively control the flow of charge through the memory cell ME. For example, the selection element SE may be a transistor. In this case, a memory cell of a 1TR-1 MTJ configuration can be provided. The gate of the transistor TR may be electrically coupled to the first wiring, for example, a word line. The other end of the memory cell ME may be connected to the bit line. The transistor is a non-limiting example of a selection device and may be a field effect transistor or a bipolar transistor. In another embodiment, the selection element SE may comprise a PN junction diode DI. Or any other diode capable of obtaining cell selectivity in accordance with the potential difference between the word line WL and the bit line BL in place of or in addition to the diode, Directional rectification characteristics for the two-way rectifier.

For the selection element SE, various selection elements for providing cell selectivity can be applied for high capacity of memory elements, improvement of ON current, or multi-bit driving, and the present invention is not limited thereto. For example, the cell selectivity or other selectivity of the magnetic memory cell itself using an Ovonic switching effect, a quantum effect, or a nanoscale phenomenon that replaces or replaces the transistor or diode-based switching device described above, The selection device itself may be omitted.

Figures 3A and 3B are cross-sectional views illustrating a multi-layer magnetic thin film stack 50A, 50B according to various embodiments of the present invention.

3A, a multilayer magnetic thin film stack 50A includes a cobalt (Co) layer 21 formed on a substrate 10, an iron (Fe) layer 22 on a cobalt layer 21, and an iron layer 22 ) Of a metal oxide layer (30). The cobalt layer 21 and the iron layer 22 form a double magnetic layer structure 20 in which no other layers are interposed therebetween and are magnetically coupled to each other.

The metal oxide layer 30 is a magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), titanium oxide (TiO _2), ruthenium oxide (RuO _2), strontium oxide (SrO), calcium oxide (CaO _2), hafnium (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), and silicon oxide (SiO ₂ ), a mixture thereof, or a laminated thin film thereof. Preferably, the metal oxide layer 20 may be a magnesium oxide layer that allows a strong (001) surface to be formed on the underlying iron layer 22 with strong surface magnetic anisotropy. The magnesium oxide layer may have a monocrystalline or polycrystalline crystal structure having a textured or preferential oriented surface in the Miller index (001) direction with respect to the underlying iron layer 22.

The iron layer 22 is a layer having a first surface 22S1 in contact with the metal oxide layer 30. [ At least the first surface 22S1 of the iron layer 22 comprises pure iron and at the first surface 22S1 a hybrid bonding is made between the 3d orbitals of iron and the 2p orbital of oxygen in the metal oxide layer 30 . Since the hybrid coupling is performed only between iron and oxygen and there is no other impurity intervening material, the surface anisotropy energy between the iron layer 22 and the metal oxide layer 30 induced by the hybrid coupling can be maximized. In general, the surface anisotropy energy induced between the MgO layer / Fe layer is theoretically about 1.6 times larger than the surface anisotropic energy induced between the MgO layer / Co layer, so that when applied to the MTJ structure, cobalt (Co) Fe) and a higher PMA due to a larger surface anisotropy energy than the mixed MgO layer / CoFe layer or MgO layer / CoFeB layer.

According to an embodiment of the present invention, the cobalt layer 21 is disposed on the second surface 22S2 of the base opposite to the first surface 22S1 of the iron layer 22 in contact with the metal oxide layer 30, As such, the multilayer magnetic thin film stack has a coarse layer layer 21 and a double magnetic layer structure 20 of a ferrous layer 22. When a magnetic layer is formed only of the iron layer 22, it is difficult to realize the PMA because of the large bulk anisotropy of iron, and may cause an increase in write current due to high saturation magnetization (Ms). However, according to the embodiment of the present invention, since the magnetic layer has the double magnetic layer structure 20 divided into the iron layer 22 and the cobalt layer 21, the alloying due to the mixing among these metals is suppressed And an excessive increase in magnetic moment due to alloying of iron and cobalt can be suppressed. As a result, the dual magnetic layer structure 20 according to the embodiment of the present invention can realize an optimal vertical magnetic anisotropy while at the same time reducing the energy for magnetic switching of the dual magnetic layer structure to realize a low power nonvolatile memory device have.

The total thickness of the dual magnetic layer structure 20 can be limited since the perpendicular magnetization characteristics of the dual magnetic layer structure 20 according to embodiments of the present invention are due to the interfacial effect. In one embodiment, the total sum of the thickness tl of the iron layer 22 and the thickness t2 of the cobalt layer 21 may be in the range of 0.88 nm to 1.14 nm. When the thickness of the double magnetic layer structure 20 is more than 1.14, the magnetization direction is changed to a direction parallel to the plane due to the manifestation of bulk anisotropy. In addition, when the thickness of the double magnetic layer structure 20 is less than 0.88 nm, formation of a continuous magnetic layer may be difficult.

In one embodiment, the thickness t1 of the iron layer 22 may be greater than or equal to 0.52 nm and the thickness t2 of the cobalt layer 21 may be less than or equal to 0.6 nm. When the thickness of the iron layer 22 is less than 0.52 nm, the iron layer 22 is too thin and it is difficult to obtain a stable interface between the iron layer 22 and the metal oxide layer 30. As a result, It is difficult to obtain magnetic anisotropy. Even when the thickness t2 of the cobalt layer 21 exceeds 0.6 nm, the thickness of the double magnetic layer structure 20 increases and the thickness of the iron layer 22 relatively decreases, thereby making it difficult to obtain perpendicular magnetic anisotropy. In one embodiment, the thickness t ₁ of the iron layer 22 is greater than the thickness t ₂ of the cobalt layer 21 and is greater than the thickness t ₁ + t ₂ of the dual magnetic layer structure 20 0.69 or less. The iron layer 22 and the cobalt layer 21 are separated from each other so that the iron layer 22 and the metal oxide 22 are separated from each other by a value similar to the composition ratio for the perpendicular anisotropy implementation of the conventional CoFe alloy magnetic thin film, Thereby forming only the interface of the layer 30. It is also possible to improve the vertical magnetization characteristics of a given dual magnetic layer structure 20 by independently manifesting the excellent magnetic function of each of the cobalt layer 21 and the iron layer 22 through the embodiment and changing the thickness of each layer .

Referring to FIG. 3B, the multi-layer magnetic thin film stack 50B may further include a seed layer 15 for uniform growth of the dual magnetic layer structure 20 on the substrate 10. The seed layer 15 may comprise a gold layer, a copper layer, a palladium layer, a platinum layer, a ruthenium layer, a tantalum layer, or a multilayer stack of two or more thereof. The seed layer 15 as the multi-layer laminate is a simple laminate of a monolayer of a first metal and a monolayer of a second metal and a second metal or a superlattice structure formed by alternating the metal layers . The thickness of the seed layer 15 may be in the range of 0.2 nm to 10 nm, but the present invention is not limited thereto. In one embodiment, the seed layer 15 may comprise a tantalum layer 11 / ruthenium layer 12 / tantalum layer 13 formed sequentially on a substrate 10. The seed layer of the triple structure can help crystallization in the Miller index (001) direction of the double magnetic layer structure.

The multilayer magnetic thin film stack 100B may further include a protective layer 40 on the metal oxide layer 30. [ The protective layer 40 may be formed of any suitable material such as, but not limited to, rhodium (Rh), hafnium (Hf), palladium (Pd), tantalum (Ta), osmium (Os), germanium (Ge), iridium Au), and silver (Ag), or an alloy thereof.

4A and 4B are cross-sectional views illustrating the structure of memory cells 1000A and 1000B of a non-volatile memory device according to various embodiments of the present invention.

Referring to FIG. 4A, a memory cell 1000A according to an embodiment includes a first electrode EL1, for example, a magnetic tunneling junction (not shown) between a lower electrode and a second electrode EL2, for example, 100A). The magnetic tunneling junction 100A includes a tunneling barrier layer 110, a magnetically fixed layer 120 on a first side 110a of the tunneling barrier layer 110, and a second side 110b on the second side 110b of the tunneling barrier layer 110. [ And a self-free layer (130). A unidirectional arrow A indicates that the magnetically fixed layer 120 is fixed and the bi-directional arrow B indicates that the free layer 130 is magnetized parallel to the magnetization direction of the magnetization fixed layer 120 or magnetized antiparallel Which can be reversible. In one embodiment, alteration of the magnetization direction of the magnetically free layer 130 can be accomplished by controlling the direction of the tunneling current with spin torque flowing along the magnetic tunneling junctions (MTJA, MTJB), as a non-limiting example.

A tunneling barrier layer 110, metal oxide layer 30 described with reference to Figure 3a, for example, magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), titanium oxide (TiO _2), ruthenium oxide ( RuO _2), any one of strontium oxide (SrO), calcium oxide (CaO _2), hafnium oxide (HfO _2), tantalum oxide (Ta ₂ O _5), zirconium oxide (ZrO _2), and silicon oxide (SiO ₂₎ , A mixture thereof, or a laminated thin film in which two or more layers are laminated. Preferably, the tunneling barrier layer 110 may be a NaCl-type magnesium oxide layer that allows a (001) surface with strong surface magnetic anisotropy to be formed in the adjacent iron layer 132. The magnesium oxide layer may have a single crystal or polycrystalline crystal structure having a texture in a Miller index (001) direction or a preferential oriented surface.

The magnetically fixed layer 120 may comprise a suitable ferromagnetic layer. The Fe-Pd alloy, the Co-Pd alloy, the Co-Pt alloy, the Fe-Ni-Pt alloy or the Fe-Ni-Pt alloy may be used as the ferromagnetic material layer. Alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, or a Co-Fe alloy. These alloys are merely illustrative and the present invention is not limited thereto. For example, in addition to the main components, zirconium (Zr), rhodium (Rh), hafnium (Hf), tantalum (Ta), osmium (Os), germanium (Ge), iridium (Ir) , Silicon (Si), or silver (Ag) may be added and alloyed, or an alloy such as CoFeB doped with an impurity such as boron may be used. Further, the ferromagnetic layer may be a complex compound of the above-described materials, and is not limited to a single layer, and may have a laminated structure of two or more layers.

In another embodiment, the magnetostatic layer 120 may comprise a stack of different types of magnetic layers, for example, a stack of a ferromagnetic layer or an antiferromagnetic layer, or a laminate of a magnetic layer and a non-magnetic layer. The antiferromagnetic material may include any one or two or more of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2 and NiO. The non-magnetic material may be at least one selected from the group consisting of Zr, Rh, Hf, Ta, Os, Ge, Ir, Silver (Ag). These materials are not intended to limit the present invention. The magnetic pinned layer 120 is a synthetic ferrimagnetic layer having a large magnetic tunnel resistance effect and improved thermal stability by interlayer-exchange coupling the first magnetic layer and the second magnetic layer of different kinds, ferri-magnetic layer or a synthetic anti-ferro-magnetic layer. In particular, the implementation of the synthetic ferrimagnetic layer is desirable for low power and ultra-high integration of spin-transfer switching of memory devices using magnetic tunneling junctions.

The magnetic free layer 230 may have a double magnetic layer structure including an iron layer 132 and a cobalt layer 131. The iron layer 132 includes a first surface 132S1 in which the tunneling barrier layer 110 is in direct contact with only pure iron elements and a cobalt layer 131 is formed on the second surface 132S2 of the iron layer 132. [ . Hybrid bonding is formed on the first surface 132S1 of the iron layer 132 by heat treatment between the iron 3d orbitals and the 2p orbital of oxygen in the tunneling barrier layer 110. [ Since the hybrid bonding is performed only between iron and oxygen, and there is no other impurity intervening material, the surface anisotropic energy between the iron layer 22 and the metal oxide layer 30 induced by the hybrid coupling can be maximized.

The cobalt layer 131 provides a dual magnetic layer structure divided into a cobalt layer 131 while reducing the thickness of the iron layer 132. The dual magnetic layer structure suppresses and minimizes alloying by mixing between iron and cobalt, thereby suppressing excessive increase of magnetic moment due to alloying of iron and cobalt. As a result, the magnetic free layer 230 having the double magnetic layer structure according to the embodiment of the present invention can realize the optimum vertical magnetic anisotropy while at the same time reducing the energy for magnetic switching of the magnetic free layer 230, A nonvolatile memory device can be implemented.

The total sum of the thickness t1 of the iron layer 132 and the thickness t2 of the cobalt layer 131 is 0.88 or more as described above in order to improve the perpendicular magnetization characteristics due to the interfacial effect of the magnetic free layer 130, nm to 1.14 nm. Further, in one embodiment, the thickness t1 of the iron layer 132 may be 0.52 nm or more, the thickness t2 of the cobalt layer 131 may be 0.6 nm or less, and the stable interface and perpendicular magnetic anisotropy Can be obtained. The thickness t ₁ of the iron layer 132 is larger than the thickness t ₂ of the cobalt layer 131 and may be within a range of 0.69 or less of the thickness t ₁ + t ₂ of the double layer.

In one embodiment, although not shown, a seed layer (see 15 in FIG. 3B) may be further formed between the cobalt layer 131 and the second electrode EL2. The seed layer can be a single layer of metal, or a multi-layer laminate of different metals, as described with reference to Figure 3B. Further, the multi-layer laminate may have a superlattice structure. In one embodiment, the seed layer itself may be used as the second electrode EL2.

In another embodiment, a protective layer (see 40 in FIG. 1B) may be further formed between the cobalt layer 131 and the second electrode EL2. In one embodiment, the second electrode EL2 may be provided by the protective layer.

In another embodiment, although not shown, another tunneling barrier layer and a magnetoresistive layer may be additionally stacked on the magnetic free layer 130 to form a symmetrical magnetic tunneling structure with two self- A junction may be provided. In this symmetric magnetic tunnel junction, the direction of the current for programming and erasing can be unidirectional.

4B, the memory cell 1000B includes a first electrode EL1, for example, a lower electrode and a second electrode EL2, for example, a first electrode EL1, And a magnetic tunneling junction 100B between the upper electrodes. The magnetic tunneling junction 100B includes a tunneling barrier layer 110, a magnetization pinned layer 120 on the first side 110a of the tunneling barrier layer 110, and a second pinned layer on the second side 110b of the tunneling barrier layer 110. [ And a self-free layer (130). The unidirectional arrow A indicates that the magnetostatic layer 12 is fixed in the vertical direction and the bi-directional arrow B indicates that the magnetic free layer 130 can be magnetized in parallel in the vertical direction or magnetized in antiparallel And has a reversible magnetic state.

The magnetic pinned layer 120 may have a double magnetic layer structure including an iron layer 122 and a cobalt layer 121. The iron layer 122 includes a first surface 122S1 in which the tunneling barrier layer 110 is in direct contact with only the pure iron element and an entire iron layer 122 is formed on the second surface 122S2 of the iron layer 122. [ The cobalt layer 121 is formed. Hybrid bonding is formed on the first surface 122S1 of the iron layer 122 by heat treatment between the 3d orbit of iron and the 2p orbital of oxygen in the tunneling barrier layer 110 as described above. A magnetically fixed layer 120 perpendicularly magnetized by the double magnetic layer structure of the iron layer 122 and the cobalt layer 131 may be provided.

The total sum of the thickness t1 of the iron layer 132 and the thickness t2 of the cobalt layer 131 is 0.88 nm or less as described above in order to improve the perpendicular magnetization characteristics due to the interface effect of the magnetostatic layer 130, To 1.14 nm. ≪ / RTI > Further, in one embodiment, the thickness t1 of the iron layer 132 may be 0.52 nm or more, and the thickness t2 of the cobalt layer 131 may be 0.6 nm or less. The thickness t ₁ of the iron layer 132 is larger than the thickness t ₂ of the cobalt layer 131 and may be within a range of 0.69 or less of the thickness t ₁ + t ₂ of the double layer.

Although not shown, a seed layer (see 15 in FIG. 1B) or a protective layer may be further formed between the cobalt layer 121 and the first electrode EL1. In another example, to implement the magnetostatic layer 120, a synthetic ferri-magnetic layer or a synthetic anti-ferro-magnetic layer may be provided through magnetic coupling with the dual magnetic layer structure A non-magnetic layer or a laminated structure 140 thereof. In one embodiment, the first electrode EL1 may sandwich the seed layer, the protective layer, or the magnetic layer or a part of the antiferromagnetic layer described above, but the present invention is not limited thereto.

The memory cells 1000A and 1000B according to the embodiment of the present invention are information storage members and can constitute unit storage nodes of non-volatile magnetic memory devices. A selection element, for example, a diode DI or a transistor TR for selecting a memory cell is coupled to one end of the magnetic tunneling junctions 100A and 100B of the memory cells 1000A and 1000B, And 1TR-1 MTJ structures may be provided. One end of the memory cells 1000A and 1000B may be electrically coupled to the first wiring, for example, the word line WL through the selection elements DI and TR. The other end of the memory cells 1000A, 1000B may be connected to, for example, the bit line BL. The above-described selection elements DI and TR are non-limiting examples of selection elements, and any diode and transistor capable of obtaining cell selectivity can be applied. As another example, the above-mentioned selection device can be applied to various known switching devices using an Ovonic effect, a quantum effect, or a nano-sized phenomenon. In another embodiment, the selection device itself may be omitted by securing cell selectivity by the cell selectivity of the magnetic tunneling junctions 100A, 100B itself or by other circuit elements, and the present invention is not limited thereto.

4A and 4B, a change in the magnetization direction of the magnetic free layer 120 is achieved by controlling the direction of the tunneling current with the spin torque flowing along the magnetic tunneling junctions 100A and 100B . 4A and 4B, a double magnetic layer structure of an iron layer and a cobalt layer is applied as a part or all of the magnetically fixed layer 120 or the magnetic free layer 130. However, The double magnetic layer structure according to the embodiment of the present invention can be applied to the magnetic free layer. In addition, the positions of the magnetically fixed layer 120 and the free layer 130 may be reversed with respect to each other with the tunneling barrier layer 110 therebetween. 4A and 4B, a magnetic free layer may be formed on the first surface 110a of the tunneling barrier layer 110, and a magnetization pinning layer may be formed on the second surface 110b , A double magnetic layer structure may be applied to at least one of the magnetic free layer and the magnetic pinned layer.

The magnetic pinned layer and the magnetic free layer to which the double magnetic layer structure according to the embodiment of the present invention is applied have perpendicular magnetic anisotropy. Hereinafter, the magnetic and crystallographic characteristics of a dual magnetic layer structure according to an embodiment of the present invention will be described.

Experimental Example

In order to evaluate the PMA characteristics of the double magnetic layer structure of the iron / cobalt layer according to the embodiment of the present invention, a multilayer magnetic thin film stack as shown in FIG. 3B was fabricated. The substrate 10 is a silicon bulk substrate, and an amorphous silicon oxide insulating film is formed on the surface of the silicon bulk substrate. The formation of the metal film and the magnetic film is formed through high vacuum sputtering, but this is only an exemplification and the present invention is not limited thereto.

A seed layer 15 made of a triple-metal layer of Ta / Ru / Ta was formed on the silicon oxide insulating film of the substrate 10. A cobalt layer 21 and an iron layer 22 were sequentially formed on the seed layer 15 to form a double magnetic layer structure 20. [ The cobalt layer 21 was formed to have a thickness within a range of about 0.36 nm to 0.6 nm and the iron layer 22 was formed to have a thickness within a range of 0.36 nm to 0.91 nm.

Thereafter, a MgO film 30 having a thickness of about 2 nm was formed as a tunneling barrier layer 30 on the dual magnetic layer structure 20 as a non-limiting example. On the MgO film 30, a Ta layer 40 was formed as a protective layer. The thickness of the Ta layer 40 is about 6 nm as a non-limiting example. After all the layers were formed, a heat treatment process was performed at about 250 to 300 ° C for about 30 minutes under a magnetic field of about 3T. Since the heat treatment is generally performed by a high temperature process at the subsequent stage such as a wiring process for memory fabrication, the heat treatment is performed at a temperature of about 1 x 10 < ^-6 > Torr or less Lt; / RTI > However, this is only an illustrative example, and the heat treatment temperature and time may be suitably modified according to the thickness or structure of the magnetic layer.

5 is a graph showing the magnetic properties of a double magnetic layer structure (20 in FIG. 1, Fe layer (thickness t1 = 0.65 nm) / Co layer (thickness t2 = 0.36 nm)) according to an embodiment of the present invention admit. Magnetic moment-applied magnetic field (mH ) loop vibrating sample magneto meter at room temperature; using (vibrating sample magnetometer VSM) out-of-plane (out-of-plane, the curve - ○ - Im, H _⊥) and in-plane (in-plane , Curves - - -, H _∥ ) were obtained by evaluating the magnetic properties of each magnetic thin film stack under a magnetic field.

Referring to FIG. 5, it is confirmed that only the vertical magnetic moment (curve -? -), not the horizontal magnetic moment (curve -? -), has a hysteresis characteristic. Accordingly, it can be seen that the double magnetic layer structure according to the embodiment of the present invention has perpendicular magnetic anisotropy. In the perpendicular magnetic anisotropy, the MgO of the tunneling barrier layer is crystallized to the Miller index (001) plane during the heat treatment, and the iron layer in contact with the crystallized MgO is crystallized from the first surface thereof to the (001) plane having strong surface magnetic anisotropy, Thereby inducing perpendicular magnetization anisotropy. In addition, the cobalt layer also follows the perpendicular magnetization anisotropy according to the perpendicular magnetization anisotropy of the iron layer, so that the entire double magnetic layer structure 20 becomes vertical magnetization. At this time, the cobalt layer may be crystallized or not crystallized by preferentially aligning with the Miller index (001) plane like the iron layer.

6 is a graph showing the relationship between the total thickness t1 + t2 and the total thickness t1 + t2 of the double magnetic layer structure (iron layer (thickness t1) / Co layer (thickness t2) (T1 / (t1 + t2)) of the thickness (t1) of the iron layer with respect to the thickness (t1) At this time, a sample whose thickness t1 was varied within the range of 0.36 nm to 0.91 nm and whose thickness t2 was varied within the range of 0.36 nm to 0.60 nm was prepared, and the change of saturation magnetization was measured. Table 1 shows the effective anisotropy field (h _eff ) and direction of anisotropy according to the thickness variation of the Fe layer and the Co layer.

H _eff (mT)
Iron layer 0.52 nm 0.65 nm 0.78 nm 0.91 nm
Cobalt layer
0.36 nm 270
(PMA) 300
(PMA) 100
(PMA) 500
(IMA) 0.48 nm 220
(PMA) 90
(PMA) 150
(IMA) 750
(IMA) 0.60 nm 50
(IMA) 90
(IMA) 400
(IMA) 800
(IMA)

6, when the seed layer thickness is Ta (3 nm) / Ru (3 nm) / Ta (1 nm) and the thickness of the MgO layer as the tunneling barrier layer is fixed to 2 nm , And the total thickness (t1 + t2) of the iron layer / cobalt layer was from 0.88 nm to 1.14 nm to the Miller index (001) plane. Since the perpendicular magnetization characteristics of the iron layer / cobalt layer are due to the interfacial effect, the magnetization direction is changed to the horizontal direction due to the bulk anisotropy, which increases when the thickness (t1 + t2) exceeds 1.14 nm in the embodiment. In addition, when the thickness t2 of the cobalt layer exceeds 0.6 nm, perpendicular magnetic anisotropy (PMA) is not realized, and even though the thickness t1 of the iron layer is less than 0.52 nm, Is not formed. Therefore, in order to realize perpendicular magnetic anisotropy due to the interfacial effect of the iron layer / MgO layer, it is preferable that the thickness of the iron layer is 0.52 nm or more, and the ratio of the thickness of the iron layer constituting the magnetic layer structure to the thickness of the cobalt layer The vertical magnetic anisotropy can be induced. As shown in Fig. 6 and Table 1, the ratio of the thickness t1 / (t1 + t2) for obtaining the perpendicular magnetic anisotropy is as follows. First, the thickness of the Fe layer should be thicker than that of the Co layer. It is preferable that the ratio of thickness (t1 / (t1 + t2)) is 0.69 or less.

6 is a graph showing the total thickness (t1 + t2) of the double magnetic layer structure maintained at 1 nm (straight-line), 1.13 nm (straight-line), and 1.26 nm (T1 / (t1 + t2)) of the thickness of the cobalt layer is obtained by linear fitting the variation of the saturation magnetization value obtained. The saturation magnetization of the iron layer is consistently evaluated at about 1.86 T over the entire range of thickness (t1). The saturation magnetization of the cobalt layer was largely changed to 0.52 T, 0.8 T and 1.25 T at 1 nm, 1.13 nm and 1.25 nm depending on the thickness (t2) of the Co layer.

As shown in FIG. 6, since the difference in saturation magnetization depending on the thickness can be predicted to be caused by the formation of a magnetic dead layer (MDL), the MDL of the dual magnetic layer structure is mainly formed at the interface between the Ta layer and the Co layer While the saturation magnetization is constant at the interface of the iron layer / MgO layer, so that the MDL is hardly formed. Therefore, it can be seen that it is important to construct the above-mentioned seed layer for minimizing the MDL at the interface with the magnetic layer in order to realize excellent PMA characteristics.

FIG. 7 is a graph illustrating changes in M-H loops according to an annealing temperature of a dual magnetic layer structure according to an embodiment of the present invention.

Referring to FIG. 7, an annealing process is required to crystallize the double magnetic layer structure according to an embodiment of the present invention into a Miller index (001) plane. The annealing may be performed at 250 캜 to 300 캜. The highest H _eff is obtained at annealing at about 275 ° C. The size of the hybrid bond which induces the surface magnetic anisotropy induced in the annealing process in the same structure can be roughly _{classified into} the size of H _eff . Therefore, in the case of the double magnetic layer structures shown in the embodiment of the present invention, the hybrid bonding between the p orbitals of oxygen generated at the interface between the metal oxide layer and the iron layer and the 3d orbitals of iron is most strongly induced at annealing at 275 ° C . H _eff is the magnitude of the magnetic field in which the magnetization saturates along the hard axis of the magnetic layer and the magnetic anisotropy energy thereof increases in proportion thereto. Consequently, an increase in the H _eff may be an important factor for improving the thermal stability have. On the other hand, when annealed at 300 ℃, the magnetic moment was also decreased with H _eff decrease. This is presumed to be caused by two phenomena caused by diffusion of tantalum into the magnetic layer at a temperature of 300 ° C or higher. The first is that the tantalum penetrates into the cobalt layer interface to increase the MDL, thereby reducing the magnetic moment. Second, the tantalum diffuses to the interface between the metal oxide layer and the iron layer, This is because H _eff is reduced by induction of low surface magnetic anisotropy. Therefore, annealing is required to induce surface magnetic anisotropy. If the annealing temperature is higher than 300 ° C., annealing may be performed at a temperature lower than 300 ° C. because of an increase in MDL and deterioration of magnetic properties due to a decrease in hybrid coupling force .

As a comparative example in comparison with the embodiment of the present invention, the multilayer magnetic thin film stack including the inverted iron / cobalt layer, the single iron layer, and the single cobalt layer in which the tunneling barrier layer and the cobalt layer contact each other has PMA characteristics Respectively. In these comparative examples, only the horizontal magnetic anisotropy (IMA) was observed in both the iron / cobalt layer, the single iron layer, and the single cobalt layer of the inverted structure, but no PMA was observed. It is believed that this is due to the fact that large surface anisotropy is not induced to overcome the bulk anisotropy of each structure. Specifically, in the case of the double magnetic layer structure of the iron / cobalt layer, the bulk anisotropy is expected to be similar to that of the reversed cobalt / iron layer structure, but at the interface between the cobalt layer and the MgO layer, It is presumed that the inherent bulk anisotropy can not be overcome because the lower surface magnetic anisotropy is induced and finally, the IMA is realized.

8A and 8B are graphs showing changes in magnetic anisotropy energy and surface magnetic anisotropy energy according to the thickness of a double magnetic layer structure in an embodiment of the present invention, respectively.

Referring to Figs. 8A and 8B, the effective anisotropic energy (K _eff ) can be approximated from Equation (1). In Equation 1, Ms is the saturation magnetization value, and H _eff is the effective magnetic field. The anisotropic energy is represented by the sum of the surface magnetic anisotropic energy induced at the interface with the tunneling barrier layer, the bulk magnetic anisotropic energy inherent in the magnetic layer, and the demagnetization energy generated due to the shape anisotropy.

[Formula 1]

K _eff ~ (M _S × H _eff ) / 2

Therefore, as the thickness of the double magnetic layer structure increases, the surface magnetic anisotropy energy is maintained, while the magnetic anisotropy energy of the magnetic layer itself increases, so that the perpendicular magnetic anisotropy energy is gradually decreased and the magnetization anisotropy is changed by the horizontal magnetic anisotropy . The maximum magnetic anisotropic energy of the double magnetic layer structure according to the embodiment of the present invention is about 0.163 MJ / m ^{3, which} is about 50% higher than the anisotropic energy of the conventional CoFeB magnetic layer having the same thickness. In addition, the surface magnetic anisotropic energy induced at the interface of the iron layer / MgO layer is 2.6 mJ / m ² , which is about 100% higher than that of the conventional CoFeB layer / MgO layer. The dual magnetic layer structure having the improved magnetic anisotropic energy according to the embodiment of the present invention can provide a nonvolatile memory device having improved data stability required for high integration of a memory device, thereby improving data retention characteristics.

Figure 9 is a block diagram illustrating a memory system 500 in accordance with one embodiment of the present invention.

9, the memory system 500 includes a memory controller 510 and a non-volatile memory element 520. The non- The memory controller 510 may perform an error correction code on the non-volatile memory element 520. [ The memory controller 510 can control the nonvolatile memory element 520 with reference to an instruction and an address from the outside.

When the memory controller 510 receives the write request from the host, the memory controller 510 can perform error correction encoding on the write-requested data. In addition, the memory controller 510 may control the non-volatile memory element 520 to program the encoded data into a memory area corresponding to the provided address. In addition, the memory controller 510 may perform error correction decoding on data output from the nonvolatile memory 520 during a read operation. The error included in the output data can be corrected by the error correction decoding. The memory controller 510 may include an error correction block 515 to perform the detection and correction of the error.

The non-volatile memory device 520 may include a memory cell array 521 and a page buffer 523. The memory cell array 521 is an array of memory cells including a multi-layer magnetic thin film stack or a magnetic tunneling junction as described above and may include a single level memory cell or an array of two or more bits of multi level memory cells. Upon receiving the initialization request, the memory controller 510 can initialize the string selection transistors of each memory layer to have a predetermined state by a program or erase method using a time-varying erase voltage signal according to the above-described embodiments.

10 is a block diagram illustrating an information storage device 1000 including a solid state disk (SSD) according to an embodiment of the present invention.

Referring to FIG. 10, an information storage device 1000 includes a host 1100 and an SSD 1200. The SSD 1200 may include an SSD controller 1210, a buffer memory 1220, and a non-volatile memory element 1230. The SSD controller 1210 provides electrical and physical connections between the host 1100 and the SSD 1200. In one embodiment, the SSD controller 1210 provides interfacing with the SSD 1200 in response to the bus format of the host 1100. In addition, the SSD controller 1210 can access the non-volatile memory element 1230 according to the decoded result of decoding the instruction provided from the host 1100. [ (PCI) express, Advanced Technology Attachment (ATA), Parallel ATA (PATA), SATA (Serial ATA), and the like, as a non-limiting example of the bus format of the host 1100. [ Serial ATA), and Serial Attached SCSI (SAS).

The buffer memory 1220 may temporarily store write data provided from the host 1100 or data read from the nonvolatile memory element 1230. [ When data existing in the nonvolatile memory element 1230 is cached at the time of the read request of the host 1100, the buffer memory 1220 is provided with a cache function of directly providing the cached data to the host 1100 . In general, the data transfer rate by the host 1100 bus format (e.g., SATA or SAS) may be faster than the transfer rate of the memory channel of the SSD 1200. [ In this case, a large-capacity buffer memory 1220 is provided to minimize the performance degradation caused by the speed difference. The buffer memory 1220 for this purpose may be, but is not limited to, a synchronous DRAM to provide sufficient buffering.

The nonvolatile memory element 1230 may be provided as a storage medium of the SSD 1200. For example, the non-volatile memory element 1230 may be an STT-MRAM having a large storage capacity according to the above-described embodiment. In another example, a memory system in which a NOR flash memory, a phase change memory, another magnetic memory, a resistive memory, a ferroelectric memory, or a heterogeneous memory device selected from these are mixed is also applicable as the nonvolatile memory element 1230.

11 is a block diagram illustrating a memory system 2000 in accordance with another embodiment of the present invention.

Referring to FIG. 11, a memory system 2000 according to the present invention may include a memory controller 2200 and a magnetic memory element 2100. The magnetic memory element 2100 may include the nonvolatile memory elements disclosed with reference to FIGS. The memory controller 2200 may be configured to control the magnetic memory element 2100. The SRAM 2230 can be used as an operation memory of the CPU 2210. [ The host interface 2220 may implement a data exchange protocol of the host connected to the memory system 2000. The error correction circuit 2240 included in the memory controller 2200 can detect and correct errors contained in data read from the flash memory 2100. [ The memory interface 2260 may interface with the magnetic memory element 2100 of the present invention. The CPU 2210 can perform all control operations for data exchange of the memory controller 2200. [ The memory system 2000 according to the present invention may further include a ROM (not shown) for storing code data for interfacing with a host.

The memory controller 2100 is configured to communicate with external circuitry (e.g., a host) through any of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, . The memory system 2000 according to the present invention may be implemented in a computer, a portable computer, an UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital video player, a digital video player, a device capable of transmitting and receiving information in a wireless environment, and a home network, Can be applied.

12 is a block diagram illustrating a data storage device 3000 according to another embodiment of the present invention.

Referring to FIG. 12, a data storage device 3000 according to the present invention may include a magnetic memory 3100 and a magnetic memory controller 3200. The magnetic memory controller 3200 can control the magnetic memory 3100 based on control signals received from the external circuitry of the data storage device 3000. [ The three-dimensional memory array structure of the magnetic memory 3100 may have, for example, a horizontal or vertical stacked structure based on a cross point structure, but the present invention is not limited thereto.

The data storage device 3000 of the present invention can constitute a memory card device, an SSD device, a multimedia card device, an SD card, a memory stick device, a hard disk drive device, a hybrid drive device, or a universal serial bus flash device. For example, the data storage device 3000 of the present invention may be a memory card that meets standards or specifications for using electronic devices such as digital, camera, or personal computers.

13 is a block diagram illustrating a magnetic memory device 4100 and a computing system 4000 including the same according to one embodiment of the present invention.

13, a computing system 4000 in accordance with the present invention includes a modem 4300, such as a magnetic memory device 4100, a memory controller 4200, a baseband chipset, etc., electrically coupled to a bus 4400, , A microprocessor 4500, and a user interface 4600. [

The magnetic memory element 4100 shown in Fig. 13 may be the above-described nonvolatile memory element. The computing system 4000 according to the present invention may be a mobile device, in which case a battery 4700 may be further provided for supplying the operating voltage of the computing system 4000. Although not shown, an application chipset, a camera image processor (CIS), or a mobile DRAM may be further provided in the computing system according to the present invention. The memory controller 4200 and the magnetic memory device 4100 can constitute, for example, a solid state drive / disk (SSD) using a nonvolatile memory element for storing data.

The nonvolatile memory device and / or memory controller according to the present invention may be implemented using various types of packages. For example, the magnetic memory device and / or the memory controller according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WSP). ≪ / RTI >

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

Claims (20)

A metal oxide layer;
An iron (Fe) layer having a first surface in contact with the metal oxide layer; And
And a cobalt (Co) layer contacting the second surface of the iron layer opposite to the first surface. The method according to claim 1,
The metal oxide layer has a magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), titanium oxide (TiO _2), aluminum nitride (AlN), ruthenium oxide (RuO _2), strontium oxide (SrO), calcium oxide ( CaO _2), hafnium oxide (HfO _2), tantalum oxide (Ta ₂ O _5), zirconium oxide (ZrO _2), and silicon oxide (multi-layer magnetic thin film containing any one of a mixture thereof or a layered thin film of SiO ₂₎ stack. 3. The method of claim 2,
Wherein the one surface of the iron layer has hybrid bonds between the 3d orbitals of iron and the 2p orbitals of oxygen of the metal oxide layer. The method according to claim 1,
Wherein the iron layer has a monocrystalline or polycrystalline crystal structure crystallized so as to have a texture in a Miller index (001) direction or a preferential oriented surface. 5. The method of claim 4,
Wherein the cobalt layer has a single crystal or polycrystalline crystal structure crystallized so as to have a textured or preferential oriented surface in a Miller index (001) direction along the iron layer. The method according to claim 1,
Wherein the total thickness of the iron layer and the cobalt layer is in the range of 0.88 nm to 1.14 nm. The method according to claim 1,
Wherein the thickness of the iron layer is 0.52 nm or more, and the thickness of the cobalt layer is 0.6 nm or less. The method according to claim 1,
The thickness (t ₁ ) of the iron layer is greater than the thickness (t ₂ ) of the cobalt layer,
The total thickness (t ₁ + t ₂₎ the ratio (t1 / (t1 + t2) ) of the thickness (t ₁₎ of the iron layer on the range within the multi-layer magnetic thin film stack of more than 0.69 of said iron layer and the cobalt layer. The method according to claim 1,
And a seed layer on the base of the cobalt layer. 10. The method of claim 9,
Wherein the seed layer comprises a laminated structure of a tantalum layer / a ruthenium layer / a tantalum layer sequentially formed. A magnetically fixed layer on the first side of the tunneling barrier layer and a magnetic free layer on the second side opposite to the first side of the tunneling barrier layer, the tunnel barrier layer comprising a metal oxide layer as an information storage element, An electronic device comprising a tunneling junction,
Wherein at least one of the magnetically fixed layer and the self-
An iron (Fe) layer having a first surface in contact with the metal oxide layer; And
And a cobalt (Co) layer in contact with a second surface opposite to the first surface of the iron layer. 12. The method of claim 11,
The metal oxide layer has a magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), titanium oxide (TiO _2), aluminum nitride (AlN), ruthenium oxide (RuO _2), strontium oxide (SrO), calcium oxide ( CaO _2), hafnium oxide (HfO _2), tantalum oxide (Ta ₂ O _5), zirconium oxide (ZrO _2), and silicon oxide (electron device comprising any one of a mixture or a multi-layered thin film thereof of SiO _2). 13. The method of claim 12,
Wherein the one surface of the iron layer has hybrid bonding between the 3d orbitals of iron and the 2p orbital of oxygen of the metal oxide layer. 12. The method of claim 11,
Wherein the iron layer has a single crystal or polycrystalline crystal structure crystallized so as to have a texture in a Miller index (001) direction or a preferential oriented surface. 15. The method of claim 14,
Wherein the cobalt layer has a single crystal or polycrystalline crystal structure crystallized so as to have a texture or a preferential oriented surface in a Miller index (001) direction along the iron layer. 12. The method of claim 11,
Wherein the total thickness of the iron layer and the cobalt layer is in the range of 0.88 nm to 1.14 nm. 12. The method of claim 11,
Wherein the thickness of the iron layer is 0.52 nm or more, and the thickness of the cobalt layer is 0.6 nm or less. 12. The method of claim 11,
The thickness (t ₁ ) of the iron layer is greater than the thickness (t ₂ ) of the cobalt layer,
It said iron layer and the ratio (t1 / (t1 + t2) ) of the thickness (t ₁₎ of said iron layer to the total thickness (t ₁ + t ₂₎ of the cobalt layer is an electronic device within a range of not more than 0.69. 12. The method of claim 11,
And a seed layer on the bottom of the cobalt layer. 20. The method of claim 19,
Wherein the seed layer comprises a laminated structure of a sequentially formed tantalum layer / ruthenium layer / tantalum layer.

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