KR20180004551A - Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate - Google Patents

Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate Download PDF

Info

Publication number
KR20180004551A
KR20180004551A KR1020160084259A KR20160084259A KR20180004551A KR 20180004551 A KR20180004551 A KR 20180004551A KR 1020160084259 A KR1020160084259 A KR 1020160084259A KR 20160084259 A KR20160084259 A KR 20160084259A KR 20180004551 A KR20180004551 A KR 20180004551A
Authority
KR
South Korea
Prior art keywords
boron
boron nitride
nitrogen
metal pattern
nitride compound
Prior art date
Application number
KR1020160084259A
Other languages
Korean (ko)
Inventor
김종규
정호경
황선용
한남
Original Assignee
포항공과대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 포항공과대학교 산학협력단 filed Critical 포항공과대학교 산학협력단
Priority to KR1020160084259A priority Critical patent/KR20180004551A/en
Publication of KR20180004551A publication Critical patent/KR20180004551A/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10325Boron nitride [BN], e.g. cubic, hexagonal, nanotube

Abstract

According to the present invention, a method injects raw material gas including boron or nitrogen or both boron and nitrogen onto a metal pattern after forming the metal pattern so as to induce a chemical reaction between the boron and the nitrogen on the metal pattern through a catalyst effect of metal, thereby selectively forming a boron nitride compound on the metal pattern. Therefore, the method can be compatible with a microprocessing technology used for microelectronics without using the existing lithography method after growth, and a boron nitride thin film can be obtained without exposure to the remaining organic material.

Description

금속 기판 패터닝을 통한 질화붕소 화합물 반도체의 선택적 영역 성장 방법 {METHOD FOR SITE-CONTROLLED GROWTH OF BORON NITRIDE COMPOUND SEMICONDUCTOR BY USING PATTERNED METAL SUBSTRATE}BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of growing a selective region of a boron nitride compound semiconductor by patterning a metal substrate,

본 발명은 패턴이 형성된 금속 기판을 이용한 질화붕소 화합물 반도체의 선택적 영역 성장 방법에 관한 것으로, 더욱 상세하게는 패터닝된 금속 기판을 이용하여 기상 상태의 붕소, 질소 원자 또는 붕소, 질소를 포함한 화합물들의 화학반응을 이용하여 질화붕소 화합물 반도체를 선택적 영역에 성장하는 것이다.The present invention relates to a method for growing a selective region of a boron nitride compound semiconductor using a patterned metal substrate, and more particularly, to a method for selectively growing a boron nitride compound semiconductor using a patterned metal substrate, And the boron nitride compound semiconductor is grown in the selective region by using the reaction.

질화붕소 화합물 반도체는 붕소 원자와 질소 원자로 이루어진 이원소 화합물 반도체로 육방정 질화붕소(hexagonal boron nitride), 입방정 질화붕소(cubic boron nitride), 능면정 질화붕소(rhombonedral boron nitride) 및 난층 질화붕소(turbostratic boron nitride)의 구조를 포함하는 화합물 반도체이다. 질화붕소 화합물 반도체는 열전도성, 내열성, 내식성, 전기절연성이 뛰어나 각종 기재 및 전자소자에 첨가제로 사용되고 있다.The boron nitride compound semiconductors are binary compound semiconductors composed of boron atoms and nitrogen atoms. They are hexagonal boron nitride, cubic boron nitride, rhombonedal boron nitride, and turbostratic boron nitride. boron nitride). < / RTI > The boron nitride compound semiconductors have excellent thermal conductivity, heat resistance, corrosion resistance, and electrical insulation properties and are used as additives in various substrates and electronic devices.

일례로, 육방정 구조의 질화붕소 화합물 반도체는 약 5.9 eV의 큰 밴드갭으로 인해 전기적 절연 특성을 가지고, 물리적 및 기계적으로 안정한 물성을 가지는 특징이 있다. 이러한 물성에 기반하여, 육방정 질화붕소를 2차원 물질 기반 소자에 절연체로 적용하는 연구가 많이 진행되고 있다. 특히, 육방정 질화붕소는 그래핀과의 격자 미스매치가 1.7%로 계면 구조가 안정적이며 완전한 절연체의 성질을 가지고 있으므로, 그래핀을 전기적, 구조적으로 절연시켜 다양한 전기소자에 유용하게 사용될 수 있다.For example, a hexagonal boron nitride compound semiconductor has an electrical insulation property due to a large band gap of about 5.9 eV, and has physical and mechanical properties that are stable. On the basis of these properties, many studies have been made on the application of hexagonal boron nitride as an insulator to a two-dimensional substance-based device. Particularly, hexagonal boron nitride has a lattice mismatch of 1.7% with graphene and has a stable interfacial structure and a complete insulator property. Therefore, graphene can be electrically and structurally insulated to be useful for various electric devices.

질화붕소 화합물 반도체를 이용한 많은 응용을 위해서는 질화붕소 화합물 반도체층에 대한 패턴 생성 프로세스가 필수적인데, 종래에는 패턴 생성 프로세스로 성장 후 리소그래피(Post-growth lithography) 방법을 활용해왔다.For many applications using boron nitride compound semiconductors, a pattern generation process for a boron nitride compound semiconductor layer is indispensable. Conventionally, a post-growth lithography method has been used in the pattern generation process.

그런데, 종래 방법으로 질화붕소 화합물 반도체 응용 소자를 제조하는 경우에는 마이크로일렉트로닉스(Microelectronics)에 사용되는 미세가공기술(Micro fabrication)과 호환이 어려운 문제가 있어서 대면적 소자 제조에 적용될 수 없는 문제점이 있다. 또한, 성장 후 리소그래피 과정 중 질화붕소 화합물 반도체에 제거하기가 어려운 잔여 유기물이 생성될 수 있어, 생성된 잔여 유기물은 질화붕소 화합물 반도체의 물성에 부정적인 영향을 끼치는 문제점을 야기한다.However, when a boron nitride compound semiconductor device is manufactured by a conventional method, it is difficult to be compatible with a micro fabrication technique used in a microelectronics, so that it can not be applied to the manufacture of a large-sized device. In addition, residual organic matter, which is difficult to remove in the boron nitride compound semiconductor during the post-growth lithography process, may be generated, resulting in a problem that the properties of the boron nitride compound semiconductor are adversely affected.

이에, 전술한 질화붕소 화합물 반도체의 패턴 생성 과정 중 마이크로일렉트로닉스에 사용되는 미세가공기술과 호환이 가능하고, 잔여 유기물에 대한 노출이 없어 질화붕소 화합물 반도체의 고유 특성의 저하가 발생하지 않는 질화붕소 화합물 반도체 성장 방법의 개발이 필요하다.Accordingly, it is possible to provide a boron nitride compound compound which is compatible with the microfabrication technology used in microelectronics during the pattern formation process of the above-mentioned boron nitride compound semiconductor and which does not cause exposure to residual organic substances and does not cause deterioration of intrinsic properties of the boron nitride compound semiconductor Development of a semiconductor growth method is needed.

Journal of Vacuum Science & Technology A, Volume 31, Issue 6 (2013) (Samuel Grenadier, Jing Li, Jingyu Lin, Hongxing Jiang, Dry etching techniques for active devices based on hexagonal boron nitride epilayers)(2001) (Samuel Grenadier, Jing Li, Jingyu Lin, Hongxing Jiang, Dry etching techniques for active devices based on hexagonal boron nitride epilayers)

본 발명의 목적은, 성장 후 리소그래피 방법을 사용하지 않고, 마이크로일렉트로닉스에 사용되는 미세가공기술과의 호환이 가능하고 잔여 유기물에 대한 노출이 없도록, 패턴이 형성된 금속 기판 상에 선택적 영역 성장이 가능한 질화붕소 화합물 반도체의 제조 방법을 제공하는 것이다.It is an object of the present invention to provide a method of manufacturing a nitride semiconductor device capable of selective region growth on a patterned metal substrate so as to be compatible with a microfabrication technique used in microelectronics and without exposure to residual organic material, And a method for manufacturing a boron compound semiconductor.

상기 기술적 과제를 해결하기 위해 본 발명은, 금속 패턴을 형성한 후, 상기 금속 패턴 상에 붕소, 질소 또는 붕소와 질소를 포함하는 원료 가스를 주입하여 상기 금속의 촉매효과를 통해 상기 금속 패턴 상에서 붕소와 질소의 화학반응이 일어나도록 함으로써, 질화붕소 화합물이 상기 금속 패턴 상에 선택적으로 형성되도록 하는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a metal pattern on the metal pattern; injecting a source gas containing boron, nitrogen or boron and nitrogen onto the metal pattern; And a chemical reaction of nitrogen is caused to occur, whereby a boron nitride compound is selectively formed on the metal pattern, thereby providing a selective region growing method of a boron nitride compound semiconductor.

본 발명은 패턴화된 금속 상에 원료 가스를 주입하여 화학기상증착법으로 박막을 형성하도록 함으로써, 금속의 촉매를 효과를 통해 금속 패턴 상에만 선택적으로 질화붕소 화합물의 성장이 이루어지도록 할 수 있으며, 이를 통해 종래의 성장 후 리소그래피 방법을 사용하지 않고, 마이크로일렉트로닉스에 사용되는 미세가공기술과의 호환이 가능하며 잔여 유기물에 대한 노출이 없는 질화붕소 박막을 얻을 수 있게 된다.In the present invention, a raw material gas is injected onto a patterned metal to form a thin film by a chemical vapor deposition method, whereby boron nitride compound can be selectively grown only on a metal pattern through the effect of a metal catalyst. It becomes possible to obtain a boron nitride thin film which is compatible with the microfabrication technique used in microelectronics and which is free from exposure to residual organic substances, without using the conventional post-growth lithography method.

도 1은 본 발명의 일 실시형태에 따라 h-BN 박막을 금속 패턴 상에만 선택적으로 형성하는 공정도이다.
도 2는 본 발명의 일 실시형태에 따라 h-BN 박막이 형성된 상태의 SEM 이미지이다.
도 3은 본 발명의 일 실시형태에 따라 형태의 선택적 성장 상태를 평가하기 위한 라만 분광법에 의한 분석결과를 나타낸 것이다.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process diagram for selectively forming an h-BN thin film only on a metal pattern according to an embodiment of the present invention;
2 is an SEM image of a state where an h-BN thin film is formed according to an embodiment of the present invention.
3 shows the results of Raman spectroscopic analysis for evaluating the selective growth state of the morphology according to an embodiment of the present invention.

본 발명의 일실시예는 일반적인 화학기상증착법과 금속-유기 화학기상증착법을 토대로 설명되어 있으나, 기술적 사상 또는 주요한 특징으로부터 벗어남 없이 다른 여러 가지 형태로 실시 될 수 있다.One embodiment of the present invention is described based on a general chemical vapor deposition method and a metal-organic chemical vapor deposition method, but may be carried out in various other forms without departing from the technical idea or main features.

본 발명자들은 성장 후 리소그래피(Post-growth lithography) 방법을 사용하지 않고, 질화붕소 박막의 패턴을 형성하는 방법을 연구한 결과, 화학기상증착법과 금속의 촉매를 효과를 통해 패턴화된 금속상에 질화붕소의 선택적 성장이 가능하고, 이 방법에 의할 경우 종래의 질화붕소 박막 패턴 형성방법의 문제점을 완전히 제거할 수 있음을 밝혀내고 본 발명에 이르게 되었다.As a result of studying a method of forming a pattern of a boron nitride thin film without using a post-growth lithography method, the present inventors have found that a chemical vapor deposition method and a metal catalyst can be nitrided It is possible to selectively grow boron, and this method can completely eliminate the problems of the conventional method of forming a boron nitride thin film pattern, leading to the present invention.

본 발명에 따른 질화붕소 화합물 반도체의 선택적 영역 성장 방법은, 금속 패턴을 형성한 후, 상기 금속 패턴 상에 붕소, 질소 또는 붕소와 질소를 포함하는 원료 가스를 주입하여 상기 금속의 촉매효과를 통해 상기 금속 패턴 상에서 붕소와 질소의 화학반응이 상기 금속 패턴 상에서만 선택적으로 일어나도록 하는 것에 특징이 있다.The method for growing a selective region of a boron nitride compound semiconductor according to the present invention includes the steps of forming a metal pattern and then injecting a source gas containing boron, nitrogen, or boron and nitrogen onto the metal pattern, Characterized in that the chemical reaction of boron and nitrogen on the metal pattern occurs selectively only on the metal pattern.

상기 질화붕소 화합물은, 육방정 질화붕소, 입방정 질화붕소, 능면체 질화붕소, 난층 질화붕소 중 어느 하나의 구조를 포함할 수 있다.The boron nitride compound may include any one of hexagonal boron nitride, cubic boron nitride, rhombohedral boron nitride and boron nitride.

또한, 상기 화학반응은 붕소 또는 질소 증기의 반응, 또는 붕소 또는 질소를 포함하는 화합물의 열분해에 의해 생성된 붕소 및 질소 원자의 반응일 수 있다.In addition, the chemical reaction may be a reaction of boron or nitrogen vapor, or a reaction of boron and nitrogen atoms produced by pyrolysis of a compound containing boron or nitrogen.

또한, 상기 금속 패턴은, Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Mo, Rh, Si, Ta, Ti, W, U, V, Zr, Ge 또는 이들의 합금, 황동, 청동, 및 스테인레스강으로 이루어진 그룹으로부터 선택된 하나 이상의 물질로 이루어질 수 있다.The metal pattern may be at least one selected from the group consisting of Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Mo, Rh, Si, Ta, Ti, W, U, V, Zr, Ge, , Brass, bronze, and stainless steel.

또한, 상기 금속 패턴은, SiO2, SiN, TiN, Al2O3, TiO2, Si3N4 상에 열증발장치(thermal evaporator), 전자빔증발장치(e-beam evaporator), 스퍼터(sputter) 또는 전기도금(electro-plating) 방법을 통해 형성되는 금속기판을 통해 형성될 수 있다.In addition, the metal pattern is, SiO 2, SiN, TiN, Al 2 O 3, TiO 2, Si 3 N 4 heat evaporator on the (thermal evaporator), an electron beam evaporation apparatus (e-beam evaporator), sputtering (sputter) Or a metal substrate formed through an electro-plating method.

또한, 상기 금속 패턴은, 포토리소그래피(photolithography) 또는 전자-빔 리소그래피(e-beam lithography)를 이용하여 마스크 패턴을 형성하여 증착된 금속층을 식각(etching)하거나, 금속 기판 상에 SiO2, SiN, TiN, Al2O3, TiO2, Si3N4 및 SOG(Spin on glass) 중 어느 하나의 마스크층을 증착하여 소정 패턴이 노출되는 방법으로 형성될 수도 있다.The metal pattern may be formed by forming a mask pattern using photolithography or electron-beam lithography to etch the deposited metal layer, or may be formed by etching SiO 2 , SiN, A mask layer of TiN, Al 2 O 3 , TiO 2 , Si 3 N 4 and SOG (Spin on Glass) may be deposited to expose a predetermined pattern.

또한, 상기 금속 패턴은, 플라즈마 처리, 오존 처리 또는 감광 처리 중 어느 하나 이상의 처리법을 통해, 원료가스의 반응이 용이하도록 금속의 표면 반응 상태가 제어될 수 있다.Further, the surface state of the metal can be controlled so that the reaction of the source gas can be easily performed through any one or more of the plasma treatment, the ozone treatment and the light-sensitive treatment.

또한, 상기 원료가스의 화학반응의 속도를 조절하기 위하여, 붕소, 질소를 포함하는 원료가스의 주입량을 시간에 따라 조절할 수 있다.Further, in order to control the rate of the chemical reaction of the source gas, the amount of the source gas containing boron and nitrogen may be controlled over time.

또한, 상기 붕소를 포함하는 원료가스는, 단원소 붕소, 염화 붕소, 불화 붕소, 브롬화 붕소, 요오드화 붕소를 포함한 염화 붕소물, 염화 붕소를 포함한 복합 화합물, 트리에틸 보레이트(Triethyl borate), 트리이소프로필 보레이트(Triisoproply borate), 붕소 무수물(Boric anhydride), 산화 붕소, 보레인(Borane), 보레인 피리딘 착물(Borane pyridine complex), Tri-tert-butyle borate, 데카보레인(decaborane) 중에서 선택된 1종 이상일 수 있다.The raw material gas containing boron may be at least one selected from the group consisting of monovalent boron, boron chloride, boron fluoride, boron chloride, boron chloride including boron iodide, complex compound containing boron chloride, triethyl borate, At least one selected from the group consisting of triisoproply borate, boric anhydride, boron oxide, borane, borane pyridine complex, tri-tert-butyle borate and decaborane. .

또한, 상기 질소를 포함하는 원료가스는, 질소, 암모니아, 피라진, 1차 아민 (NRH2), 2차 아민 (NR2H), 3차 아민 (NR3) 및 4차 아민 (NR4) 및 아민 계열을 포함한 화합물(여기서 R은 알킬기임) 중에서 선택된 1종 이상일 수 있다.The source gas containing nitrogen may be a gas containing nitrogen, ammonia, pyrazine, a primary amine (NRH2), a secondary amine (NR2H), a tertiary amine (NR3) (Where R is an alkyl group).

또한, 상기 붕소와 질소를 포함하는 원료가스는, 암모니아 보레인(ammonia borane), 보라진(borazine), 보레인 착물(borane complex), 보론 디메틸아민 착물(Borone dimethylamine complex), 보레인 피리딘 착물(borane pyridine complex) 중에서 선택된 1종 이상일 수 있다.The source gas containing boron and nitrogen may be at least one selected from the group consisting of ammonia borane, borazine, borane complex, boron dimethylamine complex, borane pyridine complex ( borane pyridine complex.

또한, 상기 식각 공정을 통해 마이크로미터 크기로 형성된 금속 패턴에 대해, 열적 어닐링 처리를 하여, 결정립 경계가 없는 단일 결정립의 금속 패턴이 형성되도록 할 수 있다.In addition, a metal pattern formed in a micrometer size through the etching process may be subjected to a thermal annealing process to form a metal pattern of a single crystal grain having no grain boundary.

이하 본 발명의 바람직한 실시예를 통해 본 발명을 보다 상세하게 설명한다.Hereinafter, the present invention will be described in more detail with reference to preferred embodiments of the present invention.

[실시예][Example]

도 1은 본 발명의 일 실시형태에 따라 h-BN 박막을 금속 패턴 상에만 선택적으로 형성하는 공정도이다.BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process diagram for selectively forming an h-BN thin film only on a metal pattern according to an embodiment of the present invention;

도 1에 도시된 바와 같이, 본 발명의 바람직한 실시형태에 의하면, 기판 상에 금속 박막을 형성하는 단계(제1단계)와, 형성된 금속 박막을 패턴화하는 단계(제2단계)와, 금속 패턴이 형성된 기판에 화학기상증착법을 이용하여 금속패턴 표면에만 질화붕소 화합물이 선택적으로 형성되도록 하는 단계(제3단계)로 이루어진다.As shown in FIG. 1, according to a preferred embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a metal thin film on a substrate (first step); patterning the formed metal thin film (Step 3) of selectively forming a boron nitride compound only on the surface of the metal pattern by a chemical vapor deposition method on the substrate on which the boron nitride is formed.

본 발명의 실시예에서는 상기 제1단계~제3단계를 다음과 같은 과정을 통해 진행하였다.In the embodiment of the present invention, the first through third steps are performed as follows.

사파이어 기판의 C면 상에 스퍼터(Sputter)를 이용하여 Ni 금속 박막을 600nm 두께로 증착하였다. A Ni metal thin film was deposited to a thickness of 600 nm on the C-plane of the sapphire substrate by using a sputter.

이어서, 상기 Ni 금속 박막을 포토리소그래피(Photolithography) 공정 및 Ni 식각제를 이용한 습식 식각 공정을 거쳐 사파이어 기판 위에 64㎛ 사이즈의 Ni 패턴을 형성하였다. 그리고 열적 어닐링 과정을 통해 상기 Ni 패턴의 결정성을 확보하였다.Subsequently, the Ni metal thin film was subjected to a photolithography process and a wet etching process using an Ni etchant to form a 64 μm-size Ni pattern on the sapphire substrate. And the crystallinity of the Ni pattern was secured through a thermal annealing process.

이어서, 상기 Ni 패턴 상에, 금속 유기화학 증착법(MOCVD) 공정을 이용하여 육방정 질화붕소 화합물을 Ni 패턴 위에만 선택 영역 성장하였다. 상기 육방정 질화붕소 화합물의 성장 조건으로, 온도는 1050°C, 압력은 30mbar에서 트리에틸 붕산염(Triethyl Boroate)과 암모니아(NH3)의 주입하였다.Subsequently, a hexagonal boron nitride compound was selectively grown on the Ni pattern only on the Ni pattern by a metalorganic chemical vapor deposition (MOCVD) process. As the growth conditions of the hexagonal boron nitride compound, triethyl borate and ammonia (NH 3 ) were injected at a temperature of 1050 ° C and a pressure of 30 mbar.

도 2의 좌측 이미지는 상기 방법에 의해 금속 패턴 상에 h-BN 박막을 형성한 후 SEM으로 관찰한 것이고, 우측 이미지는 금속 패턴 상에 형성된 h-BN 박막을 다른 금속 기판으로 전사한 후의 이미지를 나타낸 것이다.2, the h-BN thin film formed on the metal pattern is observed by SEM, and the right image is the image after transferring the h-BN thin film formed on the metal pattern to another metal substrate .

도 2의 좌측 이미지에 나타난 바와 같이, 형성된 SEM 이미지 상에서 패턴이 형성된 부분과 그렇지 않은 부분이 명확하게 구분되어 있으며, 도 2의 우측 이미지에서 나타난 바와 같이, 금속 기판에 전사된 후에도 그 패턴이 명확히 구분되므로, 전사된 층은 금속이 아닌 물질로 이루어져 있음을 명확히 알 수 있다.As shown in the left image of FIG. 2, the patterned portion and the non-patterned portion are clearly distinguished on the formed SEM image. As shown in the right image of FIG. 2, even when the pattern is transferred to the metal substrate, , It can be clearly seen that the transferred layer is made of a material other than a metal.

도 3은 본 발명의 일 실시형태에 따라 형태의 선택적 성장 상태를 평가하기 위한 라만 분광법에 의한 분석결과를 나타낸 것이다.3 shows the results of Raman spectroscopic analysis for evaluating the selective growth state of the morphology according to an embodiment of the present invention.

도 3에 나타난 바와 같이, 금속 패턴이 형성된 부분과 그렇지 않은 부분에 대한 라만 분광법의 분석결과는 금속 패턴 상에만 h-BN이 선택적으로 형성되었음을 명확하게 보여준다.As shown in FIG. 3, the analysis results of Raman spectroscopy on the portion where the metal pattern is formed and the portion where the metal pattern is not formed clearly show that h-BN is selectively formed only on the metal pattern.

즉, 본 발명의 실시예에 따른 방법에 의하면 종래의 성장 후 리소그래피 방법에 의하지 않고도, 질화붕소 박막의 패턴을 형성할 수 있다.That is, according to the method of the present invention, a pattern of a boron nitride thin film can be formed without using a conventional post-growth lithography method.

Claims (12)

금속 패턴을 형성한 후, 상기 금속 패턴 상에 붕소, 질소 또는 붕소와 질소를 포함하는 원료 가스를 주입하여 상기 금속의 촉매효과를 통해 상기 금속 패턴 상에서 붕소와 질소의 화학반응이 일어나도록 함으로써, 질화붕소 화합물이 상기 금속 패턴 상에 선택적으로 형성되도록 하는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.A source gas containing boron, nitrogen or boron and nitrogen is injected onto the metal pattern to cause a chemical reaction between boron and nitrogen on the metal pattern through the catalytic effect of the metal, Wherein the boron compound is selectively formed on the metal pattern. 제1항에 있어서,
상기 질화붕소 화합물은, 육방정 질화붕소, 입방정 질화붕소, 능면체 질화붕소, 난층 질화붕소 중 어느 하나의 구조를 포함하는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
Wherein the boron nitride compound includes any one of hexagonal boron nitride, cubic boron nitride, rhombohedral boron nitride and boron nitride nitride.
제1항에 있어서,
상기 화학반응은 붕소 또는 질소 증기의 반응, 또는
붕소 또는 질소를 포함하는 화합물의 열분해에 의해 생성된 붕소 및 질소 원자의 반응인, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The chemical reaction may be a reaction of boron or nitrogen vapor, or
A method for growing a selective region of a boron nitride compound semiconductor, wherein the boron or nitrogen atom is a reaction of boron and nitrogen atoms produced by pyrolysis of a compound containing boron or nitrogen.
제1항에 있어서,
상기 금속 패턴은, Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Mo, Rh, Si, Ta, Ti, W, U, V, Zr, Ge 또는 이들의 합금, 황동, 청동, 및 스테인레스강으로 이루어진 그룹으로부터 선택된 하나 이상인, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The metal pattern may be at least one selected from the group consisting of Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Mo, Rh, Si, Ta, Ti, W, U, V, Zr, Ge, , Bronze, and stainless steel. ≪ Desc / Clms Page number 24 >
제1항에 있어서,
상기 금속 패턴은, SiO2, SiN, TiN, Al2O3, TiO2, Si3N4 상에 열증발장치 (thermal evaporator), 전자빔증발장치 (e-beam evaporator), 스퍼터 (sputter) 또는 전기도금 (electro-plating) 방법을 통해 형성되는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The metal pattern, SiO 2, SiN, TiN, Al 2 O 3, TiO 2, thermal evaporation device (thermal evaporator), an electron beam evaporation apparatus (e-beam evaporator), sputtering (sputter) or electricity to the Si 3 N 4 A method for growing a selective region of a boron nitride compound semiconductor, the method comprising the steps of:
제1항에 있어서,
상기 금속 패턴은,
포토리소그래피(photolithography) 또는 전자-빔 리소그래피(e-beam lithography)를 이용하여 마스크 패턴을 형성하여 증착된 금속층을 식각(etching)하거나,
금속 기판 상에 SiO2, SiN, TiN, Al2O3, TiO2, Si3N4 및 SOG(Spin on glass) 중 어느 하나의 마스크층을 증착하여 패턴을 형성하는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The metal pattern
A mask pattern is formed using photolithography or e-beam lithography to etch the deposited metal layer,
A method of forming a pattern by depositing a mask layer of SiO 2 , SiN, TiN, Al 2 O 3 , TiO 2 , Si 3 N 4 and SOG (Spin on Glass) Region growth method.
제1항에 있어서,
상기 금속 패턴은, 플라즈마 처리, 오존 처리 또는 감광 처리 중 어느 하나 이상의 처리법을 통해, 금속의 표면 반응 상태가 제어되는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
Wherein the metal pattern is controlled in a surface reaction state of the metal through at least one of a plasma treatment, an ozone treatment, and a light-sensitive treatment.
제1항에 있어서,
상기 화학 반응의 속도를 조절하기 위하여, 붕소, 질소를 포함하는 원료가스의 주입량을 시간에 따라 조절하는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
A method for growing a selective region of a boron nitride compound semiconductor in which an amount of a source gas containing boron and nitrogen is controlled with time in order to control the rate of the chemical reaction.
제1항에 있어서,
상기 붕소를 포함하는 원료가스는,
단원소 붕소, 염화 붕소, 불화 붕소, 브롬화 붕소, 요오드화 붕소를 포함한 염화 붕소물, 염화 붕소를 포함한 복합 화합물, 트리에틸 보레이트(Triethyl borate), 트리이소프로필 보레이트(Triisoproply borate), 붕소 무수물(Boric anhydride), 산화 붕소, 보레인(Borane), 보레인 피리딘 착물(Borane pyridine complex), Tri-tert-butyle borate, 데카보레인(decaborane) 중에서 선택된 1종 이상인, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The raw material gas containing boron is,
Boron compounds such as boron chloride, boron chloride, boron fluoride, boron bromide, boron chloride including boron iodide, complex compounds including boron chloride, triethyl borate, triisoproply borate, boric anhydride Wherein the boron nitride compound semiconductor is at least one selected from boron oxide, borane, borane pyridine complex, tri-tert-butyl borate and decaborane.
제1항에 있어서,
상기 질소를 포함하는 원료가스는,
질소, 암모니아, 피라진, 1차 아민 (NRH2), 2차 아민 (NR2H), 3차 아민 (NR3) 및 4차 아민 (NR4) 및 아민 계열을 포함한 화합물(여기서 R은 알킬기임) 중에서 선택된 1종 이상인, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The nitrogen-containing raw material gas,
A compound selected from the group consisting of nitrogen, ammonia, pyrazine, a primary amine (NRH2), a secondary amine (NR2H), a tertiary amine (NR3) and a quaternary amine (NR4) Or more of a boron nitride compound semiconductor.
제1항에 있어서,
상기 붕소와 질소를 포함하는 원료가스는,
암모니아 보레인(ammonia borane), 보라진(borazine), 보레인 착물(borane complex), 보론 디메틸아민 착물(Borone dimethylamine complex), 보레인 피리딘 착물(borane pyridine complex) 중에서 선택된 1종 이상인, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 1,
The raw material gas containing boron and nitrogen,
Wherein the boron nitride compound is at least one selected from ammonia borane, borazine, borane complex, boron dimethylamine complex, borane pyridine complex, A method for growing a selective region of a semiconductor.
제6항에 있어서,
상기 식각 공정을 통해 마이크로미터 크기로 형성된 금속 패턴에 대해, 열적 어닐링 처리를 하여, 결정립 경계가 없는 단일 결정립의 금속 패턴이 형성되도록 하는, 질화붕소 화합물 반도체의 선택적 영역 성장 방법.
The method according to claim 6,
A method for growing a selective region of a boron nitride compound semiconductor, comprising: performing a thermal annealing process on a metal pattern formed on a micrometer scale through the etching process to form a single crystal grain metal pattern having no grain boundary.
KR1020160084259A 2016-07-04 2016-07-04 Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate KR20180004551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020160084259A KR20180004551A (en) 2016-07-04 2016-07-04 Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160084259A KR20180004551A (en) 2016-07-04 2016-07-04 Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate

Publications (1)

Publication Number Publication Date
KR20180004551A true KR20180004551A (en) 2018-01-12

Family

ID=61001143

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160084259A KR20180004551A (en) 2016-07-04 2016-07-04 Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate

Country Status (1)

Country Link
KR (1) KR20180004551A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109503174A (en) * 2018-11-29 2019-03-22 盐城师范学院 A kind of preparation method of ultra-thin cubic boron nitride film
KR20200135716A (en) * 2019-05-23 2020-12-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Single-crystal hexagonal boron nitride layer and method forming same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168045A (en) * 1999-12-08 2001-06-22 Sony Corp Method of manufacturing nitride-based iii-v compound layer and method of manufacturing substrate using it
KR20120009323A (en) * 2010-07-23 2012-02-01 한국기계연구원 Method for forming graphene pattern
KR20150130256A (en) * 2015-11-02 2015-11-23 삼성전자주식회사 Heterogeneous layered structure, method for preparing the heterogeneous layered structure, and electric device including the heterogeneous layered structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168045A (en) * 1999-12-08 2001-06-22 Sony Corp Method of manufacturing nitride-based iii-v compound layer and method of manufacturing substrate using it
KR20120009323A (en) * 2010-07-23 2012-02-01 한국기계연구원 Method for forming graphene pattern
KR20150130256A (en) * 2015-11-02 2015-11-23 삼성전자주식회사 Heterogeneous layered structure, method for preparing the heterogeneous layered structure, and electric device including the heterogeneous layered structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109503174A (en) * 2018-11-29 2019-03-22 盐城师范学院 A kind of preparation method of ultra-thin cubic boron nitride film
KR20200135716A (en) * 2019-05-23 2020-12-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Single-crystal hexagonal boron nitride layer and method forming same
US11289582B2 (en) 2019-05-23 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Single-crystal hexagonal boron nitride layer and method forming same

Similar Documents

Publication Publication Date Title
TWI731074B (en) Processes and methods for selective deposition on first surface of substrate relative to second surface of substrate
Shih et al. Low-temperature atomic layer epitaxy of AlN ultrathin films by layer-by-layer, in-situ atomic layer annealing
Jeon et al. Wafer‐Scale Synthesis of Reliable High‐Mobility Molybdenum Disulfide Thin Films via Inhibitor‐Utilizing Atomic Layer Deposition
He et al. Molecular beam epitaxy scalable growth of wafer‐scale continuous semiconducting monolayer MoTe2 on inert amorphous dielectrics
US8338825B2 (en) Graphene/(multilayer) boron nitride heteroepitaxy for electronic device applications
Ruhl et al. The integration of graphene into microelectronic devices
Song et al. Graphene/h‐BN heterostructures: recent advances in controllable preparation and functional applications
TWI524392B (en) Stable silicide films and methods for making the same
Asadirad et al. High‐performance flexible thin‐film transistors based on single‐crystal‐like germanium on glass
Van Veldhoven et al. Electronic properties of CVD graphene: The role of grain boundaries, atmospheric doping, and encapsulation by ALD
Lee et al. Drying‐Mediated Self‐Assembled Growth of Transition Metal Dichalcogenide Wires and their Heterostructures
Tian et al. Growth Dynamics of Millimeter‐Sized Single‐Crystal Hexagonal Boron Nitride Monolayers on Secondary Recrystallized Ni (100) Substrates
Bogdanowicz et al. Growth and isolation of large area boron‐doped nanocrystalline diamond sheets: a route toward Diamond‐on‐Graphene heterojunction
US20170365482A1 (en) Method For Growing NI-Containing Thin Film With Single Atomic Layer Deposition Technology
Gao et al. Doping mechanism in transparent, conducting tantalum doped ZnO films deposited using atomic layer deposition
KR20180004551A (en) Method for site-controlled growth of boron nitride compound semiconductor by using patterned metal substrate
Jiang et al. Toward Direct Growth of Ultra‐Flat Graphene
Liu et al. Periodical ripening for MOCVD growth of large 2D transition metal dichalcogenide domains
KR101568159B1 (en) Healing method of defect using atomic layer deposition
US11456358B2 (en) Maskless patterning and control of graphene layers
Baek et al. Low‐Temperature Carrier Transport Mechanism of Wafer‐Scale Grown Polycrystalline Molybdenum Disulfide Thin‐Film Transistor Based on Radio Frequency Sputtering and Sulfurization
JP6648563B2 (en) Semiconductor device, method of manufacturing ribbon-shaped thin film, and method of manufacturing semiconductor device
Hsieh et al. Dynamic observation on the growth behaviors in manganese silicide/silicon nanowire heterostructures
CN107634097B (en) Graphene field effect transistor and manufacturing method thereof
Lee et al. Comparison of MoS2/p‐GaN Heterostructures Fabricated via Direct Chemical Vapor Deposition and Transfer Method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application