KR20180001206A - Light emitting diode chip and display device using the same and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a light emitting diode chip preventing brightness and a response speed from being lowered without design constraints, and a display device including the same. The light emitting diode chip comprises: a light emitting diode part located on one side of a semiconductor substrate; and a thin film transistor part located on the other side of the semiconductor substrate, and connected to the light emitting diode part through the semiconductor substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode chip, a display device including the same,

The present invention relates to a light emitting diode chip, a display device including the same, and a method of manufacturing the same.

2. Description of the Related Art In recent years, display devices employing flat panel display panels such as a liquid crystal display panel, a plasma display panel, and an organic light emitting display panel have been mainly commercialized.

The liquid crystal display panel and the organic light emitting display panel display an image using a thin film transistor (Thin Film Transistor) as a switching element. Such a display device is widely used as a display device for a notebook computer, a tablet computer, a smart phone, a portable display device, and a portable information device in addition to a display device for a television or a monitor.

Since a display device using a liquid crystal display panel is not a self-emission type, an image is displayed using light emitted from a backlight unit disposed under the display panel. As described above, a display device using a separate light emitting device such as a backlight unit is limited in design, and luminance and response speed may be lowered. Further, the display device using the organic light emitting display panel is vulnerable to moisture, and reliability may be lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a light emitting diode chip and a display device including the same and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a light emitting diode chip including a light emitting diode portion disposed on one side of a semiconductor substrate and a thin film transistor portion disposed on the other side of the semiconductor substrate and connected to the light emitting diode portion through a semiconductor substrate, And a method of manufacturing the same.

Since the light emitting diode chip according to an embodiment of the present invention includes the transistor and the light emitting diode in one substrate, the light emitting diode chip can function as a display device only when mounted on a display substrate.

Therefore, the display device according to an exemplary embodiment of the present invention does not need a separate light emitting device such as a backlight unit, so there is no restriction in design, and the luminance and response speed can be prevented from being lowered.

The effects obtained in the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description .

1 is a perspective view of a display device according to an exemplary embodiment of the present invention.
2 is a perspective view of a display device in which a light emitting diode chip is separated according to an exemplary embodiment of the present invention.
3 is a circuit diagram of a display device according to an example of the present invention.
4 is a cross-sectional view of a light emitting diode chip according to an example of the present invention.
5A to 5G are cross-sectional views illustrating a method of manufacturing a light emitting diode chip according to an exemplary embodiment of the present invention.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of a light emitting diode chip, a display device including the same, and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 1 is a perspective view of a display device according to an embodiment of the present invention. FIG. 2 is a perspective view of a display device in which a light emitting diode chip according to an exemplary embodiment of the present invention is separated. Fig.

1 to 3, a display device according to an exemplary embodiment of the present invention includes a display substrate DS and a plurality of light emitting diode chips (LC).

The display substrate (DS) may be a glass substrate or a flexible plastic film. For example, the substrate for display (DS) may include a cellulose resin such as TAC (triacetyl cellulose) or DAC (diacetyl cellulose), a COP (cyclo olefin polymer) such as Norbornene derivatives, , Polyolefin such as PC (polycarbonate), PE (polyethylene) or PP (polypropylene), polyvinyl alcohol (PVA), polyether sulfone (PES), polyetheretherketone (PEEK) (Polyimide), a polysulfone (PSF), a fluoride resin, or the like, such as polyethylene terephthalate (PET), polyetherimide (PEI), polyethylenenaphthalate , But is not limited thereto.

The display substrate DS includes a plurality of gate lines GL arranged in a first direction, a plurality of data lines DL arranged in a second direction intersecting the first direction, Common lines CL arranged at a predetermined distance from the gate lines GL and power lines PL arranged in the second direction and spaced apart from the data lines DL by a predetermined distance . The plurality of gate lines GL, the data lines DL, the common lines CL and the power supply lines PL are provided with a unit cell for mounting the light emitting diode chip LC for each pixel. do.

The plurality of gate lines GL includes a gate electrode pad GP provided on one side and is connected to a gate electrode terminal G1 'of a light emitting diode chip LC to be described later.

The plurality of data lines DL includes a source electrode pad SP provided on one side and is connected to a source electrode terminal S1 of a light emitting diode chip LC to be described later.

The plurality of common lines CL includes a common electrode pad CP provided at one side and is connected to a common electrode terminal C of a light emitting diode chip LC to be described later.

The plurality of power supply lines PL includes a drain electrode pad DP provided at one side and is connected to a drain electrode terminal D2 of a light emitting diode chip LC to be described later.

Each of the plurality of light emitting diode chips (LC) is mounted on a unit cell provided on a display substrate (DS), and each of the light emitting diode chips (LC) constitutes one pixel. At this time, the light emitting diode chip LC can emit red (R), green (G), and blue (B) light, respectively, and a black matrix is provided between the plurality of light emitting diode chips LC . The light emitting diode chip (LC) Includes a transistor and a light emitting diode (LED). Accordingly, the light emitting diode chip LC according to an exemplary embodiment of the present invention is mounted on the unit cell and connected to the gate line GL, the data line DL, the common line CL, and the power supply line PL, Emitting element that emits light in response to a data signal supplied to the data line DL in response to a gate signal supplied to the data line GL. Since the display device according to the present invention does not require a separate light emitting device such as a backlight unit, there is no restriction on the design, and the luminance and response speed can be prevented from being lowered.

4 is a cross-sectional view of a light emitting diode chip according to an example of the present invention.

2 to 4, a light emitting diode chip LC according to an exemplary embodiment of the present invention includes a semiconductor substrate CS, a light emitting diode unit 100, and a thin film transistor unit 200.

The semiconductor substrate CS may be formed of a material such as sapphire (Al 2 O 3), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), or gallium arsenide (GaAs).

The light emitting diode unit 100 is provided on one side of the semiconductor substrate CS. The light emitting diode unit 100 includes a first semiconductor layer 10, an active layer 20, a second semiconductor layer 30, a transparent electrode layer 40, and an encapsulation layer 50.

The first semiconductor layer 10 is provided on one surface of the semiconductor substrate CS. This first semiconductor layer 10 provides electrons to the active layer 20. The first semiconductor layer 10 may be made of an n-GaN-based semiconductor material, and the n-GaN-based semiconductor material may be GaN, AlGaN, InGaN, AlInGaN, or the like. As the impurity used for doping the first semiconductor layer 10, Si, Ge, Se, Te, or C may be used. At this time, a buffer layer may be disposed on the semiconductor substrate CS and the first semiconductor layer 10, and the buffer layer may be made of GaN or AlN.

The active layer 20 is provided on the first semiconductor layer 10. The active layer 20 has a multi quantum well (MQW) structure having a barrier layer having a higher bandgap than that of the well layer and the well layer. For example, the active layer 20 may have a multiple quantum well structure such as InGaN / GaN.

The second semiconductor layer 30 is provided on the active layer 20 to provide holes in the active layer 20. The second semiconductor layer 30 may be made of a p-GaN semiconductor material, and the p-GaN semiconductor material may be GaN, AlGaN, InGaN, AlInGaN, or the like. As the impurity used for doping the second semiconductor layer 30, Mg, Zn, Be, or the like may be used.

The transparent electrode layer 40 is provided on the second semiconductor layer 30. This transparent electrode layer 40 reduces contact resistance with the second semiconductor layer 30 having a relatively high energy band gap. The transparent electrode layer 40 may be made of a transparent material so that light generated in the active layer 20 may be emitted upward.

The sealing layer 50 is disposed so as to surround the side surface and the upper surface of the light emitting diode unit 100 of the light emitting diode chip LC. At this time, the sealing layer 50 may be arranged to surround a part of the side surface of the semiconductor substrate CS. The sealing layer 50 protects the light emitting diode unit 100. The encapsulation layer 50 according to one example may be formed of a material such as a silicon oxide film (SiOx).

The thin film transistor unit 200 is disposed on the other side of the semiconductor substrate CS opposite to one side of the semiconductor substrate CS on which the light emitting diode unit 100 is disposed. The thin film transistor unit 200 may include a first transistor T 1, a second transistor T 2, and a common electrode terminal C.

The first transistor T1 outputs a data signal supplied to the data line DL to the second transistor T2 in response to a gate signal supplied from the gate line GL. The first transistor T1 according to an exemplary embodiment includes a first gate electrode pattern G1, a gate insulating layer GI, a first active pattern A1, a passivation layer PAS, a gate electrode terminal G1 ' A source electrode terminal S1, and a drain electrode pattern D1.

The first gate electrode pattern G1 is provided on the other side of the semiconductor substrate CS in the form of a pattern. Here, the first gate electrode pattern G1 according to an exemplary embodiment may include at least one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Copper (Cu), or an alloy thereof. However, the present invention is not limited thereto. The first gate electrode pattern G1 is covered with the gate insulating layer GI. The gate insulating layer GI according to an exemplary embodiment may include, but is not limited to, an inorganic insulating material such as a silicon oxide film (SiOx), a silicon nitride film (SiNX), or a multilayer thereof.

The first active pattern A1 is provided on the gate insulating layer GI so as to overlap with the first gate electrode pattern G1. The first active pattern A1 according to an exemplary embodiment may be made of a semiconductor such as Zinc Oxide, Tin Oxide, Ga-In-Zn Oxide, In-Zn Oxide, or In-Sn Oxide. However, But may be made of a silicon-based semiconductor. The first active pattern A1 is covered with a protective layer PAS. The passivation layer PAS may be formed of an inorganic insulating material such as silicon oxide or silicon nitride. However, the insulating layer may be formed of an organic insulating material such as photo acryl or benzocyclobutene (BCB) ≪ / RTI >

The gate electrode terminal G1 'is provided on the passivation layer PAS and is electrically connected to the first gate electrode pattern G1 by bypassing the first active pattern A1. The gate electrode terminal G1 'is electrically connected to the gate electrode pad GP provided on the display substrate DS by the chip mounting process to receive the gate signal supplied to the gate line GL. The gate electrode terminal G1 'according to an exemplary embodiment may be formed of at least one selected from the group consisting of Mo, Al, Cr, Au, Ti, Cu, or an alloy thereof, and may be composed of a single layer of the metal or alloy or multiple layers of two or more layers, but is not limited thereto.

The source electrode terminal S1 is electrically connected to the source region of the first active pattern A1 through a first source contact hole formed on the passivation layer PAS. The source electrode terminal S1 receives the data signal supplied to the data line DL by being electrically connected to the source electrode pad SP provided on the display substrate DS by the chip mounting process. The source electrode terminal S1 is made of the same material as the gate electrode terminal G1 'and is provided on the protective layer PAS together with the gate electrode terminal G1'.

The drain electrode pattern D1 is electrically connected to the drain region of the first active pattern A1 through a first drain contact hole formed on the passivation layer PAS. The drain electrode pattern D1 may be formed of the same material as the gate electrode terminal G1 'and may be provided on the protection layer PAS together with the gate electrode terminal G1'.

The second transistor T2 supplies a data current corresponding to a data signal supplied from the first transistor T1 to the light emitting diode unit 100. [ The second transistor T2 according to an exemplary embodiment includes a second gate electrode pattern G2, a gate insulating layer GI, a second active pattern A2, a passivation layer PAS, a drain electrode terminal D2, A source electrode pattern S2, and a connection electrode pattern CM.

The second gate electrode pattern G2 is provided in a pattern form on the other side of the semiconductor substrate CS so as to be adjacent to the first gate electrode pattern G1. The second gate electrode pattern G2 is electrically connected to the drain electrode pattern D1 of the first transistor T1 through the protective layer PAS and the gate contact hole formed in the gate insulating layer GI, T1. The second gate electrode pattern G2 is made of the same material as the first gate electrode pattern G1 and is provided on the other side of the semiconductor substrate CS together with the first gate electrode pattern G1. The second gate electrode pattern G2 is covered with the gate insulating layer GI.

The second active pattern A2 is provided on the gate insulating layer GI so as to overlap with the second gate electrode pattern G2. The second active pattern A2 is made of the same material as the first active pattern A1 and is provided on the gate insulating layer GI together with the first active pattern A1. The second active pattern A2 is covered with the protective layer PAS.

The drain electrode terminal D2 is electrically connected to the drain region of the second active pattern A2 through a second drain contact hole formed on the passivation layer PAS. The drain electrode terminal D2 is electrically connected to the drain electrode pad DP provided on the display substrate DS by the chip mounting process to receive the pixel driving power supplied to the power supply line PL. The drain electrode terminal D2 may be formed of the same material as the gate electrode terminal G1 'of the first transistor T1 and may be provided on the protection layer PAS together with the gate electrode terminal G1'.

The source electrode pattern S2 is electrically connected to a source region of the second active pattern A2 through a second source contact hole formed on the passivation layer PAS. The source electrode pattern S2 is electrically connected to the transparent electrode layer 40 through the connection electrode pattern CM. The semiconductor substrate CS, the first semiconductor layer 10, the active layer 20, and the second semiconductor layer 30 are vertically stacked in a partial overlap region between the source electrode pattern S2 and the transparent electrode layer 40, A first electrode connection hole H1 is formed. The source electrode pattern S2 is electrically connected to the transparent electrode layer 40 of the light emitting diode 100 through the connection electrode pattern CM filled in the first electrode connection hole H1. At this time, a connection electrode pattern CM is electrically connected to the semiconductor substrate CS, the first semiconductor layer 10, the active layer 20, and the second semiconductor layer 30 on the inner wall of the first electrode connection hole H1 And a first insulating material IL for preventing connection. That is, the source electrode pattern S2 is formed by vertically penetrating the first insulating material IL provided in the first electrode connecting hole H1 and passing through the filled electrode pattern CM to form the transparent electrode layer (light emitting diode) 40, respectively.

The common electrode terminal C is provided on the passivation layer PAS and is electrically connected to the first semiconductor layer 10 through the semiconductor substrate CS. A second electrode connected vertically through the protective layer PAS, the gate insulating layer GI and the semiconductor substrate CS is formed in a part of overlapping region between the common electrode terminal C and the first semiconductor layer 10, And a hole H2 is provided. The common electrode terminal C is electrically connected to the first semiconductor layer 10 of the light emitting diode unit 100 by being filled in the second electrode connection hole H2. At this time, a second insulating material IL2 is provided on the inner wall of the second electrode connection hole H2 to prevent the common electrode terminal C from being electrically connected to the semiconductor substrate CS. That is, the common electrode terminal C vertically penetrates the second insulating material IL2 filled in the second electrode connection hole H2 and is electrically connected to the first semiconductor layer 10 of the light emitting diode unit 100 . The common electrode terminal C may be formed of the same material as the gate electrode terminal G1 'of the first transistor T1 and may be provided on the protection layer PAS together with the gate electrode terminal G1'.

Since the light emitting diode chip LC according to the exemplary embodiment of the present invention includes a transistor and a light emitting diode (LED) on one substrate, the light emitting diode chip LC functions as a display device only when mounted on a display substrate DS. . Therefore, the display device according to an exemplary embodiment of the present invention does not need a separate light emitting device such as a backlight unit, so there is no restriction in design, and the luminance and response speed can be prevented from being lowered.

5A to 5G are cross-sectional views illustrating a method of manufacturing a light emitting diode chip according to an exemplary embodiment of the present invention. Therefore, the same reference numerals are assigned to the same components, and repetitive descriptions of the repetitive portions in the materials, structures, etc. of the respective components are omitted.

First, as shown in FIG. 5A, a first semiconductor layer 10, an active layer 20, a second semiconductor layer 30, and a transparent electrode layer 40 are sequentially formed on a base semiconductor substrate CS do.

5b, the first semiconductor layer 10, the active layer 20, the second semiconductor layer 30, and the transparent electrode layer 40 are etched to form the light emitting diode unit 100 Into several unit cells having the size of the light emitting diode chip (LC). At this time, a part of the base semiconductor substrate CS may be etched.

Third, an encapsulation layer 50 is formed on the transparent electrode layer 40, as shown in FIG. 5C. The sealing layer 50 is formed on the upper surface of the transparent electrode layer 40 as well as on the upper surface of the etched base semiconductor substrate CS, the first semiconductor layer 10, the active layer 20, the second semiconductor layer 30, 40).

Fourth, as shown in FIG. 5D, a photoresist (PR) material is coated on the base semiconductor substrate CS, and a portion excluding a space for depositing the first and second gate electrode patterns G1 and G2 Is masked with a mask, and exposed to light to pattern the photoresist PR.

Fifthly, as shown in FIG. 5E, a gate metal G is deposited on the base semiconductor substrate CS as a whole through a sputtering process.

5f, the photoresist PR on which the gate metal G is deposited is stripped to form a first gate electrode pattern G1 on the base semiconductor substrate CS, And a second gate electrode pattern G2 are formed.

7, the gate insulating layer GI is deposited entirely on the base semiconductor substrate CS, as shown in FIG. 5G.

5H, a gate insulating layer GI, a base semiconductor substrate CS, a first semiconductor layer 10, an active layer 20, and a gate insulating layer G3 are formed on a side surface of the second gate electrode pattern G2, And a first electrode connection hole (H1) vertically penetrating the second semiconductor layer (30).

5, the first electrode connecting hole H1 is filled with the first insulating material IL1, and then the first electrode connecting hole H1 is formed again.

5J, a photoresist (PR) material is coated on the gate insulating layer GI, a portion excluding the space for depositing the connection electrode pattern CM is covered with a mask, Thereby patterning the photoresist PR.

For the eleventh time, as shown in FIG. 5K, a connection electrode CM is entirely deposited on the gate insulating layer GI.

As shown in Figure 51, the photoresist PR on which the connection electrode CM is deposited is removed by a strip process so that the connection electrode pattern CM is formed in the first electrode connection hole H1, .

As shown in FIG. 5M, the photoresist (PR) material is coated on the gate insulating layer GI and a portion excluding the space for depositing the first and second active patterns A1 and A2 After masking, the photoresist (PR) is patterned by exposure.

The semiconductor film A is deposited as a whole on the gate insulating layer GI, as shown in FIG. 5N.

Fifthly, as shown in FIG. 50, the photoresist PR on which the semiconductor film A is deposited is stripped to form a first active pattern A1 on the gate insulating layer GI ) And the second active pattern A2 are formed.

Sixteenth, as shown in FIG. 5P, a protective layer PAS is entirely deposited on the gate insulating layer GI and the first and second active patterns A1 and A2.

A contact hole is formed in the passivation layer PAS to expose one side and the other side of the first active pattern A1 and one side and the other side of the second active pattern A2, Lt; / RTI > A second electrode connection hole H2 is formed through the protective layer PAS, the gate insulating layer GI and the base semiconductor substrate CS on the side surfaces of the second active pattern A2.

As shown in FIG. 5R, a second insulating material (not shown) is formed in the second electrode connecting hole H2 through the protective layer PAS, the gate insulating layer GI, and the base semiconductor substrate CS, IL2, and then the second electrode connection hole H2 is formed again.

(PR) material is coated on the passivation layer PAS and the source electrode terminal S1, the gate electrode terminal G1 ', the drain electrode pattern D1 , The drain electrode terminal D2, the source electrode pattern S2, and the common electrode terminal C are covered with a mask and then exposed to pattern the photoresist PR.

For the twentieth time, as shown in Fig. 5T, the metal layer M is entirely deposited on the protective layer PAS.

The photoresist layer PR on which the metal layer M is deposited is removed by a strip process so that the source electrode terminals S1 and S2 are formed on the protective layer PAS, A gate electrode terminal G1 ', a drain electrode pattern D1, a drain electrode terminal D2, a source electrode pattern S2, and a common electrode terminal C are formed.

Referring to FIG. 5V, the sealing layer 50 extending from the lower surface of the transparent electrode layer 40 to extend through the light emitting diode 100 is referred to as a light emitting diode 100, (CS), and the thin film transistor unit 200 are etched and separated into one light emitting diode chip LC size.

Since the light emitting diode chip LC according to the exemplary embodiment of the present invention includes a transistor and a light emitting diode (LED) on one substrate, the light emitting diode chip LC functions as a display device only when mounted on a display substrate DS. . Therefore, the display device according to an exemplary embodiment of the present invention does not need a separate light emitting device such as a backlight unit, so there is no restriction in design, and the luminance and response speed can be prevented from being lowered.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

10: first semiconductor layer 20: active layer
30: second semiconductor layer 40: transparent electrode layer
50: sealing layer 100: light emitting diode part
200: thin film transistor part DS: substrate for display
LC: Light emitting diode chip CS: Semiconductor substrate
G1 and G2: first and second gate electrode patterns GI: gate insulating layer
A1, A2: first and second active patterns S1: source electrode terminal
D1: drain electrode pattern G1 ': gate electrode terminal
S2: Source electrode pattern D2: Drain electrode terminal
C: common electrode terminal IL1, IL2: first and second insulating materials
PAS: protection layer H1, H2: first and second electrode connection holes
CM: connecting electrode pattern

Claims (10)

A semiconductor substrate;
A light emitting diode unit disposed on one side of the semiconductor substrate; And
And a thin film transistor portion disposed on the other side of the semiconductor substrate and connected to the light emitting diode portion through the semiconductor substrate. The method according to claim 1,
The light-
A first semiconductor layer disposed on one side of the semiconductor substrate;
An active layer disposed on the first semiconductor layer;
A second semiconductor layer disposed on the active layer;
A transparent electrode layer disposed on the second semiconductor layer; And
And an encapsulation layer surrounding an upper surface of the transparent electrode layer and a side surface of the light emitting diode. 3. The method of claim 2,
The thin-
A first transistor;
A second transistor which is disposed on a side surface of the first transistor and supplies a current corresponding to a signal supplied from the first transistor to the light emitting diode; And
And a common electrode terminal disposed on a side surface of the second transistor and electrically connected to the first semiconductor layer. The method of claim 3,
And the second transistor is electrically connected to the transparent electrode layer. In the display substrate,
A gate line arranged in the first direction on the display substrate;
A data line arranged in a second direction intersecting the first direction;
A common line arranged in the first direction and spaced apart from the gate line; And
And a power line arranged in the second direction and spaced apart from the data line,
A display device for mounting the light emitting diode chip according to any one of claims 1 to 4 on a display substrate. Forming a light emitting diode portion on one side of the semiconductor substrate; And
And forming a thin film transistor portion connected to the light emitting diode portion through the semiconductor substrate on the other side of the semiconductor substrate. The method according to claim 6,
Wherein forming the light emitting diode portion comprises:
Forming a first semiconductor layer on one side of the semiconductor substrate;
Forming an active layer on the first semiconductor layer;
Forming a second semiconductor layer on the active layer;
Forming a transparent electrode layer on the second semiconductor layer;
Etching the first semiconductor layer, the active layer, the second semiconductor layer, and the transparent electrode layer to a size of the light emitting diode chip; And
And forming an encapsulation layer on the transparent electrode layer. 8. The method of claim 7,
Wherein forming the thin film transistor portion comprises:
Forming first and second gate electrode patterns on the other side of the semiconductor substrate;
Forming a gate insulating layer on the first and second gate electrode patterns;
Forming a first electrode connection hole vertically through the gate insulating layer, the semiconductor substrate, the first semiconductor layer, the active layer, and the second semiconductor layer;
Forming a first insulating material in the first electrode connection hole;
Forming first and second active patterns on the gate insulating layer;
Forming a protective layer on the first and second active patterns;
Forming a second electrode connection hole vertically passing through the protective layer, the gate insulating layer, and the semiconductor substrate;
Forming a second insulating material in the second electrode connection hole;
And forming a source electrode terminal, a gate electrode terminal, a drain electrode pattern, a drain electrode terminal, a source electrode pattern, and a common electrode terminal on the protective layer. 9. The method of claim 8,
Wherein forming the source electrode terminal, the gate electrode terminal, the drain electrode pattern, the drain electrode terminal, the source electrode pattern, and the common electrode terminal on the protective layer comprises:
Coating a photoresist material on the protective layer;
Masking a portion except a space for forming the source electrode terminal, the gate electrode terminal, the drain electrode pattern, the drain electrode terminal, the source electrode pattern, and the common electrode terminal;
Forming a metal layer on the protective layer; And
And removing the photoresist material on which the metal layer is formed. Forming a gate line in a first direction on a substrate for display;
Forming a data line in a second direction that intersects the first direction;
Forming a common line in the first direction and spaced apart from the gate line;
Forming a power supply line formed in the second direction and spaced apart from the data line; And
A method of manufacturing a display device comprising the step of mounting a light emitting diode chip according to any one of claims 6 to 9 on a display substrate.

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