KR20180000653A - Fan-out semiconductor package - Google Patents

Fan-out semiconductor package Download PDF

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Publication number
KR20180000653A
KR20180000653A KR1020160094309A KR20160094309A KR20180000653A KR 20180000653 A KR20180000653 A KR 20180000653A KR 1020160094309 A KR1020160094309 A KR 1020160094309A KR 20160094309 A KR20160094309 A KR 20160094309A KR 20180000653 A KR20180000653 A KR 20180000653A
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South Korea
Prior art keywords
layer
connection
fan
semiconductor package
connection member
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KR1020160094309A
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Korean (ko)
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KR101952861B1 (en
Inventor
이상규
김진구
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삼성전기주식회사
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Priority to TW106112104A priority Critical patent/TWI636529B/en
Priority to US15/489,117 priority patent/US10043772B2/en
Publication of KR20180000653A publication Critical patent/KR20180000653A/en
Application granted granted Critical
Publication of KR101952861B1 publication Critical patent/KR101952861B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

The present disclosure relates to a semiconductor chip having a first connecting member having a through hole, an active surface disposed in a through hole of the first connecting member and having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface, And a sealing member for sealing at least a part of the semiconductor chip, a second connecting member disposed on the first connecting member and the semiconductor chip, and a connecting terminal disposed on the second connecting member, 1 connection member and the second connection member each include a re-wiring layer electrically connected to a connection pad of the semiconductor chip, and at least one pair of the connection pad and the connection terminal of the semiconductor chip is connected to the re- To a fan-out semiconductor package that is electrically connected through a path via a through-hole.

Description

[0001] FAN-OUT SEMICONDUCTOR PACKAGE [0002]

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package capable of extending a connection terminal to an area outside the area where the semiconductor chip is disposed.

One of the main trends of technology development related to semiconductor chips in recent years is to reduce the size of components. Accordingly, in the field of packages, it is required to implement a large number of pins with a small size in response to a surge in demand of small semiconductor chips and the like .

One of the proposed package technologies to meet this is the fan-out package. The fan-out package rewires the connection terminal to the area outside the area where the semiconductor chip is disposed, thereby enabling a small number of pins to be realized while having a small size.

One of the objects of the present disclosure is to provide a new structure of a fan-out semiconductor package that can improve performance and improve board level reliability.

One of the solutions proposed through the present disclosure is to connect the connection pad of the semiconductor chip to the connection terminal via, for example, a serpentine path so that the stress transmitted from the connection terminal is canceled in the course of passing through this path .

For example, a fan-out semiconductor package according to the present disclosure includes a first connection member having a through-hole, an active surface disposed in the through-hole of the first connection member and disposed on the opposite side of the active surface, A sealing member for sealing at least a part of the semiconductor chip, a first connecting member and a second connecting member disposed on the semiconductor chip, and a connecting terminal disposed on the second connecting member, Wherein the first connection member and the second connection member each include a re-wiring layer electrically connected to the connection pads of the semiconductor chip, and at least one pair of connection pads and connection terminals of the semiconductor chip are connected to the re- And may be electrically connected through a path passing through.

It is possible to provide a novel structure of the fan-out semiconductor package which can improve the board-level reliability while improving performance as one of the effects of the present disclosure.

1 is a block diagram schematically showing an example of an electronic equipment system.
2 is a perspective view schematically showing an example of an electronic apparatus.
3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.
4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.
6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.
7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.
8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.
9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.
FIG. 10 is a schematic II 'plan view cutting-out plan view of the semiconductor package of FIG.
11 is a schematic enlarged view of A of the semiconductor package of Fig.
12 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
FIG. 13 is a schematic top view of the semiconductor package of FIG. 12 taken along line II-II '; FIG.
14 is a schematic enlarged view of B of the semiconductor package of Fig.
15 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
16 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
17 and 18 schematically show the thermal shock reliability results according to the electrical paths of the connection pads and connection terminals of the semiconductor chip.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronics

1 is a block diagram schematically showing an example of an electronic equipment system.

Referring to the drawings, an electronic device 1000 accommodates a main board 1010. The main board 1010 is physically and / or electrically connected to the chip-related components 1020, the network-related components 1030, and other components 1040. They are also combined with other components to be described later to form various signal lines 1090.

Chip related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; An application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, Analog-to-digital converters, and logic chips such as application-specific integrated circuits (ICs), and the like, but it is needless to say that other types of chip-related components may be included. It goes without saying that these components 1020 can be combined with each other.

IEEE 802.11 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, as well as any other wireless or wired Any of the standards or protocols may be included. It goes without saying that the network-related component 1030 may be combined with the chip-related component 1020, as well.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), EMI (Electro Magnetic Interference) filters and MLCC (Multi-Layer Ceramic Condenser) But is not limited to, passive components used for various other purposes, and the like. It is also understood that other components 1040 may be combined with each other with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. Other components include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (Not shown), a CD (compact disk) (not shown), and a DVD (not shown), an accelerometer (not shown), a gyroscope a digital versatile disk (not shown), and the like. However, the present invention is not limited thereto, and other components used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is needless to say that the present invention is not limited thereto and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic apparatus.

Referring to the drawings, a semiconductor package is applied to various electronic apparatuses as described above for various purposes. For example, a main board 1110 is accommodated in the body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. In addition, other components, such as the camera 1130, that are physically and / or electrically connected to the main board 1010 or not may be contained within the body 1101. Some of the components 1120 may be chip related components, and the semiconductor package 100A may be, for example, an application processor, but is not limited thereto. It is needless to say that the electronic device is not necessarily limited to the smartphone 1100, but may be another electronic device as described above.

Semiconductor package

In general, a semiconductor chip has many microelectronic circuits integrated therein, but itself can not serve as a finished product of a semiconductor, and there is a possibility of being damaged by external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, and the semiconductor chip is packaged and used as electronic devices in a package state.

The reason for the necessity of semiconductor packaging is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small. On the other hand, in the case of the main board used in electronic equipment, the size of the component mounting pad and the interval between the component mounting pads are much larger than the scale of the semiconductor chip . Therefore, there is a need for a packaging technique which makes it difficult to directly mount a semiconductor chip on such a main board and can buffer the difference in circuit width between the semiconductor chips.

The semiconductor package manufactured by such a packaging technique can be classified into a fan-in semiconductor package and a fan-out semiconductor package depending on the structure and use.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)

3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.

4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

The semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; A connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222. [ May be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a medium-level printed circuit board (PCB) as well as a main board of an electronic apparatus.

A connection member 2240 is formed on the semiconductor chip 2220 in accordance with the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. [ The connecting member 2240 is formed by forming an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220 and forming a via hole 2243h for opening the connecting pad 2222, The wiring pattern 2242 and the via 2243 can be formed. Thereafter, a passivation layer 2250 for protecting the connecting member 2240 is formed, and an under-bump metal layer 2260 or the like is formed after the opening 2251 is formed. That is, through a series of processes, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260, do.

As described above, the fan-in semiconductor package is a package in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are disposed inside the element, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost have. Accordingly, many devices incorporated in a smart phone are manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in order to implement a small-sized and fast signal transmission.

However, in the fan-in semiconductor package, all of the I / O terminals must be disposed inside the semiconductor chip, so that there are many space limitations. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package can not be directly mounted on the main board of the electronic device. This is because even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have a size and a gap enough to be directly mounted on the electronic device main board.

5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.

6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.

Referring to the drawing, the fan-in semiconductor package 2200 is again rewired with the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals through the interposer substrate 2301, May be mounted on the main board 2500 of the electronic device with the fan-in semiconductor package 2200 mounted on the interposer substrate 2301. At this time, the solder ball 2270 and the like can be fixed with the underfill resin 2280 and the outside can be covered with the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the interposer substrate 2302 may be embedded in the connection pads 2220 of the semiconductor chip 2220, The I / O terminals 2222, i.e., the I / O terminals, may be re-routed again and finally mounted on the main board 2500 of the electronic device.

Since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic apparatus, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, And is mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.

In the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member 2120. [ The semiconductor chip 2120 is rewound to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connecting member 2140, and an under bump metal layer 2160 may be further formed on the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 includes an insulating layer 2141, a re-wiring layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connecting pad 2122 and the re-wiring layer 2142 .

As described above, the fan-out semiconductor package is formed by rewiring the I / O terminals to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip. If the element size is reduced, the ball size and pitch must be reduced. On the other hand, in the fan-out semiconductor package, the I / O terminals are rewired to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip so that the size of the semiconductor chip is reduced. And can be mounted on a main board of an electronic device without a separate interposer substrate as will be described later.

8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes a connection member 2120 that can rewire the connection pad 2122 to the fan-out area beyond the size of the semiconductor chip 2120 on the semiconductor chip 2120, The standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of the electronic apparatus without a separate interposer substrate or the like.

Since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the thickness of the fan-out semiconductor package can be reduced compared to a fan-in semiconductor package using the interposer substrate. Do. In addition, it has excellent thermal characteristics and electrical characteristics and is particularly suitable for mobile products. In addition, it can be implemented more compact than a general POP (Package on Package) type using a printed circuit board (PCB), and it is possible to solve a problem caused by a bending phenomenon.

On the other hand, the fan-out semiconductor package means a package technology for mounting the semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from an external impact, and the scale, (PCB) such as an interposer substrate having a built-in fan-in semiconductor package.

Hereinafter, a novel structure of a fan-out semiconductor package capable of improving the board level reliability with excellent performance will be described with reference to the drawings.

9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

10 is a schematic top plan view of the semiconductor package of FIG. 9 taken along the line I-I ';

11 is a schematic enlarged view of A of the semiconductor package of Fig.

Referring to FIG. 1, a fan-out semiconductor package 100A according to an exemplary embodiment includes a first connecting member 110 having a through hole 110H, a first connecting member 110 having a through hole 110H and a connection pad 122 A sealing member 130 for sealing at least a part of the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120, A second connection member 140 for rewiring the pad 122 to the fan-out region, an opening portion for exposing at least a part of the connection terminal pads of the second connection member 140, disposed on the second connection member 140, An underbuffer metal layer 160 disposed on the opening 151 of the passivation layer 150 and a connection terminal 170 disposed on the underbump metal layer 160 .

At this time, at least one (122-1) of the connection pads 122 of the semiconductor chip 120, for example, the connection pads 122-1 disposed on the outer side where the stress is concentrated, The via 143-1a of the second connection member 140, the re-distribution layer 142-1a of the second connection member 140, the via 143-1b of the second connection member 140, and the re-distribution layer 112a -1), the via 143-1c of the second connection member 140, and the redistribution layer 142-1b of the second connection member 140 in this order or in the reverse order, And is electrically connected to at least one of the connection terminals 170 through the connection terminal 170-1.

Generally, when the fan-out semiconductor package is directly mounted on a main board of an electronic device, stress due to thermal expansion and contraction of the main board can be transmitted to the semiconductor package through the connection terminal. If stress is not dispersed, fracture may occur inside the connection pads of the semiconductor chip, and open failure of vias in the re-wiring layer connected thereto may occur. This stress is particularly exerted on the outer region of the package, specifically the outer region surrounding it rather than the central region, with reference to the through-hole through which the semiconductor chip is disposed.

On the other hand, at least one (122-1) of the connection pads 122 of the semiconductor chip 120, such as the fan-out semiconductor package 100A according to the example, (170-1) of the connection terminals 170 through the path P1 via the re-distribution layer 112a-1 disposed on one side of the first connection member 110 as described above, The path P1 may be, for example, a meander shape in vertical cross section, and the direction may be alternately changed in one direction and the other direction. In this case, The stress transmitted from the post-connection terminal can be canceled in the course of passing through this path. As a result, board level reliability can be improved.

On the other hand, the horizontal cross-sectional areas b1 and b2 of some of the via pads 112aP1 and 112aP2 of the rewiring layer 112a-1 formed on one side of the first connecting member 110 are equal to the horizontal cross- ). ≪ / RTI > For example, the ratio (b1 or b2 / a) thereof may be about 1 to 2, and more preferably about 1 to 2 or less. The horizontal cross-sectional areas b1 and b2 of some of the via pads 112aP1 and 112aP2 of the redistribution layer 112a-1 formed on one side of the first connection member 110 are smaller than those of the redistribution layer 142 of the second connection member 140 -1a of the via pads 142P1 and 142P2. For example, the ratio (b1 or b2 / c1 or c2) may be about 1 to 2, more preferably about 1 to 2 or less. The horizontal cross-sectional area a of the connection pad 122-1 is larger than the horizontal cross-sectional areas c1 and c2 of some of the via pads 142P1 and 142P2 of the re-distribution layer 142-1a of the second connection member 140 Lt; / RTI > For example, the ratio (a / c1 or c2) may be about 1 to 2, more preferably about 1 to 2 or less. When such a large and small relationship is satisfied, the process consistency of the vias 143-1a and 143-1b of the second connection member 140 can be improved.

More specifically, the fan-out semiconductor package 100A according to the example is formed by, for example, forming the first connecting member 110 first, placing the semiconductor chip 120 inside the first connecting member 110 , Sealing them with the sealing material 130, and forming the second connecting member 140 on one side thereof. At this time, the vias 143-1a and 143-1b of the second connection member 140 are electrically connected to the semiconductor chip 120 by the tolerance generated when the semiconductor chip 120 is disposed, the shrinkage of the sealing member 130, Bonding properties may be deteriorated when the connection pads 122-1 of the chip 120 and the via pads 112aP1 and 112aP2 of the first connection member 110 are connected. In order to cover the tolerance, the horizontal cross-sectional areas (a, b1, b2) of the connection pads 122-1 of the semiconductor chip 120 and the via pads 112aP1, 112aP2 of the first connection member 110 should be widened. The width of the connection pad 122-1 of the connection pad 120 is limited. Therefore, it is preferable that the horizontal cross-sectional areas b1 and b2 of the via pads 112aP1 and 112aP2 of the first connection member 110 are relatively largest to cover tolerances that may be caused by various causes.

In an analogous manner, the fan-out semiconductor package 100A according to the example has the same structure as the fan-out semiconductor package 100A except that the exposed horizontal cross-sectional area (not shown) of the connection pad 122-1 is connected to the via 143-1a of the second connection member 140 (Not shown) of the connection area (not shown). The horizontal cross-sectional areas b1 and b2 of some of the via pads 112aP1 and 112aP2 of the rewiring layer 112a-1 formed on one side of the first connecting member 110 are connected to the vias of the second connecting member 140, (Not shown) of the connection area 143-1b. In this case, similarly, the process consistency of the vias 143-1a and 143-1b of the second connection member 140 can be improved.

Hereinafter, each configuration included in the fan-out semiconductor package 100A according to the example will be described in more detail.

The first connection member 110 can perform the functions of maintaining the rigidity of the package 100A and securing the thickness uniformity of the sealing material 130. [ It is also possible to reduce the number of bars of the second connection member 140 including the redistribution layers 112a and 112b for rewiring the connection pads 122 of the semiconductor chip 120. [ The first connecting member 110 has a through hole 110H. In the through hole 110H, the semiconductor chip 120 is disposed to be spaced apart from the first connection member 110 by a predetermined distance. The periphery of the side surface of the semiconductor chip 120 may be surrounded by the first connection member 110. However, this is merely an example and can be variously modified in other forms.

The first connecting member 110 includes an insulating layer 111. The first connection member 110 includes redistribution layers 112a and 112b disposed on one side and the other side of the insulating layer 111. [ If necessary, the first connecting member 110 may include a metal layer 112C disposed on a wall surface of the through hole 110H. Although the first connecting member 110 is shown as being composed of two insulating layers 111a and 111b, the number of insulating layers may be larger than this.

The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as glass cloth and / or an inorganic filler, Prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (bismaleimide triazine), etc. may be used. If necessary, a photo-insensitive dielectric (PID) resin may be used as an insulating material.

The rewiring layers 112a and 112b serve to rewire the connection pads 122 and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn) , Nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 112a and 112b can perform various functions according to the design design of the layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, it can serve as a via pad, a connection terminal pad, and the like.

The metal layer 112C serves to block heat generated by the semiconductor chip 120 and electromagnetic waves. The metal layer 112C is disposed on the wall surface of the through hole 110H to surround the semiconductor chip 120. [ Accordingly, the heat generated from the semiconductor chip 120 can be effectively transferred laterally and then discharged to the upper and lower portions. Further, the electromagnetic wave can be effectively blocked. The metal layer 112C may also be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium Of a conductive material can be used. In some cases, the metal layer 112C may be connected to the redistribution layers 112a and 112b and may be used as a ground (GND) pattern or the like.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit may be an application processor chip such as a known semiconductor chip, e.g., a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, But is not limited thereto.

The semiconductor chip 120 includes a body 121, a connection pad 122 formed on one surface of the body 121, and a passivation film 123 formed on one surface of the body 121 and covering a part of the connection pad 122 ). The body 121 may be formed based on, for example, an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as the base material. The connection pad 122 is for electrically connecting the semiconductor chip 120 to other components, and a conductive material, preferably aluminum (Al), may be used as the forming material. The connection pad 122 is rewired by the second connection member 140, the first connection member 110, and the like. In the semiconductor chip 120, the surface on which the connection pad 122 is disposed becomes the active surface and the surface on the opposite side becomes the inactive surface. The passivation film 123 functions to protect the body 121 from the outside. For example, the passivation film 123 may be formed of an oxide film such as SiO or a nitride film such as SiN, or may be formed of a double layer of an oxide film and a nitride film have. In addition, an insulating film (not shown) such as SiO 2 may be further disposed between the body 121 and the connection pad 122, or between the body 121 and the passivation film 123.

The sealing member 130 is an additional structure for protecting the first connecting member 110 and / or the semiconductor chip 120. [ The sealing shape is not particularly limited and may be a shape that covers at least a part of the first connection member 110 and / or the semiconductor chip 120. For example, the sealing material 130 may cover the upper side of the first connecting member 110 and the semiconductor chip 120, and may fill a space between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120 . The sealing member 130 may fill at least a part of the space between the passivation film 123 of the semiconductor chip 120 and the second connecting member 140. [ On the other hand, by filling the through hole 110H with the sealing material 130, it can act as an adhesive according to a specific material and reduce buckling.

An opening (not shown) for opening at least a part of the re-wiring layer 112b formed on the other side of the first connection member 110 may be formed on the sealing material 130. [ The opened rewiring layer 112b may be utilized as a marking pattern. Alternatively, a separate connection terminal or the like may be connected to the opened rewiring layer 112b to be applied to the package-on-package structure, and the surface mounted component SMT may be disposed on the rewiring layer 112b.

The specific material of the sealing material 130 is not particularly limited, and for example, an insulating material may be used. More specifically, for example, ABF (Ajinomoto Build-up Film) including an inorganic filler and an insulating resin but not containing glass cloth may be used as the material of the sealing material 130. In this case, the void problem or dilamination problem can be solved. On the other hand, the inorganic filler may be a known inorganic filler, and the insulating resin may be a known epoxy resin or the like, but is not limited thereto.

The second connection member 140 is a structure for rewiring the connection pad 122 of the semiconductor chip 120 to the fan-in and / or fan-out area. Several hundreds of connection pads 122 having various functions may be rewired through the second connection member 140 and may be physically and / or electrically connected to the outside through the connection terminal 170 described later . The second connection member 140 includes an insulating layer 141, a re-wiring layer 142 disposed on the insulating layer 141, and a via 143 connecting the re-wiring layer 142 through the insulating layer 141. [ .

As the material of the insulating layer 141, an insulating material may be used. In addition to the above-described insulating material, a photosensitive insulating material such as a PID resin may be used as the insulating material. In this case, the insulating layer 141 can be formed to be thinner, and the pitch of the via 143 can be more easily achieved. When the insulating layer 141 is a plurality of layers, these materials may be the same or different from each other. When the insulating layer 141 is a plurality of layers, they may be unified according to the process, and the boundaries may be unclear.

The rewiring layer 142 substantially rewires the connection pad 122 and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) , Nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The re-distribution layer 142 may perform various functions according to the design of the layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, it can serve as a via pad, a connection terminal pad, and the like. A surface treatment layer (not shown) may be further formed on the re-distribution layer 142, which is partially opened to the outside of the re-distribution layer 142, if necessary. The surface treatment layer (not shown) is not particularly limited as long as it is known in the art, and examples thereof include electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / , DIG plating, HASL, or the like.

The via 143 electrically connects the re-wiring layer 142, the connection pad 122, and the like formed in the different layers, thereby forming an electrical path in the package 100A. The via 143 may also be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. Vias 143 may also be fully filled with conductive material, or the conductive material may be formed only along the walls of the via. Further, all known shapes such as a tapered shape, a cylindrical shape, and the like can be applied to the vertical cross-sectional shape.

Although the second connection member 140 is illustrated as having one insulation layer 141 and the corresponding re-wiring layer 142 and the via 143 in the drawing, the present invention is not limited thereto, and the second connection member 140 ), It is of course possible to have a greater number of layers of insulating layers, so that a greater number of layers of re-wiring and vias may be formed. That is, the second connection member 140 may be formed of a plurality of layers.

The passivation layer 150 is a structure that can be introduced as needed and is configured to protect the second connection member 140 from external physical chemical damage or the like. The passivation layer 150 may have an opening 151 for opening at least a portion of the re-wiring layer 142 of the second connection member 140, that is, at least a portion of the connection terminal pad. The openings 151 may be formed in the passivation layer 150 in several tens to several thousands.

The material of the passivation layer 150 is not particularly limited, and for example, a photosensitive insulating material such as a photosensitive insulating resin can be used. Alternatively, a solder resist may be used. Alternatively, an insulating material including a filler and a resin but not containing glass cloth, such as ABF, may be used. The surface roughness of the passivation layer 150 may be lower than that of the general case. When the surface roughness is low as described above, various side effects that may occur during the circuit formation process, for example, Difficulties in implementation, and the like can be improved.

The under bump metal layer 160 can be introduced as needed, improving connection reliability of a connection terminal 170 to be described later, thereby improving reliability. The underbump metal layer 160 is formed in the opening 151 of the insulating layer 141 or the passivation layer 150 to be connected to the open rewiring layer 142. The under bump metal layer 160 may include a seed layer, and a conductor layer formed on the seed layer. The seed layer and the conductor layer may include a known conductive material, but may preferably include electroless copper and electrolytic copper, respectively. The seed layer may be thinner than the conductor layer.

The connection terminal 170 is a structure for physically and / or electrically connecting the package 100A to the outside. For example, the fan-out semiconductor package 100A according to the example can be directly mounted on the motherboard of the electronic device through the connection terminal 170. [ The connection terminal 170 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The connection terminal 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed as a multilayer or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. . The number, spacing, arrangement type, etc. of the connection terminals 170 are not particularly limited and can be sufficiently modified according to the design specifications of the ordinary artisan. For example, the number of the connection terminals 170 may be several tens to several thousand, depending on the number of the connection pads 122 of the semiconductor chip 120, but is not limited thereto and may be more or less have.

At least one of the connection terminals 170 is disposed in a fan-out region. The fan-out area is an area outside the area where the semiconductor chip 120 is disposed. That is, the exemplary fan-out semiconductor package 100A is a fan-out package. The fan-out package is more reliable than the fan-in package, allows multiple I / O terminals, and facilitates 3D interconnection. In addition, compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to manufacture a thin bar package that can be mounted on electronic devices without a separate substrate, and is excellent in price competitiveness.

Although not shown in the drawings, a plurality of semiconductor chips may be disposed in the through hole 110H of the first connection member 110, and a plurality of through holes 110H of the first connection member 110 may be provided, The semiconductor chips may be arranged in the respective through holes. Further, in addition to the semiconductor chip, another passive component, for example, a capacitor, an inductor, etc., can be sealed together in the through hole 110H. Also, surface mount components may be mounted on the passivation layer 150.

12 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

FIG. 13 is a schematic top view of the semiconductor package of FIG. 12 taken along line II-II '; FIG.

14 is a schematic enlarged view of B of the semiconductor package of Fig.

Referring to FIG. 1, a fan-out semiconductor package 100B according to another embodiment includes a first connection member 110 having a through hole 110H, a connection pad 122H disposed in a through hole 110H A sealing member 130 for sealing at least a part of the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120, A second connection member 140 for rewiring the pad 122 to the fan-out region, an opening portion for exposing at least a part of the connection terminal pads of the second connection member 140, disposed on the second connection member 140, An underbuffer metal layer 160 disposed on the opening 151 of the passivation layer 150 and a connection terminal 170 disposed on the underbump metal layer 160 .

At this time, at least one (122-2) of the connection pads 122 of the semiconductor chip 120, for example, the connection pad 122-2 disposed on the outer side where the stress is concentrated, The via 143-2a of the second connection member 140, the re-wiring layer 142-2a of the second connection member 140, the via 143-2b of the second connection member 140, The via 113-2 of the first connection member 110, the redistribution layer 112b-2 of the first connection member 110, the via 113-2b of the first connection member 110, The re-wiring layer 112a-2b of the first connecting member 110, the via 143-2c of the second connecting member 140, and the re-wiring layer 142-1b of the second connecting member 140 are arranged in this order And is electrically connected to at least one of the connection terminals 170 through a path P2 that passes through the connection terminal 170 in the reverse order.

As described above, at least one (122-2) of the connection pads 122 of the semiconductor chip 120, for example, the connection pads 122-2 disposed on the outer side where the stress is concentrated, At least one of the connection terminals 170 is connected via the path P2 via all of the re-wiring layers 112a-2a and 112a-2b disposed on one side of the member 110 and the re-wiring layer 112b- The path P2 may be similarly formed in the shape of a vertical section in the meander shape and the direction thereof may alternately be changed to one side direction and the other side direction As a result, the stress transmitted from the connection terminal after board mounting can be canceled in the course of passing through this path, thereby improving the board level reliability.

On the other hand, the horizontal cross-sectional areas b1 and b2 of some of the via pads 112aP1 and 112aP2 among the rewiring layers 112a-2a and 112a-2b formed on one side of the first connecting member 110 are equal to the horizontal cross- And may have a size larger than the horizontal cross-sectional area (a). For example, the ratio (b1 or b2 / a) thereof may be about 1 to 2, and more preferably about 1 to 2 or less. The horizontal cross-sectional areas b1 and b2 of some of the via pads 112aP1 and 112aP2 of the rewiring layers 112a-2a and 112a-2b formed on one side of the first connection member 110 are equal to the horizontal cross- Sectional dimensions c1 and c2 of some of the via pads 142P1 and 142P2 in the re-distribution layer 142-2a. For example, the ratio (b1 or b2 / c1 or c2) may be about 1 to 2, more preferably about 1 to 2 or less. The horizontal cross-sectional area a of the connection pad 122-2 is larger than the horizontal cross-sectional areas c1 and c2 of some of the via pads 142P1 and 142P2 of the redistribution layer 142-2a of the second connection member 140 Lt; / RTI > For example, the ratio (a / c1 or c2) may be about 1 to 2, more preferably about 1 to 2 or less. In this case, the process consistency of the vias 143-2a and 143-2b of the second connection member 140 can be improved.

For example, the first connecting member 110 may be formed first, and the semiconductor chip 120 may be disposed inside the first connecting member 110. In this case, , Sealing them with the sealing material 130, and forming the second connecting member 140 on one side thereof. At this time, the vias 143-2a and 143-2b of the second connection member 140 are electrically connected to the semiconductor chip 120 by the tolerance generated by the arrangement of the semiconductor chip 120, the contraction of the sealing member 130, Bonding properties may be deteriorated when the connection pad 122-2 of the chip 120 and the via pads 112aP1 and 112aP2 of the first connection member 110 are connected. In order to cover the tolerance, the horizontal cross-sectional areas a, b1 and b2 of the connection pads 122-2 of the semiconductor chip 120 and the via pads 112aP1 and 112aP2 of the first connection member 110 must be widened. The width of the connection pad 122-2 of the connection pad 120 is limited. Therefore, it is preferable that the horizontal cross-sectional areas b1 and b2 of the via pads 112aP1 and 112aP2 of the first connection member 110 are relatively widest to cover tolerances that may be caused by various causes.

In a similar perspective, the fan-out semiconductor package 100B according to another example is configured such that the exposed horizontal cross-sectional area (not shown) of the connection pad 122-2 is connected to the via 143- 2a (not shown). The horizontal cross sectional areas b1 and b2 of some of the via pads 112aP1 and 112aP2 of the rewiring layer 112a-2 formed on one side of the first connecting member 110 are connected to the vias of the second connecting member 140, (Not shown) of the connection area 143-2b. In this case, it is also possible to improve the process consistency of the vias 143-2a and 143-2b of the second connection member 140.

The horizontal cross-sectional areas b1 and b2 of the via pads 112aP1 and 112aP2 of the rewiring layer 112a-2 formed on one side of the first connection member 110 are smaller than those of the first connection member 110, Sectional dimensions b3 and b4 of some of the via pads 112bP1 and 112bP2 in the wiring layer 112b-2. The portion related to the tolerance is formed by the via pads 112aP1 and 112aP2 of the rewiring layer 112a-2 formed on one side and the via pads 112aP1 and 112aP2 are formed such that the horizontal sectional areas b1 and b2 are larger than the horizontal sectional areas b3 and b4. (112aP1, 112aP2) may be formed.

Meanwhile, the vias 113 electrically connect the redistribution layers 112a and 112b formed in the different layers, thereby forming an electrical path in the first connection member 110. [ The vias 113 may also be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. The via 113 may be completely filled with a conductive material, or a conductive material may be formed along the wall surface of the via hole. Further, not only a cylindrical shape in a vertical cross-sectional shape but also all shapes known in the art such as a taper shape, an hourglass shape, and the like can be applied. On the other hand, although not shown in the drawing, in the case where the insulating layer is composed of a plurality of layers, a re-wiring layer may be further formed between the insulating layers. In this case, the vias may also be composed of a plurality of layers.

Other configurations are substantially the same as those described in the fan-out semiconductor package 100A according to the example, and a detailed description thereof will be omitted.

15 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100C according to another example also includes a first connection member 110 having a through hole 110H, a connection pad 122H disposed in a through hole 110H such that the connection pad 122 faces one side A sealing member 130 for sealing at least a part of the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120 A second connection member 140 for rewiring the connection pad 122 to the fan-out region, a second connection member 140 disposed on the second connection member 140 and for exposing at least a part of the connection terminal pads of the second connection member 140 An underbump metal layer 160 disposed on the opening 151 of the passivation layer 150 and a connection terminal 170 disposed on the underbump metal layer 160. The passivation layer 150 includes an opening 151, do.

The first connection member 110 includes a first insulation layer 111a contacting the second connection member 140 and a first rewiring layer 112a which contacts the second connection member 140 and is embedded in the first insulation layer 111a. A second redistribution layer 112b disposed on the opposite side of the first insulation layer 111a on the side where the first redistribution layer 112a is embedded; a second redistribution layer 112b disposed on the first insulation layer 111a, A second insulating layer 111b covering the first insulating layer 112b and a third redistribution layer 112c disposed on the second insulating layer 111b. The fan-out semiconductor package 100C according to another example is configured such that the first connecting member 110 includes a greater number of redistribution layers 112a, 112b, and 112c and further simplifies the second connecting member 140 . Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the second linking member 140. Although not shown in the drawing, the first to third rewiring layers 112a, 112b and 112c may be electrically connected through vias (not shown) passing through the first and second insulation layers 111a and 111b .

The lower surface of the first redistribution layer 112a of the first connection member 110 may be located above the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the redistribution layer 142a of the second connection member 140 and the redistribution layer 112a of the first connection member 110 is larger than the distance between the redistribution layer 142a of the second connection member 140 and the semiconductor chip 120 May be greater than the distance between the connection pads 122. This is because the first rewiring layer 112a can be recessed into the insulating layer 111. [ The second rewiring layer 112b of the first connection member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first connection member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor chip 120 so that the second rewiring layer 112b formed in the first connection member 110 is electrically connected to the semiconductor chip 120 May be disposed at a level between the active surface and the inactive surface. The thickness of the redistribution layers 112a, 112b and 112c of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. [ The first connection member 110 may have a thickness greater than that of the semiconductor chip 120 and the rewiring layers 112a, 112b, and 112c may be formed to have a larger size in accordance with the scale. On the other hand, the redistribution layers 142a and 142b of the second connection member 140 can be formed in a relatively small size in order to reduce the thickness.

At least one of the connection pads 122 of the semiconductor chip 120, for example, a connection pad disposed on the outer side where stress is concentrated, is electrically connected to the via 143 of the second connection member 140, The vias 143 of the second connection member 140, the first rewiring layer 112a of the first connection member 110, the vias 143 of the second connection member 140, The rewiring layer 142 of the second connection member 140 may be electrically connected to at least one of the connection terminals 170 via the path P3 passing in this order or in the reverse order. Although not shown in the drawing, the path P3 is formed by connecting the first rewiring layer 112a of the first connection member 110, the first rewiring layer 112a of the first connection member 110, (Not shown) of the first connection member 110 and the first via (not shown) of the connection member 110, the second rewiring layer 112b of the first connection member 110, The first rewiring layer 112a of the member 110 may be passed in this order or in the reverse order. Alternatively, although not shown in the figure, the path P3 may be formed in a manner such that the first rewiring layer 112a of the first connection member 110, the first rewiring layer 112a of the first connection member 110, (Not shown) of the first connection member 110, a second rewiring layer 112b of the first connection member 110, a second via (not shown) of the first connection member 110, The third rewiring layer 112c of the connecting member 110, the second via (not shown) of the first connecting member 110, the second rewiring layer 112b of the first connecting member 110, (Not shown) of the first connection member 110 and the first rewiring layer 112a of the first connection member 110 in this order or in the reverse order. In this case, similarly, it is possible to improve the board level reliability.

Other configurations are substantially the same as those described in the fan-out semiconductor package 100A according to the example, and a detailed description thereof will be omitted.

16 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to FIG. 1, a fan-out semiconductor package 100D according to another embodiment includes a first connection member 110 having a through hole 110H, a connection pad 122H disposed in a through hole 110H A sealing member 130 for sealing at least a part of the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120, the first connecting member 110 and the semiconductor chip 120 A second connection member 140 for rewiring the connection pad 122 to the fan-out region, a second connection member 140 disposed on the second connection member 140 and for exposing at least a part of the connection terminal pads of the second connection member 140 An underbump metal layer 160 disposed on the opening 151 of the passivation layer 150 and a connection terminal 170 disposed on the underbump metal layer 160. The passivation layer 150 includes an opening 151, do.

The first connecting member 110 includes a first insulating layer 111a, a first redistribution layer 112a and a second redistribution layer 112b disposed on both surfaces of the first insulating layer 111a, a first insulating layer 112a , A third rewiring layer 111c disposed on the second insulating layer 111b, and a second rewiring layer 111c disposed on the first rewiring layer 112a and covering the first rewiring layer 112a, A third insulating layer 111c disposed to cover the second redistribution layer 112b and a fourth redistribution layer 112d disposed on the third insulating layer 111c. The fan-out semiconductor package 100D according to another example may also include the first connecting member 110 including a greater number of redistribution layers 112a, 112b, 112c and 112d, It can be simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the second linking member 140. The first to fourth rewiring layers 112a, 112b, 112c and 112d are electrically connected through vias (not shown) passing through the first to third insulation layers 111a, 111b and 111c .

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity and the second insulating layer 111b and the third insulating layer 111c may form a larger number of redistribution layers 112c and 112d May be introduced. The first insulating layer 111a may include an insulating material different from the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including glass cloth, an inorganic filler, and an insulating resin, and the second insulating layer 111c and the third insulating layer 111c may be inorganic But is not limited to, an ABF film or a photosensitive insulating film including a filler and an insulating resin. The lower surface of the third redistribution layer 112c of the first connection member 110 may be located below the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the redistribution layer 142a of the second connection member 140 and the third redistribution layer 112c of the first connection member 110 is larger than the distance between the redistribution layer 142a of the second connection member 140 and the semiconductor chip 120 The connection pads 122 of the first and second connection pads 122a and 122b. This is because the third rewiring layer 112c can be disposed on the second insulating layer 111b so as to be in contact with the second connection member 140. [ The first redistribution layer 112a and the second redistribution layer 112b of the first connection member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first connecting member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor chip 120 so that the first rewiring layer 112a and the second rewiring layer 112b May be disposed at a level between the active surface and the inactive surface of the semiconductor chip 120. The thickness of the redistribution layers 112a, 112b, 112c and 112d of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. [ The first connection member 110 may have a thickness greater than that of the semiconductor chip 120 and the rewiring layers 112a, 112b, 112c and 112d may be formed in a larger size. On the other hand, the redistribution layers 142a and 142b of the second connection member 140 can be formed in a relatively small size in order to reduce the thickness.

At least one of the connection pads 122 of the semiconductor chip 120, for example, a connection pad disposed on the outer side where stress is concentrated, is electrically connected to the via 143 of the second connection member 140, The vias 143 of the second connection member 140, the third rewiring layer 112c of the first connection member 110, the vias 143 of the second connection member 140, The rewiring layer 142 of the second connection member 140 may be electrically connected to at least one of the connection terminals 170 via the path P4 passing in this order or in the reverse order. Although not shown in the drawing, the path P4 is formed by connecting the third rewiring layer 112c of the first connecting member 110, the first rewiring layer 112c of the first connecting member 110, (Not shown) of the connecting member 110, a first rewiring layer 112a of the first connecting member 110, a second via (not shown) of the first connecting member 110, And the third rewiring layer 112c of the member 110 may be passed in this order or in the reverse order. Alternatively, although not shown in the drawing, the path P4 may be formed by connecting the third rewiring layer 112c of the first connection member 110, the third rewiring layer 112c of the first connection member 110, (Not shown) of the first connection member 110, the first rewiring layer 112a of the first connection member 110, the first via (not shown) of the first connection member 110, The first rewiring layer 112a of the first connection member 110 and the second via hole 112b of the first connection member 110 of the connection member 110 are electrically connected to each other through the first via hole 112a of the first connection member 110, (Not shown) of the first connection member 110 and the third redistribution layer 112c of the first connection member 110 in this order or in the reverse order. Alternatively, although not shown in the drawing, the path P4 may be formed by connecting the third rewiring layer 112c of the first connection member 110, the third rewiring layer 112c of the first connection member 110, (Not shown) of the first connection member 110, the first rewiring layer 112a of the first connection member 110, the first via (not shown) of the first connection member 110, The second wiring layer 112b of the connection member 110, the third via (not shown) of the first connection member 110, the fourth redistribution layer 112d of the first connection member 110, (Not shown) of the first connection member 110, a second via hole 112b of the first connection member 110, a first connection member 110 (not shown) of the first connection member 110, (Not shown) of the first connection member 110 and the third redistribution layer 112c of the first connection member 110 in this order or in the reverse order . In this case, similarly, it is possible to improve the board level reliability.

Other configurations are substantially the same as those described in the fan-out semiconductor package 100A according to the example, and a detailed description thereof will be omitted.

17 and 18 schematically show the thermal shock reliability results according to the electrical paths of the connection pads and connection terminals of the semiconductor chip.

Referring to the drawings, the thermal shock reliability results of the embodiment and the comparative examples 1 and 2 are remarkable. Particularly in the embodiment, the number of the first failure occurrence cycles is 2,013 times, which is about 5 times higher than the first failure cycle number of the comparative example 1 Fold. ≪ / RTI > It is also found that the thermal shock resistance is twice as high as that of the comparative example 2. In the meantime, in the embodiment shown in the drawing, when the connection pads and the connection terminals in the region where the stress is concentrated as in the fan-out semiconductor package 100A according to the example are electrically connected through a route passing through the re- In Comparative Example 1, the connection pads and connection terminals are electrically connected via a stacked via via a vertical path. In Comparative Example 2, connection pads and connection terminals are connected through a staggered via, Through a staggered path. At this time, the design and fabrication specifications of the via size of the re-distribution layer (40 um), the thickness of the insulation layer of the re-distribution layer, the size of the solder ball used as the connection terminal, Under these conditions, Daisy chain was constructed and thermal shock test was conducted to determine the opening tendency of the via due to thermal shock.

The expression " exemplary " used in this disclosure does not mean the same embodiment but is provided for emphasizing and explaining different unique features. However, the above-mentioned examples do not exclude that they are implemented in combination with the features of other examples. For example, although the description in the specific example is not described in another example, it can be understood as an explanation related to another example, unless otherwise described or contradicted by the other example.

In the present disclosure, the meaning of being connected is not a direct connection but a concept including an indirect connection. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection. Also, the first, second, etc. expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

In the present disclosure, upper, lower, upper, lower, upper, lower, and the like are determined based on the attached drawings. For example, the first connecting member is located above or above the re-wiring layer. In the present disclosure, the vertical direction means the above-described upper and lower directions, and the horizontal direction means the direction perpendicular thereto. In this case, the vertical cross-section means a case of cutting into a plane in the vertical direction, and the cross-sectional view shown in the figure is an example. In addition, the horizontal cross-section means a case where the horizontal cross-section is cut into a plane in the horizontal direction, and a plan view shown in the drawing is an example thereof. However, the claims are not limited thereto.

The terms used in this disclosure are used only to illustrate an example and are not intended to limit the present disclosure. Wherein the singular expressions include plural expressions unless the context clearly dictates otherwise.

1000: electronic device 1010: main board
1020: Chip related parts 1030: Network related parts
1040: Other parts 1050: Camera
1060: antenna 1070: display
1080: Battery 1090: Signal line
1100: Smartphone 1101: Smartphone body
1110: Smartphone mainboard 1111: mainboard insulation layer
1112: main board wiring 1120: parts
1130: Smartphone camera 2200: Fan-in semiconductor package
2220: Semiconductor device 2221: Body
2222: connection pad 2223: passivation film
2240: re-spreading portion 2241: insulating layer
2242: re-wiring layer 2243: via
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: Interposer substrate 2302: Interposer substrate
2100: Fan-out semiconductor package 2120: Semiconductor device
2121: Body 2122: Connection pad
2140: re-spreading portion 2141: insulating layer
2142: re-wiring layer 2143: via
2150: passivation layer 2160: under bump metal layer
2170: solder ball 100: semiconductor package
100A, 100B, 100C, 100D: a fan-out semiconductor package
P1, P2, P3, P4: path 110: connecting member
111, 111a, 111b, 111c: insulating layers 112a, 112b, 112c, 112d:
112C: metal layer 113: via
120: semiconductor chip 121: body
122: connection pad 123: passivation film
130: sealing material 131: opening
140: second connecting member 141: insulating layer
142: re-wiring layer 143: via
150: passivation layer 151: opening
160: under bump metal layer 170: connection terminal

Claims (18)

A first connecting member having a through hole;
A semiconductor chip disposed in the through hole of the first connection member and having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface;
A sealing member for sealing at least a part of the first connecting member and the semiconductor chip;
A second connection member disposed on the first connection member and the semiconductor chip; And
A connection terminal disposed on the second connection member; / RTI >
Wherein the first connection member and the second connection member each include a re-wiring layer electrically connected to a connection pad of the semiconductor chip,
Wherein at least a pair of the connection pads and the connection terminals of the semiconductor chip are electrically connected to each other through a path via the re-
A fan-out semiconductor package.
The method according to claim 1,
Wherein the path passes through the connecting terminal, the re-wiring layer of the second connecting member, the re-wiring layer of the first connecting member, the re-wiring layer of the second connecting member, and the connecting terminal in this order or in the reverse order,
A fan-out semiconductor package.
3. The method of claim 2,
Wherein the path includes a rewiring layer disposed on one side of the first connecting member, a via passing through the first connecting member, a rewiring layer disposed on the other side of the first connecting member, a via passing through the first connecting member, And the rewiring layer disposed on one side of the first linking member is passed in this order or in the reverse order,
A fan-out semiconductor package.
The method according to claim 1,
The re-wiring layer of the first connection member includes a via pad,
Sectional area of the via pad of the re-wiring layer of the first connection member is larger than the horizontal cross-sectional area of the connection pad of the semiconductor chip,
A fan-out semiconductor package.
The method according to claim 1,
The re-wiring layers of the first connection member and the second connection member each include a via pad,
Sectional area of the via pad of the re-wiring layer of the first connection member is larger than the horizontal cross-sectional area of the via pad of the re-wiring layer of the second connection member,
A fan-out semiconductor package.
The method according to claim 1,
The re-wiring layer of the second connection member includes a via pad,
Wherein the horizontal cross-sectional area of the connection pad of the semiconductor chip is larger than the horizontal cross-sectional area of the via pad of the re-
A fan-out semiconductor package.
The method according to claim 1,
Wherein the first connecting member comprises a first insulating layer, a first rewiring layer in contact with the second connecting member and embedded in the first insulating layer, and a second rewiring layer on the opposite side of the first rewiring layer, And a second redistribution layer disposed on the second redistribution layer,
A fan-out semiconductor package.
8. The method of claim 7,
Wherein the first connecting member further comprises a second insulating layer disposed on the first insulating layer and covering the second rewiring layer and a third rewiring layer disposed on the second insulating layer,
A fan-out semiconductor package.
8. The method of claim 7,
The distance between the re-wiring layer of the second connection member and the first re-distribution layer is larger than the distance between the re-distribution layer of the second connection member and the connection pad,
A fan-out semiconductor package.
8. The method of claim 7,
Wherein the first re-wiring layer is thicker than the re-wiring layer of the second connection member,
A fan-out semiconductor package.
8. The method of claim 7,
And the lower surface of the first re-distribution layer is located above the lower surface of the connection pad,
A fan-out semiconductor package.
9. The method of claim 8,
And the second re-wiring layer is located between the active surface and the inactive surface of the semiconductor chip,
A fan-out semiconductor package.
The method according to claim 1,
The first connecting member includes a first insulating layer, a first rewiring layer and a second rewiring layer disposed on both surfaces of the first insulating layer, a second rewiring layer disposed on the first insulating layer, An insulating layer, and a third rewiring layer disposed on the second insulating layer,
A fan-out semiconductor package.
14. The method of claim 13,
Wherein the first connecting member further comprises a third insulating layer disposed on the first insulating layer and covering the second rewiring layer and a fourth rewiring layer disposed on the third insulating layer,
A fan-out semiconductor package.
14. The method of claim 13,
Wherein the first insulating layer is thicker than the second insulating layer,
A fan-out semiconductor package.
14. The method of claim 13,
And the third re-wiring layer is thicker than the re-wiring layer of the second connection member,
A fan-out semiconductor package.
14. The method of claim 13,
Wherein the first re-distribution layer is positioned between an active surface and an inactive surface of the semiconductor chip,
A fan-out semiconductor package.
14. The method of claim 13,
And the lower surface of the third re-wiring layer is located below the lower surface of the connection pad,
A fan-out semiconductor package.
KR1020160094309A 2016-06-23 2016-07-25 Fan-out semiconductor package KR101952861B1 (en)

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