KR20170133787A - Apparatus and Method for Binary Calculation with Divisor 3 - Google Patents

Abstract

The present invention relates to a method for binary operations with divisor 3. The method includes: a step of dividing an inputted dividend (y) by modular 3 to calculate the rest (r); a step of deducting the rest (r) from the dividend (y) to calculate a value (y) which is able to be divided by the divisor 3; a step of searching for a value (b), which becomes a 2^N+1 when multiplied by 3, considering a bit number (n) of the dividend (y); and a step of calculating a share (x), which is calculated by dividing the dividend (y) by 3, by conducting a modular operation with a value calculated by multiplying the value (y) by the value (b). As such, the present invention is capable of considerably reducing the complexity of hardware and time for processing operations.

Description

[0001] Apparatus and Method for Binary Calculation with Divisor [

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for computing division in hardware and computer programming using a binary method (bit operation), and more particularly to an apparatus and a method for a special case in which arbitrary numbers are divided by three.

The implementation method for the divide operation is already various, and most of the methods to implement the general division rather than the division by a certain number. The simplest approach to divide operations is to subtract divisor by divisor. In this case, latency is inevitable due to iterative operation. The number of divisors, latency value is large.

On the other hand, 3 is the smallest value except the 2 that can be easily processed in the dividing number, and the minimum frequency of the divide operation is the minimum except for 2. However, since 3 is the smallest value except for 2 that can be simply processed in the dividing number, when the conventional dividing operation method or apparatus is used, even if the dividend is slightly increased, the delay increases and the value also varies depending on the size of the dividend, .

The present invention provides a binary operation method and apparatus for dividing a division operation into three, which reduces the complexity of the operation, minimizes the waiting delay, and divides the division into three by a certain number.

의 꼴이 되는 값(b)를 검색하는 단계와, 상기 값(y')에 상기 값(b)를 곱한 값을 모듈러

연산하여 상기 피제수(y)를 3으로 나눈 몫(x)을 산출하는 단계를 포함한다.The present invention relates to a method of dividing by 3 a method of calculating modulo 3 of an inputted dividend y to calculate the remainder r, calculating the remaining sum r by subtracting the calculated remainder r from the dividend y, Calculating a divided value y 'by multiplying 3 by the number of bits (n) of the dividend y,

Searching for a value (b) that is a form of a modulo (x, y); and modulo a value obtained by multiplying the value (y '

And calculating a quotient (x) by dividing the dividend (y) by three.

의 꼴이 되는 값(b)를 검색하고, 상기 값(y')에 상기 값(b)를 곱한 값을 모듈러

연산하여 상기 피제수(y)를 3으로 나눈 몫(x)을 산출하는 몫 산출부를 포함한다. The present invention relates to a binary arithmetic unit for dividing into three, comprising: a remainder calculating unit for calculating modulo 3 of an inputted dividend y to calculate a remainder (r); a subtracter for subtracting the calculated remainder (r) (Y ') divided by 3 and taking the bit number (n) of the dividend y as a reference, when multiplying by 3

(B) which is a form of the modulo (y) is multiplied by the value (b)

And calculating a quotient x by dividing the dividend y by three.

The present invention can not only perform a 3-division operation by a simple multiplication and a modulo operation but also can easily determine the number of times multiplied by the number of bits of a dividend, thereby drastically reducing hardware complexity and processing time.

의 꼴이 되는 값(b)를 검색하는 과정을 설명하기 위한 도면이다.
도 3은 b에 3을 곱하여 a가 되는 과정을 도시한 도면이다.
도 4는 본 발명의 일 실시 예에 따른 3으로 나누는 이진 연산 방법을 설명하기 위한 순서도이다.
도 5는 본 발명에 따라 3으로 나누는 연산을 수행한 예들을 도시한 도면이다.FIG. 1 is a block diagram of a binary division unit for division into three according to an embodiment of the present invention.
Fig. 2 shows a graph

(B) which is a form of a search result.
3 is a diagram showing a process of multiplying b by 3 to obtain a.
FIG. 4 is a flowchart for explaining a 3-division binary operation method according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating examples of performing an operation of dividing by 3 according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. , Which may vary depending on the intention or custom of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

Each block of the accompanying block diagrams and combinations of steps of the flowcharts may be performed by computer program instructions (execution engines), which may be stored in a general-purpose computer, special purpose computer, or other processor of a programmable data processing apparatus The instructions that are executed through the processor of the computer or other programmable data processing equipment will generate means for performing the functions described in each block or flowchart of the block diagram.

These computer program instructions may also be stored in a computer usable or computer readable memory capable of directing a computer or other programmable data processing apparatus to implement the functionality in a particular manner so that the computer usable or computer readable memory It is also possible for the instructions stored in the block diagram to produce an article of manufacture containing instruction means for performing the functions described in each block or flowchart of the flowchart.

And computer program instructions may be loaded onto a computer or other programmable data processing equipment so that a series of operating steps may be performed on a computer or other programmable data processing equipment to create a computer- It is also possible that the instructions that perform the data processing equipment provide the steps for executing the functions described in each block of the block diagram and at each step of the flowchart.

Also, each block or step may represent a portion of a module, segment, or code that includes one or more executable instructions for executing the specified logical functions, and in some alternative embodiments, It should be noted that functions may occur out of order. For example, two successive blocks or steps may actually be performed substantially concurrently, and it is also possible that the blocks or steps are performed in the reverse order of the function as needed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to enable those skilled in the art to more fully understand the present invention.

FIG. 1 is a block diagram of a binary division unit for division into three according to an embodiment of the present invention.

Referring to FIG. 1, a binary operation unit (hereinafter referred to as a "device") 100 divided by 3 includes a remaining calculation unit 110 and a quotient calculation unit 120. In addition, the memory 130 may further include a memory.

The remaining calculation unit 110 calculates modulus (3) (mod (y, 3)) to calculate the remainder (r) as the dividend y is input. Here, the modulo 3 operation can be referred to the domestic patent KR 10-1318992 (modulo N operation method and its apparatus).

The quotient calculating unit 120 calculates the quotient x by dividing the dividend y by three. That is, the dividend y can be expressed by Equation (1) below.

&Quot; (1) "

y = 3x + r

The quotient calculating unit 120 first subtracts the remainder r calculated from the dividend y and calculates a value y 'divided by three. That is, the value y 'can be expressed as Equation (2) below.

&Quot; (2) "

y '= y-r = y-mod (y, 3) = 3x

의 꼴이 되는 값(b)를 검색한다. 일 실시 예에 따라, N은 2m+3이 되는 조건을 만족하는 수일 수 있다. 따라서, 하기에서는 N이 2m+3인 것으로 설명하기로 한다. 즉, 몫 산출부(120)는 하기의 <수학식 3>을 만족하는 b를 검색한다. Then, the quotient calculating unit 120 calculates the number of binary bits (n) of the dividend y by multiplying 3

(B), which is the shape of the image. According to one embodiment, N may be a number satisfying the condition that 2m + 3. Therefore, in the following description, it is assumed that N is 2m + 3. That is, the quotient calculating unit 120 searches b that satisfies the following Equation (3).

&Quot; (3) &quot;

a = 3b =

Further, according to one embodiment, the quotient calculating unit 120, more specifically, determines m satisfying the condition that the value of 2m + 3 is greater than or equal to the value of n-1, and repeats '10' The binarized b whose number of times is equal to the determined m is selected.

의 꼴이 되는 미리 계산된 값(b)들을 저장하는데, 몫 산출부(120)는 저장된 값(b) 들 중 하나를 검색할 수도 있다. 이에 대한 상세한 설명은 도 2 내지 도 3을 참조하여 후술하기로 한다.Further, according to one embodiment, the memory 130 may be programmed

(B) that is a form of the stored value (b), and the quotient calculation unit 120 may retrieve one of the stored values (b). A detailed description thereof will be given later with reference to FIG. 2 to FIG.

연산하여 피제수(y)를 3으로 나눈 몫(x)을 산출한다. 즉, 상기 <수학식 2>의 양변에 산출된 값(b)를 곱하고, <수학식 3>을 대입하면 하기의 <수학식 4>와 같이 유도될 수 있다.Finally, the quotient calculating unit 120 multiplies the value (y ') by the calculated value (b)

And calculates the quotient x by dividing the dividend y by 3. That is, by multiplying the value (b) calculated on both sides of Equation (2) and substituting Equation (3), it can be derived as Equation (4).

&Quot; (4) &quot;

) y'b = 3xb = x3b = xa = x (

)

연산을 하면 몫 x는 하기의 <수학식 5>와 같이 간단히 산출될 수 있다.In the above equation (4), mod

Quot ;, the quotient x can be simply calculated as shown in Equation (5) below.

Equation (5)

x = y'b mod

의 꼴이 되는 값(b)를 검색하는 과정을 설명하기 위한 도면이고, 도 3은 b에 3을 곱하여 a가 되는 과정을 도시한 도면이다.Fig. 2 shows a graph

FIG. 3 is a diagram illustrating a process of multiplying b by 3 to obtain a value a.

의 꼴이 되는 a 값들이 도시되어 있고, 좌측에는 3을 곱하여 우측의 a 값들 되는 b 값들이 도시되어 있다. 도 2 및 도 3을 참조하면, a는 하기의 <수학식 6>과 같이 표현될 수 있다. Referring to FIG. 2,

And b values obtained by multiplying the left side by 3 and the a values on the right side are shown. Referring to FIG. 2 and FIG. 3, a can be expressed by Equation (6) below.

&Quot; (6) &quot;

연산을 이용하면 1이 되므로 곱셈연산에 유용하게 활용할 수 있다. 따라서, 본 발명에서는 이러한 성질을 이용하여 전술한 바와 같이 <수학식 5>에서 modulo

를 이용하여 x를 용이하게 산출한다. 따라서, 본 발명에서 3을 곱했을 때

의 꼴이 되는 값(b)을 검색하는 것이다. Referring to Equation (6), it can be seen that N = 2m + 3. Also, a is modulo

If it is 1, it can be used for multiplication. Therefore, in the present invention, as described above, using this property, modulo

To easily calculate x. Therefore, in the present invention, when multiplying by 3

(B), which is a form of the search result.

'이므로, m은 '0'이 되는데, b에서 '10'이 반복되는 횟수가 '0'이므로 m의 값과 동일함을 알 수 있다. 또한, 즉, b가 '1011'일 경우, a는 '

'이므로, m은 '1'이 되는데, b에서 '10'이 반복되는 횟수가 '1'이므로 m의 값과 동일함을 알 수 있다. Also, referring to FIG. 3, it can be seen that m is the number of times '10' is repeated from the upper bit in the value of binarized b. That is, when b is' 11 ', a is'

', So m is 0, which is equal to the value of m since the number of times'10' is repeated in 'b'is' 0 '. In other words, when b is' 1011 ', a is'

', So m is equal to' 1 ', and the number of times'10' is repeated in 'b'is' 1 '.

FIG. 4 is a flowchart for explaining a 3-division binary operation method according to an embodiment of the present invention.

Referring to FIG. 4, the apparatus 100 receives a modulo 3 operation mod (y, 3) according to a request to divide the dividend y, which can be expressed as Equation (1) ) To calculate the remainder r (S420).

The apparatus 100 calculates a value y 'divided by 3 by subtracting the remainder r calculated from the dividend y expressed by Equation (2) (S430).

의 꼴이 되는 값(b)를 검색한다(S440~S450). 일 실시 예에 따라, N은 2m+3이 되는 조건을 만족하는 수일 수 있다. 즉, 장치(100)는 상기의 <수학식 3>을 만족하는 b를 검색한다. Then, the apparatus 100 considers the number of binary bits (n) of the dividend y and multiplies it by 3

(B) (S440 to S450). According to one embodiment, N may be a number satisfying the condition that 2m + 3. That is, the apparatus 100 searches b that satisfies Equation (3).

의 꼴이 되는 미리 계산된 값(b)들을 저장하는데, 몫 산출부(120)는 저장된 값(b) 들 중 하나를 검색할 수도 있다. According to one embodiment, the apparatus 100 determines m that satisfies the condition that the value of 2m + 3 is greater than or equal to the value of n-1 (S440). That is, the number of bits of y may be smaller than the number of bits of a. The binarized b whose number of times '10' is repeated from the upper bit is equal to the determined m is selected (S450). Further, according to one embodiment, the memory 130 may be programmed

(B) that is a form of the stored value (b), and the quotient calculation unit 120 may retrieve one of the stored values (b).

연산하여 피제수(y)를 3으로 나눈 몫(x)을 산출한다(S460~S480). 즉, <수학식 2>의 양변에 산출된 값(b)를 곱하고(S460), <수학식 3>을 대입하여 상기의 <수학식 4>와 같이 유도하고(S470), 상기 <수학식 4>의 양변에 mod

연산을 하면 몫 x는 상기의 <수학식 5>와 같이 간단히 산출한다(S480).Finally, the device 100 multiplies the value (y ') by the calculated value (b)

And calculates the quotient x by dividing the dividend y by 3 (S460 to S480). That is, the value b calculated on both sides of Equation (2) is multiplied (S460), and Equation (3) is substituted into Equation (4) > Mod on both sides

If the calculation is performed, the quotient x is simply calculated as in Equation (5) above (S480).

FIG. 5 is a diagram illustrating examples of performing a divide-by-three operation according to the present invention.

Referring to FIG. 5, examples in which the quotient x and the remainder r are obtained when the apparatus 100 divides by 3 as '113' is input to the dividend y.

의 꼴이 되는 값들(b) 중 하나를 '10'이 반복되는 횟수가 m의 값 '2'와 동일한 '43'을 검색한다. 그런 후, 장치(100)는 값(y')인 '111'에 검색된 값(b)인 '43'을 곱하여 '4773'을 산출하고, '4773'값에 mod

연산하여 몫(x)으로 '37'이라는 올바른 값을 산출한다. 이때, 장치(100)는 ‘4773'의 이진수에서 하위 '2m+3' 비트인 '7'에 해당하는 수인 '37'을 몫으로 산출하게 된다. 한편, (b)를 참조하면, m의 값을 '1'로 잘못 결정함에 따라 오류가 발생된 예를 도시하고 있다. 즉, m이 1로 결정됨에 따라, 하위 '2m+3' 비트인 '5'에 해당하는 수를 읽으면 5가 되어 원래의 몫인 37과 전혀 다른 값이 된다. 모듈로 연산을 이용한 것이기 때문에 값이 반복되어야 하는데, 도 5를 참조하면, 올바른 값인 (a)의 경우에는 마지막 줄에 음영 표시한대로 2m+3 비트 단위로 동일한 값이 반복되는 반면, 오류가 있는 (b)의 경우에는 반복되지 않음을 확인할 수 있다.First, looking at (a), the device 100 computes the remainder (r) '2' by performing a Modular 3 operation (mod 113, 3). Then, the apparatus 100 calculates' 43 'which is a value (y') divided by 3 by subtracting '2' which is the remainder (r) calculated from '113' y. Then, the apparatus 100 determines m to satisfy the condition that the value of 2m + 3 is equal to or greater than the value of n-1, taking into consideration '7' which is the number (n) of binary bits of '113'. That is, m may be determined as '2'. Then, the apparatus 100, when multiplying 3 shown in Fig. 2

The number of times '10' is repeated is '43' which is the same as the value '2' of m. Then, the apparatus 100 calculates' 4773 'by multiplying' 111 'as the value (y') by '43' as the retrieved value (b)

And calculates a correct value of '37' as a quotient (x). At this time, the device 100 calculates' 37 'corresponding to' 7 ', which is the lower 2m + 3' bit, from the binary number of '4773' as a quotient. Referring to (b), an error is generated by erroneously determining the value of m as '1'. That is, when m is determined to be 1, if the number corresponding to '5', which is the lower 2m + 3 bit, is read, the value becomes 5, which is completely different from the original quotient of 37. Referring to FIG. 5, in the case of the correct value (a), the same value is repeated in units of 2m + 3 bits as shaded on the last line, while the same value is repeated In the case of b), it can be confirmed that it is not repeated.

Claims (8)

Calculating moduler 3 of the inputted dividend y to calculate the remainder r;
Subtracting the calculated remainder (r) from the dividend (y) and calculating a value (y ') divided by a divisor 3;
When the number of bits (n) of the dividend y is taken into account and multiplied by 3

Searching for a value b that is an approximation of &lt; RTI ID = 0.0 &gt;
The value obtained by multiplying the value (y ') by the value (b)

And calculating a quotient (x) by dividing the dividend (y) by three.
2. The method of claim 1,
2 &lt; m &gt; + 3.
3. The method of claim 2,
Determining m that satisfies a condition that a value of 2m + 3 is equal to or greater than a value of n-1;
And selecting a binarized b whose number of times '10' is repeated from the upper bit is equal to the determined number m.
The method according to claim 1,
When you multiply by 3

(B), which is a form of &lt; RTI ID = 0.0 &gt;
The searching step
And searching for one of the stored values (b).
A remaining calculation unit for modulo-3 calculation of the inputted dividend y to calculate the remainder r,
The value y 'divided by the divisor 3 is calculated by subtracting the calculated remainder r from the dividend y and when the number of bits is multiplied by 3 in consideration of the bit number n of the dividend y,

(B) which is a form of the modulo (y) is multiplied by the value (b)

And calculating a quotient (x) obtained by dividing the dividend (y) by three. 6. The method of claim 5,
2 &gt; m &lt; 3 &gt;.
7. The apparatus of claim 6, wherein the quotient calculating unit
2 &gt; + 3 is greater than or equal to a value of n-1, and selects a binarized bin whose number of times of repeating '10' from the upper bit is equal to the determined m. A binary operation unit divided by three.
The method according to claim 6,
When you multiply by 3

(B), which is a form of &lt; RTI ID = 0.0 &gt;
The quotient calculating unit
(B) stored in said memory. &Lt; Desc / Clms Page number 20 &gt;

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