KR20170127694A - Memory management apparatus in cache for providing a persistent-consistency of persistent memories and method thereof - Google Patents

Abstract

The present invention discloses a memory management device in a cache for providing a permanent storage sequence of a permanent memory and a method thereof. The present invention realizes an instant booting capable of instantly returning to previous task content when turning on a power by providing a memory writing order sequence of a main memory which is matched with a memory writing order sequence of a processor in a computer system using the permanent memory as the main memory. Also, a restoration of the main memory level can be possible in a use of the permanent memory as the main memory even in a situation requiring the restoration by a power block or a system collision. The memory management method comprises the following steps of: storing a writing order sequence in the cache memory or a separate storage space through a cache controller; and performing the memory writing order in order from the cache memory storing the writing order sequence to the main memory composed of the permanent memory, through the cache controller.

Description

[0001] The present invention relates to a memory management apparatus in a cache and a method thereof for providing a persistent storage order of a permanent memory,

The present invention relates to a memory management apparatus and method in a cache for providing a permanent storage order of a permanent memory, and more particularly, to a memory management apparatus and a method thereof in a computer system using permanent memory as a main memory, And more particularly to a memory management apparatus and method in a cache for providing a permanent storage order of a permanent memory managing a cache memory to match a write command sequence.

Since conventional computer systems use DRAM as the main memory, it is common to restart from the auxiliary memory after shutdown because the data in the DRAM is erased when the computer is turned off. Therefore, the contents of the memory must be written to the auxiliary memory through an explicit file save command.

In addition, unlike volatile DRAMs, PRAMs and MRAMs, which are developed as next-generation main memories, have non-volatile characteristics, so that permanent storage can be provided at the main memory level. Processors preferentially store data in the cache memory between the processor and main memory rather than in the main memory to speed up reading and writing of data, so that when the processor is running, the contents of the cache memory and the data stored in main memory Can be different. Methods for providing data consistency between cache memory and main memory are largely write-through and write-back methods. The write-through is a policy that updates both the cache memory and the main memory whenever a memory write command is issued by the processor to always match the contents between the cache memory and the main memory. These write-through policies use both cache memory and main memory for each memory write command, which can increase memory traffic and degrade system performance. Therefore, in order to overcome such disadvantages, it is common practice to write data only to the cache memory, and to write data to the main memory only when the data is updated only when unusual (for example, back policy. Since the current cache memory mostly uses the write-back policy, the order in which data is written to the main memory does not match the order in which the data is written to the processor. Thus, in the event of a system collision or power failure, It is impossible to recover.

Korean Patent Laid-Open No. 10-2014-0066392 [Title: Data management method of application processor including cache memory and cache memory]

It is an object of the present invention to provide a persistent storage of persistent memory that manages the cache memory so that the memory write command order of the main memory in the computer system (or memory management apparatus) that uses the permanent memory as the main memory matches the memory write command order in the processor And a method for managing the memory in the cache for providing the order.

It is another object of the present invention to provide an apparatus and method for managing memory in a cache for providing a permanent storage order of a permanent memory providing a permanent storage order in a cache memory located between a processor and a main memory.

A memory management method according to an embodiment of the present invention is a memory management method in a cache for providing a persistent storage order of a permanent memory, comprising the steps of storing a write command sequence in a cache memory or a separate storage space through a cache controller ; And sequentially executing the memory write order from the cache memory in which the write command order is stored to the main memory configured as the permanent memory through the cache controller.

According to an embodiment of the present invention, the step of storing the write command sequence in the cache memory may include: receiving a memory request transmitted from the CPU through the cache controller; Determining whether the received memory request is a write command through the cache controller; Adding a time dependency in the order of request to all the write commands to the received memory request when the received memory request is a write command through the cache controller; And storing the order of write commands in the cache memory or in a separate storage space through the cache controller.

In one embodiment of the present invention, the step of storing the order of the write command in the cache memory or the separate storage space may include the step of permanently writing the order of the write command in the cache memory or the order store of the write command allocated to the separate storage space It can be saved in the storage order.

In one embodiment of the present invention, the step of sequentially executing a memory write order from a cache memory storing the write command order to a main memory constituted of the permanent memory may include receiving, via the cache controller, And the storage of the write command sequence is completed, if the cache hit, the write and the dirty hit, the cache hit, the dirty case, and the further write order storage If it can not be executed, the write command can be executed in the subordinate memory in the permanent storage order.

In one embodiment of the present invention, the step of sequentially performing a memory writing order from a cache memory in which the write command sequence is stored to a main memory constituted of the permanent memory includes the steps of determining whether a cache hit occurs ; Checking whether the cache hit is a write and a dirty hit when the cache hit occurs through the cache controller; And when the cache hit is a write and a dirty hit, executing a write command to the lower memory in order from the address of the oldest write command to the address of the hit from among the write commands sequentially stored in order through the cache controller And sequentially executing the memory writing order from the main memory to the main memory via the cache memory.

In one embodiment of the present invention, the step of sequentially performing a memory writing order from a cache memory in which the write command sequence is stored to a main memory constituted of the permanent memory includes the steps of determining whether a cache hit occurs ; Checking whether dirty eviction occurs in the dirty state when the cache hit does not occur through the cache controller; And a write controller for executing a write command to the lower memory in order from the address of the oldest write command to the victim address among the write commands stored in order when the dirty event is generated in the dirty cache, And sequentially executing the memory writing order from the main memory to the main memory through the memory.

A memory management device in a cache for providing a persistent storage order of a permanent memory, the memory management device comprising: a central processing unit (CPU) for transferring a memory request including a write command; A cache memory to which a storage space for storing a write command sequence is allocated; A main memory configured as a permanent memory; And a cache controller that stores a write command sequence in a storage space of the cache memory and sequentially performs a memory write sequence from a cache memory in which the write command sequence is stored to a main memory composed of the permanent memory.

According to an embodiment of the present invention, the cache memory is composed of a plurality of levels or a plurality of memory layers, and each of the plurality of levels of cache memories can store the write command sequence.

As an example related to the present invention, when the memory request transmitted from the CPU is a write command, the cache controller adds a time dependency in the order of request to all the write commands to the received memory request, It is possible to store the order of the write command in the storage space of the cache memory.

In one embodiment of the present invention, when the cache hit occurs, the cache controller checks whether the cache hit is a write and a dirty hit, and when the cache hit is a write and a dirty hit, The memory write order can be sequentially performed from the address of the old write command to the address of the hit from the old write command to the main memory via the cache memory.

In one embodiment of the present invention, the low-order memory is a memory for storing a plurality of write commands in the cache memory in a specific memory hierarchy in which a plurality of write commands are sequentially stored in the cache memory, One or more memory layers below the memory layer and the main memory.

In one embodiment of the present invention, the cache controller checks whether dirty eviction occurs in a dirty state when no cache hit occurs, and when a dirty eviction occurs in the dirty state, The write command to the lower memory is sequentially executed in order from the address of the oldest write command to the victim address among the oldest write command and the memory write order to the main memory sequentially through the cache memory.

As an example related to the present invention, in the multi-processor system, in order to execute a write command to a lower memory in a persistent storage order among processors, a transition from a modified (M) state to an invalid (I) state in the cache coherency protocol When it occurs, the write command sequentially stored from the address of the oldest write command among the write commands stored in order can be executed to the lower memory.

The present invention manages the cache memory so that the memory write command sequence of the main memory coincides with the memory write command sequence in the processor in the computer system (or memory management apparatus) that uses the permanent memory as the main memory, It is possible to realize booting as soon as it is possible to return to the contents, and it is possible to recover from the main memory level in the use of the permanent memory as the main memory even in the case of power interruption or recovery due to a system collision.

In addition, the present invention provides a permanent storage order in a cache memory located between a processor and a main memory, so that the order of instructions in the memory is managed, so that the program can be accessed immediately before an error occurs when utilized for debugging a program, There is an effect that the process of re-executing the program for debugging can be omitted.

1 is a block diagram illustrating a configuration of a memory management device in a cache for providing a persistent storage order of a permanent memory according to an embodiment of the present invention.
FIGS. 2 and 3 are diagrams illustrating state transitions in a processor and a bus of a cache coherence protocol for executing a memory write command in a persistent storage order in a multiprocessor according to an embodiment of the present invention. FIG.
FIGS. 4 and 5 are exemplary views illustrating a method of constructing a space for storing a memory write order according to an embodiment of the present invention.
6, FIG. 4 is a flowchart illustrating a memory management method in a cache for providing a persistent storage order of a permanent memory according to an embodiment of the present invention. FIG.
7 is a diagram illustrating an example of a memory request address stored in a cache memory according to an embodiment of the present invention.

It is noted that the technical terms used in the present invention are used only to describe specific embodiments and are not intended to limit the present invention. In addition, the technical terms used in the present invention should be construed in a sense generally understood by a person having ordinary skill in the art to which the present invention belongs, unless otherwise defined in the present invention, Should not be construed to mean, or be interpreted in an excessively reduced sense. In addition, when a technical term used in the present invention is an erroneous technical term that does not accurately express the concept of the present invention, it should be understood that technical terms that can be understood by a person skilled in the art can be properly understood. In addition, the general terms used in the present invention should be interpreted according to a predefined or prior context, and should not be construed as being excessively reduced.

Furthermore, the singular expressions used in the present invention include plural expressions unless the context clearly dictates otherwise. The term "comprising" or "comprising" or the like in the present invention should not be construed as necessarily including the various elements or steps described in the invention, Or may further include additional components or steps.

Furthermore, terms including ordinals such as first, second, etc. used in the present invention can be used to describe elements, but the elements should not be limited by terms. Terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or similar elements throughout the several views, and redundant description thereof will be omitted.

In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It is to be noted that the accompanying drawings are only for the purpose of facilitating understanding of the present invention, and should not be construed as limiting the scope of the present invention with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a memory management device 10 in a cache for providing a persistent storage order of a permanent memory according to an embodiment of the present invention.

1, the memory management device 10 includes a CPU 100, a cache controller 200, a cache memory 300, a memory controller 400, and a main memory 500. Not all of the components of the memory management apparatus 10 shown in Fig. 1 are essential components, and the memory management apparatus 10 may be implemented by more components than the components shown in Fig. 1, The memory management device 10 may also be implemented by components.

Here, the memory management device 10 may be a computer system.

The central processing unit (CPU) (or processor) 100 includes a single processor system, a multiprocessor system, and the like.

In addition, the CPU 100 transfers (or transmits) a memory request to the cache controller 200. [ Here, the memory request may include a write command (or a memory write command / memory write request), a read command (or a memory read command / memory read request), and the like.

The cache controller 200 receives the memory request transmitted from the CPU 100.

In addition, the cache controller 200 determines (or determines) whether the received memory request is a write command (or a memory write command / memory write request).

If the received memory request is a write command, the cache controller 200 transmits all write commands to the received memory request (or to the cache controller 200) in the order of requests Add time dependency.

Also, the cache controller 200 stores the order of the write command.

That is, the cache controller 200 writes a corresponding write command in the write command sequence list stored in the cache memory 300 or in the order store of write commands allocated to a separate storage space (for example, a queue (not shown) The cache controller 200 stores the cache memory 300 having a plurality of levels (or a plurality of memory layers) in one of a plurality of levels of cache memories The cache memory 300 stores the order of the write command in the permanent storage order.

In this manner, the cache controller 200 stores the order of write commands in the order of requests (or in the order in which they are received).

Further, the cache controller 200 executes a write command when the following condition is satisfied.

That is, the cache controller 200 executes the write command in the persistent storage order to the lower memory. At this time, the step executed in the lower memory is performed by two methods. When a cache miss occurs and dirty eviction occurs in the dirty cache memory 300 and a write hit occurs to update the cache line, the cache controller 200 A write command to the lower memory is sequentially executed from the address of the oldest write command to the address of the victim or hit among the write commands stored in the order and stored in the main memory 500) in order.

If the result of the check (or determination) indicates that the received memory request is not a write command and that the writing of the write order is completed, the cache hit, write, and dirty hit , The cache controller 200 determines that the write command (or the write command stored in the order) stored in the persistent storage order in any one of the cases where the cache hit is not a cache hit, ) To the lower memory (or sequentially flushes sequentially stored write commands to the lower memory). Here, the lower memory may be a memory for storing a plurality of write commands in the cache memory 300 in a specific memory hierarchy in which a plurality of write commands are sequentially stored in the cache memory 300, (Or a plurality of cache memories 300) from a specific cache memory 300 in which a plurality of write commands are stored, to the main memory 500 Of memory).

That is, the cache controller 200 determines (or confirms) whether a cache hit occurs. Here, the cache hit includes a write hit, a read hit, and the like.

As a result of the determination, when the cache hit occurs, the cache controller 200 checks whether the cache hit is a write and a dirty hit (or whether the cache hit is a write hit and a dirty hit) .

As a result, if the cache hit is not a write or a dirty hit, the cache controller 200 performs an access function to the cache memory 300.

If it is determined that the cache hit is a write and a dirty hit, the cache controller 200 sequentially selects the write command from the address of the oldest write command to the hit address, Memory write command to the main memory 500 through the cache memory 300 in order.

As a result of the determination, if the cache hit does not occur, the cache controller 200 determines whether dirty eviction has occurred.

As a result, if the dirty event occurs in the dirty cache controller 200, the cache controller 200 sequentially issues a write command to the lower memory from the address of the oldest write command to the victim address, The memory writing order is sequentially performed to the main memory 500 via the cache memory 300.

As a result of checking, if the dirty does not occur, the cache controller 200 performs an access function to the cache memory 300.

In this way, the cache controller 200 can store the order of the write command for the single processor and execute the write command.

FIGS. 2 and 3 are diagrams illustrating state transitions in a processor and a bus of a cache coherence protocol for performing a write command in a persistent storage order in a multi-processor.

2 and 3 are examples using the Modified, Exclusive, Shared, Invalid (MESI) protocol.

The MESI protocol uses a write-back cache policy that is used for cache coherency in the multiprocessor.

Here, the modified (M) state represents a state in which data is modified (or changed), and the state of E (Exclusive) states the same contents as the main memory 500 in the cache memory 300 (I: Invalid) state indicates that the data is stored in at least two processor cores by a different processor. It indicates a status that has been modified and invalidated or in which no data is loaded.

Further, the MESI protocol indicates a state transition by a request from the current processor (or the CPU 100) and another cache memory. That is, when accessing the cache memory 300 by a memory request from the processor, if the cache memory 300 is loaded in the cache memory 300, the cache controller 200 generates a cache hit, Reads data from the cache memory (300) or writes data to the cache memory (300).

If the data for the memory request is not loaded in the cache memory 300, the cache controller 200 generates a cache miss and transmits data on the bus in order to read data. To another cache memory (or other cache controller).

A miss by a read request occurs as a read miss, and a miss by a write request occurs as a write miss.

In case of a read miss of the MESI protocol, the cache controller 200 sends a request to another processor cache memory, and if the cache memory 200 is in a cache memory of another processor, the cache controller 200 reads data from the cache memory 200, , And transitions from invalid (I) state to shared (S) state. If the cache controller 200 receives a read request from another cache memory, the cache controller 200 responds to the cache memory 300 whether the corresponding data is present in the cache memory 300, Transition from a beta (E) or modified (M) state to a shared (S) state. If the corresponding data does not exist in the cache memory of another processor, the cache controller 200 sends a read request to the lower memory. In addition, when data read from the lower memory to the cache memory 9300 by the read miss is loaded, the cache controller 200 transfers the state from the invalid (I) state to the beta (E) state because it is the only data.

In addition, in the case of a write miss of the MESI protocol, data having the latest value must be uniquely present, thereby invalidating the data in the cache memory of another processor. The cache controller 200 sends a data read request to the lower memory to load data into the cache memory 300 and then writes data to change the data. The cache memory 300 is in an invalid (I) state To the modified (M) state.

In the write state of the MESI protocol, only the data change occurs in the modified (M) state. In the beta (E) state, only the transition occurs in the modified (M) state while the data is changed. Transition occurs in the modified (M) state as the invalidation signal is sent to the memory and the data is changed.

When the cache memory 300 is evicted in order to load other data or the data is driven out of the cache memory 300 by an invalidation signal, (M) state in a dirty state, a write request is sent to the lower memory to send a write-back request to the lower memory, .

When the cache line in the clean (E or S) state is changed to the modified (M) state by the write command or the cache line in the invalid (I) state is changed to the modified (M) state by the write command in FIG. 2, The cache controller 200 stores the write order in the cache memory 300 or the separate storage space. Also, as shown in FIG. 3, when receiving an invalid (I) signal from a remote hit in a modified (M) state or when an eviction occurs locally, the cache controller 200 Write command to the memory controller 400, and the write command to the lower memory is executed in order. Finally, the write command of the processor finally arrives in the memory controller 400 in order.

In the embodiment of the present invention, the MESI is described as an example, but the present invention is not limited thereto. The present invention can also be applied to a MOESI protocol that extends the MESI protocol. That is, in the case of the MOESI protocol, an O (Owned) state is added. In the MESI protocol, when data is read by another processor in the modified state, The MOESI protocol generates the transition from the modified (M) state to the owned (O) state by the cache controller 200, thereby reducing the number of write-backs.

In the case of the MOESI protocol, when the eviction occurs in the O state, it is the same as when the dirty event occurs, so that the cache controller 200 executes the write commands in order . However, when a transition is made from the modified state to the shared state for sharing by another processor, the read request is issued to all processors. However, Should be executed.

In this way, in a multiprocessor system, when a transition from an arbitrary state to a modified state occurs in the MESI protocol to manage persistent storage order between processors, the cache controller 200 controls the cache memory 300 The order of the write commands allocated to the storage space of the storage area is stored in the write command order list stored in the store in the permanent storage order.

In addition, in the above multiprocessor system, when a transition occurs from a modified (M) state to an invalid (I) state in the MESI protocol in order to execute a write command in a persistent storage order among processors, In the case of a cache hit, a write and a dirty hit, a case where a cache hit, a dirty case is a violation, and a further write order storage is performed The cache controller 200 may execute the write command (or the write command stored in the order) in the persistent storage order to the sub-memory (or sequentially write the stored write commands in descending order) Flush to memory).

That is, in the multiprocessor system, when the transition from the modified (M) state to the invalid (I) state occurs in the MESI protocol in order to execute the write command in the persistent storage order between processors, the cache controller 200 The write command sequentially stored from the address of the oldest write command among the write commands stored in order is executed as the lower memory.

The cache memory 300 includes a plurality of memory layers (or a plurality of levels) including memories such as a first level cache and a second level cache.

The cache memory 300 is an area for storing a write command (or an address of a write command) in order of a plurality of levels (or a plurality of memory layers) under the control of the cache controller 200 It may be in a set state.

In order to store the write command, a separate storage space may be provided as shown in FIG. 4, or some space of the cache memory 9300 may be used as shown in FIG.

That is, in the case of FIG. 4, a hardware queue is configured to manage a separate space for storing a write command address.

5, one way among the ways of the cache memory 300 having n ways is used as a space for storing a write command address, and the remaining n-1 ways are allocated to the cache And is used in the memory 300.

5, some of the spaces in the cache memory 300 may be used for storing the write command, and may be operated in accordance with the operation of the cache memory 300. In addition, So that the cost can be reduced.

When a part of the cache memory 300 is used as a space for storing the write command address, the cache controller 200 may have the first address of the write order and continue to connect the next address have.

The memory controller 400 manages the main memory 500.

In addition, the memory controller 400 receives a plurality of ordered write commands transmitted from the cache controller 300.

In addition, the memory controller 400 sequentially stores a plurality of write commands arranged in the received order in the main memory 500.

The main memory 500 includes a persistent memory as a main memory.

The main memory 500 sequentially stores a plurality of write commands arranged in a sequence transmitted from the cache controller 300 under the control of the memory controller 400.

In this way, the cache memory can be managed such that the memory write command sequence of the main memory coincides with the memory write command sequence in the processor in the computer system (or memory management apparatus) using the permanent memory as the main memory.

In this way, a persistent storage order can be provided in a cache memory located between the processor and the main memory.

Hereinafter, a memory management method in a cache for providing a persistent storage order of a persistent memory according to the present invention will be described in detail with reference to FIGS. 1 to 7. FIG.

6, FIG. 4 is a flowchart illustrating a memory management method in a cache for providing a persistent storage order of a permanent memory according to an embodiment of the present invention. FIG.

First, the cache controller 200 receives a memory request transmitted from the CPU 100.

In addition, the cache controller 200 determines (or determines) whether the received memory request is a write command (or a memory write command / memory write request).

For example, the cache controller 200 determines whether the eleventh memory request transmitted from the CPU 100 is a write command (S610).

If the received memory request is a write command, the cache controller 200 transmits all write commands to the received memory request (or to the cache controller 200) in the order of requests Add time dependency.

For example, when the eleventh memory request is a write command, the cache controller 200 adds time dependency to the eleventh memory request in a requested order (S620).

Then, the cache controller 200 stores the order of the write command.

That is, the cache controller 200 stores the order of the write commands in the write command order list stored in the order store of the write commands allocated to the cache memory 300 or a separate storage space (not shown) do. At this time, the cache controller 200 may be configured to correspond to the cache memory 300 of any one of the plurality of levels of the cache memory, with respect to the cache memory 300 having a plurality of levels (or a plurality of memory layers) The order of the write commands is stored in the permanent storage order.

For example, as shown in FIG. 7, the cache controller 200 may include a plurality of levels of cache included in the cache memory 300, (Or the eleventh write command) 710 in the order store of the write command allocated to the first memory request. In this case, the first level cache to the tenth memory request 720 may be stored in advance in the first level cache.

In this manner, the cache controller 200 can store the order of the write commands in the order of requests (or in the order of receipt) (S630).

Thereafter, if the result of the check (or the determination result) indicates that the received memory request is not a write command and that the writing of the write order is completed, a cache hit, a write, and a dirty hit , The cache controller 200 determines that the write command (or the write command stored in the order) stored in the persistent storage order in any one of the cases where the cache hit is not a cache hit, ) To the lower memory (or sequentially stores the write commands sequentially stored in the lower memory). Here, the lower memory may be a memory for storing a plurality of write commands in the cache memory 300 in a specific memory hierarchy in which a plurality of write commands are sequentially stored in the cache memory 300, And one or more memory layers below the layer and the main memory 500. FIG.

That is, the cache controller 200 determines (or confirms) whether a cache hit occurs (S641).

As a result of the determination, when the cache hit occurs, the cache controller 200 checks whether the cache hit is a write and a dirty hit (or whether the cache hit is a write hit and a dirty hit) (S642).

If it is determined that the cache hit is not a write or a dirty hit, the cache controller 200 performs an access function to the cache memory 300 (S643).

If it is determined that the cache hit is a write and a dirty hit, the cache controller 200 sequentially selects the write command from the address of the oldest write command to the hit address, A memory write command is executed and the memory write order is sequentially performed to the main memory 500 via the cache memory 300 (S644).

If it is determined that the cache hit does not occur, the cache controller 200 determines whether dirty eviction has occurred in step S645.

As a result, if the dirty event occurs in the dirty cache controller 200, the cache controller 200 sequentially issues a write command to the lower memory from the address of the oldest write command to the victim address, The memory writing order is sequentially performed to the main memory 500 via the cache memory 300 (S646).

If it is determined that the dirty event does not occur, the cache controller 200 performs an access function to the cache memory 300 (S647).

For example, after the writing of the writing order for the eleventh memory request is completed, the cache controller 200 determines whether the cache hit occurs. Thereafter, when the cache hit occurs as a result of the determination, the cache controller 200 determines whether the cache hit is a write and a dirty hit. Then, when the cache hit is a write and a dirty hit, the cache controller 200 determines whether the most write out of a plurality of write commands sequentially stored in the first level cache in the cache memory 300 is an address of an old write command (For example, from the first memory request address to the eleventh memory request address) to the address (for example, the eleventh memory request address) A write command is issued to a second level cache which is a lower memory of the first level cache among a plurality of levels included in the memory 300. [ Thereafter, when the second level cache reaches the condition of executing the persistent storage order in the state where the last level cache among the plurality of levels included in the cache memory 300 is the second level cache, The controller 200 executes the write commands of the second level cache in the main memory 500 in the order recorded.

In another example, after the writing of the writing order for the eleventh memory request is completed, the cache controller 200 determines whether the cache hit occurs. Thereafter, when the cache hit does not occur as a result of the determination, the cache controller 200 determines whether dirty eviction has occurred. Thereafter, when the dirty occurrence of the dirty event occurs, the cache controller 200 determines whether the write command among the plurality of write commands sequentially stored in the first level cache in the cache memory 300 Level cache, which is a lower memory of the first level cache, among the plurality of levels included in the cache memory 300 in order from the victim address to the victim address. Thereafter, when the second level cache reaches the condition of executing the persistent storage order in the state where the last level cache among the plurality of levels included in the cache memory 300 is the second level cache, The controller 200 performs a write command of the second level cache in the main memory 500 in the order recorded (S640).

Embodiments of the present invention can be implemented in a computer system (or memory management device) that uses permanent memory as the main memory, as described above, such that the memory write command order of the main memory coincides with the memory write command order in the processor When the power is turned on, it is possible to realize booting as soon as returning to the previous work contents is possible, and it is possible to recover from the main memory level in using the permanent memory as main memory even in the case where power- .

As described above, embodiments of the present invention provide a permanent storage order in a cache memory located between a processor and a main memory to manage the order of instructions in the memory, You can access it immediately before the point, and you can omit the process of redoing the program for debugging.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or essential characteristics thereof. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

The present invention provides a permanent storage order of permanent memory managing a cache memory in a computer system using permanent memory as the main memory so that the memory write command order of the main memory coincides with the memory write command order in the processor, It is possible to recover from the main memory level in the use of the permanent memory as the main memory even in a situation where the power is cut off or the recovery due to the system collision is necessary. Memory applications and the like.

10: memory management device 100: CPU
200: cache controller 300: cache memory
400: memory controller 500: main memory

Claims (13)

A memory management method in a cache for providing a persistent storage order of permanent memory,
Storing a write command sequence in a cache memory or in a separate storage space via a cache controller; And
And sequentially executing, through the cache controller, a memory write order from a cache memory storing the write command order to a main memory configured as the permanent memory. The method according to claim 1,
Wherein the step of storing the write command sequence in the cache memory comprises:
Receiving a memory request transmitted from a CPU through the cache controller;
Determining whether the received memory request is a write command through the cache controller;
Adding a time dependency in the order of request to all the write commands to the received memory request when the received memory request is a write command through the cache controller; And
And storing the order of write commands in the cache memory or in a separate storage space through the cache controller. 3. The method of claim 2,
Storing a sequence of write commands in the cache memory or in a separate storage space,
Wherein the order of the write commands is stored in the order storage of write commands allocated to the cache memory or a separate storage space in a persistent storage order. The method according to claim 1,
Wherein the step of sequentially performing the memory writing order from the cache memory in which the write command order is stored to the main memory configured in the permanent memory,
When the memory request transmitted from the CPU is not the write command and the storage of the write command sequence is completed through the cache controller, if the cache hit is the write hit and the write hit is the dirty hit, Wherein the write command is executed in the persistent storage order into the lower memory when the event is not a hit, the event is a dirty event, and the event is no longer a case in which the write order storage can not be performed any more. The method according to claim 1,
Wherein the step of sequentially performing the memory writing order from the cache memory in which the write command order is stored to the main memory configured in the permanent memory,
Determining whether a cache hit occurs through the cache controller;
Checking whether the cache hit is a write and a dirty hit when the cache hit occurs through the cache controller; And
When the cache hit is a write and a dirty hit, the write controller issues a write command to the lower memory in order from the address of the oldest write command to the address of the hit from among the write commands stored in order And sequentially executing a memory write order from the main memory to the main memory via the cache memory. The method according to claim 1,
Wherein the step of sequentially performing the memory writing order from the cache memory in which the write command order is stored to the main memory configured in the permanent memory,
Determining whether a cache hit occurs through the cache controller;
Checking whether dirty eviction occurs in the dirty state when the cache hit does not occur through the cache controller; And
A write command to a lower memory is sequentially executed from an address of the oldest write command to a victim address among the write commands stored in order when the dirty event occurs in the dirty cache, And sequentially executing a memory write order from the main memory to the main memory. A memory management device in a cache for providing a permanent storage order of permanent memory,
A central processing unit (CPU) for transferring a memory request including a write command;
A cache memory to which a storage space for storing a write command sequence is allocated;
A main memory configured as a permanent memory; And
And a cache controller that stores a write command sequence in a storage space of the cache memory and sequentially performs a memory write sequence from a cache memory in which the write command sequence is stored to a main memory composed of the permanent memory. 8. The method of claim 7,
Wherein the cache memory comprises:
Wherein the plurality of levels of the plurality of levels or the plurality of memory layers stores the write command sequence in the plurality of levels of the cache memory, respectively. 8. The method of claim 7,
The cache controller comprising:
When the memory request transmitted from the CPU is a write command, adds a time dependency to all the write commands in the order of request to the received memory request, and stores the order of the write command in the storage space of the cache memory The memory management apparatus comprising: 8. The method of claim 7,
The cache controller comprising:
And when the cache hit is a write and a dirty hit, it is determined whether or not the cache hit is a write and a dirty hit when a cache hit occurs, To the lower memory, and sequentially executes the memory writing order from the lower memory to the main memory via the cache memory. 11. The method of claim 10,
The low-
A cache memory comprising a plurality of memory layers, comprising: at least one memory hierarchy lower than a corresponding specific memory hierarchy in which a plurality of write commands in the cache memory are stored in a specific memory hierarchy, And a main memory. 8. The method of claim 7,
The cache controller comprising:
(Dirty eviction) occurs in a state where no cache hit occurs, and when dirty eviction occurs in the dirty state, when the dirty event occurs, victim addresses in order from the main memory to the main memory via the cache memory in order. 8. The method of claim 7,
The cache controller comprising:
In a multiprocessor system, when a transition occurs from a modified (M) state to an invalid (I) state in a cache coherency protocol in order to execute a write command to a lower memory in a persistent storage order among processors, Wherein the memory management unit executes a write command stored sequentially from the address of the old write command to the lower memory.

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