KR20170118498A - Power voltage supply unit and display device including the same - Google Patents

Abstract

The present invention relates to a method and a device for controlling a load on a circuit element of a first power supply voltage supply unit by discharging a voltage charged in a capacitor to an input terminal of a first power supply voltage supply unit when the first power supply wiring is connected from the first power supply voltage supply unit to the ground, And a display device including the power supply unit. The power supply unit according to an embodiment of the present invention includes a DC-AC conversion unit that converts a first DC voltage input to an input terminal into an AC voltage swinging between a predetermined voltage lower than the first DC voltage and outputs the AC voltage to a first node, Circuit, a smoothing circuit for converting the AC voltage into a second DC voltage and outputting the second DC voltage to a second node, a plurality of resistors connected between the second node and ground, a third node connected between the plurality of resistors A control IC for monitoring the voltage, and a recycle control circuit for switching connection between the second node and the third node in accordance with the recycle signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power supply unit and a display device including the power supply unit.

The present invention relates to a power supply unit and a display device including the power supply unit.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying an image. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat panel display devices such as an organic light emitting diode (OLED) are being utilized. Of the flat panel display devices, organic light emitting display devices have been recently applied to many products because they can be driven at a low voltage, are thin, have excellent viewing angles, and have a high response speed.

The display apparatus includes a display panel in which a plurality of pixels are arranged in a matrix form. The display panel is supplied with the scan signals from the scan driver circuit to drive each of the pixels, and receives the data voltages from the data driver circuit. Further, the display panel is supplied with the high-potential power supply voltage and the low-potential power supply voltage from the power supply unit.

The power supply unit may connect the low-potential power supply wiring to the low-potential power supply voltage supply unit or to the ground according to the driving mode of the display apparatus. When the low potential power supply wiring is connected to the low potential power supply voltage supply unit, a predetermined direct current voltage is supplied to the low potential power supply voltage. When the low-potential power wiring is connected to the ground, the ground voltage is supplied to the low-potential power supply voltage.

The display device may include a capacitor such as a Multi Layer Ceramic Condenser (MLCC) to stably supply a predetermined DC voltage. However, when the low-potential power supply line is connected from the low-potential power supply voltage supply to the ground, the voltage charged in the capacitor rapidly discharges to the ground. There is a problem that much stress is applied to the circuit elements located in the discharge path due to the overcurrent due to the rapid discharge.

The present invention prevents a voltage charged in a capacitor from rapidly discharging to the ground when the first power supply line is connected to the ground from the first power supply voltage supply unit so that stress is applied to the circuit elements of the first power supply voltage supply unit due to the overcurrent And a display device including the power supply unit.

The power supply unit according to an embodiment of the present invention includes a DC-AC conversion unit that converts a first DC voltage input to an input terminal into an AC voltage swinging between a predetermined voltage lower than the first DC voltage and outputs the AC voltage to a first node, Circuit, a smoothing circuit for converting the AC voltage into a second DC voltage and outputting the second DC voltage to a second node, a plurality of resistors connected between the second node and ground, a third node connected between the plurality of resistors A control IC for monitoring the voltage, and a recycle control circuit for switching connection between the second node and the third node in accordance with the recycle signal.

A display device according to an embodiment of the present invention includes a display panel including a first power supply line and a power supply unit for supplying a first power supply voltage to the first power supply line. The power supply unit converts the first DC voltage input to the input terminal into an AC voltage swinging between a predetermined voltage lower than the first DC voltage and outputs the AC voltage to the first node, A control IC for monitoring a voltage of a third node connected between the plurality of resistors, and a control IC for controlling the voltage of the third node connected between the second node and the ground according to the recycle signal, And a recycle control circuit for switching connection between the second node and the third node.

The present invention changes from the sensing mode to the display mode through the recycle mode without changing from the sensing mode directly to the display mode. Therefore, the present invention can discharge a voltage charged in a capacitor such as a multilayer ceramic capacitor in the recycle mode to the input terminal of the first power supply voltage supply part. Accordingly, the present invention can prevent a voltage charged in a capacitor such as a multilayer ceramic capacitor from rapidly discharging to the ground. Therefore, the present invention can prevent stress from being applied to the circuit elements located in the discharge path due to the overcurrent.

1 is a block diagram showing a display device according to an embodiment of the present invention.
FIG. 2 is an exemplary view showing a lower substrate, source drive ICs, a timing controller, a data compensator, a power supply, flexible films, a source circuit board, a flexible cable, and a control circuit board of the display panel of FIG.
3 is a circuit diagram showing an example of a pixel in the display region of FIG.
4 is a circuit diagram showing the first power supply voltage supply part of the power supply part in detail.
5 is a waveform diagram showing a selection signal and a recycle control signal in a display mode, a sensing mode, and a recycle mode.
6A to 6C are exemplary diagrams showing the current flow of the first power supply voltage supply in the display mode, the sensing mode, and the recycle mode.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is an exemplary view showing a lower substrate, source drive ICs, a timing controller, a data compensator, a power supply, flexible films, a source circuit board, a flexible cable, and a control circuit board of the display panel of FIG.

1 and 2, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a flexible film 22, a scan driver 30, a timing controller 40 A power supply 50, a source circuit board 60, a control circuit board 70, and a cable 80.

The display panel 10 includes a display area AA and a non-display area NAA provided around the display area AA. The display area AA is an area where pixels P are formed to display an image. In the display panel 10, data lines (D1 to Dm, m is a positive integer of 2 or more), reference voltage lines (R1 to Rp, p are positive integers of 2 or more), scan lines (S1 to Sn, n Is a positive integer of 2 or more), and sensing lines SE1 to SEn are provided. The data lines D1 to Dm and the reference voltage lines R1 to Rp may intersect the scan lines S1 to Sn, the sensing lines SE1 to SEn, and the control lines C1 to Cn have. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing lines SE1 to SEn may be parallel to each other.

Each of the pixels P includes one of the data lines D1 to Dm, one of the reference voltage lines R1 to Rp, one of the scan lines S1 to Sn, and one of the sensing lines SE1 To SEn, respectively. Each of the pixels P of the display panel 10 includes an organic light emitting diode (OLED) as shown in FIG. 3 and a pixel driver (not shown) including a plurality of transistors for supplying current to the organic light emitting diode PD).

3, the pixel driver PD may include a scan transistor ST, a driving transistor DT, and a storage capacitor Cst. The scan transistor ST1 is turned on by the scan signal of the kth scan line Sk to supply the data voltage of the jth data line Dj to the gate electrode of the drive transistor DT. The sensing transistor ST2 connects the q-th reference voltage line Rq to the source electrode of the driving transistor DT in response to the sensing signal of the k-th sensing line SEk. The driving transistor DT controls the driving current flowing from the high potential voltage line EVDL to the organic light emitting diode OLED in accordance with the data voltage supplied to the gate electrode. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL in order to keep the voltage of the gate electrode of the driving transistor DT constant. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line EVSL and emits light with a predetermined brightness according to the driving current.

The data driver 20 may include a plurality of source driver ICs (integrated circuits) 21 as shown in FIG. Each of the source drive ICs 21 may be mounted on each of the flexible films 22. Each of the flexible films 22 may be a tape carrier package or a chip on film. Each of the flexible films 22 may be bent or bent. Each of the flexible films 22 may be attached to the lower substrate 11 and the source circuit board 60. Each of the flexible films 22 may be attached on the lower substrate 11 by a tape automated bonding (TAB) method using an anisotropic conductive flim, D1 to Dm. The source circuit board 60 may be connected to the control circuit board 70 by a cable 80. The source circuit board 60 may be a printed circuit board or a flexible printed circuit board.

Each of the source drive ICs 21 may include a data voltage supply section, a sensing data output section, and a switch circuit.

The data voltage supply unit is connected to the data lines D1 to Dm to supply the data voltages. The data voltage supply unit receives digital video data (DATA) or sensing digital data (PDATA) and a data timing control signal (DCS) from the timing control unit (40).

The data voltage supply unit converts the digital video data (DATA) into the light emission data voltages in accordance with the data timing control signal in the display mode, and supplies the light emission data voltages to the data lines (D1 to Dm). The emission data voltage is a voltage for emitting the organic light emitting diode OLED of the pixel P with a predetermined luminance.

The data voltage supply unit converts the sensing data PDATA into sensing data voltages in accordance with the data timing control signal DCS in the sensing mode and supplies them to the data lines D1 to Dm. The sensing data voltage is a voltage for sensing the driving current of the driving transistor DT of the pixel P. [

The sensing data output unit converts a current flowing in each of the reference voltage lines R1 to Rp into a voltage and converts the converted voltage into digital data sensing data SD. To this end, the sensing data output unit includes a current-voltage conversion unit for converting the current flowing in each of the reference voltage lines R1 to Rp into a voltage, an analog-to-digital conversion unit for converting the output voltage of the current- Analog < / RTI > digital converters.

The switch circuit connects the reference voltage lines (R1 to Rp) to the reference voltage supply line to which the reference voltage (VREF) is supplied in the display mode. In addition, the switch circuit connects the reference voltage lines (R1 to Rp) to the sensing data output unit in the sensing mode.

The scan driver 30 includes a scan signal output unit 31 and a sensing signal output unit 32. The scan signal output unit 31 is connected to the scan lines S1 to Sn to supply scan signals. The scan signal output unit 31 supplies scan signals to the scan lines S1 to Sn in accordance with a scan timing control signal SCS input from the timing controller 40. [

The sensing signal output unit 32 is connected to the sensing lines SE1 to SEn to supply sensing signals. The sensing signal output unit 32 supplies sensing signals to the sensing lines SE1 to SEn in accordance with a sensing timing control signal SENCS input from the timing controller 40. [

Each of the scan signal output unit 31 and the sensing signal output unit 32 may include a plurality of transistors and may be formed directly in a non-display area NDA of the display panel 10 in a gate driver in panel (GIP) . Alternatively, each of the scan signal output unit 31 and the sensing signal output unit 32 may be mounted on a flexible film (not shown) formed in the form of a driving chip and connected to the display panel 10.

The timing control unit 40 receives a driving voltage (not shown) from the power supply unit 50 and is turned on by a driving voltage (not shown). The timing controller 40 receives digital video data (DATA) and timing signals from an external system board. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 40 generates timing control signals for controlling the operation timings of the data driver 20, the scan signal output unit 31, and the sensing signal output unit 32. The timing control signals include a data timing control signal DCS for controlling the operation timing of the data driver 20, a scan timing control signal SCS for controlling the operation timing of the scan signal output unit 31, And a sensing timing control signal (SENCS) for controlling the operation timing of the unit (32).

The timing controller 40 receives the sensing data SD from the data driver 20 and compensates the digital video data DATA using the sensing data SD. Specifically, the sensing data SD is data obtained by sensing the current of the driving transistor DT through the reference voltage line when the sensing data voltages are supplied to the pixels P, respectively. That is, the sensing data SD may be digital data reflecting the threshold voltage and the electron mobility of the driving transistors of the pixels P, respectively. Therefore, when the digital video data DATA is compensated using the sensing data SD, the compensated digital video data DATA has a threshold voltage and electron mobility of the driving transistor DT of each of the pixels P It is the compensated data.

The timing controller 40 controls the display device to operate in the display mode, the sensing mode, and the recycle mode. The timing controller 40 controls the organic light emitting diodes OLED of the plurality of pixels P of the display panel 10 to emit light during the display mode. The timing controller 40 controls the source voltage of at least one of the plurality of pixels P of the display panel 10 or the anode voltage of the organic light emitting diode OLED to the reference voltage lines R1 to Rp). The timing controller 40 discharges the voltage charged in the capacitor such as the multilayer ceramic capacitor (MLCC) of the first power supply voltage supply part of the power supply part 50 to the input terminal of the first power supply voltage supply part during the recycle mode, .

The timing controller 40 can sequentially and repeatedly control the display device to operate in the display mode, the sensing mode, and the recycle mode. That is, the timing controller 40 controls the display device in the display mode, the sensing mode, the recycle mode, the display mode, the sensing mode, and the recycle mode in this order. Therefore, the timing control unit 40 can change from the sensing mode to the display mode through the recycle mode without changing the sensing mode directly to the display mode. The embodiment of the present invention can prevent a voltage charged in a capacitor such as a multilayer ceramic capacitor from rapidly discharging to the ground due to the recycle mode. Therefore, the embodiment of the present invention can prevent stress from being applied to the circuit elements located in the discharge path due to the overcurrent.

The timing controller 40 outputs the compensated digital video data DATA and the data timing control signal DCS to the data driver 20 in the display mode. The timing controller 40 outputs the sensing data PDATA and the data timing control signal DCS to the data driver 20 in the sensing mode. The sensing data PDATA may be stored in the internal memory of the timing controller 40 as predetermined data for sensing the sensing data SD.

The timing control unit 40 outputs the selection signal SS and the recycle signal RS to the power supply unit 50. [ The timing controller 40 outputs the recycle signal RS of the first logic level voltage in the display mode and the sensing mode, and the recycle signal RS of the second logic level voltage in the recycle mode. In addition, the timing controller 40 outputs the selection signal SS of the first logic level voltage in the sensing mode and the recycle mode, and outputs the sensing signal SS of the second logic level voltage in the display mode.

The power supply unit 50 supplies the first and second power supply voltages VSS and VDD to the display panel 10. The first power source voltage VSS may be a low potential voltage and the second power source voltage VDD may be a high potential voltage VDD higher than the first power source voltage. The first power voltage VSS is supplied to the cathode electrode of the organic light emitting diode OLED of each of the pixels P of the display panel 10 while the second power voltage VDD is supplied to the pixel P to the drain electrode of the driving transistor DT. Also, the power supply unit 50 supplies the reference voltage VREF to the data driver 20. Further, the power supply unit 50 may supply a driving voltage (not shown) to the data driver 20, the scan driver 30, and the timing controller 40, respectively.

The power supply unit 50 includes a first power supply voltage supply unit for supplying a first power supply voltage VSS, a second power supply voltage supply unit for supplying a second power supply voltage VDD, and a reference voltage supply unit for supplying a reference voltage VREF, Section.

The first power supply voltage supply unit receives the selection signal SS from the timing controller 40 and supplies the first power supply voltage VSS to either the ground voltage or a predetermined DC voltage higher than the ground voltage in accordance with the selection signal SS Output. The first power supply voltage supply unit supplies the ground voltage to the first power supply voltage VSS in the display mode in which the selection signal SS of the second logic level voltage is input and the selection signal SS of the first logic level voltage is supplied to the input A predetermined DC voltage is supplied in a sensing mode and a recycling mode. The voltage of the cathode electrode of the organic light emitting diode OLED of each of the pixels P can be increased when a predetermined direct current voltage higher than the ground voltage is supplied in the sensing mode and the recycling mode. Accordingly, in the sensing mode and the recycle mode, the driving current of the driving transistor DT flows to the cathode electrode through the organic light emitting diode OLED, thereby preventing the organic light emitting diode OLED from emitting light. Therefore, the embodiment of the present invention can prevent the organic light emitting diode (OLED) from emitting light in the sensing mode and the recycling mode, thereby preventing the image quality from deteriorating.

In addition, the first power supply voltage supply unit includes a capacitor such as a multilayer ceramic capacitor for stably outputting the second DC voltage. The first power supply voltage supply unit receives the recycle signal RS from the timing controller 40. When the recycle signal RS is input, the first power supply voltage supply unit supplies a voltage charged in a capacitor such as a multilayer ceramic capacitor to an input terminal of the first power supply voltage supply unit Discharge.

Further, the timing control unit 40 changes from the sensing mode to the display mode via the recycle mode without changing the sensing mode directly to the display mode. The first power supply voltage supply unit discharges the voltage charged in the capacitor such as the multilayer ceramic capacitor to the input terminal of the first power supply voltage supply unit in the recycle mode. Accordingly, the embodiment of the present invention can prevent a voltage charged in a capacitor such as a multilayer ceramic capacitor from rapidly discharging to the ground due to the recycle mode. Therefore, the embodiment of the present invention can prevent stress from being applied to the circuit elements located in the discharge path due to the overcurrent.

The timing control unit 40 and the power supply unit 50 may be mounted on the control circuit board 70. The control circuit board 70 may be connected to the source circuit board 60 by a cable 80. The control circuit board 70 may be a printed circuit board or a flexible printed circuit board. The cable 80 may be a flexible cable.

4 is a circuit diagram showing the first power supply voltage supply part of the power supply part in detail. 4 shows a detailed circuit diagram of the first power supply voltage supply unit for supplying the first power supply voltage to the first power supply line.

Referring to FIG. 4, the first power supply voltage supply unit 100 includes a buck converter 110, a recycle control circuit 120, and a voltage selection output unit 130.

The buck converter 110 converts the first DC voltage input to the input terminal IT into a second DC voltage lower than the first DC voltage, and outputs the second DC voltage to the voltage selection output unit 130. Specifically, the buck converter 110 converts the first DC voltage to an AC voltage and converts the AC voltage to a second DC voltage. The AC voltage swings between the first DC voltage and a predetermined voltage lower than the second DC voltage. In Figs. 4, 5A and 5B, it is illustrated that the predetermined voltage is the ground voltage.

The buck converter 110 may include a DC-AC conversion circuit 111, a smoothing circuit 112, and a voltage divider circuit 113, and a control IC 114.

The DC-AC conversion circuit 111 converts the first DC voltage input to the first input terminal IT into an AC voltage. And may include first and second transistors T1 and T2. Each of the first and second transistors T1 and T2 may be a field effect transistor and may be formed in an N-channel type.

The first transistor (T1) switches the connection between the input terminal (IT) and the first node (N1) in accordance with the first control signal from the control IC (114). The control electrode of the first transistor T1 is connected to the first control signal output terminal CT1 of the control IC 114. The source electrode thereof is connected to the first node N1 and the drain electrode thereof is connected to the input terminal IT. Lt; / RTI >

The second transistor (T2) switches the connection between the first node (N1) and the ground in accordance with the second control signal from the control IC (114). The control electrode of the second transistor T2 is connected to the second control signal output terminal CT2 of the control IC 114, the source electrode thereof is connected to the ground, and the drain electrode thereof is connected to the first node N1 have.

The second control signal may be an inverted signal of the first control signal. In this case, when the first transistor T1 is turned on, the second transistor T2 is turned off, and when the first transistor T1 is turned off, the second transistor T2 is turned on . Therefore, when the first transistor T1 is turned on, the first DC voltage inputted to the first node N1 is supplied to the input terminal IT, and when the second transistor T2 is turned on, One node N1 is supplied with a ground voltage. That is, the first node N1 may be supplied with a second DC voltage swinging between the first DC voltage and the ground voltage. 5A and 5B illustrate that the first direct current voltage has a potential of 12V and the ground voltage has a potential of 0V.

The smoothing circuit 112 may be an LC circuit including an inductor (I) and a second capacitor (C2). The inductor I may be connected between the first node N1 and the second node N2 and the second capacitor C2 may be connected between the second node N2 and the ground. The smoothing circuit 112 smoothes the AC voltage supplied to the first node N1 and outputs the second DC voltage.

That is, the buck converter 110 periodically cuts and converts the first DC voltage into an AC voltage using the first DC-AC conversion circuit 111, and smoothes the AC voltage using the smoothing circuit 112 And outputs the second DC voltage. Therefore, the second DC voltage output from the buck converter 110 is smaller than the first DC voltage input to the buck converter 110. [

The voltage dividing circuit 113 divides the voltage of the second node N2. The voltage divider circuit 113 may include the second and third resistors R2 and R3 and the third capacitor C3. The second and third resistors R2 and R3 are connected between the second node N2 and the ground. 4, the contact between the second and third resistors R2 and R3 and the monitoring terminal MT of the control IC 114 is defined as a third node N3 and the third capacitor C3 is defined as the second And is connected between the node N2 and the third node N3.

Since the third node N3 is connected to the monitoring terminal MT of the control IC 114, the voltage of the third node N3 divided by the voltage divider circuit 113 can be monitored by the control IC 114 have. Since the voltage at the third node N3 is the voltage divided by the voltage at the second node N2, the control IC 114 substantially monitors the voltage at the second node N2.

The control IC 114 controls the pulse widths of the first and second control signals according to the monitoring result of the voltage of the third node N3. For example, when the voltage of the third node N3 rises, the control IC 114 decreases the pulse width of the first control signal and increases the pulse width of the second control signal as shown in FIG. 5A, N2 can be prevented from rising. When the voltage of the third node N3 falls, the control IC 114 increases the pulse width of the first control signal and narrows the pulse width of the second control signal as shown in FIG. 5B, Can be prevented from being lowered.

The recycle control circuit 120 electrically connects the second node N2 and the third node N3 of the buck converter 110 when the recycle signal is input to allow the buck converter 110 to operate in the sink mode. When the buck converter 110 operates in the sink mode, the voltage charged in the multilayer ceramic capacitor MLCC is discharged through the buck converter 110 to the input terminal IT as shown in FIG. 6B, so that the sink current Flow.

The recycle control circuit 120 may include the third and fourth transistors T3 and T4 and the third resistor R3. Each of the third and fourth transistors T3 and T4 may be a field effect transistor, the third transistor T3 may be an N-channel transistor, the fourth transistor T4 may be a P- As shown in FIG.

The third transistor T3 switches the connection between the second node N2 and the third node N3 of the buck converter 110. [ The third transistor T3 is turned on by the switching of the fourth transistor T4. The control electrode of the third transistor T3 is connected between the third resistor R3 and the source electrode of the fourth transistor T4, the source electrode thereof is connected to the third node N3, (N2).

The fourth transistor T4 is turned on by a recycle signal to connect the control electrode of the third transistor T3 to the ground. Accordingly, when the fourth transistor T4 is turned on, the third transistor T3 is also turned on. The control electrode of the fourth transistor T4 may be connected to the recycle signal terminal RT, the source electrode thereof may be connected to the control electrode of the third transistor T3, and the drain electrode thereof may be connected to the ground.

The voltage selection output unit 130 outputs the second DC voltage or the ground voltage output from the buck converter 110 to the output terminal OT according to the selection signal input through the selection signal input terminal ST. The voltage selection output unit 130 may include a fifth transistor T5. The fifth transistor T5 may be a field effect transistor or an N-channel transistor.

The fifth transistor T5 is turned on by the selection signal to connect the output terminal OT to the ground. The control electrode of the fifth transistor T5 is connected to the selection signal input terminal ST, the source electrode thereof is connected to the ground, and the drain electrode thereof is connected to the output terminal OT.

When the selection signal of the first logic level voltage is input, the fifth transistor T5 is turned off. As a result, the second DC voltage output from the buck converter 110 can be output to the output terminal OT. When the selection signal of the second logic level voltage is input, the fifth transistor T5 is turned on. For this reason, the output terminal OT can be connected to the ground.

The multilayer ceramic capacitor MLCC may be connected to the output terminal OT to stably output the second direct current voltage. A multilayer ceramic capacitor (MLCC) may be replaced by a capacitor of a different kind instead of a multilayer ceramic capacitor as an example of the capacitor.

5 is a waveform diagram showing a selection signal and a recycle control signal in a display mode, a sensing mode, and a recycle mode.

Referring to FIG. 5, the display mode DM, the sensing mode SM, and the recycle mode RM are sequentially repeated. For example, it can be repeated in the display mode DM, the sensing mode SM, the recycle mode RM, the display mode DM, the sensing mode SM, and the recycle mode RM.

The selection signal SS may be output as the second logic level voltage V2 during the display mode DM and output as the first logic level voltage V1 during the sensing mode SM and the recycle mode RM. The recycle signal RS may be output as the first logic level voltage V1 during the display mode DM and the sensing mode SM and may be output as the second logic level voltage V2 during the recycle mode RM.

6A to 6C are exemplary diagrams showing the current flow of the first power supply voltage supply in the display mode, the sensing mode, and the recycle mode. Hereinafter, the operation of the first power supply voltage supply unit in the display mode DM, the sensing mode SM, and the recycle mode RM will be described in detail with reference to Figs. 4, 5, and 6A to 6C.

First, operations of the first power supply voltage supplying unit during the display mode DM will be described in detail with reference to FIGS. 4, 5, and 6A.

During the display mode DM, the selection signal SS is output to the second logic level voltage V2, and the recycle signal RS is output to the first logic level voltage V1. The fourth transistor T4 is turned off by the recycle signal RS of the first logic level voltage V1 and the third transistor T3 is also turned off due to the turn- do. The fifth transistor T5 is turned on by the selection signal SS of the second logic level voltage V2.

Since the third transistor T3 is turned off, the buck converter 110 normally outputs the second DC voltage. However, since the fifth transistor T5 is turned on, the source current of the buck converter 110 flows to the ground instead of the output terminal OT. Therefore, the first power supply voltage VSS has the ground potential during the display mode DM.

Second, the operation of the first power supply voltage supply unit during the sensing mode SM will be described in detail with reference to FIGS. 4, 5, and 6B.

During the sensing mode SM, the selection signal SS is output as the first logic level voltage V1 and the recycle signal RS is output as the first logic level voltage V1. The fourth transistor T4 is turned off by the recycle signal RS of the first logic level voltage V1 and the third transistor T3 is also turned off due to the turn- do. The fifth transistor T5 is turned off by the selection signal SS of the first logic level voltage V1.

Since the third transistor T3 is turned off, the buck converter 110 normally outputs the second DC voltage. Since the fifth transistor T5 is turned off, the source current of the buck converter 110 flows to the output terminal OT. Therefore, the first power supply voltage VSS has the potential of the second DC voltage during the sensing mode SM.

Third, the operation of the first power supply voltage supply unit during the recycle mode RM will be described in detail with reference to FIGS. 4, 5, and 6C.

During the recycle mode RM, the selection signal SS is output as the first logic level voltage V1 and the recycle signal RS is output as the second logic level voltage V2. The fourth transistor T4 is turned on by the recycle signal RS of the second logic level voltage V2. Due to the turn-on of the fourth transistor T4, the control electrode of the third transistor T3 is connected to the ground, so that the third transistor T3 is also turned on. The fifth transistor T5 is turned off by the selection signal SS of the first logic level voltage V1.

Since the third transistor T3 is turned on, the second node N2 and the third node N3 of the buck converter 110 are electrically connected. Accordingly, when the second node N2 is connected to the third node N3, the control IC 114 controls the pulse width of the first control signal to be narrowed and the pulse width of the second control signal to be widened, This causes the buck converter 110 to operate in the sink mode. When the buck converter 110 operates in the sink mode, the voltage charged in the multilayer ceramic capacitor MLCC is discharged to the input terminal IT of the buck converter 110 as shown in FIG. 6B, so that a sink current flows do.

As described above, the embodiment of the present invention changes from the sensing mode to the display mode through the recycle mode without changing the sensing mode directly to the display mode. Thus, the embodiment of the present invention can discharge the voltage charged in the capacitor such as the multilayer ceramic capacitor in the recycle mode to the input terminal of the first power supply voltage supply part. Accordingly, the embodiment of the present invention can prevent a voltage charged in a capacitor such as a multilayer ceramic capacitor from rapidly discharging to the ground. Therefore, the embodiment of the present invention can prevent stress from being applied to the circuit elements located in the discharge path due to the overcurrent.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

10: display panel 20: data driver
21: Source drive IC 22: Flexible film
30: scan driver 31: scan signal output unit
32: sensing signal output unit 40: timing control unit
50: power supply unit 60: source circuit board
70: Control circuit board 80: Cable
110: Buck converter 111: DC-AC conversion circuit
112: smoothing circuit 113: voltage dividing circuit
114: Control IC 120: Recycle control circuit
130: Voltage selection output section

Claims (12)

A DC-AC conversion circuit that converts a first DC voltage input to an input terminal into an AC voltage swinging between a predetermined voltage lower than the first DC voltage and outputs the AC voltage to a first node;
A smoothing circuit converting the AC voltage into a second DC voltage and outputting the second DC voltage to a second node;
A plurality of resistors connected between the second node and ground;
A control IC for monitoring a voltage of a third node connected between the plurality of resistors; And
And a recycle control circuit for switching connection between said second node and said third node in accordance with a recycle signal. The method according to claim 1,
The DC-AC conversion circuit includes:
A first transistor for switching a connection between the input terminal and the first node according to a first control signal; And
And a second transistor for switching a connection between the first node and a terminal to which the second DC voltage is input according to a second control signal which is an inverted signal of the first control signal. The method according to claim 1,
The smoothing circuit includes:
An inductor connected between the first node and a second node, and a first capacitor connected between the second node and ground. The method according to claim 1,
The recycle control circuit includes:
A third transistor for switching a connection between the second node and the third node; And
And a fourth transistor for supplying a turn-on voltage to the control electrode of the third transistor when the recycle signal is input. The method according to claim 1,
And a voltage selection output unit for outputting the second DC voltage or the ground voltage according to the selection signal. The method according to claim 1,
And a multilayer ceramic capacitor connected between the second node and the ground. A display panel including a first power supply line; And
And a power supply unit for supplying a first power supply voltage to the first power supply wiring,
The power supply unit,
A DC-AC conversion circuit that converts a first DC voltage input to an input terminal into an AC voltage swinging between a predetermined voltage lower than the first DC voltage and outputs the AC voltage to a first node;
A smoothing circuit converting the AC voltage into a second DC voltage and outputting the second DC voltage to a second node;
A plurality of resistors connected between the second node and ground;
A control IC for monitoring a voltage of a third node connected between the plurality of resistors; And
And a recycle control circuit for switching connection between said second node and said third node in accordance with a recycle signal. 8. The method of claim 7,
Wherein the display panel further comprises a plurality of pixels each including an organic light emitting diode and a driving transistor for supplying a driving current to the organic light emitting diode,
A cathode electrode of the organic light emitting diode is electrically connected to the first power supply line,
Sequentially controlling a display mode for emitting an organic light emitting diode of each of the plurality of pixels, a sensing mode for sensing at least one predetermined voltage of the plurality of pixels, and a recycle mode for outputting the recycle signal, And a timing controller for outputting a recycle signal of the first logic level voltage in the display mode and the sensing mode and outputting a recycle signal of the second logic level voltage in the recycle mode. 9. The method of claim 8,
Wherein the recycle control circuit electrically connects the second node and the third node when the recycle signal of the second logic level voltage is input, and when the recycle signal of the first logic level voltage is input, And disconnects the connection of the third node. 9. The method of claim 8,
Wherein the power supply unit further comprises a voltage selection output unit for outputting the second DC voltage or the ground voltage according to a selection signal. 11. The method of claim 10,
Wherein the timing control unit comprises:
And outputs a selection signal of a second logic level voltage to the voltage selection output unit in the display mode and outputs a selection signal of a first logic level voltage in the sensing mode and the recycle mode to the voltage selection output unit. 12. The method of claim 11,
Wherein the voltage selection output unit outputs the ground voltage to the first power supply voltage when a selection signal of the second logic level voltage is input and outputs the second DC voltage when the selection signal of the first logic level voltage is input And outputs the first power supply voltage.

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