KR20170116920A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device including a field-effect transistor, and more particularly, to a method of manufacturing a semiconductor device including forming a semiconductor layer including a first semiconductor material and a second semiconductor material on a substrate, Patterning to form a pre-active pattern; oxidizing the exposed both sidewalls of the pre-active pattern to form oxide films on the sidewalls, respectively; And removing the semiconductor pattern interposed between the pair of upper patterns to form an active pattern including the pair of upper patterns. Wherein the oxide films comprise an oxide of the first semiconductor material and the concentration of the second semiconductor material in the top patterns is greater than the concentration of the second semiconductor material in the semiconductor pattern.

Description

[0001] The present invention relates to a method for manufacturing semiconductor devices,

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a field effect transistor.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. Semiconductor devices can be classified into a semiconductor memory element for storing logic data, a semiconductor logic element for processing logic data, and a hybrid semiconductor element including a memory element and a logic element. As the electronics industry develops, there is a growing demand for properties of semiconductor devices. For example, there is an increasing demand for high reliability, high speed and / or multifunctionality for semiconductor devices. In order to meet these requirements, structures in semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more and more highly integrated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device including a field effect transistor having improved electrical characteristics.

Another object of the present invention is to provide a method of manufacturing a semiconductor device including a field effect transistor having improved electrical characteristics.

According to the concept of the present invention, a method of manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material; Patterning the semiconductor layer to form a preliminary active pattern; Oxidizing the exposed both sidewalls of the pre-active pattern to form oxide films on the sidewalls, forming top patterns in the pre-active pattern when the oxide films are formed; And removing the semiconductor pattern interposed between the pair of upper patterns to form an active pattern including the pair of upper patterns. The concentration of the second semiconductor material in the upper patterns may be greater than the concentration of the second semiconductor material in the semiconductor pattern.

According to the concept of the present invention, a method of manufacturing a semiconductor device includes: forming an active pattern on a substrate; And forming a gate electrode extending in one direction across the active pattern. Wherein forming the active pattern comprises forming a bottom pattern and a pair of channel patterns on the bottom pattern, the bottom pattern comprising a first semiconductor material, the pair of channel patterns comprising a first semiconductor And a portion of the gate electrode interposed between the pair of channel patterns may be reduced in width in the one direction as it is further away from the substrate.

A semiconductor device according to the concept of the present invention includes a substrate; The active pattern on the substrate, the active pattern comprising a lower pattern and a pair of channel patterns on the lower pattern; And a gate electrode extending in one direction across the channel patterns, wherein the lower pattern comprises a first semiconductor material, the pair of channel patterns forming a second semiconductor material different from the first semiconductor material And a portion of the gate electrode interposed between the pair of channel patterns decreases in width in the one direction as the portion is away from the substrate.

According to the concept of the present invention, a method of manufacturing a semiconductor device includes: forming a base pattern protruding from a substrate; Forming a semiconductor layer covering the base pattern on the substrate; Oxidizing the semiconductor layer to form an oxide film, and forming a channel semiconductor layer between the oxide film and the substrate and between the oxide film and the base pattern; Patterning the channel semiconductor layer to form channel semiconductor patterns on both sidewalls of the base pattern; And removing the portion of the base pattern between the channel semiconductor patterns to form an active pattern including the pair of channel semiconductor patterns, wherein the base pattern includes a first semiconductor material, Layer comprises a first semiconductor material and a second semiconductor material different from the first semiconductor material.

According to the concept of the present invention, a method of manufacturing a semiconductor device includes forming a lower pattern protruding from a substrate, an active pattern including a pair of channel patterns spaced apart from each other in a first direction on the lower pattern; And forming a gate electrode across the active pattern and extending in the first direction, wherein forming the active pattern comprises: forming on the substrate a semiconductor comprising a first semiconductor material and a second semiconductor material, Forming a layer; And forming an oxide layer of the first semiconductor material by performing an oxidation process and forming a layer in which the second semiconductor material is concentrated under the thin oxide layer or on one side of the oxide layer, Each of the patterns includes at least a portion of the enriched layer.

According to embodiments of the present invention, a semiconductor layer including a first semiconductor material and a second semiconductor material may be oxidized to form a pair of channel patterns. At this time, the second semiconductor material is concentrated during the oxidation process, and the channel patterns may contain the second semiconductor material at a high concentration. That is, the channel patterns including the second semiconductor material can be formed without additional processes such as deposition and patterning of the second semiconductor material, thereby reducing the processing cost. Furthermore, since the widths of the channel patterns and the pitch between the channel patterns can be relatively small, it can be advantageous for high integration of devices.

1 is a plan view illustrating a semiconductor device according to embodiments of the present invention.
FIG. 2A is a cross-sectional view taken along line A-A 'of FIG. 1, FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1, and FIG. 2C is a cross- sectional view taken along line C-C 'of FIG.
3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are plan views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention.
3b, 4b, 5b, 6b, 7b, 8b, 9b and 10b are sectional views taken along the line A-A 'in Figs. 3a, 4a, 5a, 6a, 7a, 8a, 9a and 10a, 8d, 9d and 9c are cross-sectional views taken along lines B-B 'of Figs. 3a, 4a, 5a, 6a, 7a, 8a, 9a and 10a, 10d are sectional views taken along the line C-C 'of Figs. 8A, 9A, and 10A, respectively.
11A and 11B illustrate a semiconductor device according to embodiments of the present invention. FIG. 11A is a cross-sectional view taken along line B-B 'of FIG. 1, and FIG. 11B is a cross- Fig.
12 and 13 illustrate a method of manufacturing a semiconductor device according to embodiments of the present invention. FIG. 12 is a cross-sectional view taken along line B-B 'of FIG. 4A, &Quot;
14A to 14C illustrate a semiconductor device according to embodiments of the present invention. FIG. 14A is a cross-sectional view taken along line A-A 'of FIG. 1, and FIG. 14B is a cross- And Fig. 14C is a cross-sectional view taken along the line C-C 'in Fig.
15A, 16A, 17A, 18A, 19A, 20A, 21A and 22A are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
15A, 15B, 16B, 17B, 18B, 19B, 20B, 21B and 22B are sectional views taken along the line A-A 'of FIGS. 15A, 16A, 17A, 18A, 19A, 20A, 21A and 22A, 17c, 18c, 19c, 20c, 21c and 22c are sectional views taken along the line B-B 'in Figs. 15A, 16A, 17A, 18A, 19A, 20A, 21A and 22A.
23 and 24 are sectional views corresponding to line B-B 'in FIG. 22A for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
25A and 25B illustrate a semiconductor device according to embodiments of the present invention. FIG. 25A is a sectional view taken along the line B-B 'in FIG. 1, and FIG. 25B is a sectional view taken along the line C- Fig.
FIG. 26 is a sectional view taken along the line B-B 'in FIG. 15A, FIG. 27 is a sectional view taken along the line B-B' in FIG. 16A, , And Fig. 28 is a cross-sectional view taken along the line B-B 'in Fig. 17A.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a plan view illustrating a semiconductor device according to embodiments of the present invention. FIG. 2A is a cross-sectional view taken along line A-A 'of FIG. 1, FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1, and FIG. 2C is a cross- sectional view taken along line C-C 'of FIG.

Referring to FIGS. 1, 2A, 2B, and 2C, a substrate 100 having a PMOSFET region PR and an NMOSFET region NR may be provided. In one example, the substrate 100 may be a silicon substrate. The PMOSFET region PR may be an active region in which P-type transistors are arranged, and the NMOSFET region NR may be an active region in which N-type transistors are arranged. In one example, the PMOSFET region PR and the NMOSFET region NR may be provided in plural and arranged along the first direction D1.

According to an embodiment of the present invention, the PMOSFET region PR and the NMOSFET region NR may constitute one cell region. The cell region may be a memory cell region in which a plurality of memory cells for storing data are formed. In one example, on the cell region of the substrate 100, memory cell transistors constituting SRAM cells may be disposed. In other words, the cell region may be part of the esram cells. On the other hand, the cell region may be a logic cell region in which the logic transistors constituting the logic circuit of the semiconductor device are disposed. In one example, on the cell region of the substrate 100, logic transistors constituting a processor core or I / O terminal may be disposed. In other words, the cell region may be part of the processor core or I / O terminal.

A first active pattern AP1 extending in a second direction D2 intersecting the first direction D1 may be provided on the PMOSFET region PR. On the NMOSFET region NR, a second active pattern AP2 extending in the second direction D2 may be provided. The first and second active patterns AP1 and AP2 are shown on the PMOSFET region PR and the NMOSFET region NR, respectively, but are not limited thereto. For example, although not shown, two or more first active patterns AP1 may be disposed on the PMOSFET region PR, and two or more second active patterns A2 may be disposed on the NMOSFET region NR .

The first active pattern AP1 may include a first lower pattern LP1 and first channel patterns CH1 on a first lower pattern LP1. The second active pattern AP2 may include the second lower pattern LP2 and the second channel patterns CH2 on the second lower pattern LP2. The first and second lower patterns LP1 and LP2 may extend in a third direction D3 perpendicular to the upper surface of the substrate 100. [ In other words, the first and second lower patterns LP1 and LP2 may vertically protrude from the substrate 100. [ Furthermore, from a plan viewpoint, the first and second lower patterns LP1 and LP2 may have a line or bar shape extending in the second direction D2.

According to an embodiment of the present invention, the first and second lower patterns LP1 and LP2 may be a part of the substrate 100. [ In other words, the first and second lower patterns LP1 and LP2 may include the same semiconductor material as the substrate 100. [ The first and second lower patterns LP1 and LP2 may include a first semiconductor material, for example, the first semiconductor material may be silicon (Si). The first lower pattern LP1 may have an N-type conductivity and the second lower pattern LP2 may have a P-type conductivity.

Device isolation patterns ST may be provided on both sides of each of the first and second lower patterns LP1 and LP2. In one example, at least one device isolation patterns ST may fill a space between the first and second lower patterns LP1 and LP2. In one example, the device isolation patterns ST may include silicon oxide or silicon oxynitride.

The oxidation patterns 115 may be interposed between the first and second lower patterns LP1 and LP2 and the device isolation patterns ST, respectively. Each of the oxidation patterns 115 may include a vertical portion directly covering a side wall extending in the second direction D2 of the first or second lower pattern LP1, LP2. Further, each of the oxidation patterns 115 may include a horizontal portion directly covering a part of the upper surface of the substrate 100. The vertical portion may have a first thickness T1 and the horizontal portion may have a first thickness T1. That is, the oxidation patterns 115 may be conformally formed. The oxidation patterns 115 may comprise an oxide of the first semiconductor material. In one example, the oxidation patterns 115 may comprise silicon oxide.

The upper surfaces of the first and second lower patterns LP1 and LP2 may be located at substantially the same level as each other. The upper surfaces of the oxidation patterns 115 may be substantially coplanar with the upper surfaces of the element isolation patterns ST. The upper surfaces of the first and second lower patterns LP1 and LP2, the upper surfaces of the element isolation patterns ST, and the upper surfaces of the oxidation patterns 115 may be located at substantially the same level . As another example, although not shown, the upper surfaces of the first and second lower patterns LP1 and LP2 may be located at a higher level than the upper surfaces of the element isolation patterns ST and the oxidation patterns 115 . As another example, although not shown, the upper surfaces of the first and second lower patterns LP1 and LP2 may be located at a lower level than the upper surfaces of the element isolation patterns ST and the oxidation patterns 115 have.

The first channel patterns CH1 may have a shape protruding vertically between the element isolation patterns ST and the oxidation patterns 115. [ That is, the first channel patterns CH1 may have a pin shape. Likewise, the second channel patterns CH2 may have a shape protruding vertically between the element isolation patterns ST and the oxidation patterns 115. That is, the second channel patterns CH2 may have a pin shape.

As shown in FIG. 2B, the pair of first channel patterns CH1 may be spaced apart from each other in the first direction D1 on the first lower pattern LP1. That is, in view of the cross section in the first direction D1, the pair of first channel patterns CH1 may be disposed on both side portions of the first lower pattern LP1, respectively. In one example, one side wall of each of the first channel patterns CH1 may be aligned with one side wall of the first lower pattern LP1. However, the embodiments of the present invention are not limited thereto. Each of the first channel patterns CH1 may have a first width W1 in the first direction D1. At this time, the first width W1 may be smaller than the first thickness T1 of the oxidation pattern 115. Likewise, the pair of second channel patterns CH2 may be spaced apart from each other in the first direction D1 on the second lower pattern LP2. That is, in view of the cross section in the first direction D1, the pair of second channel patterns CH2 may be disposed on both sides of the second lower pattern LP2, respectively. In one example, one side wall of each of the second channel patterns CH2 may be aligned with one side wall of the second lower pattern LP2. However, the embodiments of the present invention are not limited thereto. Each of the second channel patterns CH2 may have a first width W1 in a first direction D1.

According to an embodiment of the present invention, the first and second channel patterns CH1 and CH2 may include a second semiconductor material. The second semiconductor material may be different from the first semiconductor material. In other words, the first and second channel patterns CH1 and CH2 may include a semiconductor material different from the first and second lower patterns LP1 and LP2. The first and second channel patterns CH1 and CH2 may further include a first semiconductor material. That is, the first and second channel patterns CH1 and CH2 may include a first semiconductor-second semiconductor compound. In the first and second channel patterns CH1 and CH2, the concentration (e.g., atomic concentration (at%)) of the second semiconductor material is greater than the concentration (e.g., atomic concentration But it is not particularly limited. In one example, the second semiconductor material may be germanium (Ge), and thus the first and second channel patterns CH1, CH2 may comprise germanium (Ge) or silicon-germanium (SiGe). The first channel patterns CH1 may have an N-type conductivity type, and the second channel patterns CH2 may have a P-type conductivity type.

On the other hand, the concentration of the second semiconductor material of the first and second channel patterns CH1 and CH2 may be changed in the first direction D1 within the above range. The concentration of germanium in one portion of the first channel pattern CH1 adjacent to the oxidation pattern 115 is less than the concentration of germanium in the other portion of the first channel pattern CH1 adjacent to the center of the first lower pattern LP1 May be greater than the concentration of germanium. The concentration of germanium in one portion of the second channel pattern CH2 adjacent to the oxidation pattern 115 is less than the concentration of germanium in the other portion of the second channel pattern CH2 adjacent to the center of the second lower pattern LP2 Lt; / RTI > Specifically, the average concentration of germanium in the first and second channel patterns CH1 and CH2 may be about 20 at% to about 100 at%. Preferably, the average concentration of germanium in the first and second channel patterns CH1, CH2 may be about 50 at% to about 99.9 at%.

On the substrate 100, gate electrodes GE extending in the first direction D1 may be provided so as to intersect with the first and second active patterns AP1 and AP2. The gate electrodes GE may be spaced apart from each other in the second direction D2. Each of the gate electrodes GE may cover upper surfaces and sidewalls of the first channel patterns CH1 and upper surfaces and sidewalls of the second channel patterns CH2. That is, the gate electrodes GE may have a tri-gate structure. Each of the gate electrodes GE is formed on the upper surface of the first lower pattern LP1 between the pair of first channel patterns CH1 and the upper surface of the second lower pattern LP2 between the pair of second channel patterns CH2. 2 upper pattern LP2. Further, each of the gate electrodes GE may traverse the device isolation patterns ST while extending in the first direction D1.

A gate insulating pattern GI may be provided under each of the gate electrodes GE and gate spacers GS may be provided on both sides of each of the gate electrodes GE. Furthermore, a capping pattern GP covering the upper surface of each of the gate electrodes GE can be provided. The gate insulating pattern GI may extend into a space between the gate electrode GE and the gate spacers GS. Further, the gate insulating pattern GI may horizontally extend along the gate electrode GE, and may directly cover the element isolation patterns ST and the oxidation patterns 115.

The gate electrodes GE may include at least one of a doped semiconductor, a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a metal (e.g., aluminum, tungsten, etc.). The gate insulating patterns GI may include at least one of a silicon oxide film, a silicon oxynitride film, and a high-k film having a higher dielectric constant than the silicon oxide film (for example, hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate) . The capping patterns GP and the gate spacers GS may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, respectively.

The first source / drain patterns SD1 may be disposed on the first lower pattern LP1 on both sides of the gate electrode GE and on the second lower pattern LP2 on both sides of the gate electrode GE. And the second source / drain patterns SD2 may be disposed. That is, each of the first channel patterns CH1 may be positioned vertically below the gate electrode GE and between a pair of first source / drain patterns SD1 that are horizontally adjacent to each other. Each of the second channel patterns CH2 may be positioned vertically below the gate electrode GE and between a pair of second source / drain patterns SD2 that are horizontally adjacent to each other. As shown in Fig. 2C, in view of the cross section in the first direction D1, a pair of first source / drain patterns SD1 are arranged on both sides of the first lower pattern LP1 . In addition, a pair of second source / drain patterns SD2 may be disposed on both sides of the second lower pattern LP2, respectively. As another example, unlike the illustrated example, a pair of first source / drain patterns SD1 may be connected to one another to form one first source / drain pattern SD1. In this case, the pair of first channel patterns CH1 may be in common contact with the first source / drain pattern SD1. Similarly, a pair of second source / drain patterns SD2 may be connected to each other to form one second source / drain pattern SD2.

The first source / drain patterns SD1 may be epitaxial patterns grown epitaxially on the first lower pattern LP1. Each of the first channel patterns CH1 may be interposed between the pair of first source / drain patterns SD1. The upper surface of the first source / drain patterns SD1 may be located at a higher level than the upper surfaces of the first channel patterns CH1. The second source / drain patterns SD2 may be epitaxial patterns grown epitaxially on the second lower pattern LP2. Each of the second channel patterns CH2 may be interposed between the pair of second source / drain patterns SD2. The upper surface of the second source / drain patterns SD2 may be located at a higher level than the upper surfaces of the second channel patterns CH2.

The first source / drain patterns SD1 may comprise epitaxial patterns, a material which provides a compressive strain on the first channel pattern CH1 interposed between the pair. The second source / drain patterns SD2 may comprise epitaxial patterns as well as materials that provide a tensile strain on the second channel pattern (CH2) interposed between the pair. The first and second source / drain patterns SD1 and SD2 provide tensile and compressive strains to the first and second channel patterns CH1 and CH2, respectively, so that when the field effect transistor is operating, And the mobility of the carriers generated in the second channel patterns CH1 and CH2 can be improved. For example, when the first and second channel patterns CH1 and CH2 include germanium (Ge) or silicon-germanium (SiGe), the first and second source / drain patterns SD1 and SD2 are Silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In this case, the fraction of silicon and / or the fraction of germanium in the first source / drain patterns SD1 may be different from the fraction of silicon and / or germanium in the second source / drain patterns SD2. The first source / drain patterns SD1 on the PMOSFET region PR may have a P-type conductivity and the second source / drain patterns SD2 on the NMOSFET region NR may have an N- Lt; / RTI >

The first interlayer insulating film 140 may be disposed on the substrate 100. The first interlayer insulating film 140 may cover the sidewalls of the gate spacers GS and the first and second source / drain patterns SD1 and SD2. The upper surface of the first interlayer insulating film 140 may be substantially coplanar with the upper surfaces of the capping patterns GP. A second interlayer insulating film 150 may be disposed on the first interlayer insulating film 140. For example, each of the first and second interlayer insulating films 140 and 150 may include a silicon oxide film or a silicon oxynitride film.

Source / drain contacts CA may be disposed on both sides of at least one of the gate electrodes GE. The source / drain contacts CA may be electrically connected to the first and second source / drain patterns SD1 and SD2 through the second interlayer insulating film 150 and the first interlayer insulating film 140. [ From a plan viewpoint, the source / drain contacts CA may traverse at least one first source / drain pattern SD1. From a plan viewpoint, the source / drain contacts CA may traverse at least one second source / drain patterns SD2.

Each source / drain contact CA may include a first conductive pattern 160 and a second conductive pattern 165 on the first conductive pattern 160. The first conductive pattern 160 may be a barrier conductive film. For example, the first conductive pattern 160 may include at least one of a titanium nitride film, a tungsten nitride film, and a tantalum nitride film. The second conductive pattern 165 may be a metal film. As an example, the second conductive pattern 165 may comprise at least one of tungsten, titanium, and tantalum. Although not shown, a metal silicide film may be interposed between each of the source / drain contacts CA and the first and second source / drain patterns SD1 and SD2. As an example, the metal silicide film may include at least one of titanium silicide, tantalum-silicide, and tungsten-silicide, for example.

Although not shown, wirings for respectively connecting to the source / drain contacts CA on the second interlayer insulating film 150 can be arranged. The wirings may comprise a conductive material.

A semiconductor device according to embodiments of the present invention may include channel patterns containing a high concentration of a second semiconductor material on a substrate including a first semiconductor material. At this time, the second semiconductor material may be selected from materials capable of improving the electrical characteristics of the field-effect transistor. As a result, the electrical characteristics of the semiconductor device can be improved.

3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are plan views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. 3b, 4b, 5b, 6b, 7b, 8b, 9b and 10b are sectional views taken along the line A-A 'in Figs. 3a, 4a, 5a, 6a, 7a, 8a, 9a and 10a, 8d, 9d and 9c are cross-sectional views taken along lines B-B 'of Figs. 3a, 4a, 5a, 6a, 7a, 8a, 9a and 10a, 10d are sectional views taken along the line C-C 'of Figs. 8A, 9A, and 10A, respectively.

Referring to FIGS. 3A to 3C, a semiconductor layer 103 may be formed on the entire surface of the substrate 100. The semiconductor layer 103 may be formed through a selective epitaxial growth process in which the upper surface of the substrate 100 is a seed layer. In one example, the substrate 100 may be a silicon substrate and the semiconductor layer 103 may comprise a first semiconductor material (e.g., silicon) and a second semiconductor material (e.g., germanium). In other words, the semiconductor layer 103 may comprise a first semiconductor-second semiconductor compound. In one example, the semiconductor layer 103 may comprise silicon-germanium (SiGe). In this case, the average concentration of germanium in the semiconductor layer 103 may be less than 20 at% in order to minimize the occurrence of defects due to the difference in lattice constant between the substrate 100 and the semiconductor layer 103.

The substrate 100 may include a PMOSFET region PR and an NMOSFET region NR. A detailed description of the PMOSFET region PR and the NMOSFET region NR may be the same as that described with reference to Fig. 1 and Figs. 2A to 2C.

4A to 4C, the semiconductor layer 103 and the upper portion of the substrate 100 are patterned to form a first active pattern pAP1 on the PMOSFET region PR and a second active pattern pAP2 on the NMOSFET region NR. A preliminary active pattern (pAP2) can be formed. The first and second preliminary active patterns pAP1 and pAP2 may have a line or bar shape extending in the second direction D2. For example, to form the first and second preliminary active patterns pAP1 and pAP2, an anisotropic etching process may be used in which the semiconductor layer 103 and the substrate 100 are sequentially etched.

Forming the first and second preliminary active patterns pAP1 and pAP2 includes forming mask patterns MA on the semiconductor layer 103 and forming the mask patterns MA on the semiconductor layer 103 using an etching mask. (103) and an upper portion of the substrate (100). Thereby, the first trenches TR1 defining the first and second preliminary active patterns pAP1 and pAP2 may be formed. Each of the mask patterns MA may include a buffer pattern M1 and a hard mask pattern M2 which are sequentially stacked. For example, the buffer pattern M1 may include a silicon oxide film or a silicon oxynitride film, and the hard mask pattern M2 may include a silicon nitride film.

Specifically, the semiconductor layer 103 may be patterned to form the first and second semiconductor patterns 105a and 105b, and the upper portion of the substrate 100 may be patterned to form the first and second lower patterns LP1 and LP2 may be formed. The first and second semiconductor patterns 105a and 105b may be formed on the first and second lower patterns LP1 and LP2, respectively. The first and second lower patterns LP1 and LP2 may be a part of the substrate 100 and the first and second lower patterns LP1 and LP2 may be vertically protruded from the substrate 100. [ . The first semiconductor pattern 105a and the first lower pattern LP1 may constitute a first preliminary active pattern pAP1 and the second semiconductor pattern 105b and the second lower pattern LP2 may form a second preliminary active pattern A pattern (pAP2) can be formed.

5A to 5C, an oxidation process may be performed on the entire surface of the substrate 100 to form the oxide films 110. FIG. Specifically, the sidewalls of the first and second pre-active patterns pAP1 and pAP2 exposed by the mask patterns MA during the oxidation process and the top surface of the substrate 100 can be oxidized. Accordingly, the oxide films 110 covering the sidewalls of the first and second preliminary active patterns pAP1 and pAP2 and the top surface of the substrate 100 can be formed. The oxide films 110 may fill portions of the first trenches TR1, respectively. On the other hand, the upper surfaces of the first and second preliminary active patterns pAP1 and pAP2 may be protected by the mask patterns MA during the oxidation process, and may not be oxidized. As an example, the oxidation process may be performed using an oxidizing gas comprising at least one of oxygen, water vapor, and ozone.

During the oxidation process, the first semiconductor material (e.g., silicon) in the substrate 100 and the first and second pre-active patterns pAP1, pAP2 may be selectively oxidized, And may be formed of an oxide (e.g., a silicon oxide film) of the first semiconductor material. For example, the first and second lower patterns LP1 and LP2, which are part of the substrate 100 and the substrate 100, are made of silicon, so that the oxide films 110 can be grown by consuming the silicon therein. The thicknesses of the substrate 100 and the first and second lower patterns LP1 and LP2 may be reduced at the same time as the oxide films 110 are grown. Specifically, the substrate 100 after the oxidation process and the first and second lower patterns LP1 and LP2 after the oxidation process are compared with the boundary IF of the substrate 100 before the oxidation process and the first and second lower patterns LP1 and LP2 LP1, and LP2 may be reduced by the second thickness T2. On the other hand, the oxide films 110 may be conformally formed with a first thickness T1, and the first thickness T1 may be larger than the second thickness T2.

Through the oxidation process, a pair of first upper patterns UP1 from the first semiconductor pattern 105a and a third semiconductor pattern 107a interposed between the pair of first upper patterns UP1 are formed . Through the oxidation process, a pair of second upper patterns UP2 from the second semiconductor pattern 105b and a fourth semiconductor pattern 107b interposed between the pair of second upper patterns UP2 are formed .

Generally, when an oxidation process using an oxidizing gas is performed on a silicon-germanium film, silicon can be preferentially oxidized. Specifically, the oxide films 110 are formed on the first and second semiconductor materials (for example, silicon-germanium as the first semiconductor-second semiconductor compound) in the first and second semiconductor patterns 105a and 105b Can be grown by preferentially consuming the first semiconductor material (e.g., silicon). At this time, a second semiconductor material (for example, germanium) not participating in the oxidation reaction may be moved into the first and second semiconductor patterns 105a and 105b. As a result, layers in which a second semiconductor material (for example, germanium) is concentrated can be formed below the oxide films 110 grown on the first and second semiconductor patterns 105a and 105b, respectively. The layers in which the second semiconductor material is concentrated may correspond to the first and second upper patterns UP1 and UP2.

The first and second upper patterns UP1 and UP2 may be defined as portions in which the second semiconductor material is concentrated to about 20 at% or more in the first and second semiconductor patterns 105a and 105b . The first and second upper patterns UP1 and UP2 may be formed of portions in which the second semiconductor material is concentrated at about 50 at% or more in the first and second semiconductor patterns 105a and 105b Can be defined. On the other hand, the concentration of the second semiconductor material of the first and second upper patterns UP1 and UP2 may be changed in the first direction D1 within this. The concentration of germanium in one portion of the first upper pattern UP1 adjacent to the oxide film 110 is greater than the concentration of germanium in the other portion of the first upper pattern UP1 adjacent to the third semiconductor pattern 107a Lt; / RTI > The concentration of germanium in one portion of the second upper pattern UP2 adjacent to the oxide film 110 is larger than the concentration of germanium in the other portion of the second upper pattern UP2 adjacent to the fourth semiconductor pattern 107b .

On the other hand, the concentration of the second semiconductor material of the third and fourth semiconductor patterns 107a and 107b is higher than the concentration of the second semiconductor material of the first and second semiconductor patterns 105a and 105b before the oxidation process . This may be because, during the oxidation process, the second semiconductor material of the first and second semiconductor patterns 105a and 105b is segregated into the first and second upper patterns UP1 and UP2.

6A to 6C, an element isolation film 113 that completely fills the first trenches TR1 may be formed. The device isolation film 113 may cover the mask patterns MA. For example, the device isolation film 113 may be formed of a silicon oxide film or a silicon oxynitride film. Then, the planarization process can be performed on the device isolation film 113 until the upper surfaces of the mask patterns MA are exposed. As an example, the planarization process may include an etch back and / or a chemical mechanical polishing (CMP) process.

Subsequently, the mask patterns MA exposed by the planarization process can be selectively removed. The openings OP can be formed in the device isolation film 113 while the mask patterns MA are removed. The openings OP may expose upper surfaces of the first and second upper patterns UP1 and UP2 and upper surfaces of the third and fourth semiconductor patterns 107a and 107b.

7A to 7C, the third and fourth semiconductor patterns 107a and 107b exposed by the openings OP are selectively removed to form the first and second active patterns AP1 and AP2, Respectively. The first active pattern AP1 may include a first lower pattern LP1 and a pair of first upper patterns UP1 on the first lower pattern LP1. The second active pattern AP2 may include a pair of second upper patterns UP2 on the second lower pattern LP2 and the second lower pattern LP2. On the other hand, the third and fourth semiconductor patterns 107a and 107b are selectively removed so that the second trenches 107a and 107b are formed between the pair of first upper patterns UP1 and the pair of second upper patterns UP2. Respectively, can be formed. The second trenches TR2 may expose the upper surfaces of the first and second lower patterns LP1 and LP2, respectively.

More specifically, the etching process of the third and fourth semiconductor patterns 107a and 107b is performed by changing the etching rate between the first and second upper patterns UP1 and UP2 and the third and fourth semiconductor patterns 107a and 107b Different etch recipes can be used. In other words, in the etching process, the etching rates of the third and fourth semiconductor patterns 107a and 107b may be higher than the etching rates of the first and second upper patterns UP1 and UP2. For example, in the etching process, the etching rates of the third and fourth semiconductor patterns 107a and 107b may be two times higher than the etching rates of the first and second upper patterns UP1 and UP2. Preferably, the etch rate of the third and fourth semiconductor patterns 107a and 107b relative to the etchant may be at least ten times higher than the etch rate of the first and second top patterns UP1 and UP2.

The difference in etch rate may be due to the difference in concentration of the second semiconductor material between the first and second upper patterns UP1 and UP2 and the third and fourth semiconductor patterns 107a and 107b. As an example, the etching process may be wet etching using an etchant containing ammonium hydroxide. As another example, the etching process may be dry etching using hydrogen bromide. At this time, the etching rates of the third and fourth semiconductor patterns 107a and 107b having a high silicon content may be larger than the etching rates of the first and second upper patterns UP1 and UP2 having a high germanium content.

8A to 8D, the oxide films 110 and the device isolation film 113 are recessed, so that the oxide patterns 115 and the device isolation patterns ST can be formed. Thus, the first and second upper patterns UP1 and UP2 can be exposed between the oxidation patterns 115 and the device isolation patterns ST. Specifically, the first and second upper patterns UP1 and UP2 may be formed to have pin shapes vertically protruded between the device isolation patterns ST and the oxidation patterns 115. [

Then, sequentially stacked sacrificial gate patterns 120 and gate mask patterns 125 may be formed on the first and second active patterns AP1 and AP2. The sacrificial gate patterns 120 may be formed in a line or bar shape extending in the first direction D1 across the first and second upper patterns UP1 and UP2.

Specifically, forming the sacrificial gate patterns 120 and the gate mask patterns 125 includes sequentially forming a sacrificial gate film and a gate mask film on the entire surface of the substrate 100, and patterning them. can do. The sacrificial gate film may comprise a polysilicon film. The gate mask film may include a silicon nitride film or a silicon oxynitride film.

Gate spacers GS may be formed on both sidewalls of each of the sacrificial gate patterns 120. Formation of the gate spacers GS may comprise conformally forming a gate spacer film on the substrate 100 on which the sacrificial gate patterns 120 are formed and anisotropically etching the gate spacer film. The gate spacer film may be formed of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

9A to 9D, first source / drain patterns SD1 may be formed on both sides of each of the sacrificial gate patterns 120 on the first active pattern AP1. Second source / drain patterns SD2 may be formed on both sides of each of the sacrificial gate patterns 120 on the second active pattern AP2.

Specifically, the first source / drain patterns SD1 are formed by etching the upper portions of the first upper patterns UP1 with the gate mask patterns 125 and the gate spacers GS as an etching mask , And the remaining first upper patterns UP1 as a seed layer. The formation of the second source / drain patterns SD2 includes etching the upper portions of the second upper patterns UP2 with the gate mask patterns 125 and the gate spacers GS as an etch mask, And a second epitaxial growth process in which the second upper patterns UP2 are formed as a seed layer. As an example, the selective epitaxial growth process may include a Chemical Vapor Deposition (CVD) process or a molecular beam epitaxy (MBE) process. On the other hand, the first upper pattern UP1 between the pair of first source / drain patterns SD1 may be defined as a first channel pattern CH1 and the pair of second source / drain patterns SD2 ) May be defined as a second channel pattern (CH2).

The pair of first source / drain patterns SD1 may be formed to cause a compressive strain in the first channel pattern CH1 interposed therebetween. A pair of second source / drain patterns SD2 may be formed to induce a tensile strain in the second channel pattern (CH2) interposed therebetween. For example, when the first and second channel patterns CH1 and CH2 include germanium (Ge) or silicon-germanium (SiGe), the first and second source / drain patterns SD1 and SD2 are Silicon (Si), germanium (Ge), and silicon-germanium (SiGe). At this time, it is possible to control the fraction of silicon and / or the fraction of germanium in the first source / drain patterns SD1 to provide a compressive strain in the first channel pattern CH1 and the second source / drain patterns SD2) and / or the fraction of germanium in the second channel pattern (CH2) to provide a tensile strain to the second channel pattern (CH2). The first source / drain patterns SD1 may be doped with a P-type impurity, and the second source / drain patterns SD2 may be doped with an N-type impurity, for example, at the same time as the epitaxial growth process or after the epitaxial growth process. Impurities can be doped.

Referring to FIGS. 10A to 10D, a first interlayer insulating film 140 may be formed on the front surface of the substrate 100. For example, the first interlayer insulating film 140 may be formed of a silicon oxide film or a silicon oxynitride film. Then, a process of planarizing the first interlayer insulating film 140 may be performed until the upper surfaces of the sacrificial gate patterns 120 are exposed. The planarization process may include an etch-back and / or CMP process. When the first interlayer insulating film 140 is planarized, the gate mask patterns 125 on the sacrificial gate patterns 120 may be removed together.

The sacrificial gate patterns 120 may be respectively replaced with gate electrodes GE. In particular, forming the gate electrodes GE includes removing the exposed sacrificial gate patterns 120 to form gap regions between the gate spacers GS, a gate dielectric layer sequentially filling the gap regions, and Forming a gate conductive film, and planarizing the gate dielectric film and the gate conductive film to form a gate insulation pattern (GI) and a gate electrode (GE) in respective gap regions. For example, the gate dielectric layer may be formed of at least one of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer. The gate conductive film may be formed of at least one of a doped semiconductor, a conductive metal nitride, and a metal.

Thereafter, the gate insulating patterns GI and the gate electrodes GE in the gap regions are partially recessed, and capping patterns GP are formed on the gate electrodes GE, respectively. In one example, the capping patterns GP may be formed of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Referring again to FIG. 1 and FIGS. 2A to 2C, a second interlayer insulating film 150 may be formed on the first interlayer insulating film 140. For example, the second interlayer insulating film 150 may be formed of a silicon oxide film or a silicon oxynitride film.

Then, source / drain contacts CA may be formed on both sides of at least one of the gate electrodes GE. Specifically, contact holes may be formed through the second interlayer insulating film 150 and the first interlayer insulating film 140 to expose the first and second source / drain patterns SD1 and SD2. When the contact holes are formed, the upper portions of the first and second source / drain patterns SD1 and SD2 may be partially etched. Then, a first conductive pattern 160 and a second conductive pattern 165 filling sequentially the respective contact holes may be formed. The first conductive pattern 160 may be a barrier conductive film, and may be formed of at least one of, for example, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film. The second conductive pattern 165 may be a metal film, and may be formed of at least one of tungsten, titanium, and tantalum, for example.

Although not shown, wirings for respectively connecting to the source / drain contacts CA on the second interlayer insulating film 150 can be formed subsequently. The wirings may comprise a conductive material.

A method of manufacturing a semiconductor device according to embodiments of the present invention may oxidize a side wall of a semiconductor pattern including a first semiconductor material and a second semiconductor material to form a pair of channel patterns. At this time, the second semiconductor material is concentrated during the oxidation process so that the channel patterns can contain the second semiconductor material at a high concentration. That is, channel patterns including the second semiconductor material can be formed without additional processing such as deposition and patterning of the second semiconductor material, thereby reducing the processing cost. Furthermore, since the widths of the channel patterns and the pitch between the channel patterns can be relatively small, it can be advantageous for high integration of devices.

11A and 11B illustrate a semiconductor device according to embodiments of the present invention. FIG. 11A is a cross-sectional view taken along line B-B 'of FIG. 1, and FIG. 11B is a cross- Fig. In the present embodiment, detailed description of technical features overlapping with those described with reference to FIG. 1 and FIGS. 2A to 2C will be omitted. The same reference numerals as those of the semiconductor device according to the embodiment of the present invention described above can be provided with the same reference numerals.

Referring to FIGS. 1, 2A, 11A and 11B, a first active pattern AP1 extending in a second direction D2 may be provided on the PMOSFET region PR, and the NMOSFET region NR may be provided. A second active pattern AP2 extending in the second direction D2 may be provided.

The first active pattern AP1 may include a first lower pattern LP1 and first channel patterns CH1. The second active pattern AP2 may include a second lower pattern LP2 and second channel patterns CH2.

11A and 11B, in view of the cross section in the first direction D1, each of the first and second lower patterns LP1 and LP2 is formed in a vertical direction (third direction D3) As shown in FIG. In other words, the sidewall of each of the first and second lower patterns LP1 and LP2 may have a positive slope.

One side wall of each of the first channel patterns CH1 may be aligned with the side wall of the first lower pattern LP1. That is, one side wall of each of the first channel patterns CH1 may have a positive slope. Therefore, each of the first channel patterns CH1 can form an angle? With the upper surface of the first lower pattern LP1, and one angle? Can be 60 to 89 degrees. One side wall of each of the second channel patterns CH2 may be aligned with the side wall of the second lower pattern LP2. That is, one side wall of each of the second channel patterns CH2 may have a positive slope. Accordingly, each of the second channel patterns CH2 can form an angle? With the upper surface of the second lower pattern LP2.

On the substrate 100, gate electrodes GE extending in the first direction D1 across the first and second channel patterns CH1 and CH2 may be provided. Referring again to FIG. 11A, in view of the cross section in the first direction D1, each gate electrode GE has a portion GEp interposed between the pair of first channel patterns CH1 . At this time, the width of one portion GEp may decrease as the distance from the substrate 100 increases. Specifically, one portion GEp may have a second width W2 at the bottom thereof and a third width W3 at the top thereof, and the third width W3 may be smaller than the second width W2 . Each of the gate electrodes GE may further include another portion interposed between the pair of second channel patterns CH2, and a detailed description thereof may be similar to the one portion GEp described above .

12 and 13 illustrate a method of manufacturing a semiconductor device according to embodiments of the present invention. FIG. 12 is a cross-sectional view taken along line B-B 'of FIG. 4A, &Quot; In the present embodiment, the detailed description of the technical features overlapping with those described with reference to Figs. 3A to 10D is omitted.

Referring to FIGS. 4A, 4B, and 12, first and second preliminary active patterns pAP1 and pAP2 may be formed by patterning the result of FIGS. 3A to 3C. The width of each of the first and second preliminary active patterns pAP1 and pAP2 in the first direction D1 becomes smaller in the vertical direction (third direction D3) . In other words, each of the first and second preliminary active patterns pAP1 and pAP2 may be formed such that the width thereof decreases as the distance from the substrate 100 increases. The sidewall of each of the first and second preliminary active patterns pAP1 and pAP2 may have a positive slope.

Referring to FIGS. 5A, 5B, and 13, an oxidation process may be performed on the entire surface of the substrate 100 to form oxide films 110. The oxide films 110 are formed and the third semiconductor pattern 105a is sandwiched between the pair of first upper patterns UP1 and the pair of first upper patterns UP1, (107a) may be formed. A pair of second upper patterns UP2 from the second semiconductor pattern 105b and a fourth semiconductor pattern 107b interposed between the pair of second upper patterns UP2 may be formed .

The first and second upper patterns UP1 and UP2 are formed along the inclined profile of the first and second pre-active patterns pAP1 and pAP2 described with reference to Figs. 4A, 4B, and 12 . Thus, each of the first upper patterns UP1 can form an angle &thetas; with the upper surface of the first lower pattern LP1, and one angle &thetas; Lt; / RTI > Each of the second upper patterns UP2 may form an angle? With the upper surface of the second lower pattern LP2.

Each of the third and fourth semiconductor patterns 107a and 107b may be formed so that the width thereof decreases as the distance from the substrate 100 increases. For example, each of the third and fourth semiconductor patterns 107a and 107b may have a fourth width W4 in a first direction D1 below the first and second semiconductor patterns 107a and 107b, And may have a fifth width W5. The fifth width W5 may be smaller than the fourth width W4.

The subsequent steps may be performed similarly to those described above with reference to Figs. 6A to 10D, and finally, the semiconductor elements described with reference to Figs. 1, 2A, 11A, and 11B may be formed.

14A to 14C illustrate a semiconductor device according to embodiments of the present invention. FIG. 14A is a cross-sectional view taken along line A-A 'of FIG. 1, and FIG. 14B is a cross- And Fig. 14C is a cross-sectional view taken along the line C-C 'in Fig. In the present embodiment, detailed description of technical features overlapping with those described with reference to FIG. 1 and FIGS. 2A to 2C will be omitted. The same reference numerals as those of the semiconductor device according to the embodiment of the present invention described above can be provided with the same reference numerals.

Referring to FIGS. 1 and 14A to 14C, a first active pattern AP1 extending in a second direction D2 may be provided on the PMOSFET region PR, and a second active pattern AP1 may be provided on the NMOSFET region NR. A second active pattern AP2 extending in the direction D2 may be provided.

The first active pattern AP1 may include a first lower pattern LP1 and a pair of first channel patterns CH1 on the first lower pattern LP1. The first lower pattern LP1 may include first sidewall patterns SWP1 on both sidewalls of the recessed first base pattern rBP1 and the recessed first base pattern rBP1. The second active pattern AP2 may include a second lower pattern LP2 and a pair of second channel patterns CH2 on the second lower pattern LP2. The second lower pattern LP2 may include second sidewall patterns SWP2 on both sidewalls of the recessed second base pattern Rbp2 and the recessed second base pattern rBP1.

The first and second lower patterns LP1 and LP2 may extend in a third direction D3 perpendicular to the upper surface of the substrate 100. [ In other words, the first and second lower patterns LP1 and LP2 may vertically protrude from the substrate 100. [ Furthermore, from a plan viewpoint, the first and second lower patterns LP1 and LP2 may have a line or bar shape extending in the second direction D2.

According to an embodiment of the present invention, the recessed first and second base patterns rBP1 and rBP2 may be part of the substrate 100. [ That is, the recessed first and second base patterns rBP1 and rBP2 may include the same semiconductor material as the substrate 100. [ The recessed first and second base patterns rBP1, rBP2 may comprise a first semiconductor material, for example the first semiconductor material may be silicon. Meanwhile, the first and second sidewall patterns SWP1 and SWP2 may include a second semiconductor material. The second semiconductor material may be different from the first semiconductor material. In other words, the first and second sidewall patterns SWP1 and SWP2 may include a semiconductor material different from the recessed first and second base patterns rBP1 and rBP2. The first and second sidewall patterns SWP1 and SWP2 may further include a first semiconductor material. That is, the first and second sidewall patterns SWP1 and SWP2 may include the first semiconductor-second semiconductor compound. The concentration of the second semiconductor material (for example, atomic concentration (at%)) is less than the concentration (for example, atomic concentration (at%)) of the first semiconductor material in the first and second sidewall patterns SWP1 and SWP2 But it is not particularly limited. In one example, the second semiconductor material may be germanium (Ge). In this case, the average concentration of germanium in the first and second sidewall patterns SWP1 and SWP2 may be about 20 at% to about 100 at%. That is, the first and second sidewall patterns SWP1 and SWP2 may include silicon-germanium (SiGe) or germanium (Ge).

Device isolation patterns ST may be provided on both sides of each of the first and second lower patterns LP1 and LP2. The liner patterns 119 may be interposed between the first and second lower patterns LP1 and LP2 and the element isolation patterns ST and between the substrate 100 and the element isolation patterns ST . The liner patterns 119 may comprise silicon nitride (SiN), silicon carbide nitride (SiCN), silicon boron nitride (SiBN), or silicon boron nitride carbide (SiCBN).

The upper surfaces of the first and second lower patterns LP1 and LP2 may be located at substantially the same level as each other. The upper surfaces of the liner patterns 119 can be substantially coplanar with the upper surfaces of the element isolation patterns ST. For example, the upper surfaces of the first and second lower patterns LP1 and LP2, the upper surfaces of the element isolation patterns ST, and the upper surfaces of the liner patterns 119 may be located at substantially the same level . As another example, although not shown, the upper surfaces of the first and second lower patterns LP1 and LP2 may be located at a higher level than the upper surfaces of the element isolation patterns ST and the liner patterns 119 . As another example, although not shown, the upper surfaces of the first and second lower patterns LP1 and LP2 may be located at a lower level than the upper surfaces of the element isolation patterns ST and liner patterns 119 have.

The first channel patterns CH1 may have a shape protruding vertically between the element isolation patterns ST and the liner patterns 119. [ That is, the first channel patterns CH1 may have a pin shape. Likewise, the second channel patterns CH2 may have a shape protruding vertically between the element isolation patterns ST and the liner patterns 119. That is, the second channel patterns CH2 may have a pin shape.

As shown in FIG. 14B, the pair of first channel patterns CH1 may be spaced apart from each other in the first direction D1 on the first lower pattern LP1. That is, in view of the cross section in the first direction D1, the pair of first channel patterns CH1 are formed on both sides of the first lower pattern LP1 (i.e., the first sidewall patterns SWP1) Respectively. In one example, one side wall of each of the first channel patterns CH1 may be aligned with one side wall of the first sidewall pattern SWP1. Likewise, the pair of second channel patterns CH2 may be spaced apart from each other in the first direction D1 on the second lower pattern LP2. That is, in view of the cross section in the first direction D1, the pair of second channel patterns CH2 are formed on both sides of the second lower pattern LP2 (i.e., the second sidewall patterns SWP2) Respectively. In one example, one side wall of each of the second channel patterns CH2 may be aligned with one side wall of the second sidewall pattern SWP2. Each of the first channel patterns CH1 may have a first width W1 in the first direction D1 and may be connected to the first sidewall pattern SWP1 under the first width D1 to form an integral body. Each of the second channel patterns CH2 may have a first width W1 in the first direction D1 and may be connected to the second sidewall pattern SWP2 thereunder to form an integral body. Each of the second channel patterns CH2 may have a first width W1 in a first direction D1.

The first and second channel patterns CH1 and CH2 may include the same material as the first and second sidewall patterns SWP1 and SWP2. That is, the first and second channel patterns CH1 and CH2 may include a second semiconductor material or a first semiconductor-second semiconductor compound. In one example, the first and second channel patterns CH1 and CH2 may comprise germanium (Ge) or silicon-germanium (SiGe). In this case, the average concentration of germanium in the first and second channel patterns CH1 and CH2 may be about 20 at% to about 100 at%. The first channel patterns CH1 may have an N-type conductivity type, and the second channel patterns CH2 may have a P-type conductivity type.

The gate electrodes GE may extend in the first direction D1 to cross the first and second active patterns AP1 and AP2. Each of the gate electrodes GE may cover upper surfaces and sidewalls of the first channel patterns CH1 and upper surfaces and sidewalls of the second channel patterns CH2. Each of the gate electrodes GE is formed on the upper surface of the first lower pattern LP1 between the pair of first channel patterns CH1 and the upper surface of the second lower pattern LP2 between the pair of second channel patterns CH2. 2 upper pattern LP2. Further, each of the gate electrodes GE may traverse the device isolation patterns ST while extending in the first direction D1.

The first source / drain patterns SD1 may be disposed on the first lower pattern LP1 on both sides of the gate electrode GE and on the second lower pattern LP2 on both sides of the gate electrode GE. And the second source / drain patterns SD2 may be disposed. That is, each of the first channel patterns CH1 may be positioned vertically below the gate electrode GE and between a pair of first source / drain patterns SD1 that are horizontally adjacent to each other. Likewise, each of the second channel patterns CH2 may be positioned vertically below the gate electrode GE and between a pair of second source / drain patterns SD2 that are horizontally adjacent to each other. 14C, a pair of first source / drain patterns SD1 are formed on both sides of the first lower pattern LP1 (that is, 1 sidewall patterns SWP1). In addition, a pair of second source / drain patterns SD2 may be disposed on both sides (i.e., second sidewall patterns SWP2) of the second lower pattern LP2. As another example, unlike the illustrated example, a pair of first source / drain patterns SD1 may be connected to one another to form one first source / drain pattern SD1. In this case, the pair of first channel patterns CH1 may be in common contact with the first source / drain pattern SD1. Similarly, a pair of second source / drain patterns SD2 may be connected to each other to form one second source / drain pattern SD2.

Other configurations are the same as those described with reference to Figs. 2A to 2C, and thus detailed description thereof will be omitted.

15A, 16A, 17A, 18A, 19A, 20A, 21A and 22A are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. 15A, 15B, 16B, 17B, 18B, 19B, 20B, 21B and 22B are sectional views taken along the line A-A 'of FIGS. 15A, 16A, 17A, 18A, 19A, 20A, 21A and 22A, 17c, 18c, 19c, 20c, 21c and 22c are sectional views taken along the line B-B 'in Figs. 15A, 16A, 17A, 18A, 19A, 20A, 21A and 22A.

15A to 15C, an upper portion of the substrate 100 is patterned to form a first base pattern BP1 on the PMOSFET region PR and a second base pattern BP2 on the NMOSFET region NR. Can be formed. The first and second base patterns BP1 and BP2 may have a line or bar shape extending in the second direction D2 and may be spaced from each other in the first direction D1. In addition, the first and second base patterns BP1 and BP2 may vertically protrude from the substrate 100. [ According to an embodiment, the widths of the first and second base patterns BP1 and BP2 in the first direction D1 may be constant, but the embodiments of the present invention are not limited thereto.

Forming the first and second base patterns BP1 and BP2 includes forming the mask patterns MA on the substrate 100 and forming the mask patterns MA on the substrate 100 using an etching mask. RTI ID = 0.0 > anisotropically < / RTI > Thereby, the first trenches TR1 defining the first and second base patterns BP1 and BP2 may be formed. Each of the mask patterns MA may include a buffer pattern M1 and a hard mask pattern M2 which are sequentially stacked. For example, the buffer pattern M1 may include a silicon oxide film or a silicon oxynitride film, and the hard mask pattern M2 may include a silicon nitride film.

Referring to FIGS. 16A to 16C, a semiconductor layer 104 may be formed on a substrate 100. The semiconductor layer 104 may be formed to cover the upper surfaces of the substrate 100, the sidewalls of the first and second base patterns BP1 and BP2, and the sidewalls and upper surfaces of the mask patterns MA. According to one embodiment, the semiconductor layer 104 may be formed using an epitaxial growth process. As an example, the epitaxial growth process may include a Chemical Vapor Deposition (CVD) process or a molecular beam epitaxy (MBE) process. The semiconductor layer 104 may be grown conformally on the entire surface of the substrate 100 on which the first and second base patterns BP1 and BP2 are formed without selective epitaxial growth on the substrate 100. [ . The semiconductor layer 104 includes a first semiconductor material (e.g., silicon) and a second semiconductor material (e. G., Germanium), similar to the semiconductor layer 103 described with reference to Figures 3A- . In other words, the semiconductor layer 104 may comprise a first semiconductor-second semiconductor compound. As an example, the semiconductor layer 104 may comprise silicon-germanium (SiGe). In this case, the average concentration of germanium in the semiconductor layer 104 may be less than 20 at% in order to minimize the occurrence of defects due to the difference in lattice constant between the substrate 100 and the semiconductor layer 104.

Referring to FIGS. 17A to 17C, the semiconductor layer 104 may be oxidized to form an oxide film 111. FIG. That is, the oxide film 111 is formed on the upper surface of the substrate 100, the sidewalls of the first and second base patterns BP1 and BP2, and the sidewalls of the mask patterns MA along the profile of the semiconductor layer 104 And upper surfaces.

According to one embodiment, forming the oxide film 111 may include performing at least one processing cycle on the entire surface of the substrate 100, which includes sequentially performing an oxidation process and a heat treatment process. For example, the oxidation process may be performed using an oxidizing gas comprising at least one of oxygen, water vapor, and ozone. The heat treatment process may be performed at a temperature of about 400 ° C to 1200 ° C. Preferably, the oxide film 111 may be formed by performing the above-described process cycle a plurality of times.

During the oxidation process, the first semiconductor material (e.g., silicon) in the semiconductor layer 104 may be selectively oxidized and thus the oxide film 111 may be oxidized to an oxide of the first semiconductor material (e.g., a silicon oxide film) . In other words, the oxide film 111 is formed on the first semiconductor material (for example, silicon) of the first and second semiconductor materials (for example, silicon-germanium as the first semiconductor- ) Can be preferentially consumed. A subsequent thermal processing process can facilitate the transfer of the first semiconductor material (e.g., silicon) within the substrate 100 and the first and second underlying patterns BP1, BP2 into the semiconductor layer 104 . Thus, the substrate 100 and the first semiconductor material (e.g., silicon) in the first and second base patterns BP1 and BP2 are implanted into the adjacent semiconductor layer 104 And can participate in the oxidation reaction. For example, since the substrate 100 and the first and second base patterns BP1 and BP2, which are part of the substrate 100, are made of silicon, the oxide film 111 is supplied from them It can be grown by consuming silicon. As a result, the oxide film 111 on the upper surface of the substrate 100 and the sidewalls of the first and second base patterns BP1 and BP2 is formed thicker than the oxide film 111 on the surface of the mask patterns MA . That is, the third thickness T3 of the oxide film 111 may be larger than the fourth thickness T4.

On the other hand, during a process cycle, a second semiconductor material (e.g., germanium) of the semiconductor layer 104 that has not participated in the oxidation reaction is implanted into the substrate 100 and the first and second underlying patterns BP1 and BP2 And concentrated or moved to the surface of the mask patterns MA and concentrated. Thereby, layers in which a second semiconductor material (for example, germanium) is concentrated can be formed below or on one side of the oxide film 111 formed by oxidizing the semiconductor layer 104. As such, the layers in which the second semiconductor material (e. G., Germanium) is concentrated can be defined as the channel semiconductor layer 112. As an example, the average concentration of germanium in the channel semiconductor layer 112 may be between 20 at% and 100 at%. That is, the channel semiconductor layer 112 may be a silicon germanium layer or a germanium layer.

The channel semiconductor layer 112 has a first portion P1 on the upper surface of the substrate 100, a second portion P2 on the sidewalls of the base patterns BP1 and BP2, And a third portion P3. That is, the first portion P1 of the channel semiconductor layer 112 is formed between the oxide film 111 and the substrate 100, the second portion P2 is formed between the oxide film 111 and the sidewalls of the base patterns BP1 and BP2, The third portion P3 may be interposed between the oxide film 111 and the mask patterns MA, respectively. On the other hand, at least a part of the second portion P2 of the channel semiconductor layer 112 may overlap with the mask patterns MA.

  18A to 18C, a front anisotropic etching process is performed on the substrate 100 to form the first channel semiconductor patterns CSP1 on the sidewalls of the first base pattern BP1, The second channel semiconductor patterns CSP2 may be formed on the sidewalls of the pattern BP2. The anisotropic etching process may be performed until the oxide film 111 and the channel semiconductor layer 112 are sequentially etched to expose the upper surface of the substrate 100 and the upper surface of the mask patterns MA. As a result of the anisotropic etching process, the first and third portions P1 and P3 of the oxide film 111 and the channel semiconductor layer 112 are completely removed, while the channel semiconductor layer 112 under the mask patterns MA is removed, The second portion P2 of the first channel semiconductor pattern CSP1 may be formed of the first and second channel semiconductor patterns CSP1 and CSP2. One sidewalls of the first and second channel semiconductor patterns CSP1 and CSP2 may be aligned with one side walls of the mask patterns. That is, the first and second channel semiconductor patterns CSP1 and CSP2 may be formed in a self-aligned manner to the mask patterns MA.

The first channel semiconductor patterns CSP1 may extend in the second direction D2 along the sidewalls of the first base pattern BP1. Likewise, the second channel semiconductor patterns CSP2 may extend in the second direction D2 along the sidewalls of the second base pattern BP2. The first base pattern BP1 and the first channel semiconductor patterns CSP1 may be defined as a first preliminary active pattern pAP1 and the second base pattern BP2 and the second channel semiconductor patterns CSP2 ) May be defined as a second pre-activation pattern (pAP2).

  19A to 19C, a liner film 117 may be formed on the front surface of the substrate 100. [ That is, the liner film 117 may cover the upper surface of the substrate 100, the sidewalls of the first and second preliminary active patterns pAP1 and pAP2, and the upper surface of the mask patterns MA. According to one embodiment, the liner film 117 may be formed of a nitride-based material. In one example, the liner film 117 may comprise silicon nitride (SiN), silicon carbide nitride (SiCN), silicon boron nitride (SiBN), or silicon boron nitride carbide (SiCBN). The liner film 117 may be formed by atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) or plasma nitridation. The liner film 117 can prevent damage to the first and second channel semiconductor patterns CSP1 and CSP2 in a subsequent process. For example, the liner film 117 may be formed by exposing the exposed sidewalls of the first and second channel semiconductor patterns CSP1 and CSP2 to the heat generated in the subsequent step of forming the device isolation film 113, Can be prevented from being oxidized by the oxygen atom contained in the oxide film.

Subsequently, an element isolation film 113 which completely fills the first trenches TR1 can be formed. The device isolation film 113 may cover the mask patterns MA. For example, the device isolation film 113 may be formed of a silicon oxide film or a silicon oxynitride film. Then, the planarization process can be performed on the device isolation film 113 until the upper surfaces of the mask patterns MA are exposed. As an example, the planarization process may include an etch back and / or a chemical mechanical polishing (CMP) process.

20A to 20C, the element isolation films 113 can be recessed to form element isolation patterns ST. The device isolation patterns ST may be formed to have a height higher than the top surface of the substrate 100 and a top surface lower than the top surfaces of the first and second preliminary active patterns pAP1 and pAP2. Thus, the upper portions of the first and second preliminary active patterns pAP1 and pAP2 can vertically protrude between the element isolation patterns ST. The liner film 117 covering the protruded upper portions of the first and second preliminary active patterns pAP1 and pAP2 may be exposed by the element isolation patterns ST.

21A to 21C, the liner film 117 exposed by the device isolation patterns ST may be selectively removed to form the liner patterns 119. In this case, The uppermost surfaces of the liner patterns 115 may be substantially coplanar with the upper surfaces of the element isolation patterns ST. In addition, the mask patterns MA may be selectively removed to expose the top surfaces of the first and second pre-active patterns pAP1 and pAP2. That is, the upper surfaces of the first and second base patterns BP1 and BP2 may be exposed.

22A to 22C, the exposed first and second base patterns BP1 and BP2 are selectively removed to form a pair of first semiconductor patterns CSP1 and a pair of second channel semiconductors CSP1, And the second trenches TR2 may be formed between the patterns CSP2, respectively. The second trenches TR2 may have bottoms defined by the top surfaces of the recessed first and second base patterns rBP1, rBP2. The top surfaces of the recessed first and second base patterns rBP1 and rBP2 are lower than the top surfaces of the first and second channel semiconductor patterns CSP1 and CSP2, May be higher than the upper surface. For example, the upper surfaces of the recessed first and second base patterns BP1 and BP2 may be located at substantially the same level as the upper surfaces of the element isolation patterns ST. As another example, although not shown, the upper surfaces of the recessed first and second base patterns BP1 and BP2 may be located at a higher level than the upper surfaces of the element isolation patterns ST. As another example, although not shown, the upper surfaces of the recessed first and second base patterns BP1 and BP2 may be located at a lower level than the upper surfaces of the element isolation patterns ST.

On the other hand, together with the formation of the second trenches TR2, the formation of the first and second active patterns AP1 and AP2 can be completed. The first active pattern AP1 may include a first lower pattern LP1 and a pair of first upper patterns UP1 on the first lower pattern LP1. The first lower pattern LP1 may include first sidewall patterns SWP1 on both sidewalls of the recessed first base pattern rBP1 and the recessed first base pattern rBP1. The first sidewall pattern SWP1 is defined as a portion of the first channel semiconductor pattern CSP1 located at a level lower than the top surface of the recessed first base pattern rBP1, May be defined as another portion of the first channel semiconductor pattern CSP1 located at a higher level than the top surface of the first base pattern rBP1. The second active pattern AP2 may include a pair of second upper patterns UP2 on the second lower pattern LP2 and the second lower pattern LP2. The second lower pattern LP2 may include second sidewall patterns SWP2 on both sidewalls of the recessed second base pattern Rbp2 and the recessed second base pattern rBP1. The second sidewall pattern SWP2 is defined as a portion of the second channel semiconductor pattern CSP2 located at a lower level than the upper surface of the recessed second base pattern Rbp2, May be defined as another portion of the second channel semiconductor pattern CSP2 located at a higher level than the upper surface of the second base pattern rBP2.

The selective removal of the first and second base patterns BP1 and BP2 is performed to remove the etch selectivity between the first and second channel semiconductor patterns CSP1 and CSP2 and the first and second base patterns BP1 and BP2 Or the like. In other words, in the etching process, the etching rates of the first and second base patterns BP1 and BP2 may be higher than the etching rates of the first and second channel semiconductor patterns CSP1 and CSP2. The first and second channel patterns CSP1 and CSP2 may be formed on the substrate 100 in such a manner that the first and second base patterns BP1 and BP2 that are part of the substrate 100 include a first semiconductor material (e.g., silicon) The etch rate of the first and second base patterns BP1 and BP2 with respect to the etchant is controlled by the first and second channel semiconductor patterns CSP1 and CSP2 ), Which is higher than the etching rate of the silicon wafer. As an example, the etching process may be wet etching using an etchant containing ammonium hydroxide. As another example, the etching process may be dry etching using hydrogen bromide. At this time, the etch rates of the first and second base patterns BP1 and BP2 formed of silicon may be larger than the etch rates of the first and second channel semiconductor patterns CSP1 and CSP2 having a high germanium content. This makes it easier to selectively remove the first and second base patterns BP1 and BP2 so that the first and second active patterns AP1 and AP2 including the first and second upper patterns UP1 and UP2, , AP2) can be increased.

The subsequent steps may be performed similarly to those described above with reference to Figs. 8A to 10D, and finally, the semiconductor elements described with reference to Figs. 1 and 14A to 14C may be formed.

23 and 24 are sectional views corresponding to line B-B 'in FIG. 22A for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. In the present embodiment, detailed description of technical features overlapping with those described above with reference to Figs. 15A to 22C will be omitted.

23, after the steps of FIGS. 19A to 19C, the liner film 117 and the mask patterns MA are removed so that the openings OP can be formed in the device isolation film 13. FIG. The openings OP may expose the upper surfaces of the first and second channel semiconductor patterns CSP1 and CSP2 and the upper surfaces of the first and second base patterns BP1 and BP2.

Referring to FIG. 24, the first and second base patterns BP1 and BP2 exposed by the openings OP are selectively removed to form a pair of first semiconductor patterns CSP1 and a pair of And second trenches TR2 may be formed between the second channel semiconductor patterns CSP2. The second trenches TR2 may have bottoms defined by the top surfaces of the recessed first and second base patterns rBP1, rBP2. The selective removal of the first and second base patterns BP1 and BP2 may be performed in the same manner as described in Figs. 22A to 22C.

Thereafter, the liner film 117 and the element isolation film 113 are recessed so that the liner patterns 117 and the element isolation patterns ST can be formed. At the same time, And the second activation patterns AP1 and AP2 can be completed.

25A and 25B illustrate a semiconductor device according to embodiments of the present invention. FIG. 25A is a sectional view taken along the line B-B 'in FIG. 1, and FIG. 25B is a sectional view taken along the line C- Fig. In the present embodiment, detailed descriptions of technical features overlapping with those described above with reference to FIG. 1 and FIGS. 14A to 14C will be omitted. The same reference numerals as those of the semiconductor device according to the embodiment of the present invention described above can be provided with the same reference numerals.

Referring to FIGS. 1, 14A, 25A and 25B, a first active pattern AP1 extending in the second direction D2 may be provided on the PMOSFET region PR, and the NMOSFET region NR may be provided. A second active pattern AP2 extending in the second direction D2 may be provided.

The first active pattern AP1 may include a first lower pattern LP1 and a pair of first channel patterns CH1 on the first lower pattern LP1. The first lower pattern LP1 may include first sidewall patterns SWP1 on both sidewalls of the recessed first base pattern rBP1 and the recessed first base pattern rBP1. The second active pattern AP2 may include a second lower pattern LP2 and a pair of second channel patterns CH2 on the second lower pattern LP2. The second lower pattern LP2 may include second sidewall patterns SWP2 on both sidewalls of the recessed second base pattern rBP2 and the recessed second base pattern rBP2.

25A and 25B, in view of the cross section in the first direction D1, each of the first and second lower patterns LP1 and LP2 is arranged in the vertical direction (third direction D3) As shown in FIG. In other words, the sidewall of each of the first and second lower patterns LP1 and LP2 may have a positive slope. One side wall of each of the first channel patterns CH1 may be aligned with the side wall of the first lower pattern LP1 (i.e., the side wall of the first sidewall pattern SWP1). That is, one side wall of each of the first channel patterns CH1 may have a positive slope. Therefore, each of the first channel patterns CH1 can form an angle? With the upper surface of the first lower pattern LP1, and one angle? Can be 60 to 89 degrees. One side wall of each of the second channel patterns CH2 may be aligned with the side wall of the second lower pattern LP2 (i.e., the side wall of the second sidewall pattern SWP2). That is, one side wall of each of the second channel patterns CH2 may have a positive slope. Accordingly, each of the second channel patterns CH2 can form an angle? With the upper surface of the second lower pattern LP2.

On the substrate 100, gate electrodes GE extending in the first direction D1 across the first and second channel patterns CH1 and CH2 may be provided. Referring again to FIG. 25A, in view of the cross section in the first direction D1, each of the gate electrodes GE has a portion GEp interposed between the pair of first channel patterns CH1 . At this time, the width of one portion GEp may decrease as the distance from the substrate 100 increases. Specifically, one portion GEp may have a second width W2 at the bottom thereof and a third width W3 at the top thereof, and the third width W3 may be smaller than the second width W2 . Each of the gate electrodes GE may further include another portion interposed between the pair of second channel patterns CH2, and a detailed description thereof may be similar to the one portion GEp described above .

FIG. 26 is a sectional view taken along the line B-B 'in FIG. 15A, FIG. 27 is a sectional view taken along the line B-B' in FIG. 16A, , And Fig. 28 is a cross-sectional view taken along the line B-B 'in Fig. 17A. In the present embodiment, detailed description of technical features overlapping with those described above with reference to Figs. 15A to 22C will be omitted.

15A, 15B and 26, an upper portion of the substrate 100 is patterned to form a first base pattern BP1 on the PMOSFET region PR and a second base pattern BP2 on the NMOSFET region NR. (BP2) may be formed. The width in the first direction D1 of each of the first and second base patterns BP1 and BP2 decreases in the vertical direction (third direction D3), unlike the case described with reference to FIG. . In other words, each of the first and second base patterns BP1 and BP2 may be formed such that the width thereof decreases as the distance from the substrate 100 increases. The sidewall of each of the first and second base patterns BP1 and BP2 may have a positive slope.

16A, 16B, and 27, a semiconductor layer 104 may be formed on the substrate 100. In this case, The semiconductor layer 104 may be formed to cover the top surfaces of the substrate 100, the inclined sidewalls of the first and second base patterns BP1 and BP2, and the sidewalls and top surfaces of the mask patterns MA. have.

17A, 17B, and 28, a process cycle including at least one step of performing an oxidation process and a heat treatment process sequentially is performed on the entire surface of the substrate 100 to form a channel semiconductor A layer 112 may be formed. The channel semiconductor layer 112 includes a first portion P1 between the oxide film 111 and the substrate 100, a second portion P2 between the oxide film 111 and the sidewalls of the base patterns BP1 and BP2, And a third portion P3 between the oxide film 111 and the mask patterns MA.

The second portion P2 of the channel semiconductor layer 112 can be formed along the inclined profile of the first and second base patterns BP1 and BP2 described above with reference to Figs. 15A, 15B and 26 have. Accordingly, the second portion P2 of the channel semiconductor layer 112 can form an angle? With the upper surface of the first portion P1, and one angle? Lt; / RTI >

The subsequent steps may be performed similarly to those described above with reference to Figs. 18A to 22C, and finally, the semiconductor elements described with reference to Figs. 1, 14A, 25A, and 25B may be formed.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (10)

Forming on the substrate a semiconductor layer comprising a first semiconductor material and a second semiconductor material;
Patterning the semiconductor layer to form a preliminary active pattern;
Oxidizing the exposed both sidewalls of the pre-active pattern to form oxide films on the sidewalls, forming top patterns in the pre-active pattern when the oxide films are formed; And
And removing the semiconductor pattern interposed between the pair of upper patterns to form an active pattern including the pair of upper patterns,
Wherein a concentration of the second semiconductor material in the upper patterns is greater than a concentration of the second semiconductor material in the semiconductor pattern. The method according to claim 1,
Wherein the oxide films comprise an oxide of the first semiconductor material,
Wherein the upper patterns are formed by concentration of the second semiconductor material in the preliminary active pattern when the oxide films are formed. The method according to claim 1,
Wherein patterning the semiconductor layer comprises etching the top of the substrate to form trenches defining the preliminary active pattern. Board;
The active pattern on the substrate, the active pattern comprising a lower pattern and a pair of channel patterns on the lower pattern; And
And a gate electrode extending in one direction across the channel patterns,
Wherein the lower pattern comprises a first semiconductor material and the pair of channel patterns comprise a second semiconductor material different from the first semiconductor material,
Wherein a portion of the gate electrode interposed between the pair of channel patterns decreases in width in the one direction as the distance from the substrate increases. Forming a base pattern protruding from the substrate;
Forming a semiconductor layer covering the base pattern on the substrate;
Oxidizing the semiconductor layer to form an oxide film, and forming a channel semiconductor layer between the oxide film and the substrate and between the oxide film and the base pattern;
Patterning the channel semiconductor layer to form channel semiconductor patterns on both sidewalls of the base pattern; And
Removing a portion of the base pattern between the channel semiconductor patterns to form an active pattern including the pair of channel semiconductor patterns,
Wherein the base pattern comprises a first semiconductor material and the semiconductor layer comprises a second semiconductor material different from the first semiconductor material and the first semiconductor material. 6. The method of claim 5,
Wherein the oxide film comprises an oxide of the first semiconductor material,
Wherein the channel semiconductor layer is formed by concentrating the second semiconductor material under the oxide film or on one side of the oxide film when the oxide film is formed. 6. The method of claim 5,
Wherein oxidizing the semiconductor layer comprises conducting a process cycle at least once including sequentially performing an oxidation process and a heat treatment process. 6. The method of claim 5,
The base pattern is formed by:
Forming a mask pattern on the substrate; And
Etching the upper portion of the substrate with the mask pattern using an etch mask to form trenches defining the underlying pattern. 9. The method of claim 8,
After formation of the trenches, the mask pattern remains on the top surface of the base pattern,
Wherein the semiconductor layer is formed to cover the upper surface of the base pattern. Forming an active pattern including a lower pattern protruding from the substrate and a pair of channel patterns spaced apart from each other in the first direction on the lower pattern; And
Forming a gate electrode across the active pattern and extending in the first direction,
The active pattern is formed by:
Forming a semiconductor layer on the substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material; And
Forming an oxide layer of the first semiconductor material by performing an oxidation process and forming a layer in which the second semiconductor material is concentrated under the thin oxide layer or on one side of the oxide layer,
Wherein each of the pair of channel patterns comprises at least a portion of the concentrated layer.

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