KR20170103204A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20170103204A
KR20170103204A KR1020160025668A KR20160025668A KR20170103204A KR 20170103204 A KR20170103204 A KR 20170103204A KR 1020160025668 A KR1020160025668 A KR 1020160025668A KR 20160025668 A KR20160025668 A KR 20160025668A KR 20170103204 A KR20170103204 A KR 20170103204A
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layer
plug
forming
hydrogen annealing
opening
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KR1020160025668A
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Korean (ko)
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박규태
심양호
이혜미
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에스케이하이닉스 주식회사
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Priority to KR1020160025668A priority Critical patent/KR20170103204A/en
Publication of KR20170103204A publication Critical patent/KR20170103204A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H01L27/10885—
    • H01L27/10891—

Abstract

The present invention relates to a method of manufacturing a semiconductor device capable of filling openings of high aspect ratio without padding or voids, and a method of manufacturing a semiconductor device according to the present invention includes forming a plurality of bit line structures on a substrate; Forming a sacrificial layer between the bit line structures; Etching the sacrificial layer to form a plurality of sacrificial pillars and a plurality of openings located between the sacrificial pillars; Forming a plurality of plug separating portions filling each of the openings; Removing the sacrificial pillars to form contact holes between the plurality of plug separators; Performing hydrogen annealing to deform the sidewall profile of the plug separation portion and the contact hole; And filling the polysilicon layer in the contact hole in which the hydrogen annealing has been performed.

Figure P1020160025668

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a semiconductor device,

The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a high aspect ratio capping method.

The sidewall profile of high aspect ratio openings (e.g., gaps, contact holes) in the semiconductor device fabrication process is an important variable in the subsequent gap fill process.

Embodiments of the present invention provide a method of manufacturing a semiconductor device that can fill openings with high aspect ratios without shims or voids.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes forming a plurality of bit line structures on a substrate; Forming a sacrificial layer between the bit line structures; Etching the sacrificial layer to form a plurality of sacrificial pillars and a plurality of openings located between the sacrificial pillars; Forming a plurality of plug separating portions filling each of the openings; Removing the sacrificial pillars to form contact holes between the plurality of plug separators; Performing hydrogen annealing to deform the sidewall profile of the plug separation portion and the contact hole; And filling the polysilicon layer in the contact hole in which the hydrogen annealing has been performed.

A method for fabricating a semiconductor device according to an embodiment of the present invention includes: forming a nitrogen-containing structure including an opening on a substrate; Performing hydrogen annealing to deform the top portion profile of the opening; And filling the conductive layer in the opening in which the hydrogen annealing is performed.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming a first insulating layer on a substrate; Forming a first opening in the first insulating layer; Forming a sacrificial layer to fill the first opening; Etching a portion of the sacrificial layer to form a second opening; Filling a second insulating layer within the second opening; Removing the sacrificial layer to form a third opening between the second insulating layers; Performing hydrogen annealing to deform the sidewall profile of the third opening and the second insulating layer; And filling the conductive layer within the third opening in which the hydrogen annealing has been performed.

The technique can perform a gap fill without shims or voids in a subsequent capping process by implementing hydrogen annealing to induce migration after forming a high aspect ratio opening.

1A to 1K are plan views showing a method of manufacturing a semiconductor device according to the first embodiment.
2A to 2K are cross-sectional views taken along lines A-A 'and B-B' in FIGS. 1A to 1K.
3A illustrates a semiconductor device according to the second embodiment.
3B is a cross-sectional view taken along line A-A 'and line B-B' in FIG. 3A.
3C is a cross-sectional view taken along the line C-C 'in FIG. 3A.
4A to 4K illustrate an example of a method for forming a semiconductor device according to the second embodiment.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

The following embodiments can describe semiconductor processing for high aspect ratio gap fill.

1A to 1K are plan views showing a method of manufacturing a semiconductor device according to the first embodiment. 2A to 2K are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. 2A to 2K are cross-sectional views taken along lines A-A 'and B-B' in FIGS. 1A to 1K.

As shown in Figs. 1A and 2A, a plurality of first structures 12 may be formed on the substrate 11. [ The first structure 12 may be formed by a photolithography process and an etching process. The first structure 12 may be referred to as a 'first pattern'. The first structure 12 may comprise an insulating material. The first structure 12 may comprise silicon oxide or silicon nitride. In another embodiment, the first structure 12 may comprise a conductive material, in which case the first structure 12 may subsequently be covered with a spacer layer (not shown). When viewed in top view, the first structure 12 may be line-shaped. A first opening (L) in the form of a line may be defined between the plurality of first structures (12).

As shown in Figs. 1B and 2B, a sacrifice layer 13A may be formed. The sacrificial layer 13A may fill the first opening L1 between the first structures 12. The sacrificial layer 13A may be a material having an etch selectivity to the first structure 12. Here, the etching selection ratio may be a selection ratio for dry etching or wet etching. For example, if the first structure 12 comprises silicon nitride, the sacrificial layer 13A may be a material having an etch selectivity to silicon nitride. The sacrificial layer 13A may be silicon oxide. In another embodiment, if the first structure 12 is a silicon oxide, the sacrificial layer 13A may be silicon nitride. In this embodiment, the sacrifice layer 13A may be a silicon oxide base-SOD (Spin On Dielectric). By forming the sacrifice layer 13A by the spin-on coating method as described above, the first opening L can be filled without voids.

As shown in Figs. 1C and 2C, the sacrificial layer 13A may be planarized. Thus, the sacrificial structure 13 can be formed. In order to form the sacrificial structure 13, the sacrificial layer 13A may be planarized such that the upper surface of the first structure 12 is exposed. The planarization of the sacrificial layer 13A can be performed by a CMP (Chemical Mechanical Polishing) process. When viewed in top view, the sacrificial structure 13 may be in the form of a line located between the first structures 12. The sacrificial structure 13 may be referred to as a " sacrificial pattern ".

As described above, the first structure 12 and the sacrificial structure 13 can alternately be formed alternately. When viewed in top view, both the first structure 12 and the sacrificial structure 13 may be line-shaped. Thus, the first structure 12 and the sacrificial structure 13 may be parallel.

As shown in Figs. 1D and 2D, a first mask layer 14 may be formed. The first mask layer 14 may be formed on the first structure 12 and the sacrificial structure 13. The first mask layer 14 may comprise a plurality of first portions 14A. The first portion 14A of the first mask layer 14 may be line-shaped. A portion of the first structure 12 and the sacrificial structure 13 can be simultaneously exposed by the first portion 14A of the first mask layer 14. [

Next, a part of the sacrificial structure 13 can be etched. The sacrificial structure 13 can be selectively etched using the first mask layer 14 as an etching barrier. A plurality of second openings 15 may be formed by etching of the sacrificial structure 13. [ The residual sacrificial structure 13R may be covered by the first mask layer 14. [ The size of the second opening 15 may be defined by the first structure 12 and the residual sacrificial structure 13R. The height of the second opening 15 may be the same as that of the first structure 12. When viewed in top view, the second opening 15 may be rectangular in shape. Since the height of the first structure 12 is high, the second opening 15 can have a high aspect ratio. In order to form the second opening 15, the sacrificial structure 13 may be etched by dry etching. Some sidewalls of the second opening 15 may have a sloped sidewall profile. For example, in the direction of B-B ', the sidewall of the second opening 15 may have a positive slope 15P that has a smaller line width than the upper portion. Such a beneficial slope 15P may be induced by a polymer or the like generated during the etching process of the sacrificial structure 13.

As shown in Figs. 1E and 2E, the first mask layer 14 can be removed.

After the first mask layer 14 is removed, the first structure 12 and the residual sacrificial structure 13R may remain on the substrate 11. [ The residual sacrificial structure 13R and the first structure 12 may define a second opening 15. [ Some sidewalls of the second opening 15 may be provided by the residual sacrificial structure 13R. Some of the sidewalls provided by the residual sacrificial structure 13R may have a pitched slope 15P. Other sidewalls of the second opening 15 may be provided by the first structure 12. Other sidewalls provided by the first structure 12 may have vertical sidewalls.

A second structure 16 filling the second opening 15 may be formed, as shown in Figures 1F, 2F, 1G and 2G. The second structure 16 may be referred to as a 'second pattern'. The residual sacrificial structure 13R and the second structure 16 may be different materials. The second structure 16 may be a material having an etch selectivity to the remaining sacrificial structure 13R. For example, if the residual sacrificial structure 13R comprises silicon oxide, the second structure 16 may be a material having an etch selectivity to silicon oxide. The second structure 16 may be a nitrogen-containing material. The second structure 16 may be silicon nitride. The first structure 12 and the second structure 16 may be the same material and may have an etch selectivity to the remaining sacrificial structure 13R.

The method of forming the second structure 16 is as follows. Referring to Figures 1F and 2F, a silicon nitride layer 16A may be formed on the first structure 12 and the remaining sacrificial structures 13R to fill the second opening 15. [ 1G and 2G, the silicon nitride layer 16A is planarized so that the upper surface of the first structure 12 and the remaining sacrificial structure 13R are exposed to form the second structure 16, . The planarization of the silicon nitride layer 16A can be performed by a CMP (Chemical Mechanical Polishing) process. When viewed in top view, the second structure 16 may be rectangular in shape. That is, the second structure 16 may be in a shape located in the second opening 15. The second sidewall 15 of the second structure 16 has the negative slope 16N because the second structure 16 is filled in the second opening 15 with the pivotal slope 15P.

As described above, the second structure 16 and the residual sacrificial structure 13R may be positioned between the plurality of first structures 12. The second structure 16 and the remaining sacrificial structure 13R may form an isolation line extending in either direction. The first structure 12 and the insulation line may be parallel. The first structure 12 and the insulation line may alternately be formed alternately.

As shown in Figs. 1H and 2H, the residual sacrificial layer 13R can be selectively removed. Therefore, the space from which the residual sacrificial structure 13R is removed can remain in the third opening 17. [ The size of the third opening 17 may be defined by the second structure 16 and the first structure 12. The first structure 12 and the second structure 16 may be a separation layer between neighboring third openings 17. The residual sacrificial structure 13R can be removed by wet etching. During removal of the residual sacrificial structure 13R, the first structure 12 and the second structure 16 may not be lost. When viewed in top view, the third opening 17 may be rectangular in shape. The third opening 17 can expose the surface of the substrate 11. [

The process of forming the series of third openings 17 as described above may be referred to as a damascene process. That is, by forming the third opening 17 by the damascene process, the fine third opening 17 can be easily formed.

The second structure 16 may include a plurality of sidewalls, e.g., a first sidewall S1 and a second sidewall S2. The first sidewall S1 and the second sidewall S2 may be opposed to each other. The first sidewall S1 and the second sidewall S2 may have a negative slope 16N.

The sidewall of the third opening 17 may have a slope profile. For example, the sidewall of the third opening 17 may have a negative slope that has a larger line width than the upper portion. Such a negative slope of the third opening 17 can be induced by the negative slope 16N of the second structure 16. [

The third opening 17, which has a partially negative slope, is disadvantageous for the subsequent gap fill process. For example, a void may be generated in the gap fill process.

This embodiment can deform the negative slope 16N of the second structure 16 by a thermal process.

After forming the third opening 17, the third opening 17 and the second structure 16 may be exposed to the thermal process 18, as shown in Figures 1I and 2I. By the thermal process 18, the migration 18M may occur. For example, migration (18M) of elements contained in the second structure 16 may occur. Thus, the sidewall profile of the second structure 16 can be deformed. The sidewalls of the second structure 16 prior to the thermal process 18 have a negative slope 16N while the second structure 16M on which the thermal process 18 has been performed may have a vertical sidewall profile 16V . Thus, by vertically deforming the sidewall profile of the second structure 16M, the third opening 17M after the thermal process 18 has a vertical sidewall profile. Therefore, voids may not occur in the subsequent opening process 17M in the subsequent capping process. The thermal process 18 may include hydrogen annealing. Hydrogen annealing performs a heat treatment in a hydrogen containing atmosphere. Migration (18M) of nitrogen atoms contained in the second structure 16 occurs by hydrogen annealing. Migration 18M may occur from the top of the second structure 16.

Hydrogen annealing can proceed in-situ or ex-situ. In situ hydrogen annealing can be performed in the deposition equipment of the subsequent preform structure layer 19A. Excit hydrogen annealing may be performed in a separate furnace before deposition of the subsequent preform layer 19A. The preform layer 19A may comprise a polysilicon layer. Thus, in situ hydrogen annealing can be performed in the deposition equipment of the polysilicon layer. Excit hydrogen annealing may be performed in a separate furnace prior to polysilicon layer deposition.

In situ hydrogen annealing can be performed at a low pressure of 3 Torr or less and at a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour. In situ hydrogen annealing can be performed while flowing hydrogen gas (H 2 ) at a flow rate of 1 to 10 l. The pressure can be optimized according to the degree of improvement of the top portion profile of the second structure 16M. When the hydrogen annealing and the polysilicon layer gap fill process are performed in situ, the profile can be improved and the polysilicon layer can be capped at one time.

Exhaust hydrogen annealing can be performed at a low pressure of 3 Torr or less and a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour. Exhaust hydrogen annealing can be performed while flowing hydrogen gas (H 2 ) at a flow rate of 1 to 10 l. The pressure can be optimized according to the degree of improvement of the top portion profile of the second structure 16M.

As shown in FIGS. 1J and 2J, the pre-structure layer 19A may be imaged on the third opening 17M where the thermal process 18 has been performed. The preform layer 19A can fill the third opening 17M without voids. The preform layer 19A may comprise a polysilicon layer. The preform layer 19A may comprise a polysilicon layer doped with a dopant.

As shown in FIGS. 1K and 2K, the third structure 19 may be formed in the third opening 17M. The third structure 19 may be referred to as a 'third pattern'. The third structure 19 may fill the third opening 17M. In order to form the third structure 19, an etch-back process or a CMP process of the preliminary structure layer 19A may be performed. The third structure 19 may be located between the first structures 12. The third structure 19 may be electrically connected to a part of the substrate 11. The first structure 12 and the second structure 16 may be referred to as an 'insulative structure' and the third structure 19 may be referred to as a 'conductive structure'. The first structure 12 and the second structure 16 may be a silicon nitride layer and the third structure 19 may be a polysilicon layer. Thus, this embodiment can capture the polysilicon layer without voids or shims in the opening of the high aspect ratio formed in the nitrogen containing structure.

In accordance with the foregoing, it is possible to induce migration through hydrogen annealing and thus to adjust the physical threshold number of the third opening 17M. As a result, the gap fill characteristic of the preliminary structure layer 19A can be improved.

3A illustrates a semiconductor device according to the second embodiment. The second embodiment describes an example in which hydrogen annealing is applied in a semiconductor device having a memory cell such as a DRAM or the like. 3B is a cross-sectional view taken along line A-A 'and line B-B' in FIG. 3A. 3C is a cross-sectional view taken along the line C-C 'in FIG. 3A.

The semiconductor device 100 may include a memory cell region R10. A plurality of memory cells may be formed in the memory cell region R10. Each memory cell may include a buried word line 107, a bit line 113, and a memory element 121.

The semiconductor device 100 will be described in detail.

The device isolation layer 102 and the active region 103 are formed on the substrate 101. [ A plurality of active regions 103 can be defined in the memory cell R10 by the device isolation layer 102. [

A word line trench 105 is formed in the substrate 101 of the memory cell region R10. A gate insulating layer 106 is formed on the surface of the word line trench 105. A buried word line 107 is formed that partially fills the word line trenches 105 on the gate insulating layer 106. A sealing layer 108 is formed on the buried word line 107. The sealing layer 108 may have the same height as the surface of the substrate 101. The buried word line 107 may be at a lower level than the surface of the substrate 101. [ The word line trenches 105 may be line-shaped across the active region 103 and the device isolation layer 102. A hard mask layer 104 may be formed on the substrate 101.

A pair of first and second doped regions 109 and 110 may be formed in the active region 103. The first and second doped regions 109 and 110 may be spaced apart from each other by a word line trench 105. The first and second doped regions 109 and 110 may be referred to as a source region and a drain region. Thus, the buried word line 107 and the pair of first and second doped regions 109 and 110 can be buried gate type transistors. The buried gate type transistor can improve the short channel effect by the buried word line 107.

A bit line contact plug 112 is formed on a substrate 101. The bit line contact plug 112 is connected to the first doped region 109. The bit line contact plug 112 is located in the first contact hole 111. The first contact hole 111 may be formed in the hard mask layer 104. The first contact hole 111 is a contact hole exposing the first doped region 109. The lower surface of the bit line contact plug 112 may be lower than the upper surface of the substrate 101. [ The bit line contact plug 112 may be formed of polysilicon or a metal material. A portion of the bit line contact plug 112 may have a line width smaller than the diameter of the first contact hole 111. [ Accordingly, a gap is formed on both sides of the bit line contact plug 112. The gap G is formed independently on both sides of the bit line contact plug 112. As a result, one bit line contact plug 112 and a pair of gaps G are located in the first contact hole 111, and the pair of gaps G are separated by the bit line contact plug 112 do. A gap G may be located between the bit line contact plug 112 and the silicon plug 418. [

A bit line structure (BL) is formed on the bit line contact plug (112). The bit line structure BL includes a bit line 113 and a bit line cap layer 114 on the bit line 113. The bit line structure BL has a line shape extending in a direction intersecting with the buried word line 107. A portion of the bit line 113 is connected to the bit line contact plug 112. In the A-A 'direction, the bit line 113 and the bit line contact plug 112 may have the same line width. Thus, the bit line 113 may extend in either direction while covering the bit line contact plug 112. The bit line 113 may comprise a metallic material. The bit line cap layer 114 may comprise an insulating material. A spacer element 115 may be formed on the sidewalls of the bit line structure BL and the bit line contact plug 112. The spacer element 115 may comprise a plurality of spacers. A portion of the spacer element 115 may be filled in the gap G on either side of the bit line contact plug 112.

A cell contact structure may be formed between neighboring bit line structures BL. The cell contact structure is formed in the second contact hole 117. The cell contact structure may be connected to the second doped region 110. When viewed in a direction parallel to the bit line structure BL (direction B-B '), a plug separating portion 116 may be formed between adjacent cell contact structures. The plug separator 116 may be formed between neighboring bit line structures BL. A second contact hole 117 may be further formed between adjacent bit line structures BL. The second contact hole 117 may be formed in the laminated structure of the hard mask layer 104 and the plug separator 116.

The cell contact structure may include a silicon plug 118, a metal plug 120, and a metal silicide 119 between the silicon plug 118 and the metal plug 120. The silicon plug 118 may comprise doped polysilicon and the metal plug 120 may comprise tungsten. The metal silicide 119 is an ohmic contact layer, and the contact resistance is reduced by the metal silicide 119. The metal silicide 119 may comprise cobalt suicide.

A memory element 121 may be formed on the metal plug 120 of the cell contact structure. Memory element 121 may include a capacitor including a storage node. The storage node may include a pillar type. Although not shown, a dielectric layer and a plate node may be further formed on the storage node. The storage node may be cylindrical in addition to the pillar form. In other embodiments, variously implemented memory elements may be connected on the cell contact structure. When the memory element 121 comprises a storage node, the cell contact structure may be referred to as a storage node contact plug (SNC).

As described above, when viewed in a direction parallel to the bit line structure BL (direction B-B '), the plug separation portion 116 can be formed between neighboring cell contact structures. The plug separator 116 may comprise silicon nitride. The plug separating portion 116 may be a structure in which migration occurs at the top portion by hydrogen annealing.

4A to 4K illustrate an example of a method for forming a semiconductor device according to the second embodiment. 4A to 4K are cross-sectional views taken along line A-A 'and line B-B' in FIG. 3A.

As shown in Fig. 4A, a device isolation layer 32 is formed on a substrate 31. Fig. The device isolation layer 32 may be formed through an STI (Shallow Trench Isolation) process. For example, after the substrate 31 is etched to form the trench 32T, the trench 32T may be filled with an insulating material. The active region 33 can be defined by the device isolation layer 32. The active region 33 may be an island type having a short axis and a long axis. A plurality of active regions 33 can be separated by the device isolation layer 32. [ The isolation layer 32 may include silicon nitride, silicon oxide, or a combination thereof.

A hard mask layer 34 may be formed on the substrate 31. The hardmask layer 34 may comprise silicon oxide. The hardmask layer 34 may comprise TEOS (Tetra-Ethyl-Ortho-Silicate).

The word line trench 35 can be formed by etching the substrate 31 using the hard mask layer 34. [ The word line trench 35 may traverse the active region 33 and the device isolation layer 32.

A buried word line structure including a gate insulating layer 36, a buried word line 37, and a sealing layer 38 may be formed in the substrate 31. [ The buried wordline structure may be formed in the wordline trench 35.

Next, the first and second doped regions 39 and 40 may be formed in the active region 33. [ The first and second doped regions 39 and 40 may be referred to as a source region and a drain region. The first doped region 39 is a portion to which a bit line is to be connected, and the second doped region 40 is a portion to which a memory element is to be connected.

Next, a first contact hole 41 may be formed. In order to form the first contact hole 41, the hard mask layer 34 may be etched using a contact mask (not shown). The first contact hole 41 may have a circular shape or an elliptical shape when viewed in a plan view. A part of the substrate 31 is exposed by the first contact hole 41. [ The first contact hole 41 may have a diameter controlled to a certain line width. The first contact hole 41 may be shaped to expose a part of the active region 33. For example, the first doped region 39 may be exposed by the first contact hole 41. The first contact hole 41 has a diameter larger than the width of the minor axis of the active region 33. Therefore, in the etching process for forming the first contact hole 41, the first doped region 39 and a part of the device isolation layer 32 can be etched. That is, the first doped region 39 and the device isolation layer 32 under the first contact hole 41 can be recessed to a certain depth. Thus, the bottom of the first contact hole 41 can be expanded.

Next, a spare plug 42A is formed. A method of forming the preliminary plug 42A will be described below. First, a first conductive layer (not shown) filling the first contact hole 41 is formed on the entire surface of the substrate 31 including the first contact hole 41. Next, the first conductive layer may be selectively etched. For example, the first conductive layer may be etched so that the surface of the hard mask layer 34 is exposed. Thereby, a preliminary plug 42A filling the first contact hole 41 is formed. The surface of the preliminary plug 42A may be coplanar with the surface of the hardmask layer 34, or may be a lower height. Subsequently, the preliminary plug 42A can be doped with an impurity by a doping process such as an implant. In this embodiment, the spare plug 42A may comprise polysilicon. In another embodiment, spare plug 42A may be formed of a metal containing material.

As shown in FIG. 4B, the second conductive layer 43A and the capping layer 44A may be stacked. The second conductive layer 43A and the capping layer 44A may be sequentially stacked on the preliminary plug 42A and the hard mask layer 34. [ The second conductive layer 43A includes a metal-containing material. The second conductive layer 43A may comprise a metal, a metal nitride, a metal suicide, or a combination thereof. In this embodiment, the second conductive layer 43A may include tungsten (W). In another embodiment, the second conductive layer 43A may comprise a layer of titanium nitride and tungsten (TiN / W). At this time, the titanium nitride can serve as a barrier. The capping layer 44A may be formed of an insulating material having an etch selectivity to the second conductive layer 43A and the preliminary plug 42A. The capping layer 44A may comprise silicon oxide or silicon nitride. In this embodiment, the capping layer 44A is formed of silicon nitride.

As shown in FIG. 4C, a bit line structure BL and a bit line contact plug 42 are formed. The bit line structure BL and the bit line contact plug 42 may be formed by an etching process using a bit line mask (not shown).

The capping layer 44A and the second conductive layer 43A are etched using a bit line mask (not shown) as an etching barrier. Accordingly, the bit line structure BL including the bit line 43 and the bit line cap layer 44 can be formed. The bit line 43 may be formed by etching the second conductive layer 43A. The bit line cap layer 44 is formed by etching the capping layer 44A.

Subsequently, the preliminary plug 42A is etched with the same line width as that of the bit line 43. Then, A bit line contact plug 42 is thus formed. A bit line contact plug 42 may be formed on the first doped region 39. The bit line contact plug 42 interconnects the first doped region 39 and the bit line 43. A bit line contact plug 42 is formed in the first contact hole 41. The line width of the bit line contact plug 42 is smaller than the diameter of the first contact hole 41. Therefore, a gap G can be formed around the bit line contact plug 42. [

As described above, the gap G is formed in the first contact hole 41 by forming the bit line contact plug 42. This is because the bit line contact plug 42 is etched to be smaller than the diameter of the first contact hole 41. The gap G is formed independently on both sidewalls of the bit line contact plug 42, not in the surrounding shape surrounding the bit line contact plug 42. As a result, one bit line contact plug 42 and a pair of gaps G are located in the first contact hole 41, and the pair of gaps G are separated by the bit line contact plug 42 do. A portion of the bit line structure, i.e., a portion that is not in contact with the bit line contact plug 42, can be extended to be located on the hard mask layer 34.

As shown in FIG. 4D, a spacer element 45 may be formed. Spacer element 45 may be located on the sidewalls of bit line contact plug 42 and bit line structure BL.

The spacer element 45 may comprise a plurality of spacers. A portion of the spacer element 45 may fill the gap G. [ The spacer element 45 may comprise silicon nitride, silicon oxide, or a combination thereof. For example, after forming the first nitride spacers 45A lining the sidewalls of the bit line contact plugs 42, the bit line structures BL and the gaps G, a gap is formed on the first nitride spacers 45A, The first oxide spacer 45B filling the gap G can be formed. After forming the second oxide spacer 45C on the first oxide spacer 45B, a second nitride spacer 45D may be formed on the second oxide spacer 45C. The first nitride spacer 45A may not remain on the upper surface of the hard mask layer 34. [ A first oxide deposition and etch back process may be performed to form the first oxide spacer 45B. A second oxide deposition and etch back process may be performed to form the second oxide spacer 45C. In another embodiment, a portion of the spacer element 45, e.g., the first oxide spacer 45B and the second oxide spacer 45C, may be removed in a subsequent process. Thus, air can be formed in the spacer element 45. For convenience of description, reference numerals for the first nitride spacer 45A, the first oxide spacer 45B, the second oxide spacer 45C, and the second nitride spacer 45D in the subsequent drawings are omitted .

Next, a sacrificial layer 46 may be formed. The sacrificial layer 46 may fill between the bit line structures BL. The sacrificial layer 46 may be a material having an etch selectivity to the spacer element 45. Here, the etching selection ratio may be a selection ratio for dry etching or wet etching. For example, if the spacer element 45 comprises silicon nitride, the sacrificial layer 46 may be a material having an etch selectivity to silicon nitride. The sacrificial layer 46 may be silicon oxide. In this embodiment, the sacrificial layer 46 may be a silicon oxide base-SOD (Spin On Dielectric). Thus, the bit line structures BL can be filled with the sacrificial layer 46 without voids.

Subsequently, the sacrificial layer 46 may be planarized. Thus, the line-shaped sacrifice layer 46 may remain between the bit line structures BL. The sacrificial layer 46 may be planarized so that the upper surface of the bit line structure BL is exposed, in order to retain the sacrificial layer 46 in the form of a line. The planarization of the sacrificial layer 46 may be performed by a CMP process. In view of the top view, the sacrificial layer 46 may be in the form of a line located between the bit line structures BL.

As described above, the bit line structure BL and the sacrifice layer 46 can be formed alternately alternately. The bit line structure BL and the sacrificial layer 46 may all be line-shaped. Thus, the bit line structure BL and the sacrificial layer 46 can be parallel.

As shown in FIG. 4E, a first mask layer 47 may be formed. The first mask layer 47 may be formed on the bit line structure BL and the sacrificial layer 46. The first mask layer 47 may include a plurality of first portions 47A. The first portion 47A of the first mask layer 47 may be line-shaped. A portion of the bit line structure BL and the sacrificial layer 46 can be simultaneously exposed by the first portion 47A of the first mask layer 47. [

Next, a part of the sacrificial layer 46 may be etched. The sacrificial layer 46 can be selectively etched using the first mask layer 47 as an etching barrier. A plurality of openings 48 may be formed by etching the sacrificial layer 46. The sacrificial layer may have a pillar shape and may remain. This will be abbreviated as sacrificial pillars 46R. The sacrificial pillars 46R may be covered by the first mask layer 47. [ The size of the opening 48 may be defined by the bit line structure BL and the sacrificial pillars 46R. The height of the opening 48 may be the same as the bit line structure BL. When viewed in top view, the opening 48 may be rectangular in shape. The opening 48 may have a high aspect ratio. In order to form the opening 48, the sacrificial layer 46 may be etched by dry etching. The opening 48 may have a slope sidewall profile. For example, the sidewall of the opening 48 may have a gripping slope 48P having a smaller line width than the upper portion. Such a beneficial slope 48P may be induced by a polymer or the like generated during the etching process of the sacrificial layer 46. [ During the etching process of the sacrificial layer 46, the spacer element 45 may serve as an etch stop layer.

As shown in FIG. 4F, the first mask layer 47 may be removed.

Next, a plug separating portion 49 filling the opening 48 can be formed. The sacrificial pillars 46R and the plug separation portions 49 may be different materials. The plug separating portion 49 may be a material having an etch selectivity to the sacrificial pillars 46R. For example, if the sacrificial pill 46R comprises silicon oxide, the plug separation portion 49 may be a material having an etch selectivity to silicon oxide. The plug separating portion 49 may be a nitrogen-containing material. The plug separation portion 49 may be silicon nitride.

A method of forming the plug separation portion 49 is as follows. A silicon nitride layer may be formed to fill the opening 48. Subsequently, the silicon nitride layer may be planarized to expose the upper surfaces of the bit line structure BL and the sacrificial pillars 46R to form the plug separator 49. [0035] FIG. Planarization of the silicon nitride layer can be performed by a CMP process. The plug separating portion 49 may be made of silicon nitride. When viewed in the top view, the plug separating portion 49 may have a rectangular shape. That is, the plug separating portion 49 may be in a shape located in the opening 48.

As described above, the plug separation portion 49 and the sacrificial pillars 46R can be located between the plurality of bit line structures BL. The plug separating portion 49 and the sacrificial pillars 46R can form an insulating line extending in either direction. The bit line structure BL and the insulated line may be parallel. The bit line structure BL and the insulation line can alternately be formed alternately.

As shown in Fig. 4G, the sacrificial pillars 46R can be selectively removed. Therefore, the space from which the sacrificial pillars 46R are removed can remain in the second contact holes 50. [ The size of the second contact hole 50 can be defined by the plug separating portion 49, the bit line structure BL and the spacer element 45. The plug separation portion 49 may be a separation layer between adjacent second contact holes 50. The sacrificial pillars 46R may be removed by wet dip-out. During removal of the sacrificial pillars 46R, the bit line structure BL, the spacer element 45 and the plug separator 49 may not be lost. When viewed from the top view, the second contact hole 50 may have a rectangular shape.

Next, the bottom portion of the second contact hole 50 is extended. To this end, part of the spacer element 45 is etched back. Subsequently, the hard mask layer 34 is etched by self-alignment to the sidewalls of the spacer elements 45. Thus, the second doped region 40 is exposed under the second contact hole 50. A portion of the second doped region 40 and the element isolation layer 32 may be subsequently recessed to a certain depth.

The plug separating portion 49 defining the second contact hole 50 may include a first side wall S1 and a second side wall S2. The first sidewall S1 and the second sidewall S2 may be the sidewalls of the second contact hole 50. The first sidewall S1 and the second sidewall S2 may be opposed to each other.

The side wall of the plug separating portion 49 may have a slope profile. For example, the sidewall of the plug separating portion 49 may have a negative slope 49N having a larger line width than the upper portion. Such a negative slope 49N can be induced by the sidewall profile of the opening (48 in FIG. 9E). The opening 48 having the flexible slope 48P is filled with the plug separating portion 49 so that the side wall of the plug separating portion 49 has the negative slope 49N. Since the second contact hole 50 is defined between the plug separating portions 49, some sidewalls of the second contact hole 50 can also have a negative slope 49N. The other sidewalls of the second contact hole 50, i.e., the sidewalls defined by the spacer element 45, may be vertical.

This embodiment can deform the negative slope 49N by a thermal process.

The second contact hole 50 and the plug separating portion 49 may be exposed to the hydrogen annealing 51, as shown in Fig. 4H. By the hydrogen annealing 51, migration may occur. For example, migration of the elements contained in the plug separation portion 49 may occur. Thus, the sidewall profile of the plug separating portion 49 can be deformed. The sidewalls of the plug separator 49 prior to the hydrogen annealing 51 have a negative slope 49N but the plug separator 49M exposed to the hydrogen annealing 51 may have a vertical sidewall profile 49V . As described above, when the sidewall profile of the plug separating portion 49M is vertically deformed, voids may not be generated in the subsequent capping process. The hydrogen annealing 51 performs a heat treatment in a hydrogen-containing atmosphere. The migration of the nitrogen atoms contained in the plug separation portion 49 occurs by the hydrogen annealing 51. [ Migration may occur from the top portion of the second contact hole 50. Since the plug separating portion 49M has a vertical sidewall profile 49V, the second contact hole 50M exposed to the hydrogen annealing 51 also has a vertical sidewall profile.

The hydrogen anneal 51 may proceed to an in-situ or ex situ. In situ hydrogen annealing may be performed in the deposition equipment of the subsequent polysilicon layer. Excit hydrogen annealing may be performed in a separate furnace prior to polysilicon layer deposition.

In situ hydrogen annealing can be performed at a low pressure of 3 Torr or less and at a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour. In situ hydrogen annealing can be performed while flowing hydrogen gas (H 2 ) at a flow rate of 1 to 10 l. The pressure can be optimized according to the degree of improvement of the top portion profile of the plug separating portion 49M. When the hydrogen annealing and the polysilicon layer gap fill process are performed in situ, the profile can be improved and the polysilicon layer can be capped at one time.

Exhaust hydrogen annealing can be performed at a low pressure of 3 Torr or less and a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour. Exhaust hydrogen annealing can be performed while flowing hydrogen gas (H 2 ) at a flow rate of 1 to 10 l. The pressure can be optimized according to the degree of improvement of the top portion profile of the plug separating portion 49M.

In the case where the hydrogen annealing 51 is omitted, a necking phenomenon of the plug separating portion 49 may be caused. By the necking phenomenon, the difference in the threshold value between the upper portion and the lower portion of the plug separating portion 49 can be 4.5 nm.

Under 750 ℃ / 30 bun / H 2 / 1Torr conditions when performing the hydrogen anneal 51, the necking phenomena can be improved. The difference in the threshold value between the upper portion and the lower portion of the plug separating portion 49M can be reduced to the level of 2.4 nm.

When performing the hydrogen anneal 51 is under 800 ℃ / 10 bun / H 2 / 1Torr condition, the necking phenomena can be improved. The difference in the threshold value between the upper portion and the lower portion of the plug separating portion 49M can be reduced to the level of 1.9 nm.

As described above, the hydrogen annealing 51 can be optimized for pressure, temperature, time, and gas flow rate to improve the top portion profile of the plug separation portion 49M.

In another embodiment, the hydrogen annealing may be performed after removing the sacrificial pillars 46R and before exposing the bottom portion of the second contact hole 50.

As shown in FIG. 4I, the polysilicon layer 52A may be applied to the second contact hole 50M. The polysilicon layer 52A may fill the second contact hole 50M. Polysilicon layer 52A may comprise polysilicon doped with a dopant. Because second contact hole 50M has a vertical sidewall profile, polysilicon layer 52A can be filled without shims or voids. Since the polysilicon layer 52A is imaged without shims or voids, it is possible to prevent the penetration of metal atoms into the silicon plug in the subsequent metal material process. Also, since the polysilicon layer 52A is imaged without shims or voids, an additional etch process for removing shims or voids can be omitted. In addition, since the top portion profile of the plug separation portion 49M can be deformed by the in-situ hydrogen annealing 51 in the polysilicon layer 52A deposition equipment, the trim portion for deforming the top portion profile of the plug separation portion 49M The etching process may be omitted.

As shown in FIG. 4J, a silicon plug 52 may be formed in the second contact hole 50M. The silicon plug 52 may partially fill the second contact hole 50M. In order to form the silicon plug 52, the CMP process and the etch-back process of the polysilicon layer 52A may be sequentially performed. The silicon plug 52 may be located between the bit line structures BL. The silicon plug 52 may be lower in height than the top surface of the bit line structure BL. The silicon plug 52 may be electrically connected to the second doped region 40. The silicon plug 52 may be referred to as a " polysilicon plug ". The silicon plug 52 may be doped with phosphorus, arsenic, or boron.

As described above, migration can be induced through the hydrogen annealing 51, thereby adjusting the physical threshold number of the second contact hole 50M. As a result, the gap fill characteristics of the polysilicon layer 52A can be improved.

As shown in FIG. 4K, a metal silicide 53 may be formed. The metal silicide 53 may be formed by a deposition of a silicidable metal layer and a thermal process. The metal silicide 53 may be formed on the silicon plug 52. The metal silicide 53 may be formed by reacting silicon in the upper region of the silicon plug 52 with metal of the silicidable metal layer. After forming the metal silicide 53, the unreacted silicidizable metal layer can be selectively removed. The metal silicide 53 is not limited to cobalt silicide. For example, another metal (for example, titanium, nickel, or the like) capable of reacting with silicon to form a silicide may be used to form a metal silicide.

A metal plug 54 may be formed and a metal plug 54 may be formed in the second contact hole 50M. A metal plug 54 may be formed on the metal silicide 53. The metal plug 54 may comprise a low resistance metal. Further, the metal plug 54 can be formed by laminating a barrier layer and a low-resistance metal. For example, the barrier layer may comprise Ti / TiN, and the low resistance metal may comprise tungsten. The metal plug 54 may be coplanar with the top surface of the bit line structure. The stacked structure of silicon plug 52, metal silicide 53, and metal plug 54 may form a storage node contact plug.

Next, a memory element 55 may be formed on the metal plug 54. The memory element 55 may comprise a capacitor.

The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).

For example, the annealing for inducing the migration can be applied to the STI process for forming the device isolation layer (32 in FIG. 4A). After the trench 32T is formed by etching the substrate 31, the surface migration of the silicon can be caused by exposing it to hydrogen annealing. The annealing may be performed in a low-pressure nitrogen atmosphere. As a result, when the trench 32T is imaged by the element isolation layer 32, it can be imaged without voids.

Also, the hydrogen annealing can be applied after formation of the word line trench (35 in FIG. 4A). As a result, the void can be imaged without being voided during the step of forming the conductive layer for the buried word line 37.

In addition, the hydrogen annealing may be applied before forming the gate insulating film of the peripheral circuit region.

The hydrogen annealing can also be applied after the recess etch for the recess gate.

The hydrogen annealing may also be applied prior to forming the gate insulating film in the HKMG (High-k Metal Gate) process of the logic device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

31: substrate 32: element isolation layer
33: active region 34: hard mask layer
35: word line trench 36: gate insulating layer
37: buried word line 38: sealing layer
39: first doped region 40: second doped region
41: first contact hole 42: bit line contact plug
43: bit line 44: bit line cap layer
45: spacer element 46: sacrificial layer
48: opening 49, 49M: plug separating portion
50, 50M: second contact hole 51: hydrogen annealing
52A: polysilicon layer 52: silicon plug
53: metal silicide 54: metal plug
55: memory element

Claims (20)

Forming a plurality of bit line structures on a substrate;
Forming a sacrificial layer between the bit line structures;
Etching the sacrificial layer to form a plurality of sacrificial pillars and a plurality of openings located between the sacrificial pillars;
Forming a plurality of plug separating portions filling each of the openings;
Removing the sacrificial pillars to form contact holes between the plurality of plug separators;
Performing hydrogen annealing to deform the sidewall profile of the plug separation portion and the contact hole; And
Filling the polysilicon layer in the contact hole in which the hydrogen annealing is performed
≪ / RTI >
The method according to claim 1,
Wherein performing the hydrogen anneal and filling the polysilicon layer comprises:
In-situ or ex situ.
The method according to claim 1,
And the plug separation portion is formed of a nitrogen-containing material.
The method according to claim 1,
Wherein the plug separating portion is formed of silicon nitride.
The method according to claim 1,
Wherein the performing the hydrogen annealing comprises:
And a hydrogen flow rate is set to 1 to 10 l at a low pressure of 3 Torr or less and a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour.
The method according to claim 1,
After filling the polysilicon layer,
Forming a silicon plug that partially recesses the polysilicon layer to partially fill the contact hole;
Forming a metal silicide on the silicon plug;
Forming a metal plug on the metal silicide; And
Forming a memory element on the metal plug
≪ / RTI >
The method according to claim 1,
Prior to forming the bit line structure,
Etching the substrate to form a trench;
Performing hydrogen annealing to deform the sidewall profile of the trench; And
Forming a device isolation layer in the hydrogen annealed trench;
≪ / RTI >
8. The method of claim 7,
After the step of forming the device isolation layer,
Etching the substrate on which the device isolation layer is formed to form a word line trench;
Performing hydrogen annealing to modify the sidewall profile of the wordline trench; And
Forming a buried word line located in the word line trench where the hydrogen annealing is performed and extending in a direction crossing the bit line structure
≪ / RTI >
Forming a nitrogen containing structure including an opening over the substrate;
Performing hydrogen annealing to deform the top portion profile of the opening; And
Filling the conductive layer in the opening in which the hydrogen annealing is performed
≪ / RTI >
10. The method of claim 9,
The step of performing the hydrogen annealing and the step of filling the conductive layer,
In-situ or ex situ.
10. The method of claim 9,
Wherein the conductive layer comprises polysilicon.
10. The method of claim 9,
Wherein the nitrogen-containing structure comprises silicon nitride.
13. The method of claim 12,
Wherein the performing the hydrogen annealing comprises:
And a hydrogen flow rate is set to 1 to 10 l at a low pressure of 3 Torr or less and a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour.
Forming a first insulating layer over the substrate;
Forming a first opening in the first insulating layer;
Forming a sacrificial layer to fill the first opening;
Etching a portion of the sacrificial layer to form a second opening;
Filling a second insulating layer within the second opening;
Removing the sacrificial layer to form a third opening between the second insulating layers;
Performing hydrogen annealing to deform the sidewall profile of the third opening and the second insulating layer; And
Filling the conductive layer in a third opening in which the hydrogen annealing has been performed
≪ / RTI >
15. The method of claim 14,
Wherein the second insulating layer is formed of a material including an element migrated by the hydrogen annealing.
15. The method of claim 14,
Wherein the second insulating layer is formed of a nitrogen-containing material.
15. The method of claim 14,
The step of performing the hydrogen annealing and the step of filling the conductive layer,
In-situ or ex situ.
15. The method of claim 14,
Wherein the conductive layer comprises polysilicon.
15. The method of claim 14,
Wherein the first insulating layer and the second insulating layer each include silicon nitride.
15. The method of claim 14,
Wherein the performing the hydrogen annealing comprises:
And a hydrogen flow rate is set to 1 to 10 l at a low pressure of 3 Torr or less and a temperature of 700 to 850 占 폚 for 30 minutes to 1 hour.

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KR20200073817A (en) * 2018-12-14 2020-06-24 삼성전자주식회사 Semiconductor device including spacer and method of manufacturing the same
CN113540091A (en) * 2021-07-08 2021-10-22 长鑫存储技术有限公司 Semiconductor device structure and preparation method
US11557596B2 (en) 2020-07-17 2023-01-17 Samsung Electronics Co., Ltd. Semiconductor memory device
WO2023035739A1 (en) * 2021-09-10 2023-03-16 International Business Machines Corporation Subtractive patterning of interconnect structures
WO2024027332A1 (en) * 2022-08-02 2024-02-08 长鑫存储技术有限公司 Preparation method for semiconductor structure and semiconductor structure

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CN110534515A (en) * 2018-05-24 2019-12-03 长鑫存储技术有限公司 Reduce the manufacturing method and semiconductor memory of unit contact deficiency
KR20200073817A (en) * 2018-12-14 2020-06-24 삼성전자주식회사 Semiconductor device including spacer and method of manufacturing the same
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