KR20170089389A - Memory allocation apparatus and method for large-scale sparse matrix multiplication on a single machine - Google Patents

Abstract

Disclosed are a device and a method for allocating a memory for single machine based large scale sparse matrix multiplication. The method for allocating a memory comprises the following steps: identifying the whole region of the memory; confirming a size of a first region in the memory requiring for loading a first sparse matrix of two sparse matrices, a size of a second region in the memory requiring for loading a second sparse matrix of two sparse matrices, and a size of a third region in the memory for recording a multiplication result with respect to the two sparse matrices; and allocating the memory region according to a multiplication method of the two sparse matrices based on the whole region of the identified memory and a sum of the size of the first region, the size of the second region, and the size of the third region.

Description

[0001] MEMORY ALLOCATION APPARATUS AND METHOD FOR LARGE-SCALE SPARSE MATRIX MULTIPLICATION ON A SINGLE MACHINE [0002]

The present invention relates to an apparatus and a method for allocating a memory for a large capacity sparse matrix multiplication based on a single machine, and more particularly, to a memory allocation apparatus and method for allocating memory areas necessary for efficiently performing a multiplication of two sparse matrices with a single machine .

Today, there is a need for a method for effectively analyzing the increase in the graph size of the social network and the web. Currently, methods for analyzing large capacity graphs based on distributed processing systems have been proposed. Multiplication of two sparse matrices is a key operation in graph operations.

However, the multiplication of two sparse matrices is more inefficient in a distributed processing system. The reason is as follows. First, the data to be processed for each node of each distributed processing system must be stored. Two sparse matrix multiplications occur when data for two matrices must be redundant for each node. In the case of a large amount of data, a large amount of storage space may be required.

Second, communication between nodes is required to produce the final result. Each node can produce incomplete results. Therefore, a process of merging them is necessary, and communication is generated between the nodes. Also, since the two sparse matrix multiplications can produce very large results, the communication cost can be further increased.

Third, the distribution of the elements of the sparse matrices that represent graphs such as social networks or webs used in graph operations follows a power-law degree distribution. Because of this distribution, it is difficult to evenly distribute the workload to each node, making it difficult to fully utilize the distributed processing system.

Therefore, there is a need for multiplication of two sparse matrices based on a single machine to solve this problem.

The present invention provides an apparatus and method for effectively performing a multiplication of two sparse matrices for each multiplication scheme by allocating different memory areas according to a method of multiplying two sparse matrices.

A method of allocating memory according to an embodiment of the present invention includes: identifying an entire area of a memory; The size of the first area in the memory needed to load the first sparse matrix of the two sparse matrices, the size of the second area in the memory required to load the second sparse matrix, and the result of multiplying the two sparse matrices Confirming a size of a third area in the memory to make the first area; And allocating the area of the memory according to the multiplication method of the two sparse matrices based on the total area of the identified memory and the sum of the size of the identified first area, the size of the second area and the size of the third area Step < / RTI >

The allocating step may allocate a minimum area to the second area and the third area of the memory and allocate the remaining area to the first area when multiplying the two sparse matrices based on the inner product .

In the allocating step, the second area and the third area may be allocated the same size area.

Wherein the allocating step allocates a minimum area to the first area of the memory when the two sparse matrices are multiplied based on the row-row product, allocates the remaining area to the second area and the third area, can do.

In the allocating step, the second area and the third area may be allocated the same size area.

Wherein the allocating step allocates the area corresponding to one half of the memory to the third area of the memory when the two sparse matrices are multiplied based on the outer product and allocates the remaining area to the first area and the second area It is possible to allocate them separately.

In the allocating step, the first area and the second area may be allocated areas of the same size.

Loading a partial matrix of the first sparse matrix into the allocated first region and loading a partial matrix of the second sparse matrix into the allocated second region; Performing a multiplication on the partial matrix of the two loaded sparse matrices; And writing the result of performing the multiplication of the partial matrix of the two sparse matrices to the allocated third region and processing the processed result.

Wherein the loading step comprises: identifying a partial matrix of the first sparse matrix and a partial matrix of the second sparse matrix that remains unloaded; And loading the remaining partial matrixes into the first area and the second area, respectively.

A memory allocation apparatus according to an embodiment of the present invention includes a memory for loading a partial matrix of the two sparse matrices to multiply two sparse matrices; A size of a first area in the memory required to load a first sparse matrix of the two sparse matrices; a size of a second area in the memory required to load a second sparse matrix; Determining a size of a third area in the memory for recording a result of the multiplication for the two sparse matrices, determining a size of the identified area, a size of the second area, And a processor for allocating an area of the memory according to a method of multiplying the two sparse matrices based on a sum of sizes of the two sparse matrices.

When multiplying the two sparse matrices based on inner products, the processor allocates a minimum area to the second area and the third area of the memory, and allocates the remaining area to the first area.

When multiplying the two sparse matrices based on a row-row product, the processor allocates a minimum area to the first area of the memory, allocates the remaining area to the second area and the third area, have.

The processor allocates a region corresponding to one-half of the memory to a third region of the memory, and allocates the remaining region to the first region and the second region when multiplying the two sparse matrices based on the outer product. You can allocate them separately.

The processor loads the partial matrix of the first sparse matrix into the allocated first region, loads the partial matrix of the second sparse matrix into the allocated second region, and updates the partial matrix of the loaded two sparse matrix A result of performing a multiplication of a partial matrix of the two sparse matrices after performing multiplication may be recorded and processed in the allocated third region.

When the allocated third area is full, the processor stores the result recorded in the third area in the storage device, and when the result recorded in the third area is generated by a row-row product or an outer prodect , And integrate the results stored in the storage device.

According to an embodiment of the present invention, the two sparse matrix multiplication can be effectively performed for each multiplication scheme by allocating different memory areas according to the multiplication method of the two sparse matrices.

1 is a block diagram illustrating a memory allocation apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating three different two-sparse matrix multiplication schemes according to an embodiment of the present invention.
3 is a diagram illustrating an example of a memory allocation method according to three different two-sparse matrix multiplication schemes according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating a method of performing a multiplication operation on two sparse matrices by a memory allocation apparatus according to an embodiment of the present invention. Referring to FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a memory allocation apparatus according to an embodiment of the present invention.

The memory allocation apparatus 100 may include a processor 110, a memory 120, and a storage device 130. The processor 110 effectively performs a multiplication of two sparse matrices for each multiplication scheme by allocating different memory areas in the memory 120 according to a multiplication method of two sparse matrices to perform a multiplication of two sparse matrices . At this time, the memory allocation apparatus 100 may be composed of a single machine, and the multiplication method of the two sparse matrices may include at least one of an inner product, a row-row product, and an outer product.

Specifically, the memory allocation apparatus 100 of the present invention assumes a situation where it is impossible for two sparse matrices to be loaded into the memory 120 at one time. In this case, the memory allocation apparatus 100 can first decompose the two sparse matrices into submatrons considering the size of the entire area of the memory 120. [

Thereafter, the memory allocation apparatus 100 divides the area for loading the partial matrixes of the two sparse matrices into the memory 120 and the area for recording the result generated by multiplying the partial matrixes of the two sparse matrices by a method of multiplying two sparse matrices You can assign them separately.

The memory allocation apparatus 100 may load the submatrix of the two sparse matrices into an area allocated to load each of the partial matrices of the two sparse matrices and perform multiplication according to the multiplication method of each of the two sparse matrices. Thereafter, the memory allocation apparatus 100 writes the result of the multiplication in an area allocated for recording a result generated by multiplying a partial matrix of two sparse matrices, and when the area is full, 130).

FIG. 2 is a diagram illustrating three different two-sparse matrix multiplication schemes according to an embodiment of the present invention.

The multiplication of two sparse matrices is an operation of multiplying two sparse matrices (first sparse matrix and second sparse matrix) as shown in Equation 1 below to generate a new third result matrix. This operation is repeatedly multiplied and added between elements in the matrix. (1) inner product, (2) row-row product, and (3) outer product, depending on the order of performing multiplication and addition between elements and the order of accessing elements in two sparse matrices .

[Formula 1]

제2 희소행렬The third result matrix = the first sparse matrix

The second sparse matrix

More specifically, a method of multiplying two sparse matrices by using (1) an inner product among the methods of multiplying two sparse matrices is as follows.

[Formula 2]

Here, C [i] [k] represents a third result matrix, and A [i] [j] and B [j] [k] may represent a first sparse matrix and a second sparse matrix, respectively. Each element of the row vector A [i] [] included in the first sparse matrix A is divided into one element of the column vector B [k] included in the second sparse matrix B corresponding to each element, Can be multiplied. At this time, the elements of the row vector (A [i] []) included in the first sparse matrix A and the elements of the column vectors B [] [k] included in the second sparse matrix B corresponding to the respective elements (C [i] [k]) included in the third result matrix C can be generated by summing the results generated by the multiplication between the first and second result matrices.

In order to enable the multiplication between the two elements, the column index of the element A [i] [j] in the first sparse matrix A and the element B [j] [k] Must be the same. As a result, one row vector included in the first sparse matrix A and one column vector included in the sparse matrix B are calculated to generate one row vector included in the third result matrix C , It is possible to generate the final third result matrix C by repeating it for n row vectors included in the first sparse matrix A. [

In order to perform multiplication of a large-capacity sparse matrix based on an inner product, a first sparse matrix A is stored in a memory so as to be sequentially accessed to a row vector, and a second sparse matrix B is stored in a memory Should be stored. This is because the first sparse matrix A requires access on a row vector basis and the sparse matrix B requires access on a column vector basis.

Next, a method of multiplying two sparse matrices by using a row-row product in the method of multiplying two sparse matrices is expressed by Equation 3 below.

[Formula 3]

Here, C [i] [] represents a third result matrix, and A [i] [j] and B [j] [] may represent a first sparse matrix and a second sparse matrix, respectively. A plurality of row vectors B [k], B [] [l], ... included in the second sparse matrix B and one row vector A [i] To generate one row vector C [i] [] included in the third result matrix C, as shown in FIG. At this time, each element (A [i] [j]) of the row vector included in the first sparse matrix A corresponds to one element included in the second sparse matrix B corresponding to each of the elements A [i] [j] (C [i] []) included in the third result matrix C, which is calculated and incomplete, with all the elements existing in the row vector B [j] [] of the row vector C [i]

As a result, by combining a plurality of row vectors included in the incomplete third result matrix C generated by the operation of one row vector included in the first sparse matrix A and the plurality of row vectors included in the second sparse matrix B, One row vector included in the third result matrix C can be generated. It can be repeated for n row vectors included in the first sparse matrix A to generate the final third result matrix C. [

In order to perform a multiplication of a large-capacity sparse matrix based on a row-row product, both the first sparse matrix A and the second sparse matrix B must be stored in the memory so as to sequentially access the row vectors. This is because both the first sparse matrix A and the second sparse matrix B require access on a row vector basis.

Finally, among the multiplication methods of two sparse matrices, (3) a method of multiplying two sparse matrices by using an outer product is as follows.

[Formula 4]

Here, C [] [] represents a third result matrix, and A [] [j] and B [j] [] may represent a first sparse matrix and a second sparse matrix, respectively. A single column vector A [j] included in the first sparse matrix A is multiplied by one row vector B [j] [] included in the second sparse matrix B to generate an incomplete total third result matrix C Lt; / RTI > At this time, each element (A [i] [j]) of one column vector included in the first sparse matrix A is all contained in the row vector B [j] [] included in the second sparse matrix B (C [i] []), which is incompletely included in the computed and incomplete total third result matrix C, can be generated.

As a result, an incomplete entire third result generated by an operation of all the elements existing in one column vector included in the first sparse matrix A and one row vector B [j] [] included in the second sparse matrix B A plurality of incomplete row vectors included in the matrix C can be generated. In this manner, all column vectors included in the first sparse matrix A and all the row vectors included in the second sparse matrix B are computed according to the same index pair, and a plurality of incomplete row vectors included in the incomplete overall result matrix C And generate the final third result matrix C by integrating the generated incomplete plurality of row vectors.

3 is a diagram illustrating an example of a memory allocation method according to three different two-sparse matrix multiplication schemes according to an embodiment of the present invention.

The multiplication of two sparse matrices according to the size of the area for loading the partial matrixes of the two sparse matrices allocated for the multiplication of the two sparse matrices and the size of the area for recording the result generated by multiplying the partial matrixes of the two sparse matrices Since the performance is changed, it is necessary to grasp the characteristics of the method of multiplying two sparse matrices and a memory allocation method corresponding thereto.

(1) Multiplication of large capacity sparse matrices based on Inner product works similar to joining two relations using block nested loop join which is well known in database field. First, the memory allocation apparatus 100 can decompose the first sparse matrix A into sub-matrix units composed of a plurality of row vectors and load them into the memory 120. [ The memory allocation apparatus 100 may then perform a multiplication operation on the elements that can be multiplied while decomposing the entire second sparse matrix B into sub-matrix units and loading them into the memory 120. [ This process is also repeated until all the partial matrices of the first sparse matrix A are processed, so that the entirety of the second sparse matrix B is loaded by the number of partial matrices of the first sparse matrix A. [ The memory allocation apparatus 100 may store the computed result in the memory 120 and transfer the result to the storage device 130 when the memory area for the result is full.

(1) loading a partial matrix of two sparse matrices into a memory according to the size of a memory area allocated to the first sparse matrix A, the second sparse matrix B, and the third result matrix C; (2) The performance of the process of storing the third result matrix C generated as a result of the multiplication on the partial matrix of the storage device 130 is different. In order to optimize the performance of the two processes, the memory allocation apparatus 100 applies a memory allocation method that minimizes IO cost in a block nested loop join.

That is, the memory allocation apparatus 100 allocates the memory 120 necessary for recording the second area in the memory 120 necessary for loading the second sparse matrix and the third result matrix C resulting from the multiplication for the two sparse matrices, The minimum area can be allocated to the third area within the area. The memory allocation apparatus 100 may allocate all of the remaining areas allocated to the second area and the third area for the first area in the memory 120 required for loading the first sparse matrix

Accordingly, the memory allocation apparatus 100 can reduce the number of times of loading the entire second sparse matrix by reducing the number of times the first sparse matrix is divided and loaded. At this time, since the amount of the third result matrix C generated as a result of multiplying by the two sparse matrices is constant irrespective of the size of the memory area, the amount to be recorded does not change even if the size of the area to be allocated is minimized. Accordingly, when the inner product is performed and the two sparse matrices are multiplied, the memory allocation apparatus 100 can hold the second resultant matrix C that is the result of the multiplication of the two sparse matrices and the second region in which the second sparse matrix B can be loaded It is possible to minimize the IO cost by minimizing the third area and allocating the remaining memory areas to the first area where the first sparse matrix A can be loaded.

(2) Multiplication of large-capacity sparse matrices based on row-row products also works similar to joining two relations using block-nested loop joins as well as inner products-based multiplication of large scalar matrices. When performing a multiplication of a large sparse matrix using the row-row product, the way of loading the two sparse matrices is the same as the inner product. That is, two sparse matrices can be divided into partial matrices, loaded into memory, and multiplication operations can be performed. However, it is difficult to optimize the performance by applying only the method of block nested loop join because it obtains an intermediate result which is not perfect by multiplying the partial matrix of two sparse matrices differently from inner product. Therefore, the present invention proposes a method for optimizing the performance by analyzing the characteristics of the row-row product.

(1) loading a partial matrix of two sparse matrices into the memory 120 according to the size of a memory area allocated to the first sparse matrix A, the second sparse matrix B, and the third result matrix C, (2) 120), (3) storing the sorted intermediate results in the storage device 130, (4) merging the intermediate results in the storage device 130 into the final result, Performance is different. In order to improve the performance of the process of loading the partial matrix of two sparse matrices into the memory, the same method as in the inner product can be used. However, since this method does not minimize the total execution time, memory must be allocated considering the performance of the remaining processes.

The performance of the process of sorting and merging intermediate results on memory 120 is influenced by the size of the third region on memory 120 that allocates to third result matrix C. [ At this time, as the size of the third area allocated to the third result matrix C is larger, the number of elements to be aligned at one time increases, which increases the cost of sorting.

There are two methods for improving the performance of the process of writing the sorted intermediate results to the storage device 130. [ First, the size of the third area allocated to the third result matrix C is increased so that the storage area 130 is sequentially accessed. Second, the number of intermediate results merged on the memory 120 is increased to reduce the amount of storage in the storage device 130.

If the size of the third area allocated to the third result matrix C is large, there are many intermediate results that can be stored before being stored in the storage device 130, and there is a high probability that there are elements that can be merged with each other. When the size of the second area allocated to the second sparse matrix B is increased, the number of rows included in the first sparse matrix A and the number of rows included in the second sparse matrix B, which can be calculated in succession, The intermediate results that can be included are continuously included in the third area. Therefore, the larger the size of the second area allocated to the second sparse matrix B and the third area allocated to the third result matrix C, the greater the number of intermediate results to be merged on the memory 120. [

The performance of the process of merging the intermediate results in the storage device 130 into the final result is improved as the number of elements to be merged is reduced and the number of files is decreased. That is, it is the same as the method of improving the performance of the process of storing the sorted intermediate results in the storage device 130.

At this time, the sizes of the memory areas to be allocated to the first sparse matrix A, the second sparse matrix B, and the third result matrix C are influenced by the performance of different multiplication operation processes.

The size of the first area allocated to the first sparse matrix A affects only the performance of the process of loading the partial matrix of the first sparse matrix and the partial matrix of the second sparse matrix into the memory 120. [ It is inefficient to improve the performance of this process by allocating a large memory area size to the first sparse matrix A as in the inner product. Accordingly, the memory allocation apparatus 100 can map the second sparse matrix B to the outer relation in the nested loop join, and allocate a minimum memory area size to the first sparse matrix A.

In this case, when allocating most of the size of the allocated and remaining memory area to the second area for loading the partial matrix of the second sparse matrix B, the size of the third area allocated to the third result matrix C is small, The number of results is reduced. Therefore, in order to increase the number of intermediate results to be merged, a second area for allocating the partial matrix of the first sparse matrix A to the first area for allocating the remaining memory area to the second sparse matrix B, And a third area allocated to the matrix C is required.

The intermediate results when one row vector included in the first sparse matrix A is multiplied by a plurality of row vectors included in the second sparse matrix B are all the results that can be merged into one row vector included in the third result matrix C admit. That is, since an intermediate result for one row vector included in the third result matrix C is obtained by multiplying one element included in the first sparse matrix A and one row vector included in the second sparse matrix B, The number of the row vectors included in the third result matrix C obtained by multiplying one row vector included in the matrix A and k row vectors included in the second sparse matrix B is at most k. Therefore, the size of the third area allocated to the third result matrix C should be equal to or larger than the size of the second area allocated to the second sparse matrix B, in order to secure a space for storing all the intermediate results that can be merged.

As the size of the second area allocated to the second sparse matrix B increases, the performance of the process of loading the partial matrix of the first sparse matrix and the partial matrix of the second sparse matrix into the memory 120 is improved, Since the performance of the process of sorting the intermediate results on the memory 120 is improved as the size of the third area allocated to the matrix C is smaller, the memory allocation apparatus 100 can not allocate the partial matrix of the first sparse matrix A The size of the remaining memory area allocated to the first area may be equally divided into a second area allocated to the second sparse matrix B and a third area allocated to the third result matrix C,

(3) The multiplication method of large-capacity sparse matrices based on the outer product works similar to the sort merge join which is well known in the database field. The memory allocation apparatus 100 may compare the column vectors included in the first sparse matrix A and the indexes of the row vectors included in the second sparse matrix B to perform a multiplication operation in the same case. Since the indexes of the column vectors included in the first sparse matrix A and the indexes of the row vectors included in the second sparse matrix B do not overlap with each other, they operate similarly to the sort merge join without overlapping join attributes.

At this time, the memory allocation apparatus 100 loads the first sparse matrix A into the first area on the memory 120 in units of partial matrix consisting of a plurality of column vectors, and the second sparse matrix B is composed of a plurality of row vectors And may be loaded into the second area on the memory 120 in units of submatrices. The memory allocation apparatus 100 performs a multiplication operation using the partial matrix of the first sparse matrix A and the partial matrixes of the second sparse matrix B loaded on the memory 120, 3 result matrix C in a third area on the memory 120 and store the third result matrix C in the storage device 130 when the memory space corresponding to the third area is full.

(1) loading a partial matrix of two sparse matrices into a memory according to the sizes of memory areas allocated to the first sparse matrix A and the second sparse matrix B and the result matrix C, as in the case of the row-row product, (2) (3) storing the sorted intermediate results in the storage device 130; (4) merging the intermediate results in the storage device 130 into the final result; The performance of the process changes.

The number of times of reading the first sparse matrix A and the second sparse matrix B without regard to the size of the first region allocated to the first sparse matrix A and the second region allocated to the second sparse matrix B as the characteristics of the sort merge join is However, the greater the size of the first area and the second area on the memory 120 to be allocated, the more sequential access is made to the storage device 130.

The performance of the process of storing the sorted intermediate results in the storage device 130 is improved as the size of the third area allocated to the third result matrix C is larger. This is because not only the sequential access to the storage device 130 but also the amount of writing intermediate results can be reduced. When the incomplete third result matrix C generated as a result of the multiplication of one row vector included in the first sparse matrix A and one row vector included in the second sparse matrix B is written in the third region, If it is not full, then it can contain the result of the multiplication operation on the vector. At this time, the intermediate results for the elements belonging to the same position in the generated incomplete third result matrix C are merged in a third region on the memory 120, merged and merged into one value. Also, since many elements are written to a single file, the number of files that store intermediate results is reduced. Thus enhancing the performance of external alignment to merge intermediate results in storage device 130.

For example, the m-ary merger sort shows better performance when the number of all elements to be sorted is equal, and the number of internally sorted files is less. On the other hand, the performance of the process of aligning the intermediate result in the third area on the memory 120 becomes worse as the size of the third area allocated to the third result matrix C is larger. If many intermediate results are merged in the third region on the memory 120, the amount of intermediate results in the storage device 130 is reduced and the cost of sorting and merging is reduced.

However, since the positions of the elements in the sparse matrix are irregular, it is difficult to predict the amount of the intermediate result to be merged in the third area on the memory 120, so that the memory allocation method capable of achieving the optimum performance through experiments has been confirmed. As a result, the memory allocation apparatus 100 allocates the third area corresponding to half the size of the entire memory area 120 to the third result matrix C generated as a result of the multiplication of the two sparse matrices, allocates the third area to the remaining memory The size of the area may be equally divided into a first area allocated to the first sparse matrix A and a second area allocated to the second sparse matrix B. [

FIG. 4 is a flowchart illustrating a method of performing a multiplication operation on two sparse matrices by a memory allocation apparatus according to an embodiment of the present invention. Referring to FIG.

In step 410, the memory allocation apparatus 100 may identify the size of the entire area of the memory 120. [

In step 420, the memory allocation apparatus 100 determines the size of the first area on the memory 120 needed to load the first sparse matrix, the size of the second area on the memory 120 required to load the second sparse matrix Size and size of the third region on the memory 120 for recording the third result matrix generated as a result of the multiplication for the first sparse matrix and the second sparse matrix.

In step 430, the memory allocation apparatus 100 determines whether or not the first rare < RTI ID = 0.0 > (n) < The area of the memory 120 may be allocated according to the multiplication method of the matrix and the second sparse matrix.

The present invention assumes a situation where it is impossible for the first sparse matrix and the second sparse matrix to be loaded on the memory 120 at one time. Therefore, when the size of the entire area of the identified memory 120 is smaller than the sum of the size of the identified first area, the size of the second area, and the size of the third area, the memory allocation apparatus 100 allocates the first sparse matrix The area of the memory 120 can be allocated according to the multiplication method of the second sparse matrix.

Specifically, when performing the multiplication operation on the inner product-based large capacity sparse matrix, the memory allocation apparatus 100 calculates the multiplication result for the second region and the two sparse matrices in the memory 120 necessary for loading the second sparse matrix A minimum area is allocated for a third area in the memory 120 required to record the generated third result matrix, a second area is allocated for a first area in the memory 120 required to load the first sparse matrix, All the remaining areas allocated to the third area can be allocated

When the memory allocation apparatus 100 performs a multiplication operation on a large-capacity sparse matrix based on a row-row product, the memory allocation apparatus 100 allocates a minimum area for the first area in the memory 120 required for loading the first sparse matrix A second area allocated to the second sparse matrix and a third area assigned to the third result matrix can be allocated to the first area and the remaining area of the memory 120 equally.

In addition, when the memory allocation apparatus 100 performs a multiplication operation on an outer product-based large-capacity sparse matrix, the memory allocation apparatus 100 allocates the first result matrix to the entire memory 120 for the third result matrix generated as a result of the multiplication of the first sparse matrix and the second sparse matrix. A third area corresponding to a half size of the area is allocated, and a first area allocated to the first sparse matrix A and a second sparse matrix B are allocated to the third area, and the remaining memory areas are equally divided .

In step 440, the memory allocation apparatus 100 may load the partial matrix of the first sparse matrix into the allocated first region and load the partial matrix of the second sparse matrix into the allocated second region.

In step 450, the memory allocation apparatus 100 may perform a multiplication operation on the partial matrices of the first sparse matrix and the second sparse matrix that are loaded. Then, the memory allocation apparatus 100 writes the third result matrix generated as a result of the multiplication operation into the third area on the memory 120. When the third area is full, the third result matrix May be stored in the storage device 130.

Unlike the multiplication operation for the partial matrixes of the first sparse matrix and the second sparse matrix using the inner product, the first sparse matrix and the partial matrix of the second sparse matrix are calculated using the row-row product and the outer product, , It is possible to obtain an incomplete intermediate result. Accordingly, when performing the multiplication operation on the partial matrixes of the first sparse matrix and the second sparse matrix using the row-row product and the outer product, the memory allocation apparatus 100 allocates the third result matrix stored in the storage device 130 To produce a final third result matrix.

In step 460, the memory allocation apparatus 100 may identify the presence or absence of a partial matrix of the first sparse matrix and the second sparse matrix that remains unloaded. If there is a partial matrix remaining unloaded among the partial matrixes of the first sparse matrix and the second sparse matrix, the memory allocation apparatus 100 repeatedly performs steps 440 through 450 to calculate the first sparse matrix and So that a multiplication operation can be performed on all partial matrices of the second sparse matrix.

Alternatively, if there is no partial matrix remaining unloaded among the partial matrixes of the first sparse matrix and the second sparse matrix, the memory allocation apparatus 100 may terminate the multiplication operation for the two sparse matrices.

The methods according to embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and configured for the present invention or may be available to those skilled in the art of computer software.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

100: memory allocation device
110: Processor
120: Memory
130: Storage device

Claims (17)

Identifying an entire area of memory;
The size of the first area in the memory needed to load the first sparse matrix, the size of the second area in the memory needed to load the second sparse matrix, and the multiplication result for the first sparse matrix and the second sparse matrix Confirming a size of a third area in the memory for writing the generated third result matrix; And
And a second sparse matrix multiplication method based on a sum of the entire area of the identified memory and the size of the identified first area, the size of the second area, and the size of the third area, Quot;
/ RTI > The method according to claim 1,
Wherein the assigning comprises:
When multiplying the first sparse matrix and the second sparse matrix based on inner product,
Allocating a minimum area to a second area and a third area of the memory, and allocating a remaining area to the first area. 3. The method of claim 2,
Wherein the second area and the third area are allocated the same size area. The method according to claim 1,
Wherein the assigning comprises:
When the first sparse matrix and the second sparse matrix are multiplied based on the row-row product,
Allocating a minimum area to the first area of the memory, and allocating the remaining area to the second area and the third area. 5. The method of claim 4,
Wherein the second area and the third area are allocated the same size area. The method according to claim 1,
Wherein the assigning comprises:
When multiplying the first sparse matrix and the second sparse matrix based on the outer product,
Allocating an area corresponding to half the size of the memory to a third area of the memory, and allocating the allocated area to the first area and the second area. The method according to claim 6,
Wherein the first area and the second area are allocated the same size area. The method according to claim 1,
Loading a partial matrix of the first sparse matrix into the allocated first region and loading a partial matrix of the second sparse matrix into the allocated second region;
Performing a multiplication of the partial matrix of the loaded first sparse matrix and the partial matrix of the second sparse matrix; And
And a third result matrix generated by performing a multiplication of the partial matrix of the first sparse matrix and the partial matrix of the second sparse matrix in the allocated third region and processing
≪ / RTI > 9. The method of claim 8,
Wherein the loading step comprises:
Identifying a partial matrix of the first sparse matrix and a partial matrix of the second sparse matrix that remains unloaded; And
Loading the remaining partial matrixes into a first area and a second area, respectively
≪ / RTI > A memory for loading the partial matrix of the first sparse matrix and the partial matrix of the second sparse matrix to multiply the first sparse matrix and the second sparse matrix;
Identifying a total area of the memory, determining a size of a first area in the memory necessary to load the first sparse matrix, a size of a second area in the memory required to load a second sparse matrix, The size of the first region, the size of the second region, and the size of the first region, and the size of the second region in the memory, A processor for allocating an area of the memory according to a multiplication scheme of the first sparse matrix and the second sparse matrix based on a sum of sizes of three areas,
And a memory. 11. The method of claim 10,
The processor comprising:
When multiplying the first sparse matrix and the second sparse matrix based on inner product,
Allocating a minimum area to the second area and the third area of the memory, and allocating the remaining area to the first area. 11. The method of claim 10,
The processor comprising:
When the first sparse matrix and the second sparse matrix are multiplied based on the row-row product,
Allocating a minimum area to the first area of the memory, and allocating the allocated area to the second area and the third area. 11. The method of claim 10,
The processor comprising:
When multiplying the first sparse matrix and the second sparse matrix based on the outer product,
Allocating an area corresponding to half the size of the memory to a third area of the memory, and allocating the allocated area to the first area and the second area. 11. The method of claim 10,
The processor comprising:
A partial matrix of the first sparse matrix is loaded in the allocated first region, a partial matrix of the second sparse matrix is loaded in the allocated second region, and a partial matrix of the loaded first sparse matrix and a partial matrix of the second rare matrix And a third result matrix generated by performing a multiplication with respect to the partial matrix of the matrix is written to the allocated third region and processed. 15. The method of claim 14,
The processor comprising:
Storing the result recorded in the third area in a storage device when the allocated third area is full,
And integrates the result stored in the storage device when the result recorded in the third area is generated by a row-row product or an outer product. Identifying an entire area of memory;
The size of the first area in the memory needed to load the first sparse matrix of the two sparse matrices, the size of the second area in the memory required to load the second sparse matrix, and the result of multiplying the two sparse matrices Confirming a size of a third area in the memory to make the first area;
Allocating a region of the memory according to a multiplication scheme of the two sparse matrices based on the total area of the identified memory, the size of the identified first area, the size of the second area, and the size of the third area ;
Loading a partial matrix of the first sparse matrix into the allocated first region and loading a partial matrix of the second sparse matrix into the allocated second region;
Performing a multiplication on the partial matrix of the two loaded sparse matrices; And
Recording a result of performing a multiplication of a partial matrix of the two sparse matrices in the allocated third area;
Merging the results recorded in the allocated third area;
Storing the result recorded in the third area in a storage device when the allocated third area is full; And
Integrating the results stored in the storage device
/ RTI > 17. The method of claim 16,
Wherein the assigning comprises:
When the two sparse matrices are multiplied based on inner product,
Allocating a minimum area to the second area and the third area of the memory, allocating the remaining area to the first area,
When the two sparse matrices are multiplied based on the row-row product,
Allocating a minimum area to the first area of the memory, allocating the remaining area to the second area and the third area,
When the two sparse matrices are multiplied based on the outer product,
Allocating an area corresponding to one half of the memory to a third area of the memory, and allocating the remaining area to the first area and the second area.

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