KR20170081118A - Storage device including nonvolatile memory device and controller, operating method of storage device, and access method for accessing storage device - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a method of operating the storage device including a controller for controlling the nonvolatile memory device. The method of operation of the present invention comprises the steps of transmitting to the host device map data mapping physical addresses of the nonvolatile memory device and logical addresses of the host device, receiving a read request from the host device, Reading the data based on the physical address, and if the read request does not include the physical address, converting the logical address of the read request to the second physical address and reading the data based on the second physical address .

Description

Technical Field [0001] The present invention relates to a storage device including a nonvolatile memory device and a controller, an operation method of the storage device, and an access method for accessing the storage device. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to semiconductor memory, and more particularly, to a storage device including a nonvolatile memory device and a controller, a method of operating the storage device, and an access method for accessing the storage device.

A storage device is a device that stores data under the control of a host device such as a computer, a smart phone, a smart pad, or the like. The storage device stores data in a semiconductor memory, in particular, a nonvolatile memory such as a hard disk drive (HDD), a device storing data on a magnetic disk, a solid state drive (SSD) Lt; / RTI >

The non-volatile memory may be a ROM, a PROM, an EPROM, an EEPROM, a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM) RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like.

In order to reduce the manufacturing cost of the storage device, attempts have been made to remove a large-capacity buffer memory such as a dynamic random access memory (DRAM) from the storage device. Typically, the buffer memory of the storage device is used to store the metadata necessary to manage the non-volatile memory device of the storage device. For example, the metadata may include map data that includes mapping information between the physical addresses of the non-volatile memory device and the logical addresses used by the host device.

When a large-capacity buffer memory such as DRAM is removed from the storage device, the metadata must be managed using a low-capacity, high-speed buffer memory provided inside the controller of the storage apparatus. However, the capacity of the buffer memory inside the controller is smaller than the capacity of the meta data, more specifically, the map data. Accordingly, when the map data necessary for performing a write request or a read request from the host device is not loaded in the buffer memory inside the controller, an operation of loading necessary map data from the nonvolatile memory device into the buffer memory inside the controller . This increases the time that the storage device responds to a write request or a read request of the host device and reduces the operation speed of the storage device and the computing device employing the storage device.

Therefore, researches have been made on devices and methods that prevent a decrease in the response speed or the operation speed of a storage device even if a large-capacity buffer memory such as a DRAM is removed from the storage device.

It is an object of the present invention to provide a storage device having an improved operation speed, a method of operating the storage device, and an access method for accessing the storage device.

A method of operating a storage device including a controller configured to control a non-volatile memory device and a non-volatile memory device according to embodiments of the present invention is characterized in that the storage device stores the physical addresses of the non-volatile memory device and the logical addresses Reading data from the non-volatile memory device based on a physical address if the read request includes a physical address, and < RTI ID = 0.0 > Converting the logical address of the read request to a second physical address if the read request does not include the physical address, and reading data from the non-volatile memory device based on the second physical address.

A storage device according to embodiments of the present invention includes a non-volatile memory device and a controller configured to control the non-volatile memory device. The controller is configured to transmit map data to the host device to map the physical addresses of the non-volatile memory device and the logical addresses of the host device. The controller reads data from the non-volatile memory device based on the physical address if the read request received from the host device includes a physical address associated with the map data, and if the read request received from the host device does not contain a physical address, And to read data from the non-volatile memory device based on the logical address.

A nonvolatile memory device according to embodiments of the present invention and an access method for accessing a storage device including the nonvolatile memory device are configured to read map data that maps physical addresses and logical addresses of a nonvolatile memory device from a storage device If the logical address of the read object is associated with the map data, detecting the logical address and the mapped physical address from the map data and sending a read request containing the physical address to the storage device, And if not associated with the data, sending a read request containing the logical address to the storage device.

According to embodiments of the present invention, the map data of the storage device is transmitted to the host device. The host device may send a read request containing the physical address to the storage device based on the map data. The operation speed of the computing device including the storage device and the storage device is improved because the address conversion is performed for the read request including the physical address or the operation for reading the map data from the nonvolatile memory device is not accompanied.

Further, the management authority for the map data transmitted to the host device is owned by the host device, not by the storage device. Therefore, since the management authority for the memory of the host device does not need to be transferred to the storage device, embodiments of the present invention can be implemented using existing interfaces without requiring the interface between the host device and the storage device to be changed. Thus, the cost of implementing the embodiments of the present invention is reduced.

1 is a block diagram illustrating a computing device in accordance with an embodiment of the present invention.
2 is a flowchart illustrating an operation method of a storage apparatus according to embodiments of the present invention.
3 is a flow chart showing how the storage device transmits some or all of the map data to the host device at power-on.
4 shows an example of a map data request in which the host apparatus requests map data to the storage apparatus 1300. FIG.
5 shows an example of a command descriptor block of a map data request in which a host device requests map data to a storage device.
6 shows another example of a command descriptor block of a map data request in which the host device requests map data to the storage device.
7 shows an example of a response in which the storage device transmits map data to the host device in response to the request of Fig. 5 or Fig.
8 shows an example in which map data, storage map cache data, and host map cache data are respectively managed in the RAM of the nonvolatile memory device, the controller, and the host device.
9 is a flowchart showing how the host apparatus requests map data to the storage apparatus in the first mode.
10 is a flow chart showing how a host device requests map data to a storage device in a second mode.
11 is a flowchart showing a method in which a host device transfers a write request to a storage device to perform writing.
12 is a flowchart showing a method in which a host device transfers a read request to a storage device to perform writing.
13 shows an example of a command descriptor block of a read request in which the host device requests reading from the storage device).
15 shows an example of a command descriptor block in which a host device transmits a plurality of physical addresses and signatures via a separate command UPIU.
Figure 16 is a flow chart showing how the controller manages signatures.
17 is a flowchart showing an example in which encryption is performed when the controller transmits map data to the host device.
18 is a flowchart showing an example in which the storage device performs defragmentation.
19 is a flowchart showing an example in which a computing device supports defragmentation of a storage device.
20 is a flow chart showing how a host device accesses a storage device;
21 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

1 is a block diagram illustrating a computing device 1000 in accordance with an embodiment of the present invention. Referring to Figure 1, a computing device 1000 includes a processor 1100, a memory 1200, a storage device 1300, a modem 1400, and a user interface 1500.

The processor 1100 may control all operations of the computing device 1000 and may perform logical operations. The processor 1100 may be a hardware-based data processing device that includes circuitry that is physically configured to execute code or operations represented by instructions contained in the program. For example, the processor 1100 may be configured as a system-on-chip (SoC). The processor 1100 may be a general purpose processor, a special purpose processor, or an application processor.

The RAM 1200 may communicate with the processor 1100. The RAM 1200 may be the processor 1100 or the main memory of the computing device 1000. The processor 1100 may temporarily store the code or data in the RAM 1200. [ The processor 1100 can execute the code using the RAM 1200 and process the data. The processor 1100 may use RAM 1200 to execute various software, such as an operating system and an application. The processor 1100 can use the RAM 1200 to control all operations of the computing device 1000. The RAM 1200 may be a volatile memory such as SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM) or the like, or a random access memory such as a PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM Ferroelectric RAM), and the like.

The storage device 1300 may communicate with the processor 1100. The storage device 1300 can store data that needs to be preserved in the long term. That is, the processor 1100 may store data to be stored in the storage device 1300 in the long term. The storage device 1300 may store a boot image for driving the computing device 1000. The storage device 1300 may store source codes of various software, such as an operating system and an application. The storage device 1300 may store data processed by various software, such as an operating system and an application.

Illustratively, the processor 1100 can load the source codes stored in the storage device 1300 into the RAM 1200 and execute the loaded codes in the RAM 1200 to drive various software, such as an operating system, an application have. The processor 1100 may load data stored in the storage device 1300 into the RAM 1200 and process the data loaded into the RAM 1200. [ The processor 1100 may store in the storage device 1300 data to be stored in the RAM 1200 for a long period of time.

The storage device 1300 may include non-volatile memory devices such as flash memory, Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM)

The modem 1400 may communicate with an external device under the control of the processor 1100. [ For example, the modem 1400 can perform wired or wireless communication with an external device. The modem 140 may be any one of long term evolution (LTE), WiMax, GSM, CDMA, Bluetooth, Near Field Communication (NFC), WiFi, (Serial Attachment), a High Speed Interchip (HSIC), a Small Computer System Interface (SCSI), a Firewire, and the like, as well as various wireless communication schemes such as RFID (Radio Frequency Identification) , PCI (PCI Express), Nonvolatile Memory Express (NVMe), Universal Flash Storage (UFS), SD (Secure Digital), SDIO, Universal Asynchronous Receiver Transmitter (UART), Serial Peripheral Interface (SPI) , HS-SPI (High Speed SPI), RS232, I2C (Integrated Circuit), HS-I2C, I2S, Integrated Digital Interchip Sound, Sony / Philips Digital Interface (MIC) based on at least one of various wired communication methods such as eMMC (embedded MMC) Can be performed.

The user interface 1500 may communicate with the user under the control of the processor 1100. For example, the user interface 1500 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, The user interface 1500 may include user output interfaces such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an AMOLED (Active Matrix OLED) display, an LED, a speaker,

The storage device 1300 includes a non-volatile memory device 110 and a controller 120. The non-volatile memory device 110 may provide a main storage to the computing device 1300. The controller 120 may perform write, read, and erase operations on the non-volatile memory device 110 at the request of the host device. The controller 120 can perform various background operations necessary to manage the nonvolatile memory device 110 regardless of the control of the host device. The controller 120 can manage various kinds of metadata necessary for managing the nonvolatile memory device 110. Metadata is stored in the non-volatile memory device 110 and can be read from the non-volatile memory device 110 when the controller 120 is needed.

Illustratively, the metadata managed by the controller 120 may include map data MD. The map data MD may include mapping information between the physical addresses of the storage space of the non-volatile memory device 110 and the logical addresses assigned to the storage device 1300 by the host device. The map data (MD) may be stored in the nonvolatile memory device (110). The controller 120 may load a part of the map data MD necessary for performing a request or background operation from the host apparatus into the internal buffer memory as the storage map cache data MCD_S. For example, the internal buffer memory may be static random access memory (SRAM). When the storage map cache data (MCD_S) is updated at the time of performing an operation in response to a request from the host device or performing a background operation, the controller 120 updates the map data of the nonvolatile memory device 110 To the nonvolatile memory device 110. The nonvolatile memory device 110 may be a nonvolatile memory device.

The capacity of the buffer memory of the controller 120 is smaller than that of the map data MD. Therefore, the entire map data MD can not be loaded into the controller 120. [ If the portion of the map data MD necessary for performing the request or the background operation from the host apparatus is not loaded into the controller 120 as the storage map cache data MCD_S, the controller 120 reads the map cache data MCD_S To be erased or written to the nonvolatile memory device 110 and read the necessary part from the nonvolatile memory device 110. [ This is a factor that increases the time during which a request or background operation from the host device is performed.

In order to prevent such a problem, the storage apparatus 1300 according to the embodiment of the present invention is configured to transmit all or a part of the map data MD to the host apparatus. The host device is configured to store all or part of the map data (MD) transmitted from the story device in the RAM 1200 as host map cache data (MCD_H). Thereafter, referring to the host map cache data (MCD_H), the host device can transmit a read request including the physical address to the storage device 1300. [ If the read request includes a physical address, the controller 120 may skip the operation of performing the address translation or reading the necessary portion of the map data (MD) from the nonvolatile memory device 110. Thus, the time when the storage apparatus 1300 performs the request from the host apparatus is reduced, and the operation speed of the storage apparatus 1300 and the computing apparatus 1000 is improved.

The host map cache data (MCD_H) stored in the RAM 1200 of the host apparatus 1000 is managed by the host apparatus, not by the storage apparatus 1300. The embodiments of the present invention can be applied without changing the interface between the host device and the storage device 1300 from the conventional ones since there is no need to transfer the management authority of the RAM 1200 of the host device to the storage device 1300 have. Thus, the cost of applying the embodiments of the present invention is reduced.

FIG. 2 is a flow chart illustrating a method of operating a storage device 1300 in accordance with embodiments of the present invention. Referring to FIGS. 1 and 2, in step S110, the storage device 1300 may transmit at least a portion of the map data (MD) to the host device. For example, the controller 120 may transmit storage map cache data (MCD_S) loaded in an internal buffer memory to the host device. The controller 120 may read some of the map data MD from the nonvolatile memory device 110 and store the storage map cache data MCD_S and the stored storage map cache data MCD_S to the host device.

In step S120, the storage apparatus 1300 may receive a read request from the host apparatus. For example, the controller 120 may receive a read request including a read command and an address from the host device.

In step S130, the storage apparatus 1300 can determine whether the read request received from the host apparatus includes a physical address (PA). For example, the controller 120 can identify the address as a physical address (PA) if an address exists in a portion allocated to locate the physical address PA among the read requests received from the host device. As another example, when the address included in the read request received from the host device is Out-of-Bound, the controller 120 sets the Out-of-Bound portion to the physical address (PA) . If the read request includes the physical address, step S140 is skipped and step S150 is performed. If the read request includes the physical address, step S140 is performed, and step S150 is performed.

In step S140, the controller 120 may convert the logical address LA included in the read request into a physical address (PA). For example, when a part necessary for the conversion in the map data MD is loaded into the controller 120 as the storage map cache data MCD_S, the controller 120 refers to the storage map cache data MCD_S, The logical address LA included in the physical address PA can be converted. The controller 120 can read the portion necessary for the conversion from the nonvolatile memory device 110 when the portion necessary for the conversion in the map data MD is not loaded into the controller 120 as the storage map cache data MCD_S have. When the capacity of the buffer memory of the controller 120 is insufficient, the controller 120 deletes some or all of the storage map cache data MCD_S and reads a portion necessary for the conversion from the nonvolatile memory device 110. [ When the portion to be deleted in the storage map cache data MCD_S is updated after being read from the nonvolatile memory device 110, the controller 120 causes the nonvolatile memory device 110 to update the updated map data MD, It is possible to delete the updated portion. For example, the controller 120 can select an object to be deleted from among the storage map cache data (MCD_S) based on the LRU (Least Recently Used) method.

In step S150, the controller 120 can read data from the nonvolatile memory device 110 using the converted physical address (PA) received from the host device or referring to the storage map cache data (MCD_S).

As described above, when reading is performed based on the physical address (PA) received from the host device, the controller 120 does not need an operation to convert the logical address LA to the physical address (PA) The operating speed of the computing device 1000 and the computing device 1000 is improved.

3 is a flow chart showing how the storage device 1300 transmits some or all of the map data MD to the host device at power-on. Referring to Figures 1 and 3, in step S210, the host device, the controller 120, and the non-volatile memory device perform power-on training. Power-on training can include ZQ training to adjust termination resistance, link training to adjust sink or skew, and initialization communication to exchange information needed for communication.

In step S220, the host device can request map data (MD) to the controller 120. [ For example, the host device can request a portion of the map data (MD) by specifying a necessary portion. For example, the host device can designate a portion of map data (MD) in which data necessary for driving the computing system 1000 is stored, such as a file system, a boot image, an operating system, and the like. As another example, the host device can request the map data (MD) to the controller 120 without specifying otherwise.

In step S231, the controller 120 can read the first part MD1 from the nonvolatile memory device 110 out of the map data MD. The first part MD1 may be stored in the controller 120 as the storage map cache data MCD_S. In step S241, the controller 120 may transmit the first part MD1 stored in the storage map cache data MCD_S to the host device. The first part MD1 may be stored in RAM 1200 as host map cache data MCD_H.

In step S232, the controller 120 can read the second portion MD2 from the nonvolatile memory device 110 out of the map data MD. The second portion MD2 may be stored in the controller 120 as the storage map cache data MCD_S. In step S242, the controller 120 may transmit the second part MD2 stored in the storage map cache data MCD_S to the host device. The second part MD2 may be stored in RAM 1200 as host map cache data MCD_H.

In step S23n, the controller 120 can read the n-th part MDn from the nonvolatile memory device 110 in the map data MD. The n-th portion MDn may be stored in the controller 120 as the storage map cache data MCD_S. In step S24n, the controller 120 may transmit the n-th part MDn stored in the storage map cache data MCD_S to the host device. The n-th portion MDn may be stored in the RAM 1200 as host map cache data (MCD_H).

In step S250, the host device, the controller 120, and the nonvolatile memory device 110 can complete the initialization upload.

As described above, the host device and storage device 1300 may upload some or all of the map data MD to the RAM 1200 after the power-on training is completed. For example, some or all of the map data MD may include readings to the non-volatile memory device 110 a plurality of times and transmissions to the host device. However, some or all of the map data MD is not limited to being executed a plurality of times, and can be completed by reading one non-volatile memory device 110 and transmitting to one host device.

When the initialization upload is completed, the host device can normally start access to the storage device 1300. However, the host device and the storage device 1300 are not limited to performing the initialization upload, and the initialization upload may be omitted. The host device can normally perform access to the storage device 1300 without initialization upload.

4 shows an example of a map data request in which the host apparatus requests map data (MD) to the storage apparatus 1300. FIG. Illustratively, the map data request is described with reference to a command UPIU (UFS Protocol Information Unit) of UFS (Universal Flash Storage). However, the map data request that the host device sends to the storage device 1300 is not limited to the command UPIU of the UFS. The map data request may be suitably selected according to the type of interface between the host device and the storage device 1300. [

The command UPIU may include the 0th to 31st blocks (0 to 31), for example, the 0th to 31st bytes. The zeroth block (0) indicates the transaction type. For example, in the case of the command UPIU, the 0th block (0) may be 'xx00 0001b'.

The first block indicates a flag (Flag). The flag may include a read flag indicating a read, a write flag indicating a write, and a property flag indicating a property. For example, the read flag indicates that the command UPIU is associated with a read. The write flag indicates that the command UPIU is associated with a write. The property flags may indicate whether the command UPIU is simple (simple), ordered (sequential), head of queue, or the like.

The second block 2 indicates the logical number (LUN, Logical Unit Number) of the target device. The third block 3 indicates a task tag.

A part of the fourth block 4 may be used as the first option block OB1, and the remaining part may indicate the command set type. For example, the command set type may include a SCSI (SCSI) command set, a UFS specific command set, a vendor specific command set, and the like.

The fifth to seventh blocks 5 to 7 may be used as the first option block OB. The eighth block 8 indicates the total length of the EHS (Extra Header Segment). The ninth block 9 may be used as the first option block OB1. The tenth and eleventh blocks 10 and 11 indicate the data segment length and indicate the most significant bit (MSB) to the least significant bit (LSB). The data segment length indicates the number of valid bytes in the data segment.

The twelfth to fifteenth blocks 12 to 15 indicate the size of data to be received from the storage device 1300 by the host device or the size of data to be transmitted to the storage device 1300 by the host device.

The 16th to 31st blocks 16 to 31 may include 0 to 15 command descriptor blocks (CDB [0] to CDB [15], command descriptor blocks), respectively. The 16th to 31st blocks 16 to 31 may include a command and an address based on UFS or Small Computer System Interface (SCSI).

An end-to-end Cyclic Redundancy Check (CRC) code (Header E2ECRC) may be optionally added after the 31st block 31 of the command UPIU. For example, if the first bit (HD) of the 0th field is '0', the end-to-end cyclic redundancy check code of the header may be omitted.

Part of the fourth block 4, the fifth to seventh blocks 5 to 7, and the ninth block 9 are used as the first option block OB1. The first option block OB1 may include a signature (SIG) when the command UPIU includes the physical address PA. If the command UPIU does not include the physical address PA, the first option block OB1 may not include the signature SIG. When the first option block OB1 does not include the signature SIG, at least some of the first option blocks OB1 may be used as a reserved block. Even when the first option block OB1 includes a signature, at least a part of the first option block OB1 can be used as a reserved block. The signature SIG will be described in more detail below with reference to the accompanying drawings.

5 shows an example of a command descriptor block (CDB) of a map data request in which the host apparatus requests map data (MD) to the storage apparatus 1300. [ Illustratively, a map data request is described with reference to a command descriptor block (CDB) of a read buffer command of a UFS (Universal Flash Storage). However, the map data request transmitted from the host apparatus to the storage apparatus 1300 is not limited to the command descriptor block (CDB) of the UFS read buffer command. The map data request may be suitably selected according to the type of interface between the host device and the storage device 1300. [

Referring to Figures 1, 4 and 5, the rows of the command descriptor block (CDB) indicate each byte of the command descriptor block (CDB). Illustratively, the command descriptor block (CDB) of the read buffer command may include the 0th through 9th bytes (0 through 9). The columns of the command descriptor block (CDB) indicate the respective bits (Bit) of each byte of the command descriptor block (CDB). For example, each byte may comprise the 0th through 7th bits (0 through 7).

The 0th to 7th bits (0 to 7) of the 0th byte (0) of the command descriptor block (CDB) indicate an operation code. For example, the operation code of the read buffer command may be '3Ch'.

The 0th to 4th bits (0 to 4) of the first byte 1 of the command buffer block (CDB) of the read buffer command may indicate a mode (MODE). For example, the mode may include vendor specific or data. The ninth byte 9 of the command descriptor block (CDB) may include a control CONTROL. For example, the control may be '00h'.

The remaining configuration of the command buffer block (CDB) of the read buffer command may be different when the read buffer command is used for general purposes and when used to request map data (MD). For example, the general purpose of the read buffer command is to test the buffer memory of the logical unit, to test the integrity of the service delivery subsystem, to download the microcode of the storage device 1300, 1300) by the specifications of the UFS for purposes other than the request of the map data (MD), such as obtaining the error history and statistics of the data, the tunneling of the command and the data, Lt; / RTI >

When the read buffer command is used for general purposes, the fifth to seventh bits 5 to 7 of the first byte 1 of the command descriptor block (CDB) can be used as a reserved block. The 0th to 7th bits (0 to 7) of the second byte 2 of the command descriptor block (CDB) can be used as a buffer identifier (BUFFER ID). The buffer identifier (BUFFER ID) can identify the buffer in the logical unit. The third to fifth bytes 3 to 5 of the command descriptor block (CDB) may indicate a buffer offset (BUFFER OFFSET). The buffer offset (BUFFER OFFSET) may include the least significant bit (LSB) from the most significant bit (MSB). The buffer offset (BUFFER OFFSET) may indicate the byte offset of the buffer identified by the buffer identifier. The sixth through eighth bytes 6 through 8 of the command descriptor block (CDB) may indicate the ALLOCATION LENGTH. The ALLOCATION LENGTH may include the least significant bit (LSB) from the most significant bit (MSB). The ALLOCATION LENGTH may indicate the number of bytes from the BUFFER OFFSET that the host device desires to receive.

When the read buffer command is used for the purpose of requesting the map data MD, the fifth to seventh bits 5 to 7 of the first byte of the command descriptor block (CDB) and the second to eighth bytes And can be used as the second option block OB2. The second option block OB2 may include an argument or a description indicating the request of the map data MD. The second option block OB2 may include information on a portion of the map data MD that the host device wants to receive. For example, the second option block OB2 may comprise information of logical addresses or logical addresses associated with the portion of the map data MD desired to be received. The second option block OB2 may include information on the size of the map data MD desired to be received by the host device.

6 shows another example of a command descriptor block (CDB) of a map data request in which the host apparatus requests map data (MD) to the storage apparatus 1300. Fig. Illustratively, a map data request is described with reference to a command descriptor block (CDB) of a mode sense command of UFS (Universal Flash Storage). However, the map data request transmitted from the host apparatus to the storage apparatus 1300 is not limited to the command descriptor block (CDB) of the UFS mode sense command (Read Buffer Command). The map data request may be suitably selected according to the type of interface between the host device and the storage device 1300. [

Referring to Figures 1, 4 and 6, the rows of the command descriptor block (CDB) indicate each byte of the command descriptor block (CDB). Illustratively, the command descriptor block (CDB) of the mode sense command may include the 0th through 9th bytes (0 through 9). The columns of the command descriptor block (CDB) indicate the respective bits (Bit) of each byte of the command descriptor block (CDB). For example, each byte may comprise the 0th through 7th bits (0 through 7).

The 0th to 7th bits (0 to 7) of the 0th byte (0) of the command descriptor block (CDB) indicate an operation code. For example, the operation code of the read buffer command may be '5Ah'.

The third bit 3 of the first byte 1 of the command descriptor block CDB indicates the value of 'DBD' and is designated '1b'. The fourth bit 4 of the first byte 1 of the command descriptor block CDB indicates the value of 'LLBAA' and is designated as '0b'. The ninth byte 9 of the command descriptor block (CDB) may include a control CONTROL. For example, the control may be '00h'.

The remaining configuration of the command descriptor block (CDB) of the mode sense command may be changed when the mode sense command is used for general purpose and when it is used for requesting the map data (MD). For example, the general purpose of the mode sense command may be to store data by the UFS specification for purposes other than the request of the map data (MD), such as by requesting parameters in the storage device 1300, It may be an adopted purpose.

When the read buffer command is used for general purposes, the 0th to 2nd bits (0 to 2) and the 5th to 7th bits (5 to 7) of the first byte 1 of the command descriptor block (CDB) Can be used as a reserved block. The 0th to 5th bits (0 to 5) of the second byte of the command descriptor block (CDB) may indicate a page code (PAGE CODE). The page code (PAGE CODE) can identify the page mode page to be returned. The sixth and seventh bits 6, 7 of the command descriptor block (CDB) may point to a page control (PC). The page control (PC) can identify the type of mode parameter values to be returned among the mode pages. For example, a page control (PC) can identify the return of a current value, the return of a bit mask indicating a changeable value, the return of default values, or the return of stored values. The third byte 3 of the command descriptor block (CDB) may indicate a sub page code (SUBPAGE CODE). The SUBPAGE CODE may identify the subpage mode page to be returned. The fourth to sixth bytes 4 to 6 of the command descriptor block (CDB) may be a reserved block. The seventh and eighth bytes 7, 8 of the command descriptor block (CDB) may indicate the ALLOCATION LENGTH. The ALLOCATION LENGTH may include the least significant bit (LSB) from the most significant bit (MSB). The ALLOCATION LENGTH may indicate the number of bytes of pages that the host device wishes to receive.

When the mode sense command is used for the purpose of requesting the map data MD, the 0th to 2nd bits (0 to 2) and the 5th to 7th bits (1 to 4) of the first byte of the command descriptor block 5 to 7), and the second to eighth bytes may be used as the third option block OB3. The third option block OB3 may include an argument or a description indicating the request of the map data MD. The third option block OB3 may include information on a portion of the map data MD that the host device wants to receive. For example, the third option block OB3 may include information of logical addresses or logical addresses associated with the portion of the map data MD that it wants to receive. The second option block OB2 may include information on the size of the map data MD desired to be received by the host device.

Fig. 7 shows an example of a response in which the storage device transmits map data (MD) to the host device in response to the request of Fig. 5 or Fig. Illustratively, the map data response is described with reference to UPIU (DATA IN UPIU), which is data of UFS (Universal Flash Storage). However, the map data response transmitted from the storage device 1300 to the host device is not limited to the UPIU (DATA IN UPIU) which is the UFS data. The map data response may be suitably selected according to the type of interface between the host apparatus and the storage apparatus 1300. [

Referring to FIGS. 1 and 7, the data UPIU (DATA IN UPIU) includes 0th to 31st blocks (0 to 31), for example, 0th to 31st bytes. The 0 block indicates the transaction type. For data UPIU (DATA IN UPIU), the transaction type may be 'xx10 0010b'. The first block indicates a flag (Flag). The second block 2 indicates a logical number (LUN, Logical Unit Number). The third block 3 indicates a task tag.

The fourth through seventh blocks of the UPIU (DATA IN UPIU), which is data, may be reserved blocks. The eighth block indicates the total length of the EHS (Extra Header Segment). The ninth block may be a reserved block. The tenth and eleventh blocks 10 and 11 indicate a data segment length and include a most significant bit (MSB) to a least significant bit (LSB). The Data Segment Length indicates the number of valid bytes in the Data Segment. The twelfth to fifteenth blocks 12 to 15 indicate a data buffer offset and include a most significant bit (MSB) to a least significant bit (LSB). The data buffer offset indicates the offset of the data included in the corresponding data UPIU (DATA IN UPIU) among the entire data. The 16th to 19th blocks 16-19 refer to a data transfer count and include a most significant bit (MSB) to a least significant bit (LSB). The Data Transfer Count indicates the number of bytes loaded into the Data Segment, and more specifically, the number of valid bytes.

The 20th to 31st blocks 20 to 31 of the UPIU (DATA IN UPIU), which is data, may be reserved blocks. An end-to-end Cyclic Redundancy Check (CRC) code (Header E2ECRC) of the header may be optionally added after the 31st block 31 of the UPIU (DATA IN UPIU) . For example, if the first bit (HD) of the 0th field is '0', the end-to-end cyclic redundancy check code of the header may be omitted.

After the end-to-end cyclic redundancy check code (Header E2ECRC) of the header or after the 31st block 31, a data segment is added. The data segment includes k-th to k + k-length -1 segments (DATA [0] to DATA [Length-1]). When the end-to-end cyclic redundancy check code (Header E2ECRC) of the header is omitted, that is, if the first bit (HD) of the 0th field is '0', k may be 32. The length may be a value specified by the data segment length of the tenth and eleventh blocks 10 and 11. [

An end-to-end Cyclic Redundancy Check (CRC) code (Data E2ECRC) of the data is written after the k + length -1 field of the UPIU (DATA IN UPIU) . For example, if the second bit (DD) of the 0th field is '0', the end-to-end cyclic redundancy check code (Data E2ECRC) of the data may be omitted.

The storage device 1300 may load the map data MD into a data segment and transmit it to the host device. For example, the storage device 1300 may load a portion of map data (MD) corresponding to the logical address or size requested by the host device into a data segment and transmit the loaded data segment to the host device.

8 shows map data MD, storage map cache data MCD_S, and host map cache data MCD_H in the nonvolatile memory device 110, the controller 120, and the RAM 1200 of the host apparatus, . 1 and 8, the map data MD stored in the nonvolatile memory device 110 is stored in the nonvolatile memory device 110 in the storage space of the nonvolatile memory device 110 between the physical addresses PA and the logical addresses LA. And may include mapping information. The map data (MD) can be managed in units of map data blocks. Each map data block includes a plurality of entries, and each entry may contain mapping information between consecutive logical addresses (LA) and consecutive physical addresses (PA).

Offsets (01 to 12) may be assigned to the map data blocks. For example, the offsets 01 through 12 may correspond to the logical addresses LA or LA mapped in each map data block, according to the physical addresses PA of the nonvolatile memory device 110 in which each map data block is stored. May be assigned according to physical addresses PA. For example, the physical addresses of the non-volatile memory device 110 or the logical addresses assigned to the non-volatile memory device 110 are divided at regular intervals, and mapping information associated with each divided group forms each map data block can do.

The controller 120 reads the map data MD in units of map data blocks from the nonvolatile memory device 110 and stores the map data MD in the storage map cache data MCD_S. When storing the storage map cache data MCD_S, the controller 120 can generate the header HD_S. The header HD_S may include the offsets of the map data blocks stored in the storage map cache data MCD_S in the controller 120.

When the controller 120 transmits the storage map cache data MCD_S to the host device, the controller 120 can generate a signature SIG. For example, a signature SIG may be generated based on a logical address (LA) and a physical address (PA) of each entry included in each map data block. For example, the controller 120 performs encryption using the Advanced Encryption Standard (AES), performs a hash function, or scrambles the logical address (LA) and the physical address (PA) of each entry of each map data block, To generate additional data. The controller 120 may select a part or all of the generated additional data as a signature (SIG). The controller 120 may transmit the logical addresses LA, physical addresses PA and signatures SIG of each map data block to the host device along with the offset.

The RAM 1200 of the host device may store the map data blocks transmitted from the controller 120 as host map cache data MCD_H. When storing the host map cache data (MCD_H), the host device can generate the header HD_H. The header HD_H may contain the offsets of the map data blocks stored in the host map cache data MCD_H in the RAM 1200. Each map data block stored in the host map cache data MCD_H may include logical addresses LA, physical addresses PA and signatures SIG.

Illustratively, when the host device requests map data (MD) to the controller 120, the host device may forward the offset of the desired map data block to the controller 120. When a map data block is received from the controller 120, the host device can compare the offset of the received map data block with the offset of the header HD_H and select a new addition or update according to the comparison result. When the host device requests the controller to read, the host device can transmit the offset of the map data block including the physical address and the physical address. The controller 120 compares the offset of the received map data block with the offset registered in the header HD_S to determine whether the map data block is stored in the storage map cache data MCD_S.

Illustratively, the size of the space allocated to store the host map cache data MCD_H in the RAM 1200 may be equal to or less than the size of the map data MD. If the size of the space allocated to the host map cache data MCD_H is smaller than the size of the map data MD, the host device can select the release policy of the host map cache data MCD_H. For example, when the space required for storing a new map data block in the storage space allocated to the host map cache data (MCD_H) is insufficient, the host apparatus stores host map cache data (MCD_H ) Can be discarded.

Illustratively, the size of the space allocated to store the host map cache data MCD_H in the RAM 1200 may be larger than the size of the map data MD. A portion larger than the size of the map data MD can be used as a spare space. For example, when the map data MD is updated by garbage collection or wear leveling in the storage device 1300, the controller 120 transmits the updated portion to the host device . The spare space can be used to store updated portions. The Old Portion of the host map cache data MCD_H corresponding to the updated portion can be invalidated.

9 is a flowchart showing how the host apparatus requests map data (MD) in the first mode to the storage apparatus 1300. FIG. Referring to FIGS. 1 and 9, in step S210, the host device may request map data (MD) to the controller 120 in the first mode. Illustratively, the first mode may be specified in the second option block OB2 of FIG. 5 or the third option block OB3 of FIG.

In response to the map data request of the first mode, the controller 120 may collect the updated storage map cache data (MCD_S) in step S220. For example, the controller 120 reads from the map data MD stored in the nonvolatile memory device 110 and collects storage map cache data MCD_S newly added to the storage map cache data MCD_S of the controller 120 can do. For example, the controller 120 loads the storage map cache data MCD_S from the map data MD stored in the nonvolatile memory device 110 to the controller 120, and then stores the logical addresses LA and physical addresses It is possible to collect the storage map cache data (MCD_S) in which the mapping relationship between the storage map cache data (PA) is updated. For example, the storage map cache data (MCD_S) that was previously transmitted to the host device and has not been updated can be excluded from the collection target.

For example, the controller 120 starts collecting the updated storage cache map data (MCD_S) until the size of the collected storage cache map data (MCD_S) reaches the reference size, (KCD_S) until there is no host request pending on the storage device 1300 until all of the outstanding requests from the host device have been completed have.

When the collection of the updated storage cache data MCD_S is completed, the controller 120 may transmit the collected storage cache map data MCD_S to the host device in step S230. In step S240, the controller 120 may write updated cache map data (MCD_S) among the collected cache map data (MCD_S) to the nonvolatile memory device (110).

Illustratively, steps S230 and S240 may be performed simultaneously. For example, the controller 120 transmits the collected storage cache map data MCD_S to the host device and the controller 120 writes the updated storage cache map data MCD_S to the nonvolatile memory device 110 (Or backing up) may be shadowed with respect to each other. For example, when the controller 120 attempts to transmit the collected storage cache map data MCD_S to the host device, the controller 120 stores the updated storage cache map data MCD_S in the nonvolatile memory device 110 Can be performed together. For example, when the controller 120 attempts to write updated storage cache map data (MCD_S) to the non-volatile memory device 110, the controller 120, regardless of the conditions mentioned in step S220, Storage cache map data MCD_S to the host device.

Illustratively, the collected storage map cache data (MCD_S) may be transferred via the UPIU, which is the data described with reference to FIG. For example, the collected storage map cache data (MCD_S) may be delivered via a UPIU that is one or more than one data.

 When the transfer of the storage map cache data MCD_S is completed through the UPIU, which is data, the host device can forward the map data request of the first mode to the storage device 1300 again in step S250. That is, steps S210 through S240 may be continuously performed while the host apparatus and the storage apparatus 1300 communicate with each other. For example, the map data request of the first mode may be a nameless request because it does not request a specific portion of the map data MD.

10 is a flowchart showing how the host apparatus requests map data (MD) in the second mode to the storage apparatus 1300. Referring to FIGS. 1 and 10, in step S310, the host device may request the controller 120 for map data MD in a second mode. The map data request in the second mode may be sent with logical addresses (LA) of the portion of the map data (MD) that the host wishes to receive. As another example, the map data request of the second mode may be sent with the offset of the map data block of the map data (MD) that the host wants to receive. Illustratively, the second mode may be specified in the second option block OB2 of FIG. 5 or the third option block OB3 of FIG.

In step S320, the controller 120 determines whether a portion of the map data (MD) requested by the host device hits the storage map cache data (MCD_S). For example, the controller 120 can determine whether a portion of the map data (MD) requested by the host device is loaded in the controller 120 as the storage map cache data (MCD_S). If the hit of the storage map cache data (MCD_S) occurs, step S330 may be omitted and step S340 may be performed. If the hit of the storage map cache data MCD_S does not occur, that is, if a miss of the storage map cache data MCD_S occurs, the step S330 may be performed after the step S330 is performed.

In step S330, the controller 120 reads a portion of the map data (MD) requested by the host device from the nonvolatile memory device 110 and stores it as the storage cache map data (MCD_S). In step S340, the controller 120 may transmit the portion of the map data (MD) requested by the host apparatus among the storage cache map data (MCD_S) to the host apparatus.

Illustratively, the portion of the requested map data (MD) may be carried over the UPIU, which is the data described with reference to FIG. For example, the portion of the requested map data (MD) may be carried over a UPIU that is one or more than a plurality of data. For example, the map data request of the second mode requests a specific portion of the map data (MD), so it may be a named request.

11 is a flowchart showing a method by which a host device transmits a write request to the storage device 1300 to perform writing. Referring to FIGS. 1 and 11, in step S310, a write event may occur in the host device. For example, data may be written to or written to specific logical addresses LA of the storage device 1300 at the host device.

As the write event occurs, in step S320, the host device may invalidate the portion of the host map cache data (MCD_H) associated with the logical addresses (LA) of the write event. For example, the host device may release or delete the portion of the host map cache data (MCD_H) associated with the logical addresses (LA) of the write event from the RAM 1200.

In step S330, the host device may send a write request to the controller 120 that includes logical addresses LA. The write request may be delivered as the command UPIU described with reference to FIG.

In response to the write request from the host device, in step S340, the controller 120 may select the physical addresses PA of the non-volatile memory device 110 to which data is to be written.

In step S350, the controller 120 may send the selected physical addresses (PA) and the write command to the nonvolatile memory device 110, thereby performing the write requested by the host device.

In step S360, the controller 120 may update the storage map cache data MCD_S by reflecting the mapping relationship between the selected physical addresses PA and the logical addresses LA included in the write request.

Illustratively, steps S350 and S360 may be performed in the order shown, contrary to the order shown, or concurrently.

In step S370, the controller 120 may send a response to the host device. For example, the response may be sent with logical addresses (LA) included in the write request, mapped physical addresses (PA) and signature (SIG), or transmitted without physical addresses (PA) and signature . For example, if the logical addresses LA included in the write request, for example a contiguous logical address range, are mapped with one contiguous physical address range, The start physical address of the range and the corresponding signature (SIG) in the response.

As another example, if the logical addresses LA included in the write request, for example a contiguous logical address range, are mapped with two or more contiguous physical address ranges, the controller 120 may determine that two or more consecutive physical (S) corresponding to their starting physical addresses in the ranges of addresses, and their corresponding signatures (SIG). If the capacity of the response is insufficient to transmit two or more starting physical addresses, the controller 120 may transmit the response without including a physical address (PA) and a signature (SIG).

In step S380, when the physical address PA and the signature SIG are received, steps S390 and S393 are omitted and step S395 is performed. If the physical address PA and the signature SIG have not been received, steps S390 and S393 are performed and then step S395 is performed.

In step S390, the host device may request the controller 120 to issue a physical address (PA). For example, the host device may request the physical address (PA) from the controller 120 through the map data request of the second mode described with reference to FIG. The host device may be sent to the controller 120 with a map data request associated with logical addresses (LA) included in the write request.

In step S393, the controller 120 may transmit the starting physical addresses of two or more consecutive physical address ranges to the host device in response to the map data request.

In step S395, the host device can update the host map cache data (MCD_H) based on the physical address (PA) and the signature (SIG) received from the controller 120.

12 is a flowchart showing a method in which a host device transfers a read request to the storage device 1300 to perform writing. Referring to FIGS. 1 and 12, in step S410, a read event may occur in the host device. For example, there may be a demand to read data stored in specific logical addresses LA of the storage device 1300 at the host device.

As the read event occurs, in step S420, the host device determines whether a portion of the map data (MD) associated with the logical address (LA) of the read event is loaded in the RAM 1200 as host map cache data (MCD_H) . The host device refers to the host map cache data MCD_H in step S430 to determine whether the physical address corresponding to the logical address LA is included in the host map cache data MCD_H PA and signature SIG and sends a read request to controller 120 that includes physical address PA, logical address LA and signature SIG. If the necessary map data MD in association with the read event is not loaded into the host map cache data MCD_H, the host device can transmit a read request including the logical address LA to the controller 120 in step S480 .

Illustratively, when a read event of a host device is associated with one continuous physical address range, the host device must transmit the starting physical address of one successive physical address and its associated signature (SIG). When a read event of the host device is associated with two or more consecutive physical address ranges, the host device must transmit the starting physical addresses of the ranges of two or more consecutive physical addresses and their associated signatures (SIG). If the size of the command UPIU or command descriptor block (CDB) is insufficient to transmit two or more starting physical addresses and signatures, the host device may send a plurality of starting physical addresses and their associated signatures SIG to the controller 120.

If a read request including a physical address (PA), a logical address (LA) and a signature (SIG) is received from the host device in step S430, the controller 120 determines whether the storage cache map data (MCD_S) do. For example, if the map data block associated with the physical address PA or the logical address LA included in the read request is loaded into the controller 120 as the storage cache map data MCD_S, the storage cache map data MCD_S, Is a hit. If the storage map cache data MCD_S is a hit, the controller 120 obtains the physical address PA by referring to the storage cache map data MCD_S in step S450, and stores the obtained physical address PA and read command Volatile memory device 110 to perform a read request.

If it is determined in step S440 that the cache map data MCD_S is a miss rather than a hit, the controller determines whether the signature SIG is correct in step S460. For example, the controller 120 may generate a signature from the physical address (PA) and the logical address (LA) included in the read request, and compare the signature (SIG) included in the generated signature and the read request. If the generated signature and the signature (SIG) contained in the read request are the same, the physical address (PA) included in the read request is determined to be non-hacked normal. In step S470, the controller 120 may transmit the physical address (PA) and the read command included in the read request to the nonvolatile memory device 110 to perform the read request.

If it is determined in step S480 that the read request including the logical address LA is received or if the signature SIG included in the read request is not normal in step S460, The logical address LA can be converted into the physical address PA. For example, if the map data block associated with the logical address LA included in the read request is loaded into the storage map cache data MCD_S, the controller 120 directly refers to the storage map cache data MCD_S, (LA) to a physical address (PA). If the map data block associated with the logical address LA included in the read request is not loaded into the storage map cache data MCD_S, the controller 120 reads the logical address LA corresponding to the logical address LA from the non-volatile memory device 110 The map data block is read and the read map data block is stored as the storage map cache data MCD_S and the logical address LA can be converted into the physical address PA by referring to the storage map cache data MCD_S . Thereafter, in step S493, the controller 120 may transmit the converted physical address (PA) and the command to the nonvolatile memory device 110 to perform a read request.

In step S495, the nonvolatile memory device 110 may transmit the data to the controller 120 in response to a read command received in step S450, a read command received in step S470, or a read command received in step S493.

In step S497, the controller 120 can transmit the data received from the nonvolatile memory device 110 to the host device.

13 shows an example of a command descriptor block (CDB) of a read request in which the host device requests the storage device 1300 to read. Illustratively, an example of a command descriptor block (CDB) of a first mode read request in which the host device transmits only the logical address LA without the physical address PA is shown in FIG. Illustratively, the read request in the first mode is described with reference to the command descriptor block (CDB) of the read (10) Command (Read (10) Command) of UFS (Universal Flash Storage). However, the read request in the first mode that the host device transmits to the storage device 1300 is not limited to the command descriptor block (CDB) of the read (10) command of the UFS (Read (10) Command). The read request of the first mode may be suitably selected according to the type of interface between the host apparatus and the storage apparatus 1300. [

Referring to Figures 1, 4 and 13, the rows of the command descriptor block (CDB) indicate each byte of the command descriptor block (CDB). Illustratively, the command descriptor block (CDB) of the read (10) command may include the 0th through 9th bytes (0 through 9). The columns of the command descriptor block (CDB) indicate the respective bits (Bit) of each byte of the command descriptor block (CDB). For example, each byte may comprise the 0th through 7th bits (0 through 7).

The 0th to 7th bits (0 to 7) of the 0th byte (0) of the command descriptor block (CDB) indicate an operation code. For example, the operation code of the read (10) command may be '28h'.

The first bit (1) of the first byte (1) of the command descriptor block (CDB) of the read (10) command may not be used. The first bit (1) of the first byte (1) may indicate FUA_NV. The second bit 2 of the first byte 1 may be a reserved block. The third bit 3 of the first byte 1 may indicate a Force Unit Access (FUA). The FUA may indicate whether to use the data cache. The fourth bit 4 of the first byte 1 indicates a DPO (Disable Page Out). The DPO can indicate how to set the retention priority. The fifth through seventh bits 5 through 7 of the first byte 1 are RDPROTECT and may have a value of '000b'.

The second to fifth bytes 2 to 5 of the command descriptor block (CDB) of the read (10) command indicate the logical address (LOGICAL ADDRESS, LA). The logical address LA may include a most significant bit (MSB) to a least significant bit (LSB).

The 0th to 4th bits (0 to 4) of the sixth byte 6 of the command descriptor block (CDB) of the read (10) command indicate the group number (GROUP NUMBER). The group number (GROUP NUMBER) may indicate the Context ID associated with the read request. The fifth to seventh bits 5 to 7 of the sixth byte 6 may be a reserved block.

The seventh and eighth bytes 7 and 8 of the command descriptor block (CDB) of the read (10) command indicate the transmission length (TRANSFER LENGTH). The transfer length (TRANSFER LENGTH) indicates the length of data to be read through the read request.

The ninth byte 9 of the command descriptor block (CDB) of the read (10) command may include a control CONTROL. For example, the control may be '00h'.

Fig. 14 shows another example of a command descriptor block (CDB) of a read request in which the host apparatus requests reading from the storage apparatus 1300. Fig. Illustratively, an example of a command descriptor block (CDB) of a read request in the second mode in which the host device transmits only the physical address (PA) and the logical address (LA) is shown in Fig. Illustratively, the read request in the second mode is described with reference to the command descriptor block (CDB) of the Read (16) Command (Read (16) Command) of UFS (Universal Flash Storage). However, the read request of the second mode that the host device transmits to the storage apparatus 1300 is not limited to the command descriptor block (CDB) of the Read (16) Command of the UFS. The read request in the second mode may be suitably selected according to the type of interface between the host device and the storage device 1300. [

1, 4, and 14, the rows of the command descriptor block (CDB) indicate each byte of the command descriptor block (CDB). Illustratively, the command descriptor block (CDB) of the read (10) command may include the 0th to 15th bytes (0-15). The columns of the command descriptor block (CDB) indicate the respective bits (Bit) of each byte of the command descriptor block (CDB). For example, each byte may comprise the 0th through 7th bits (0 through 7).

The 0th to 7th bits (0 to 7) of the 0th byte (0) of the command descriptor block (CDB) indicate an operation code. For example, the operation code of the read (16) command may be '88h'.

The first bit (1) of the first byte (1) of the command descriptor block (CDB) of the read (16) command may not be used. The first bit (1) of the first byte (1) may indicate FUA_NV. The second bit 2 of the first byte 1 may be a reserved block. The third bit 3 of the first byte 1 may indicate a Force Unit Access (FUA). The FUA may indicate whether to use the data cache. The fourth bit 4 of the first byte 1 indicates a DPO (Disable Page Out). The DPO can indicate how to set the retention priority. The fifth through seventh bits 5 through 7 of the first byte 1 are RDPROTECT and may have a value of '000b'.

The second to ninth bytes 2 to 9 of the command descriptor block (CDB) of the read (16) command indicate the fourth option block OB4. The fourth option block OB4 may include a most significant bit (MSB) to a least significant bit (LSB). The fourth option block OB4 may include a logical address LOGICAL ADDRESS, LA and a physical address PHYSICAL ADDRESS, PA.

The tenth through thirteenth bytes 10-13 of the command descriptor block (CDB) of the read (16) command indicate the transmission length (TRANSFER LENGTH). The transfer length (TRANSFER LENGTH) indicates the length of data to be read through the read request.

The 0th to 4th bits (0 to 4) of the 14th byte 14 of the command descriptor block (CDB) of the read (16) command indicate the group number (GROUP NUMBER). The group number (GROUP NUMBER) may indicate the Context ID associated with the read request. The fifth and sixth bits 5 and 6 of the 14th byte 14 may be reserved. The seventh bit 7 of the 14th byte 14 may be ignored.

The 15th byte 15 of the command descriptor block (CDB) of the read (16) command may include a control CONTROL. For example, the control may be '00h'.

15 shows an example of a command descriptor block (CDB) in which a host device transmits a plurality of physical addresses (PA) and signatures (SIG) via a separate command UPIU. Illustratively, a plurality of physical addresses and signatures SIG are described with reference to a command descriptor block (CDB) of a Mode Select Command of Universal Flash Storage (UFS). However, it is not limited to the command descriptor block (CDB) of the Mode Select Command of the UFS that the host device transmits a plurality of physical addresses (PA) and signatures (SIG) to the storage device 1300 . The transmission of the plurality of physical addresses (PA) and signatures (SIG) may be suitably selected according to the type of interface between the host device and the storage device 1300. [

1, 4 and 15, the rows of the command descriptor block (CDB) indicate each byte of the command descriptor block (CDB). Illustratively, the command descriptor block (CDB) of the read (10) command may include the 0th to 15th bytes (0-15). The columns of the command descriptor block (CDB) indicate the respective bits (Bit) of each byte of the command descriptor block (CDB). For example, each byte may comprise the 0th through 7th bits (0 through 7).

The 0th byte of the command descriptor block (CDB) indicates an operation code. In the case of the mode selection command, the operation code may be '55h'.

The zeroth bit of the first byte (1) of the command descriptor block (CDB) of the mode selection command indicates SP (Save Pages). The first to third bits 1 to 3 of the first byte 1 may be a fifth option block OB5. The fourth bit 4 of the first byte 1 indicates PF (Page Format) and may be '1b'. The fifth through seventh bits 5 through 7 of the first byte 1 may be the fifth option block OB5.

The second to sixth bytes 2 to 6 of the command descriptor block (CDB) of the mode selection command may be the fifth option block OB5.

The seventh and eighth bytes 7, 8 of the command descriptor block (CDB) of the mode selection command may indicate the parameter list length (PARAMETER LIST LENGTH).

The 15th byte 15 of the command descriptor block CDB of the command descriptor block CDB of the mode selection command may include the control CONTROL. For example, the control may be '00h'.

The fifth option block OB5 may include a reserved block when the mode selection command is used for other purposes than transmitting the physical addresses PA and the signatures SIG. When the mode selection command is used to transmit physical addresses PA and signatures SIG, the fifth option block OB5 includes an argument for informing the transmission of physical addresses PA and signatures SIG an argument or a description, and may include a reserved block.

In response to the mode select command, the controller 120 may send a Ready to Transfer UPIU to the host device. In response to the transmit ready UPIU, the host device may send a data out UPIU (Data Out UPIU) containing the physical addresses (PA) and signatures (SIG) to the controller 120.

Illustratively, the host device may transmit the read (10) or read (16) command described with reference to FIG. 13 or 14 and the mode select command of FIG. 15 in combination to the controller 120.

16 is a flowchart showing how the controller 120 manages the signature (SIG). Referring to FIGS. 1 and 16, in step S510, the controller 120 determines whether to transmit the physical address PA or the map data block MDk to the host device. If the physical address PA or the map data block MDk is not transmitted to the host device, Steps S520 and S530 are omitted. When the physical address PA or the map data block MDk is transmitted to the host device, steps S520 and S530 are performed.

In step S520, the controller 120 may generate a signature (SIG) from the physical address PA and its corresponding logical address LA. Alternatively, the controller 120 may generate a signature block SIGk corresponding to the map data block MDk from the physical address PA and the logical address LA of each entry of the map data block MDk.

In step S530, the controller 120 may transmit the physical address PA and the corresponding signature SIG, or the map data block MDk and the corresponding signature block SIGk to the host device.

In step S540, the controller 120 determines whether a logical address (LA), a physical address (PA), and a signature (SIG) are received from the host apparatus. If the logical address (LA), the physical address (PA), and the signature (SIG) are not received from the host device, steps S550 to S570 are omitted. When the logical address (LA), the physical address (PA), and the signature (SIG) are received from the host apparatus, steps S550 to S570 are performed.

In step S550, the controller 120 generates a signature SIG_G from the received logical address LA and the received physical address PA. In step S560, the controller 120 determines whether the received signature (SIG) is identical to the generated signature (SIG_G). If the received signature (SIG) and generated signature (SIG_G) are the same, then in step S570 controller 120 determines that the received signature (SIG) is correct. If the received signature SIG is not the same as the generated signature SIG_G, the controller 120 determines in step S580 that the received signature SIG is incorrect and hacking or data loss for the host map cache data MCD_H It is determined that there is a possibility of occurrence. The controller 120 may notify the host device that the signature SIG is incorrect.

17 is a flowchart showing an example in which encryption is performed when the controller 120 transmits map data (MD) to the host apparatus. Referring to FIGS. 1 and 17, in step S610, the controller 120 determines whether the physical address PA or the map data block MDk is transmitted to the host apparatus. If the physical address PA or the map data block MDk is not transmitted to the host device, steps S620 and S630 are omitted. When the physical address PA or the map data block MDk is transmitted to the host device, steps S620 and S630 are performed.

In step S620, the controller 120 may encrypt the physical address PA and the signature SIG, or may encrypt the physical addresses PA and signatures SIG of the map data block MDk. In step S630, the controller 120 may transmit the map data block MDk including the encrypted physical address PA_E and the signature SIG_E or the encrypted physical address PA_E and the signature SIG_E to the host device .

In step S640, the controller 120 determines whether a logical address (LA), an encrypted physical address (PA_E), and an encrypted signature (SIG_E) are received from the host apparatus. If the logical address LA, the encrypted physical address PA_E, and the encrypted signature SIG_E are not received from the host device, steps S650 and S660 are omitted. When the logical address (LA), the encrypted physical address (PA_E), and the encrypted signature (SIG_E) are received from the host device, steps S650 and S660 are performed.

In step S650, the controller 120 decrypts the encrypted physical address PA_E and the encrypted signature SIG_E. In step S660, the controller 120 can use the decrypted physical address PA and the signature SIG. For example, as described with reference to FIG. 16, the controller 120 can determine whether the decrypted signature (SIG) is correct using the decrypted signature (SIG). If the decrypted signature (SIG) is correct, the controller 120 may send the decrypted physical address (PA) and the read command to the non-volatile memory device 110, as described with reference to Fig.

As described above, when the portion of the map data MD loaded into the RAM 1200 of the host apparatus as the host map cache data MCD_H is encrypted, the security of the map data MD is improved and the storage device 1300 Can be improved.

18 is a flowchart showing an example in which the storage device 1300 performs defragmentation. Referring to FIGS. 1 and 18, in step S710, the controller 120 may determine whether it is idle. For example, the controller 120 may determine that it is idle if there is no pending request issued by the host device.

If the idle state is determined, the controller 120 can perform defragmentation in step S720. Defragmentation involves migrating data belonging to one or more contiguous physical address ranges and belonging to one contiguous logical address range so that data belonging to one contiguous logical address range falls within one contiguous physical address range . In step S730, the controller 120 may update the storage map cache data (MCD_S) by reflecting the result of the defragmentation.

When defragmentation is performed as described above, the number of cases in which the host device must transmit a plurality of physical addresses to the controller 120 together with a read request is reduced. Thus, the operating speed of the storage device 1300 and the computing device 1000 is improved.

FIG. 19 is a flowchart showing an example in which the computing device 1000 supports defragmentation of the storage device 1300. FIG. Referring to FIGS. 1 and 19, in step S810, a power save event occurs in the host apparatus. The power save event indicates that the condition for the host device to enter the power saving mode is satisfied.

If a power save event occurs, the host device determines in S820 whether the storage device 1300 requires defragmentation. For example, the host device may be connected to the storage device 1300 through the device information of the response UPIU (Response UPIU) transmitted from the storage device 1300, or via separate reporting transmitted from the storage device 1300. [ ) Can identify if defragmentation is necessary.

If defragmentation is required in the storage device 1300 when the power saving event occurs, the host device prohibits the power saving mode in step S830 and allows the storage device 1300 to perform defragmentation. In step S840, the controller 120 can access the nonvolatile memory device 110 to perform defragmentation. In step S850, the controller 120 may update the storage map cache data (MCD_S) by reflecting the result of the defragmentation.

When the defragmentation is completed, or when defragmentation is not required, the host device, the controller 120, and the nonvolatile memory device 110 can enter the power saving mode in step S860.

20 is a flow chart showing how the host device accesses the storage device 1300. FIG. Referring to FIG. 20, in step S910, the host device can read map data from the storage device 1300. FIG. The map data may be stored in the RAM 1200 as host map cache data (MCD_H).

In step S920, a read event may occur in the host device.

In step S930, the host device can determine whether it is associated with the logical address (LA) of the read event and the host map cache data (MCD_H) stored in the RAM 1200. [ For example, the host device can determine whether the portion of the map data (MD) associated with the logical address (LA) of the read event is loaded in the RAM 1200 as host map cache data (MCD_H).

If the logical address LA is associated with the host map cache data MCD_H, the host device refers to the host map cache data MCD_H in step S940 to determine the physical address PA associated with the logical address LA of the read event. And send a read request containing the physical address PA to the storage device 1300. [

If the logical address LA is not associated with the host map cache data MCD_H, then in step S950 the host device may send a read request containing the logical address LA of the read event to the storage device 1300. [

The storage device 1300 may include a solid state drive (SSD) or a hard disk drive (HDD). The storage device 1300 may be a personal computer memory card (PCMCIA), a compact flash card (CF), a smart media card (SM), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro) Memory cards such as SD cards (SD, miniSD, microSD, SDHC), Universal Serial Bus (USB) memory cards, Universal Flash Storage (UFS), and the like. The storage device 1300 may include an embedded memory such as an embedded MultiMediaCard (eMMC), a UFS, a Perfect Page NAND (PPN), and the like.

21 is a block diagram illustrating a non-volatile memory device 110 in accordance with an embodiment of the present invention. 1 and 21, the nonvolatile memory device 110 includes a memory cell array 111, a row decoder circuit 113, a page buffer circuit 115, a data input / output circuit 117, and a control logic circuit 119).

The memory cell array 111 includes a plurality of memory blocks BLK1 to BLKz. Each memory block includes a plurality of memory cells. Each memory block may be connected to the row decoder circuit 113 via at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL. Each memory block may be coupled to the page buffer circuit 115 via a plurality of bit lines (BL). The plurality of memory blocks BLK1 to BLKz may be commonly connected to the plurality of bit lines BL. The memory cells of the plurality of memory blocks BLK1 to BLKz may have the same structures.

Illustratively, each of the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. The memory cells of the memory cell array 111 can be erased in units of one memory block. The memory cells belonging to one memory block can be erased simultaneously. As another example, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of subblocks may be a unit of an erase operation.

The row decoder circuit 113 is connected to the memory cell array 111 via a plurality of ground selection lines GSL, a plurality of word lines WL and a plurality of string selection lines SSL. The row decoder circuit 113 operates under the control of the control logic circuit 119. The row decoder circuit 113 decodes the address received from the controller 120 through the input and output channels and outputs the string selection lines SSL, word lines WL and ground selection lines GSL And the like.

The page buffer circuit 115 is connected to the memory cell array 111 through a plurality of bit lines BL. The page buffer circuit 115 is connected to the data input / output circuit 117 through a plurality of data lines DL. The page buffer circuit 115 operates under the control of the control logic circuit 119.

The data input / output circuit 117 is connected to the page buffer circuit 115 through a plurality of data lines DL. The data input / output circuit 117 outputs the data read by the page buffer circuit 115 to the controller 120 through the input / output channel and the data received from the controller 120 via the input / output channel to the page buffer circuit 115 .

The control logic circuit 119 may receive the command from the controller 120 via the input / output channel and receive the control signal via the control channel. The control logic circuit 119 receives the command received via the input / output channel in response to the control signal, routes the address received through the input / output channel to the row decoder circuit 113, and outputs the data received via the input / And can be routed to the data input / output circuit 117. The control logic circuit 119 may decode the received command and control the non-volatile memory device 110 in accordance with the decoded command.

22 is a circuit diagram showing a memory block BLKa according to an embodiment of the present invention. Referring to FIG. 22, the memory block BLKa includes a plurality of cell strings CS11, CS21, CS12, and CS22. The plurality of cell strings CS11, CS21, CS12, and CS22 may be arranged along a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 arranged along the row direction form the first row and the cell strings CS21 and CS22 arranged along the row direction form the first row, Two rows can be formed. The cell strings CS11 and CS21 arranged along the column direction form the first column and the cell strings CS12 and CS22 arranged along the column direction form the second column can do.

Each cell string may include a plurality of cell transistors. The plurality of cell transistors include ground selection transistors GST, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb. The ground selection transistor GST, the memory cells MC1 to MC6 and the string selection transistors SSTa and SSTb of each cell string are arranged such that the cell strings CS11, CS21, CS12 and CS22 are arranged along the rows and columns And may be stacked in a height direction perpendicular to the plane (for example, the plane on the substrate of the memory block BLKa).

The plurality of cell transistors may be charge trap type transistors having threshold voltages varying depending on the amount of charge trapped in the insulating film.

The sources of the lowermost ground selection transistors (GST) may be connected in common to the common source line (CSL).

The control gates of the ground selection transistors GST of the cell strings CS11 and CS12 of the first row are commonly connected to the ground selection line GSL1 and the control gates of the cell strings CS21 and CS22 of the second row The control gates of the selection transistors GST are connected in common to the ground selection line GSL2. That is, cell strings in different rows are connected to different ground selection lines.

The control gates of the memory cells located at the same height (or in sequence) from the substrate (or the ground selection transistors GST) are commonly connected to one word line, and the control gates of the memory cells located at different heights May be connected to different word lines WL1 to WL6, respectively. For example, the memory cells MC1 are commonly connected to the word line WL1. The memory cells MC2 are connected in common to the word line WL2. The memory cells MC3 are commonly connected to the word line WL3. The memory cells MC4 are connected in common to the word line WL4. The memory cells MC5 are commonly connected to the word line WL5. The memory cells MC6 are connected in common to the word line WL6.

Cell strings in different rows are connected to different string selection lines. The string select transistors of the same height (or sequence) of cell strings in the same row are connected to the same string select line. String selection transistors of different heights (or sequences) of cell strings in the same row are connected to different string selection lines.

The columns of the plurality of cell strings CS11, CS21, CS12, and CS22 are connected to different bit lines BL1 and BL2, respectively. For example, the string selection transistors SSTb of the cell strings CS11 and CS21 in the first column are connected in common to the bit line BL1. The string selection transistors SST of the cell strings CS12 and CS22 in the second column are connected in common to the bit line BL2.

As described above, the memory block BLKa is provided as a three-dimensional memory array. The three-dimensional memory array may be uniformly (or at least partially) coupled to one or more physical levels of arrays of memory cells MC1-MC6 having an active region disposed above a circuit associated with operation of the silicon substrate and the memory cells MC1- monolithically. The circuitry associated with the operation of the memory cells MC1 to MC6 may be located in or on the substrate. What is uniformly formed means that the layers of each level of the three-dimensional array are directly deposited on the lower-level layers of the three-dimensional array.

As an example according to the technical idea of the present invention, a three-dimensional memory array includes vertical NAND strings (or cell strings) having vertical directionality, and at least one memory cell is located on another memory cell. The at least one memory cell includes a charge trapping layer. Each vertical NAND string further comprises at least one selection transistor located above the memory cells MC1 - MC6. At least one selection transistor has the same structure as the memory cells MC1 to MC6 and is formed uniformly together with the memory cells MC1 to MC6.

A configuration in which the three-dimensional memory array is composed of a plurality of levels and the word lines or bit lines are shared between levels is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587 U.S. Patent No. 8,559,235, and U.S. Published Patent Application No. 2011/0233648, which are incorporated herein by reference.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

1000; Computing device
1100; Processor
1200; Random access memory
1300; Storage device
1400; modem
1500; User interface
110; Nonvolatile memory device
120; controller
111; The memory cell array
113; Row decoder circuit
115; Page buffer circuit
PFC; Pass-fail check circuit
117; Data input / output circuit
119; Control logic circuit

Claims (20)

A method of operating a storage device comprising a non-volatile memory device and a controller configured to control the non-volatile memory device, the method comprising:
The storage device transmitting map data to the host device mapping the physical addresses of the nonvolatile memory device and the logical addresses of the host device;
The storage device receiving a read request from the host device;
Reading data from the non-volatile memory device based on the physical address if the read request includes a physical address; And
Converting the logical address of the read request to a second physical address if the read request does not include the physical address and reading data from the nonvolatile memory device based on the second physical address Way. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
Upon power-on, the controller reading at least a portion of the map data from the non-volatile memory device and sending the at least a portion to the host. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller storing identifiers associated with blocks of the map data, and transmitting the stored identifiers to the host. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller receiving a map data request from the host device;
The controller collecting mapping information between the logical addresses and the physical addresses; And
And when the size of the collected information reaches a reference size, the controller transmits the collected information to the host device as the map data. 5. The method of claim 4,
Wherein the controller collects the information when the logical addresses and mapping information between the physical addresses are added or updated. 5. The method of claim 4,
Wherein the transmitting the map data to the host device comprises:
And after the map data is transmitted to the host device, the controller again receiving the map data request from the host device. 5. The method of claim 4,
And the controller writes the collected information to the nonvolatile memory device while the controller transmits the collected information to the host device as the map data. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller receiving a map data request from the host device;
The controller collecting mapping information between the logical addresses and the physical addresses; And
The controller periodically transmitting the collected information as the map data to the host device. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller receiving a map data request from the host device;
The controller collecting mapping information between the logical addresses and the physical addresses; And
And transmitting, by the controller, the collected information to the host device as the map data when there is no unprocessed request among the requests transmitted from the host device. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller receiving a map data request and a logical address from the host device;
The controller collecting information of the logical address and the mapped physical address; And
And the controller sending the collected information as the map data to the host device. The method according to claim 1,
The controller receiving a write request and data from the host device;
The controller writing the data to the nonvolatile memory device in response to the write request;
And if the data has been written to one continuous physical address range of the non-volatile memory device, the controller sends a write response to the host device including a starting physical address of the continuous physical address range How it works. 12. The method of claim 11,
If the data has been written to two or more contiguous physical address ranges of the non-volatile memory device, the controller sends a write response with the physical address excluded to the host device;
The controller receiving a map data request from the host device; And
The controller sending a start address of each of the two or more consecutive physical address ranges to the host device in response to the map data request. The method according to claim 1,
Reading the data from the nonvolatile memory device based on the physical address if the read request includes a physical address,
Generating a signature from a physical address and a logical address of the read request;
Reading data from the non-volatile memory device based on the physical address if the signature of the read request matches the generated signature. 14. The method of claim 13,
Converting the logical address of the read request into the second physical address if the signature of the read request and the generated signature do not match and reading data from the nonvolatile memory device based on the second physical address ≪ / RTI > The method according to claim 1,
Wherein the step of the storage device receiving a read request from the host device comprises:
Wherein when the data corresponding to the read request belongs to one continuous physical address range of the non-volatile memory device, the controller reads the read request including the starting physical address of the one continuous physical address range from the host device ; And
Wherein when the data corresponding to the read request belongs to two or more consecutive physical address ranges of the non-volatile memory device, the controller reads from the host device the read request excluding the physical address and the two or more consecutive physical address ranges ≪ / RTI > receiving a second request comprising the starting physical addresses of each of the plurality of physical addresses. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller generating signatures from logical addresses and physical addresses of the map data; And
The controller sending the signatures with the map data to the host device. The method according to claim 1,
Wherein the transmitting the map data to the host device comprises:
The controller encrypting at least the physical addresses of the map data; And
The controller transmitting the map data, which maps the encrypted physical addresses and the logical addresses, to the host device,
Wherein reading data from the nonvolatile memory device based on the physical address comprises:
The controller decrypting the physical address; And
And the controller reading data from the non-volatile memory device based on the decoded physical address. The method according to claim 1,
Further comprising defragmenting the controller such that the data stored in the non-volatile memory device and corresponding to consecutive logical addresses corresponds to consecutive physical addresses. A nonvolatile memory device; And
And a controller configured to control the nonvolatile memory device,
Wherein the controller is configured to transmit to the host device map data mapping the physical addresses of the nonvolatile memory device and the logical addresses of the host device,
Wherein the controller reads data from the nonvolatile memory device based on the physical address if the read request received from the host device includes a physical address associated with the map data, And read data from the non-volatile memory device based on the logical address of the read request if the physical address is not included. An access method for accessing a nonvolatile memory device and a storage device including the nonvolatile memory device, comprising:
Reading map data for mapping physical addresses and logical addresses of the nonvolatile memory device from the storage device;
Detecting a physical address mapped with the logical address from the map data if the logical address of the read object is associated with the map data and transmitting a read request including the physical address to the storage device; And
And if the logical address of the read object is not associated with the map data, sending a read request comprising the logical address to the storage device.

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