KR20170069761A - Transistor substrate and display device comprising the same - Google Patents

Abstract

The present invention relates to a transistor substrate and a display device including the transistor substrate.
According to the present invention, there is provided a semiconductor device including a transistor substrate including a transistor and a capacitor, wherein a capacitor of the transistor substrate includes a common wiring, a semiconductor layer, and a gate insulating film interposed between the common wiring and the semiconductor layer, And a gap is provided so that a part of light supplied from the backlight unit is provided to the semiconductor layer of the capacitor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a transistor substrate,

The present invention relates to a display device, and more particularly, to a display device including a transistor substrate in which transistors and capacitors are implemented.

As the display technology is developed, flat panel display devices are widely used. Examples of flat panel display devices include a liquid crystal display (OLED) device and an organic light emitting diode (OLED) display device. Of these, liquid crystal display devices are widely used in TVs, monitors, notebooks, and mobile phones because of their advantages of miniaturization, light weight, thinness, and low power driving.

The liquid crystal display device includes a panel portion and a backlight portion, and the panel portion is provided with a color filter substrate having a color filter (CF), a transistor substrate having a thin film transistor (TFT) And a liquid crystal layer interposed between the substrates.

1 shows an example of a conventional transistor substrate.

Referring to FIG. 1, a conventional transistor substrate is first arranged such that a gate wiring 110a and a common wiring (Vcom) 110b face each other on a transparent substrate such as a glass substrate.

The gate wiring 110a and the common wiring 110b are covered with a gate insulating film 120. [ A semiconductor layer 130a serving as an active layer is disposed on the gate insulating film and a portion of the common wiring 110b for implementing MIS (Metal Insulator Semiconductor) A semiconductor layer 130b serving as an electrode is disposed at an upper position of the semiconductor layer 130b. This semiconductor layer 130b is generally present under the drain layer under the 4-MASK process for transistor substrate fabrication.

 A source electrode of the transistor is disposed above a part of the semiconductor layer 130a. The source electrode becomes a part of the data line 140a. A drain electrode 140b is disposed on an upper portion of another portion of the semiconductor layer 130a and an upper portion of the semiconductor layer 130b.

The data line 140a and the drain electrode 140b are covered with the passivation layer 150. [ A photoacid layer 160 is disposed on the passivation layer 150.

The drain electrode 140b is connected to the pixel electrode 170. [ Holes for passing through the photoacryl layer 160 and the passivation layer 150 are formed for connection between the drain electrode 140b and the pixel electrode 170. [

2 shows another example of a conventional transistor substrate.

2, the gate wiring 110a, the common wiring 110b, the gate insulating film 120, the semiconductor layers 130a and 130b, the data wiring 140a, the drain electrode 140b, and the passivation layer 140b, (150) has a structure similar to that of the transistor substrate shown in FIG.

In the case of the transistor substrate shown in FIG. 2, the color filter layers 210 and 220 are disposed on the passivation layer 150, and correspond to a transistor substrate having a color filter on transistor (COT) structure.

FIG. 3 shows an example in which the gate wiring 110a, the common wiring 110b, the data wiring 140a, and the drain electrode 140b shown in FIGS. 1 and 2 are implemented.

A part of the data line 140a protrudes and overlaps with the gate line 110a and a part of the drain electrode 140b overlaps with the gate line 110b as shown in Fig.

A semiconductor layer is disposed under a part of the drain electrode 140b superimposed on the common wiring 110b, and a capacitor having a part of the common wiring 140b and a semiconductor layer as electrodes is implemented.

FIG. 4 shows an example of a capacitor that can be implemented in the transistor substrate shown in FIGS. 1 and 2. FIG.

Referring to FIG. 4, one capacitor A is implemented by the common wiring 110b, the gate insulating film 120, and the semiconductor layer 130b. Another capacitor B may be realized by the common electrode 180 connected to the drain electrode 140b, the photoacrylic layer / passivation layers 160 and 150 and the common line 110b.

However, in the case of the MIS capacitor including the common wiring 110b, the gate insulating film 120 and the semiconductor layer 130b under the drain electrode 140b, when a high-luminance backlight is applied, An inverse afterimage, which is an opposite pattern to the pattern, occurs. The inverse afterimage is a phenomenon in which a white area is observed darker than a black area. In the case of such an afterimage, there is almost no recovery even after long-term exposure after the afterimage test.

This inverse afterimage problem is caused by the fact that the number of electrons at the interface between the semiconductor layer and the gate insulating film of the MIS capacitor is low and the probability that holes exist at the interface between the semiconductor layer and the gate insulating film when the positive data signal is applied is low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a transistor substrate on which a MIS capacitor is implemented in which a problem of reverse image retention can be reduced.

It is another object of the present invention to provide a display device including a transistor substrate capable of reducing the afterimage problem.

According to an aspect of the present invention, there is provided a transistor substrate including a gate wiring, a common wiring, a gate insulating film, a semiconductor layer, a data wiring, and a drain electrode.

The gate wiring is disposed on the substrate along the first direction, and has a gate electrode. The common wiring is disposed on the substrate so as to face the gate wiring. The gate insulating film covers the gate wiring and the common wiring.

 A semiconductor layer is disposed at an upper portion overlapping the gate electrode and at an upper portion overlapped with the common wiring. The data wiring has a source electrode disposed along the second direction intersecting with the gate wiring and the common wiring, and overlapped with the gate electrode and the semiconductor layer. The drain electrode is disposed to be spaced apart from the source electrode, and overlaps the semiconductor layer and the common wiring. The drain electrode may be connected to the pixel electrode.

At this time, the common wiring has a gap in a part overlapping with the drain electrode.

The MIS capacitor is implemented in a portion where the common wiring and the drain electrode are overlapped. Due to the presence of a gap in a part of the common wiring, light provided in the backlight can be introduced into the semiconductor layer of the MIS capacitor.

The probability of holes being present at the interface between the semiconductor layer and the gate insulating film is increased and the probability of hole existence at the interface between the semiconductor layer and the gate insulating film is low, It is possible to reduce the problem of inverse image deterioration.

On the other hand, it is preferable that the width of the gap is 4 탆 or more. When the width of the gap is 4 탆 or more, sufficient light can be supplied to the semiconductor layer.

Further, the gap may be filled with a gate insulating film. In terms of the process, the gap is realized at the time of the common electrode arrangement, and in the arrangement of the gate insulating film, the gap can also be filled with the gate insulating film.

According to an aspect of the present invention, there is provided a transistor substrate including a first metal layer (gate metal layer) defining a gate wiring and a common wiring, a gate insulating film covering the first metal layer, A semiconductor layer defining an active layer; and a second metal layer (source / drain metal layer) disposed on the semiconductor layer and defining a data line and a drain electrode.

At this time, a portion where the common wiring and the semiconductor layer face each other with the gate insulating film therebetween defines a capacitor, and a gap is provided in the common wiring facing the semiconductor layer.

In the four-mask application manufacturing process, a gate metal layer defining a gate wiring and a common wiring is disposed by one mask, and a source / drain metal layer defining a data wiring and a drain electrode including a source electrode by another mask Layer. At this time, a MIS capacitor is implemented in a specific portion of the gate metal layer and the source / drain metal layer.

At this time, since the gap exists in the common wiring facing the semiconductor layer, the light provided in the backlight can flow into the semiconductor layer of the MIS capacitor, thereby increasing the probability of existence of holes at the interface between the semiconductor layer and the gate insulating film And it is possible to reduce the occurrence of the afterimage.

On the other hand, the width of the gap is preferably 4 탆 or more. When the width of the gap is 4 mu m or more, sufficient light can be supplied to the semiconductor layer of the MIS capacitor.

Further, the gap may be filled with a gate insulating film. When the gate insulating layer is disposed on the gate metal layer, the gap may also be filled with the gate insulating layer.

According to an aspect of the present invention, there is provided a display device including a backlight unit for providing light to a front surface, and a transistor substrate disposed on a front surface of the backlight unit, the transistor substrate including a transistor and a capacitor.

In this case, the capacitor of the transistor substrate includes a common wiring, a semiconductor layer, and a gate insulating film interposed between the common wiring and the semiconductor layer, wherein a gap is provided in a part of the common wiring so that a part of light supplied from the backlight unit, Is provided on the semiconductor layer.

The light provided in the backlight can be introduced into the semiconductor layer of the MIS capacitor due to the presence of a gap in a part of the common wiring in the region where the MIS capacitor of the transistor substrate is realized. It is possible to increase the degree of mobility of holes by the introduced light. As a result, the probability that a hole exists at the interface between the semiconductor layer and the gate insulating film increases, and the problem of inverse image retention can be reduced.

According to the display device of the present invention, a part of the light supplied from the backlight unit can be provided to the semiconductor layer of the capacitor region of the transistor substrate.

This increases the probability that a hole is present at the interface between the semiconductor layer and the gate insulating film, thereby reducing the problem of inverse image retention caused by a low probability of hole presence at the interface between the semiconductor layer and the gate insulating film.

In addition, in the case of the transistor substrate according to the present invention, since there is a gap in a part of the drain electrode, a kind of parallel structure can be provided, and as a result, an additional effect of reducing the resistance can be obtained.

1 shows an example of a conventional transistor substrate.
2 shows another example of a conventional transistor substrate.
2 is a schematic view of a conventional curved liquid crystal display panel.
FIG. 3 shows an example in which the gate wiring, the common wiring, the data wiring and the drain electrode shown in FIGS. 1 and 2 are implemented.
FIG. 4 shows an example of a capacitor that can be implemented in the transistor substrate shown in FIGS. 1 and 2. FIG.
5A shows a portion of a transistor substrate according to an embodiment of the present invention, in which gate wirings, common wirings, data wirings, and drain electrodes are implemented.
Fig. 5B is an enlarged view of a portion of the gate wiring and the common wiring in Fig. 5A.
6 illustrates an example of a transistor and a MIS capacitor implemented in a transistor substrate according to the present invention.
FIG. 7 shows the distribution of electrons and holes in a conventional MIS capacitor implemented in a transistor substrate when a positive data signal is applied (a) and a negative data signal is applied (b).
8 shows the degree of shift of the capacitor value under the high-temperature and high-luminance backlight of the MIS capacitor having the structure shown in FIG.
9 shows distributions of electrons and holes in the MIS capacitor implemented in the transistor substrate according to the embodiment of the present invention when the positive data signal is applied (a) and when the negative data signal is applied (b).
10 shows the degree of shift of the capacitor value under the high-temperature and high-luminance backlight of the MIS capacitor having the structure shown in FIG.

Hereinafter, various embodiments of a transistor substrate and a display device including the transistor substrate according to the present invention will be described with reference to the drawings.

The terms including ordinals such as first, second, etc. in the following can be used to describe various elements, but the constituent elements are not limited by such terms. These terms are used only to distinguish one component from another.

Also, in the present invention, the expression " is in a state of being in contact with another part "means not only" in which part is in contact with another part, On top of other parts in the state of being further formed in the middle ".

FIG. 5A shows a part of a transistor substrate according to an embodiment of the present invention, in which an example of a gate wiring, a common wiring, a data wiring and a drain electrode is realized, and FIG. 5B is a cross- FIG. 6 illustrates an example in which a transistor and a MIS capacitor are implemented in the transistor substrate according to the present invention.

5A, 5B and 6, a transistor substrate according to the present invention includes a gate wiring 110a, a common wiring 110b, a gate insulating film 120, semiconductor layers 130a and 130b, a data wiring 140a, And a drain electrode 150.

The gate wiring 110a is disposed on the substrate 101 along the first direction, and a part of the gate wiring 110a becomes a gate electrode.

The common wiring 110a is disposed on the substrate 101 so as to face the gate wiring 110a.

The gate insulating film 120 covers the gate wiring 110a and the common wiring 110b.

The semiconductor layer 130a overlies the gate electrode of the gate line 110a and is disposed on the upper portion and serves as a channel between the source and the drain, that is, an active layer. In the manufacturing process using the 4-mask, the semiconductor layer 130b is also disposed on the upper portion overlapping the common wiring.

The data wiring 140a is disposed along the second direction crossing the gate wiring 110a and the common wiring 110b. A portion of the data line 140a that is partially protruded overlaps with the gate electrode of the gate line 110a and a part of the semiconductor layer 130a, and this portion becomes the source electrode.

The drain electrode 140b is disposed to be spaced apart from the source electrode and overlapped with another portion of the semiconductor layer 130a. The drain electrode 140b is also disposed on the common wiring 110b and also on the semiconductor layer 130b disposed on the common wiring 110b.

A photo-acryl layer 160 is disposed on the data line 140a and the drain electrode 140b. Unlike the example shown in Fig. 6, the data wiring 140a and the drain electrode 140b may be covered with the passivation layer, and the photo-acrylic layer 160 may be disposed on the passivation layer.

The drain electrode 140b is connected to the pixel electrode 170. [ Holes for passing through the photoacryl layer 160 are formed for connection between the drain electrode 140b and the pixel electrode 170. [ Further, the common wiring 110b may be connected to a common electrode which is alternately disposed apart from the pixel electrode.

In the case of the transistor substrate shown in Fig. 6, a separate color filter substrate is required. As another example, as in the example shown in Fig. 2, a color filter on transistor (COT) structure in which a color filter is implemented on a transistor substrate is also applicable to the present invention.

Meanwhile, in the case of the transistor substrate according to the present invention, a gap 510 is provided in a part of the common wiring 110b. The portion where the gap 510 is provided may include a portion overlapping with the drain electrode 140b, that is, a portion where the MIS capacitor is implemented.

The gap 510 is provided in one or a plurality of portions on the common wiring 110b where the MIS capacitor is implemented. In addition, the gap 510 may be provided in other portions in addition to the common wiring portion in which the MIS capacitor is implemented, as the case may be.

An MIS capacitor is implemented in a portion where the common wiring 110b and the drain electrode 140b overlap. Considering only the MIS capacitor structure, one or more holes are formed in the metal electrode.

The light provided in the backlight can be introduced into the semiconductor layer 130b of the MIS capacitor due to the presence of the gap 510 in a part of the common wiring 110b. It is possible to increase the degree of mobility of the hole in the direction of the gate insulating film 120 at a portion adjacent to the drain electrode 140b by the incident light and thus a hole exists at the interface between the semiconductor layer 130b and the gate insulating film 120 Probability increases.

As a result, it is possible to reduce the problem of inverse image retention caused by a low possibility of holes at the interface between the semiconductor layer 130b and the gate insulating film 120. [

On the other hand, the width d of the gap 510 is preferably 4 탆 or more, more preferably 4 to 20 탆. When the width of the gap 510 is 4 占 퐉 or more, sufficient light can be supplied to the semiconductor layer.

Further, referring to FIG. 6, the gap 51 may be filled with the gate insulating film 120. The gap 510 may be filled with the gate insulating film 120 in the arrangement of the gate insulating film which is performed after the placement of the common electrode 110b have.

On the other hand, considering the manufacturing process using the 4-mask, the transistor substrate according to the present invention may include a first metal layer (gate metal layer), a gate insulating film, a semiconductor layer, and a second metal layer (source / drain metal layer) .

The first metal layer (gate metal layer) defines the gate wiring 110a and the common wiring 110b. The first metal layer may be disposed using a first mask, for example, through a sputtering process, a photolithography process, a wet etching process, and a photoresist removal process.

The gate insulating film 120 covers the first metal layer. The gate insulating layer 120 may be disposed, for example, by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

The semiconductor layers 130a and 130b are disposed on the gate insulating film 120 and define the active layer of the transistor and the semiconductor electrode of the MIS capacitor. The semiconductor layers 130a and 130b may be made of, for example, polysilicon. The semiconductor layers 130a and 130b may be disposed on the gate insulating layer 120 through a PECVD process in the same manner as the gate insulating layer 120 is.

The second metal layer (source / drain metal layer) is disposed on the resulting semiconductor layer 130a, 130b using a second mask. The data line 140a and the drain electrode 140b can be defined by the second metal layer (source / drain metal layer). The arrangement of the second metal layer (source / drain metal layer) can be arranged through, for example, a sputtering process, a photolithography process, a wet etching process, and a photoresist removing process in the same manner as the first metal layer (gate metal layer) arrangement.

Through the third mask, the photoacryl layer 160 may be disposed, for example, through a coating process, a photolithography process, a dry etching process, and a photoresist removing process.

A pixel electrode and a common electrode for implementing the pixel may be disposed through the fourth mask. The pixel electrode and the common electrode may be disposed through, for example, a sputtering process, a photolithography process, a wet etching process, and a photoresist removing process.

On the other hand, in the present invention, a portion where the common wiring 110b and the semiconductor layer 130b face each other with the gate insulating film 120 therebetween defines a capacitor. At this time, a gap 510 is formed in the common wiring 110b facing the semiconductor layer 130b.

As in the foregoing example, in the four-mask application manufacturing process, a gate metal layer defining the gate wiring 110a and the common wiring 110b is disposed on the substrate by one mask. A source / drain metal layer defining the data line 140a and the drain electrode 140b including the source electrode is disposed on the gate insulating film and the semiconductor layer by the other mask.

 At this time, a MIS capacitor is implemented in a specific portion of the gate metal layer and the source / drain metal layer. In the present invention, there is a gap in the portion of the common wiring 110b facing the semiconductor layer 130b at the portion where the MIS capacitor is implemented. This allows the light provided in the backlight to flow into the semiconductor layer of the MIS capacitor, thereby increasing the probability that holes are present at the interface between the semiconductor layer and the gate insulating film, thereby reducing the occurrence of the afterglow.

The gate line 110a and the common line 110b may be made of a metal material and the pixel electrode 170 and the common electrode 180 may be made of a transparent conductive oxide (TCO) material such as ITO.

As described above, the width of the gap 510 is preferably 4 mu m or more. Also, the gap 510 may be filled with the gate insulating film 120.

FIG. 7 shows the distribution of electrons and holes in a conventional MIS capacitor implemented in a transistor substrate when a positive data signal is applied (a) and a negative data signal is applied (b). 8 shows the degree of shift of the capacitor value under the high temperature and high brightness backlight of the MIS capacitor having the structure shown in FIG.

9 shows distributions of electrons and holes in the MIS capacitor implemented in the transistor substrate according to the embodiment of the present invention when the positive data signal is applied (a) and when the negative data signal is applied (b). 10 shows the degree of shift of the capacitor value under the high-temperature and high-luminance backlight of the MIS capacitor having the structure shown in FIG.

7 and 9 have a MIS capacitor structure including a gate metal layer 710, a gate insulating film 720, a semiconductor layer 730, and a drain metal layer 740 from below. 9, a gap 715 is provided in the gate metal layer 710. [

Referring to FIGS. 7 and 9, the application of a negative data signal can be performed by using an electron hole distribution in a capacitor of a conventional transistor substrate (FIG. 7 (b)) and an electron and hole distribution 9 (b)) exhibited a similar tendency.

However, the application of the positive data signal is different from that of the first embodiment.

That is, referring to the electron hole distribution (FIG. 7A) in the capacitor of the conventional transistor substrate, the probability that holes exist at the interface between the semiconductor layer 730 and the gate insulating film 720 is not high.

9A), the probability that a hole exists at the interface between the semiconductor layer 730 and the gate insulating film 720 in the case of applying a positive data signal (refer to FIG. 9A) Is high.

The increase in the probability that a hole exists at the interface between the semiconductor layer 730 and the gate insulating film 720 can be regarded as a result of the light supplied from the lower backlight being introduced into the semiconductor layer 730 due to the presence of the gap 715.

8 and 10, in the case of the capacitor implemented in the conventional transistor substrate, the degree of positive shift (FIG. 8) is relatively large. However, in the case of the capacitor implemented in the transistor substrate of the present invention, The degree of positive shift (FIG. 10) is relatively small due to the presence of the catalyst.

According to these results, in the case of the transistor substrate according to the present invention, it is possible to contribute to reduction of inverse afterimage.

Meanwhile, the display device according to the present invention includes a backlight unit for providing light to the front surface and the above-described transistor substrate. The display device according to the present invention may include various known elements such as a cover top, a guide panel, a bottom cover, etc. without limitation. Further, when the display device according to the present invention is a liquid crystal display device, a liquid crystal layer and a color filter substrate (color filter layer in the case of a COT structure) are included.

In the display device, the transistor substrate is disposed on the front surface of the backlight unit. The transistor substrate is provided with a transistor and a capacitor as described above.

At this time, the capacitor of the transistor substrate according to the present invention includes a common wiring, a semiconductor layer, and a gate insulating film interposed between the common wiring and the semiconductor layer. In particular, in the present invention, a gap is provided in a part of the common wiring of the capacitor region so that a part of the light supplied from the backlight unit is provided to the semiconductor layer of the capacitor.

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is therefore to be understood that such changes and modifications are intended to be included within the scope of the present invention unless they depart from the scope of the present invention.

101: substrate 110a: gate wiring
110b: common wiring 120: gate insulating film
130a, 130b: semiconductor layer 140a: data wiring
140b: gate electrode 150: passivation layer
160: Photo acrylic layer 170: Pixel electrode
180: common electrode 210, 220: color filter
510: gap 710: gate metal layer
715: gap 720: gate insulating film
730: semiconductor layer 740: drain metal layer

Claims (7)

A gate wiring disposed on the substrate along the first direction and having a gate electrode;
A common wiring disposed on the substrate so as to face the gate wiring;
A gate insulating film covering the gate wiring and the common wiring;
An upper portion overlapping the gate electrode, and a semiconductor layer disposed on the upper portion overlapping the common wiring;
A data line disposed along a second direction crossing the gate line and the common line and having a source electrode overlapped with the gate electrode and the semiconductor layer; And
And a drain electrode spaced apart from the source electrode and arranged to overlap the semiconductor layer and the common wiring,
And the common wiring has a gap in a part overlapping with the drain electrode.
The method according to claim 1,
And the width of the gap is 4 占 퐉 or more.
The method according to claim 1,
And the gap is filled with the gate insulating film.
A first metal layer defining a gate wiring and a common wiring;
A gate insulating layer covering the first metal layer;
A semiconductor layer disposed on the gate insulating film and defining an active layer;
A second metal layer disposed on the semiconductor layer and defining a data line and a drain electrode,
A portion where the common wiring and the semiconductor layer face each other with a gate insulating film therebetween defines a capacitor, and a gap is provided in a common wiring facing the semiconductor layer.
5. The method of claim 4,
And the width of the gap is 4 占 퐉 or more.
5. The method of claim 4,
And the gap is filled with the gate insulating film.
A backlight unit for providing light to the front surface; And
And a transistor substrate disposed on the front surface of the backlight unit and having a transistor and a capacitor,
Wherein a capacitor of the transistor substrate includes a common wiring, a semiconductor layer, and a gate insulating film interposed between the common wiring and the semiconductor layer, wherein a gap is provided in a part of the common wiring, and a part of light supplied from the backlight unit is electrically connected to the semiconductor Layer. ≪ / RTI >

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