KR20170067509A - Multi bit capacitorless dram and manufacturing method thereof - Google Patents
Multi bit capacitorless dram and manufacturing method thereof Download PDFInfo
- Publication number
- KR20170067509A KR20170067509A KR1020150174252A KR20150174252A KR20170067509A KR 20170067509 A KR20170067509 A KR 20170067509A KR 1020150174252 A KR1020150174252 A KR 1020150174252A KR 20150174252 A KR20150174252 A KR 20150174252A KR 20170067509 A KR20170067509 A KR 20170067509A
- Authority
- KR
- South Korea
- Prior art keywords
- nanowire
- nanowire channels
- substrate
- channels
- capacitorless dram
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000002070 nanowire Substances 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 9
- 230000001681 protective effect Effects 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000015654 memory Effects 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 239000011777 magnesium Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 239000004341 Octafluorocyclobutane Substances 0.000 description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 3
- 235000019407 octafluorocyclobutane Nutrition 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 238000003917 TEM image Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 206010017577 Gait disturbance Diseases 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- CEAKTVBWPSRRNH-UHFFFAOYSA-N lanthanum(3+) oxygen(2-) Chemical compound [O-2].[La+3].[O-2].[La+3] CEAKTVBWPSRRNH-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H01L27/10802—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
-
- H01L27/10817—
-
- H01L27/10844—
-
- H01L27/1085—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
A multi-bit capacitorless DRAM according to the present invention includes a substrate, a source and a drain formed on the substrate, a plurality of nanowire channels formed on the substrate, a gate insulating film formed on the plurality of nanowire channels, and a gate formed on the gate insulating film. Wherein at least two of the plurality of nanowire channels have different threshold voltages. Thus, according to the capacitorless DRAM and the method of manufacturing the same according to the present invention having the above-described structure, it is possible to realize a highly integrated multi-bit capacitorless DRAM that can operate in multiple bits.
Description
The present invention relates to a capacitorless DRAM, and more particularly, to a capacitorless DRAM capable of multi-bit implementation and a method of manufacturing the same.
Dynamic random access memory (DRAM), which is one of semiconductor components that is essential for computing, consists of one transistor and one capacitor. However, since the size of the conventional DRAM must be reduced along with the size of the device, it has been considered difficult to secure a capacitor having a sufficiently large capacity. In addition, the capacitor forming process is a stumbling block due to the high step difference of the capacitor when the embedded chip is formed together with other devices. Accordingly, a capacitorless DRAM capable of storing data without a capacitor causing a complicated process is attracting attention. Since the capacitorless DRAM is not used, it has a great advantage in terms of integration and fabrication cost as compared with the conventional DRAM.
1A is a cross-sectional view schematically showing the operation principle of a conventional capacitorless DRAM, and FIG. 1B is an energy band diagram of a conventional capacitorless DRAM. The capacitorless DRAM is fabricated using a silicon-on-insulator (SOI) substrate or a general silicon substrate and a floating body device. When a predetermined voltage is applied to the
A state in which holes are accumulated in the
SUMMARY OF THE INVENTION The present invention is directed to a conventional capacitorless DRAM that operates only in a single bit, and it is an object of the present invention to provide a multi-bit capacitorless DRAM having a higher integration density than conventional capacitorless DRAMs and a method of manufacturing the same.
According to an aspect of the present invention, there is provided a multi-bit capacitorless DRAM comprising: a substrate; A source and a drain formed on the substrate; A plurality of nanowire channels formed on the substrate; A gate insulating layer formed on the plurality of nanowire channels; And a gate formed on the gate insulator, wherein at least two of the plurality of nanowire channels have different threshold voltages.
Further, the two or more nanowire channels may have different threshold voltages by changing at least one of the type, the depth, the concentration, and the angle of the doping ions.
The two or more nanowire channels may have different threshold voltages by changing the shape or area of the cross section.
In addition, the two or more nanowire channels may have different cross-sectional shapes or areas by etching at least one of different types of etch materials, concentration of etch materials, etch time, vacuum degree, and etch temperature.
A controller for controlling the operation of the capacitorless DRAM; And a storage unit for storing a driving voltage for each of the plurality of nanowire channels based on a threshold voltage of the plurality of nanowire channels.
The controller may program or erase data of two or more bits by controlling a driving voltage applied to at least one of the gate and the drain.
According to another aspect of the present invention, there is provided a method of manufacturing a multi-bit capacitorless DRAM, including: (a) depositing a hard mask on a substrate; (b) etching at least a portion of the hard mask; (c) patterning the nanowire on the substrate through an anisotropic etch; (d) forming a protective film on the substrate; (e) forming a nanowire channel in the substrate through isotropic etching; (f) repeating the steps (c) and (e) to form a plurality of nanowire channels; And (g) forming a source, a drain, and a gate, wherein (f) processes each of the plurality of nanowire channels to be formed to have different threshold voltages.
In the step (f), each time the nanowire channel is formed, a dopant is injected by varying at least one of the kind, the depth, the concentration, and the implantation angle of the doping ions, Can be processed to have different threshold voltages.
In the step (f), each of the plurality of nanowire channels is formed by varying at least one of an etching material type, an etching material concentration, an etching time, a vacuum degree, and an etching temperature, Each can be processed to have a different threshold voltage.
The method may further include forming a gate insulating film on the substrate before the step (g).
According to the multi-bit capacitorless DRAM and the method of manufacturing the same according to the present invention having the above-described structure, it is possible to implement a highly integrated DRAM capable of operating in multiple bits.
1A is a cross-sectional view schematically showing the operation principle of a conventional capacitorless DRAM.
1B is an energy band diagram of a conventional capacitorless DRAM.
2A is a perspective view of a multi-bit capacitorless DRAM according to the present invention.
2B is a cross-sectional view of the multi-bit capacitorless DRAM taken along line A-A 'in FIG. 2A.
FIG. 3 is a cross-sectional view of a multi-bit capacitorless DRAM taken along the line B-B 'in FIG. 2A, illustrating a phenomenon of ionization collision.
4 is a perspective view illustrating a main configuration of a multi-bit capacitorless DRAM according to the present invention.
FIGS. 5A through 5E are diagrams illustrating steps of forming a plurality of nanowires in a multi-bit capacitorless DRAM according to the present invention.
6A through 6C are diagrams illustrating steps of forming a plurality of nanowires in a multi-bit capacitorless DRAM according to the present invention.
7A and 7B are diagrams showing only a plurality of formed nanowire channels in a highlighted state.
8A and 8B are transmission electron micrographs of a nanowire channel having different shapes or areas in a multi-bit capacitorless DRAM according to the present invention.
9A and 9B are graphs showing the operating voltage range of a multi-bit capacitorless DRAM according to the present invention.
10A is a block diagram illustrating a configuration of an apparatus for measuring the operation of a multi-bit capacitorless DRAM according to the present invention.
FIGS. 10B and 10C are diagrams showing pulse voltages of input operating voltages in the respective operation regions. FIG.
11A is a graph showing measured data in which the current value of the first operating region is outputted by the pulse-type operating voltage shown in FIG. 10B.
FIG. 11B is a graph showing measured data in which the current value of the second operating region is output by the pulse-type operating voltage shown in FIG. 10C. FIG.
12 is a flowchart illustrating a method of manufacturing a multi-bit capacitorless DRAM according to an embodiment of the present invention.
The following description of the invention refers to the accompanying drawings which illustrate, by way of example, specific embodiments that may be practiced. The described embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.
The multi-bit capacitorless DRAM according to the present invention includes two or more channel regions. The two or more channel regions may be formed of nanowires, and two or more nanowire channels may be formed with different intrinsic threshold voltages by different ion implantation processes or by different etching processes. Since two or more nanowire channels have different threshold voltages, they have their own operating voltages that cause a collision ionization phenomenon.
FIG. 2A is a perspective view of a multi-bit capacitorless DRAM according to the present invention, and FIG. 2B is a cross-sectional view of a capacitorless DRAM taken along line A-A 'in FIG. 2A. Particularly, FIG. 2B further shows the structure of the
The multi-bit capacitorless DRAM according to the present invention includes a
The
The
The
Furthermore, the
Before describing the material, the structure, and the formation method thereof with respect to the plurality of
FIG. 3 is a cross-sectional view of the capacitorless DRAM taken along the line B-B 'in FIG. 2A, illustrating the ionization collision phenomenon.
First, the
When the voltage corresponding to the first driving voltage region is applied to the
On the other hand, the
At this time, the first threshold voltage and the second threshold voltage may be different from each other, whereby the first driving voltage region and the second driving voltage region are different. To make the first and second threshold voltages have different values, the following scheme can be used.
(1) In forming a plurality of nanowire channels, different threshold voltages may be obtained by varying at least one of the kind, depth, concentration, and angle of the doping ions.
(2) When forming a plurality of nanowire channels, different threshold voltages may be obtained by changing shapes or areas of respective cross sections. At this time, in each nanowire channel forming step, by changing at least one of the kind of the etching material, the concentration of the etching material, the etching time, the degree of vacuum and the etching temperature, the shape (triangle, circle, rhombus, Can be made different.
The
Control of the intrinsic operating voltage of each of the
Hereinafter, with reference to FIGS. 4, 5A to 5E, and 6A to 6C, a method of forming a plurality of nanowire channels in a multi-bit capacitorless DRAM according to the present invention will be described.
4 is a perspective view illustrating a main configuration of a multi-bit capacitorless DRAM according to the present invention. As shown in FIG. 4, the multi-bit capacitorless DRAM according to the present invention may have a plurality of
First, a
In this embodiment, for convenience of explanation, it is assumed that a p-
When the
Then, the
As a next step, isotropic etching is used to form a separate nanowire channel with the
FIGS. 6A through 6C illustrate a process of forming a plurality of nanowire channels by forming another nanowire channel below the
As shown in FIG. 6A, after the
Next, as shown in FIG. 6B, a
The following description will briefly describe a process in which a plurality of
Thereafter, a patterned photoresist film is formed to remove regions where the
At this time, the step of removing the photoresist layer, controlling the size of the cross section of the
The
Meanwhile, the gate layer may be made of metal or polysilicon. That is, the gate layer is formed of a metal such as polysilicon, aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum (Pt) Materials, but are not limited thereto.
Then, the region to be removed from the silicon oxide and the gate layer is a region where the source and the drain are to be formed, and accordingly, appropriate patterning is performed in consideration of this. A
Thereafter, a heavily doped n + type impurity ion (
At this time, instead of using a high-concentration n-type ion (
The processes after forming the plurality of
Figures 7A and 7B show only a plurality of
Although FIG. 7B shows a plurality of
For example, in the etching step during the process of forming the plurality of
8A and 8B are transmission electron micrographs of
Although Figures 8A and 8B illustrate nanowire channels having different shapes or areas, in other embodiments, the threshold voltages of each nanowire channel can be made different by different ways. In FIG. 8B, a
For example, when forming a nanowire channel, the threshold voltage of each nanowire channel can be made different by varying at least one of the type, depth, concentration, and angle of ions doped in each nanowire channel.
9A and 9B are graphs showing the operating voltage range of a multi-bit capacitorless DRAM according to the present invention. Assuming two nanowire channels, four regions of the '00' state, the '01' state, the '10' state, and the '11' state can be used as memories.
9A and 9B, when the difference in magnitude of the current between the '00' state and the '01' state is used as a memory, this is referred to as a 'first operation region' Is used as a memory, this is referred to as a " second operation area ".
As shown in Figure 9a, the DRAM in order to '11' in the program (PROGRAM) the state of the initial state, so that the V PROGRAM2 operating region corresponding to the drain voltage (V D) is used, and the initial state of the DRAM 01 ', The drain voltage (V D ) of V PROGRAM1 is used. Accordingly, the number of bits usable in the multi-bit capacitorless DRAM according to the present invention is two, and when the number of bits is increased and the number of the nanowire channels is increased, the memory operates as a memory capable of storing a larger number of bits . 9B shows actual data representing the drain voltage region measured from the actually fabricated device. The drain voltage V D for programming into the '11' state is about 5.5 V and the drain voltage for programming into the '01' state V D ) becomes approximately 5V. However, it should be apparent to those skilled in the art that the drain voltage (V D ) is not limited thereto, but may be varied depending on other factors such as the length, width, insulating film thickness, and the like of the nanowire channel.
A controller (not shown) for controlling the operation of the multi-bit capacitorless DRAM according to the present invention, and a storage unit (not shown) for storing a driving voltage for each of the plurality of nanowire channels. At this time, the driving voltage for each of the nanowire channels is based on the threshold voltage inherent to each channel as described above.
9A and 9B, a controller (not shown) controls the driving voltage applied to the
FIG. 10A is a block diagram showing a configuration of an apparatus for measuring the operation of a multi-bit capacitorless DRAM according to the present invention. FIGS. 10B and 10C are diagrams showing, in each operation region (first operation region and second operation region) In pulse form.
The pulsed operation voltage input to the
The state where the output current I S is relatively high is a program state, and the state where the output current is relatively low is an erase state.
The pulsed operating voltage input in the case of the first operating region is as shown in FIG. 10B. In order to program the multi-bit capacitorless DRAM according to the present invention into the '01' state, a drain voltage (V D ) of V PROGRAM1 of FIG. 9A is applied to the
On the other hand, the pulse-type operating voltage input in the case of the second operation region is as shown in FIG. In order to program the capacitor-less dynamic random access memory according to the present invention the "11" state, the
11A shows actual data in which the current value of the first operating region is output by the pulse-type operating voltage shown in FIG. 10B. That is, when the drain voltage (V D ) of the V PROGRAM 1 is input to the
FIG. 11B shows actual data for which the current value of the second operating region is output by the pulse-type operating voltage shown in FIG. 10C. That is, when the drain voltage V D of V PROGRAM 2 is input to the
As described above, according to the multi-bit capacitorless DRAM and the method of manufacturing the same according to the present invention, unlike a conventional memory that can store (process) only a single bit, it can operate with multiple bits of two or more bits, Not only improvement but also high integration can be achieved.
Finally, a method of manufacturing a multi-bit capacitorless DRAM according to the present invention will be described with reference to FIG.
First, a hard mask is deposited on the substrate (S200). Subsequently, at least a part of the hard mask is etched (S210), before the patterning process of the photoresist film can be performed.
Thereafter, an anisotropic etching is performed to form a region to be a nanowire channel, and then a passivation layer is formed (S220, S230).
At this time, chlorine (Cl 2 ) gas may be used for the anisotropic etching. The protective film may be a polymer-based C x F y gas, and may be octafluorocyclobutane (C 4 F 8 ), which is one of them. However, the material used as a gas or a protective film used for anisotropic etching is not limited to the above-mentioned materials.
As a next step, an isotropic etching is used to form a nanowire channel separated from the substrate (S240). In this manner, a plurality of nanowire channels are formed (S230) while repeating the processes of nanowire patterning (S220), protective film formation (S230), and nanowire channel formation (S240) using anisotropic etching.
At this time, the plurality of nanowire channels to be formed may each have a different threshold voltage.
In one embodiment, each time the nanowire channel is formed, dopants may be implanted with different dopant species, depth, concentration, and / or implantation angle to provide different threshold voltages. In another embodiment, each time a nanowire channel is formed, it may be possible to have a different threshold voltage, by varying at least one of the type of etchant material, the etchant concentration, the etch time, the degree of vacuum, and the etch temperature will be.
The features, structures, effects and the like described in the embodiments are included in one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Accordingly, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
100 ......... substrate
101 ... insulating film
102 ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ gate
103 ‥‥‥‥‥ Source
104 ‥‥‥‥‥‥‥ drain
105 ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ Nanowire channel
106 ......... STI oxide layer
Claims (9)
A source and a drain formed on the substrate;
A plurality of nanowire channels formed on the substrate;
A gate insulating layer formed on the plurality of nanowire channels; And
And a gate formed on the gate insulating film,
Wherein at least two of the plurality of nanowire channels have different threshold voltages.
Wherein the two or more nanowire channels have different threshold voltages by differentiating at least one of the type, depth, concentration, and angle of the doping ions.
Wherein the two or more nanowire channels have different threshold voltages by different shapes or areas of cross-section.
Wherein the two or more nanowire channels are etched differently in at least one of the type of etchant material, the concentration of the etchant material, the etch time, the degree of vacuum, and the etch temperature, thereby having different cross-sectional shapes or areas.
A controller for controlling operation of the multi-bit capacitorless DRAM; And
Further comprising a storage for storing a driving voltage for each of the plurality of nanowire channels based on a threshold voltage of the plurality of nanowire channels,
The controller controls a driving voltage applied to at least one of the gate and the drain to program or erase data of two or more bits.
(b) etching at least a portion of the hard mask;
(c) patterning the nanowire on the substrate through an anisotropic etch;
(d) forming a protective film on the substrate;
(e) forming a nanowire channel in the substrate through isotropic etching;
(f) repeating the steps (c) and (e) to form a plurality of nanowire channels;
(g) forming a source, a drain, and a gate,
Wherein the step (f) processes each of the plurality of nanowire channels to be formed such that each of the plurality of nanowire channels has a different threshold voltage.
The step (f)
Each time a nanowire channel is formed, a dopant is implanted at least one of a type, a depth, a concentration, and an implant angle of doping ions, so that each of the plurality of nanowire channels is processed to have a different threshold voltage A method of manufacturing a capacitorless DRAM.
The step (f)
Treating each of the plurality of nanowire channels to have a different threshold voltage by varying at least one of the type of etchant material, the concentration of the etchant material, the etch time, the degree of vacuum, and the etch temperature each time the respective nanowire channel is formed A method of manufacturing a multi - bit capacitorless DRAM.
And forming a gate insulating film on the substrate prior to the step (g).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150174252A KR101835612B1 (en) | 2015-12-08 | 2015-12-08 | Multi bit capacitorless dram and manufacturing method thereof |
US15/044,702 US9728539B2 (en) | 2015-12-08 | 2016-02-16 | Multi bit capacitorless DRAM and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150174252A KR101835612B1 (en) | 2015-12-08 | 2015-12-08 | Multi bit capacitorless dram and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20170067509A true KR20170067509A (en) | 2017-06-16 |
KR101835612B1 KR101835612B1 (en) | 2018-03-08 |
Family
ID=59278694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020150174252A KR101835612B1 (en) | 2015-12-08 | 2015-12-08 | Multi bit capacitorless dram and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101835612B1 (en) |
-
2015
- 2015-12-08 KR KR1020150174252A patent/KR101835612B1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR101835612B1 (en) | 2018-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9728539B2 (en) | Multi bit capacitorless DRAM and manufacturing method thereof | |
US9318388B2 (en) | Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices | |
US8507973B2 (en) | Non-volatile memory device and method for fabricating the same | |
US7317230B2 (en) | Fin FET structure | |
KR101670596B1 (en) | Memory device and method for fabricating the same | |
US9142651B1 (en) | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device | |
US9064890B1 (en) | Methods of forming isolation material on FinFET semiconductor devices and the resulting devices | |
US20060249779A1 (en) | Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same | |
US8283716B2 (en) | High performance flash memory devices | |
KR20080010900A (en) | Non-volatile memory device, method of operating the same and method of fabricating the same | |
US9214553B2 (en) | Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device | |
US20170077314A1 (en) | Wafer with soi structure having a buried insulating multilayer structure and semiconductor device structure | |
CN111223934A (en) | Transistor structure and process method thereof | |
JP5956033B1 (en) | Memory cell, semiconductor integrated circuit device, and manufacturing method of semiconductor integrated circuit device | |
US10290724B2 (en) | FinFET devices having a material formed on reduced source/drain region | |
US9362278B1 (en) | FinFET with multiple dislocation planes and method for forming the same | |
TWI690058B (en) | Integrated circuit, integrated circuit including a memory device, and method for manufacturing same | |
US10090330B2 (en) | Structure and method for fully depleted silicon on insulator structure for threshold voltage modification | |
US20080023753A1 (en) | Semiconductor device and method for fabricating the same | |
KR101835611B1 (en) | Multi bit capacitorless dram using band offset technology and manufacturing method thereof | |
KR101835612B1 (en) | Multi bit capacitorless dram and manufacturing method thereof | |
US10714479B2 (en) | One-transistor dram cell device based on polycrystalline silicon with FinFET structure and fabrication method thereof | |
WO2023245756A1 (en) | Semiconductor structure and method for forming same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E601 | Decision to refuse application | ||
AMND | Amendment | ||
X701 | Decision to grant (after re-examination) |