KR20170053630A - 압축 알고리즘들을 위한 캐시 뱅크 스프레딩 - Google Patents

압축 알고리즘들을 위한 캐시 뱅크 스프레딩 Download PDF

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Publication number
KR20170053630A
KR20170053630A KR1020177006694A KR20177006694A KR20170053630A KR 20170053630 A KR20170053630 A KR 20170053630A KR 1020177006694 A KR1020177006694 A KR 1020177006694A KR 20177006694 A KR20177006694 A KR 20177006694A KR 20170053630 A KR20170053630 A KR 20170053630A
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KR
South Korea
Prior art keywords
cache
bank
cache memory
access request
compressed data
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KR1020177006694A
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English (en)
Korean (ko)
Inventor
조지 페트실라라스
앤드류 에드먼드 터너
보후슬라프 리칠릭
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퀄컴 인코포레이티드
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Publication of KR20170053630A publication Critical patent/KR20170053630A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020177006694A 2014-09-11 2015-07-23 압축 알고리즘들을 위한 캐시 뱅크 스프레딩 Withdrawn KR20170053630A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/483,902 2014-09-11
US14/483,902 US9355038B2 (en) 2014-09-11 2014-09-11 Cache bank spreading for compression algorithms
PCT/US2015/041781 WO2016039866A1 (en) 2014-09-11 2015-07-23 Cache bank spreading for compression algorithms

Publications (1)

Publication Number Publication Date
KR20170053630A true KR20170053630A (ko) 2017-05-16

Family

ID=53783380

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020177006694A Withdrawn KR20170053630A (ko) 2014-09-11 2015-07-23 압축 알고리즘들을 위한 캐시 뱅크 스프레딩

Country Status (6)

Country Link
US (1) US9355038B2 (enExample)
EP (1) EP3191967B1 (enExample)
JP (1) JP2017532657A (enExample)
KR (1) KR20170053630A (enExample)
CN (1) CN106687937B (enExample)
WO (1) WO2016039866A1 (enExample)

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US9514047B2 (en) * 2014-12-17 2016-12-06 Intel Corporation Apparatus and method to dynamically expand associativity of a cache memory
US10191850B2 (en) 2016-03-31 2019-01-29 Qualcomm Incorporated Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system
US10176090B2 (en) 2016-09-15 2019-01-08 Qualcomm Incorporated Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems
US10445261B2 (en) * 2016-12-30 2019-10-15 Intel Corporation System memory having point-to-point link that transports compressed traffic
US10503652B2 (en) * 2017-04-01 2019-12-10 Intel Corporation Sector cache for compression
US10609172B1 (en) 2017-04-27 2020-03-31 Chicago Mercantile Exchange Inc. Adaptive compression of stored data
US12105716B2 (en) * 2017-06-23 2024-10-01 Xilinx, Inc. Parallel compute offload to database accelerator
US11048419B2 (en) * 2019-01-30 2021-06-29 EMC IP Holding Company LLC Adaptively over-allocating storage space for compressed data

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US5956744A (en) 1995-09-08 1999-09-21 Texas Instruments Incorporated Memory configuration cache with multilevel hierarchy least recently used cache entry replacement
JPH10232838A (ja) * 1996-11-05 1998-09-02 Hitachi Ltd ディスク記憶システム
US6115787A (en) * 1996-11-05 2000-09-05 Hitachi, Ltd. Disc storage system having cache memory which stores compressed data
CN1081361C (zh) * 1997-11-06 2002-03-20 中国科学院计算技术研究所 高速缓冲存储器系统中的地址映射变换技术与装置
AU2610701A (en) 2000-01-03 2001-07-16 Efeckta Technologies Corporation Efficient and lossless conversion for transmission or storage of data
US6307790B1 (en) * 2000-08-30 2001-10-23 Micron Technology, Inc. Read compression in a memory
US6820182B1 (en) * 2000-10-18 2004-11-16 International Business Machines Corporation Support for exhaustion recovery in a data processing system with memory mirroring
US7266651B1 (en) 2004-09-07 2007-09-04 Sun Microsystems, Inc. Method for in-place memory interleaving and de-interleaving
US8443162B2 (en) * 2005-01-21 2013-05-14 Qualcomm Incorporated Methods and apparatus for dynamically managing banked memory
US7627735B2 (en) * 2005-10-21 2009-12-01 Intel Corporation Implementing vector memory operations
US7705753B2 (en) 2005-10-22 2010-04-27 Sytex, Inc. Methods, systems and computer-readable media for compressing data
US7996597B1 (en) 2007-04-16 2011-08-09 Juniper Networks, Inc. Mapping address bits to improve spread of banks
JP4653830B2 (ja) * 2008-09-19 2011-03-16 株式会社東芝 命令キャッシュシステム
US8700862B2 (en) * 2008-12-03 2014-04-15 Nvidia Corporation Compression status bit cache and backing store
US8627041B2 (en) 2009-10-09 2014-01-07 Nvidia Corporation Efficient line and page organization for compression status bit caching
US8918897B2 (en) 2009-11-24 2014-12-23 Cleversafe, Inc. Dispersed storage network data slice integrity verification
CN102129873B (zh) * 2011-03-29 2012-07-04 西安交通大学 提高计算机末级高速缓存可靠性的数据压缩装置及其方法
US20130265305A1 (en) * 2012-04-04 2013-10-10 Jon N. Hasselgren Compressed Depth Cache
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US9026747B2 (en) * 2012-08-16 2015-05-05 Broadcom Corporation Memory device with a logical-to-physical bank mapping cache

Also Published As

Publication number Publication date
CN106687937A (zh) 2017-05-17
WO2016039866A1 (en) 2016-03-17
CN106687937B (zh) 2020-06-23
EP3191967A1 (en) 2017-07-19
US9355038B2 (en) 2016-05-31
JP2017532657A (ja) 2017-11-02
EP3191967B1 (en) 2018-12-26
US20160077973A1 (en) 2016-03-17

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Date Code Title Description
PA0105 International application

Patent event date: 20170309

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination