KR20170048705A - Fingerprint detecting apparatus and driving method thereof - Google Patents
Fingerprint detecting apparatus and driving method thereof Download PDFInfo
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- KR20170048705A KR20170048705A KR1020150149120A KR20150149120A KR20170048705A KR 20170048705 A KR20170048705 A KR 20170048705A KR 1020150149120 A KR1020150149120 A KR 1020150149120A KR 20150149120 A KR20150149120 A KR 20150149120A KR 20170048705 A KR20170048705 A KR 20170048705A
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Abstract
Description
The present invention relates to a fingerprint detecting apparatus and a driving method thereof, and more particularly, to a fingerprint detecting apparatus and a driving method of the fingerprint detecting apparatus that minimize noise inflow and eliminate the influence of parasitic capacitance, thereby improving sensitivity.
Since fingerprints vary from person to person, they are widely used in the field of personal identification. In particular, fingerprints are widely used in various fields such as finance, crime investigation and security as personal authentication means.
A fingerprint recognition sensor has been developed to recognize these fingerprints and identify them. The fingerprint recognition sensor is a device for recognizing a fingerprint of a finger by contacting a finger of a person, and is used as a means for determining whether or not the user is a legitimate user.
In recent years, the necessity of personal authentication and security enhancement is increasing rapidly in mobile market, and security related business through mobile is actively proceeding.
Various recognition methods such as an optical method, a thermal sensing method, and a capacitive sensing method are known as a method of implementing a fingerprint recognition sensor.
Among them, the principle of the capacitive type fingerprint sensor is that the electrostatic capacitance formed between the top metal plate and the ridge of the fingerprint, the difference between the electrostatic capacitance formed between the top metal plate and the fingerprint valley, The fingerprint image is formed by digitizing and imageing.
1 is a view showing a configuration of a general fingerprint detecting apparatus.
1, a general fingerprint detecting apparatus includes a sensor array 10 in which a plurality of
Each of the
The filter and
The sample-and-
The
The
The
Such a fingerprint detection device has a limitation on the design of the external electrode 20 and a problem that a part of the drive signal from the external electrode 20 is lost and the output signal from the
In addition, since the
In addition, the size of the circuit constituting the
Therefore, there is a need for a technique capable of minimizing the influence of noise input upon fingerprint detection and minimizing the size of the fingerprint recognition device.
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art.
SUMMARY OF THE INVENTION An object of the present invention is to solve the problem of current leakage that may occur when a driving signal is applied through an external electrode in a fingerprint detection device, and to provide a design advantage.
Another object of the present invention is to solve the problem of noise inflow that may occur in the signal transmission path to the outside of the fingerprint sensing device by digitizing the sensing signal in the fingerprint sensing device.
It is another object of the present invention to eliminate the influence of the parasitic capacitance formed on the sensing electrode of the fingerprint sensing element on the output signal.
It is still another object of the present invention to maintain the potential of an object in contact with the fingerprint detection device at all positions and to remove the influence of the parasitic capacitance formed between adjacent sensing electrodes in a fingerprint detection operation.
According to an aspect of the present invention, there is provided a fingerprint detection device including a plurality of fingerprint sensing elements, each fingerprint sensing element including: a sensing electrode that forms a sensing capacitance in relation to a subject; An integrating unit for continuously accumulating a value proportional to the sensing capacitance to generate an output voltage; A comparing unit comparing the output voltage of the integrating unit with a reference voltage; And an output unit for integrating the output voltage of the comparison unit for a predetermined interval and outputting the result as a digital signal.
The fingerprint detection apparatus may further include a delta unit that subtracts an output voltage of the integrator when an output voltage of the integrator exceeds a reference voltage.
The delta unit may include a delta electrostatic capacity sharing charge with the feedback capacitance of the amplifier included in the integrating unit when the output voltage of the integrating unit exceeds the reference voltage.
The delta unit may further include an AND gate for generating a control signal for connecting the delta capacitance to the input terminal of the amplifier while the sensing electrode is initialized when the output voltage of the inductor exceeds the reference voltage have.
The delta unit may further include a D flip-flop that stabilizes an output voltage of the comparator and provides the input signal to the AND gate.
The delta unit may further include an OR gate for generating a control signal for initializing the delta capacitance in a period in which the feedback capacitance of the amplifier is initialized or a period in which the sensing electrode is initialized.
The fingerprint detection device may further include a compensating electrostatic capacity for compensating an amount of charge charged in the parasitic electrostatic capacitance formed on the sensing electrode while the sensing electrode is connected to the integrating unit.
The fingerprint detection apparatus may further include an external device for determining the size of the sensing capacitance in proportion to the number of times the output voltage of the integration section exceeds the reference voltage for a predetermined interval based on the output signal of the output section have.
A potential equal to the potential of the first sensing electrode may be supplied to at least one second sensing electrode adjacent to the first sensing electrode of the first fingerprint sensing device to be subjected to the fingerprint sensing operation.
The sensing electrodes other than the first sensing electrode and the second sensing electrode may all be connected to the ground potential.
According to another aspect of the present invention, there is provided a method of driving a fingerprint detection device including a plurality of fingerprint sensing elements, the method comprising: initializing a sensing electrode included in a fingerprint sensing element and forming a sensing capacitance in relation to the subject; ; Connecting the sensing electrode to an input terminal of an amplifier included in the integrating unit so that a value proportional to the sensing capacitance is accumulated in an output voltage of the amplifier; And determining a magnitude of the sensing capacitance based on an output signal of an output unit that generates a digital signal proportional to the number of times the output voltage value of the integrating unit exceeds the reference voltage. / RTI >
The initializing step may include subtracting the output voltage value of the integrator when the output voltage value of the integrator exceeds the reference voltage.
According to the present invention, since fingerprint sensing is possible without an external electrode in a fingerprint detecting device, current leakage due to an external environment is lost when a driving signal is applied.
According to the present invention, since the digitized signal is output as the sensing signal in the fingerprint sensing element, the possibility of noise input in the process of transmitting the output signal to the external device can be eliminated.
According to the present invention, since a separate amplifier and an analog-digital converter are not provided outside the fingerprint sensing device, the design area of the entire fingerprint detection device can be minimized.
According to the present invention, the influence of the parasitic capacitance formed on the sensing electrode of the fingerprint sensing element on the output signal can be eliminated through the compensation capacitance.
According to the present invention, by applying the potential applied to the sensing electrode in the fingerprint detection operation equally to the adjacent sensing electrodes, it is possible to eliminate the influence of the parasitic capacitance formed in accordance with the relationship between the sensing electrodes, The potential of the finger can be kept the same at all positions.
1 is a view showing a configuration of a general fingerprint detecting apparatus.
2 is a diagram showing a schematic configuration of a fingerprint detection apparatus according to an embodiment of the present invention.
3 is a diagram for explaining a method of performing a fingerprint detection operation in a sensor array according to an embodiment of the present invention.
FIG. 4 is a circuit diagram for explaining the fingerprint detection operation described with reference to FIG. 3 in detail.
5 is a circuit diagram showing the detailed configuration of the sensing driver shown in FIG.
6 is a timing chart for explaining the operation of the fingerprint detecting device circuit shown in Fig.
7 is a graph showing changes in the output voltage of the amplifier provided in the sensing driver when the sensing capacitance is absent.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.
Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Also, when an element is referred to as "comprising ", it means that it can include other elements, not excluding other elements unless specifically stated otherwise.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
2 is a diagram showing a schematic configuration of a fingerprint detection apparatus according to an embodiment of the present invention.
Referring to FIG. 2, the fingerprint detection device includes a
As shown in FIG. 2, the fingerprint detection apparatus according to the embodiment of the present invention performs a stable fingerprint detection operation without an external electrode for applying a driving signal. Meanwhile, the digital signal output from the
3 is a diagram for explaining a method of performing a fingerprint detection operation in a sensor array according to an embodiment of the present invention.
Referring to FIG. 3, when a fingerprint detection operation is performed on the specific sensing electrode 110a in the
Therefore, in one embodiment of the present invention, the sensing electrode 110c which is not subject to the current fingerprint detection operation is connected to the ground potential. The subject is in contact with not only the sensing electrode 110a to be subjected to the fingerprint detection operation but also the surrounding sensing electrode 110c so that the subject is in a state of trying to maintain the ground potential through the peripheral sensing electrode 110c. Here, the ground potential may be a potential different from the reference potential Vref, and may be implemented in accordance with various embodiments, such as a system ground potential, a positive potential higher than or equal to a predetermined potential of 0 V, or a negative potential.
Therefore, the potential of the subject is maintained at the ground potential at any position in the
Meanwhile, when a potential difference is generated between the sensing electrode 110a and the adjacent sensing electrode during the fingerprint detection operation for the specific sensing electrode 110a, the parasitic capacitance can be formed due to the relationship between the sensing electrodes.
In one embodiment of the present invention, the potential of the sensing electrode 110a, which is the object of fingerprint detection, is synchronized with at least one sensing electrode 110b adjacent thereto, so that a potential difference between adjacent sensing electrodes is not generated, It is possible to remove the parasitic electrostatic capacitance formed by the parasitic capacitance. As described later, if the ground potential and the reference potential are alternately applied to the sensing electrode 110a, which is the fingerprint detection target, and the ground potential and the reference potential are alternately applied to the adjacent sensing electrode 110b, a potential difference occurs between the adjacent sensing electrodes .
Selection of the sensing electrode 110b to which such an operation is applied can be performed in various manners.
According to an embodiment, as shown in FIG. 3, the operation may be performed on all the second sensing electrodes 110b surrounding the first sensing electrode 110a, which is a fingerprint sensing operation target. However, Of course. The object and the number selected as the second sensing electrode 110b may be set based on the magnitude of the parasitic capacitance formed or the complexity of the circuit operation required to apply the synchronized signal.
On the other hand, if the first sensing electrode 110a and the second sensing electrode 110b are defined as one cluster, it can be explained that these clusters are selected to overlap each other in the fingerprint detection operation. For example, if the first sensing electrode 110a and the second sensing electrode 110b shown in FIG. 3 are selected as the first cluster and the fingerprint detection operation is performed on the first sensing electrode 110a, The first sensing electrode in the selected second cluster may be any one of the second sensing electrodes 110b belonging to the first cluster.
FIG. 4 is a circuit diagram for explaining the fingerprint detection operation described with reference to FIG. 3 in detail.
4, a
The synchronization
The synchronization switch SWp in the
As will be described later, the
If the same potential as the potential of the
To this end, when the first switch SW1 is turned on and the
On the other hand, when the sixth switch SW6 connected to the
In this way, the potential between the
In the case where two conductors are disposed adjacent to each other with a predetermined dielectric constant interposed therebetween, when the potential difference between the two conductors is converged close to zero, the amount of charge induced by the potential difference between the two conductors converges close to zero. The parasitic capacitance formed by the relationship is removed. Thus, the parasitic capacitance Cpt formed according to the relationship between the
It is also possible to further include additional switches (not shown) for interconnecting the
In addition, the synchronization switch SWp connected to the first input terminal of the
5 is a circuit diagram showing the detailed configuration of the sensing driver shown in FIG. 5, the configuration and operation of the parasitic
Referring to FIG. 5, it can be seen that the parasitic capacitance Cp due to the influence of the circuit configuration or the relationship with other adjacent fingerprint sensing elements is formed in the
The parasitic
Specifically, the parasitic
The other end N2 of the compensating capacitance Cc is selectively connected to the first input N3 of the first amplifier A1 included in the
The other end N2 of the compensating capacitance Cc is selectively connected to the
As described later, when the
The integrating
As described above, the amount of charge charged in the parasitic capacitance Cp during the fingerprint detection operation can be canceled by the compensating capacitance Cc. If the amount of charge compensated by the compensating capacitance Cc is less than the parasitic capacitance Cp The voltage applied to the feedback capacitance Cfb of the first amplifier A1 continuously rises even if the sensing capacitance Cf does not exist, (A1) reaches the saturation region. It is therefore important to appropriately adjust the value of the compensating capacitance Cc so that the amount of charge charged in the parasitic capacitance Cp can be completely canceled. 111 of the
The integrating
The
The
According to one embodiment, the
As described above, the fluctuation range of the output voltage Vout1 of the
If the magnitude of the sensing capacitance Cf is large, the frequency at which the output voltage Vout1 of the integrating
The decimation filter DF of the
The
More specifically, the
The OR gate OR includes a reset control signal INIT for controlling ON / OFF of the reset switch SWr, a second control signal INIT for controlling on / off of the third switch SW3 and the sixth switch SW6 PH2) as an input signal, and controls the fourth switch SW4 with an output signal. Since the OR gate OR is a logic gate that outputs a high level signal as an output signal when at least one of the two input signals is at a high level, one of the reset control signal INIT and the second control signal PH2 Level signal as the output signal to switch the fourth switch SW4 to the on-state. When the fourth switch SW4 is turned on, the delta capacitance Ce is initialized.
When the reset control signal INIT is at the high level, the reset switch SWr is turned on and the feedback capacitance Cfb of the first amplifier A1 is initialized. When the second control signal PH2 is at the high level The third switch SW3 and the sixth switch SW6 are turned on and the sensing capacitance Cf, the parasitic capacitance Cp, the compensation capacitance Cc and the feedback capacitance Cfb ). ≪ / RTI > Therefore, the delta capacitance Ce is a period in which the feedback capacitance Cfb is initialized, or a period during which the charge capacitance Cf, the parasitic capacitance Cp, the compensation capacitance Cc, and the feedback capacitance Cfb, It can be said to be initialized in at least one section among the sections in which sharing is performed.
The on / off operation of the fifth switch SW5 for controlling the connection between the delta capacitance Ce and the first input terminal N3 of the first amplifier A1 is controlled by the D flip-flop D and the AND gate ).
The D flip-flop D outputs a signal having the same level as that of the input signal, receives the output voltage Vout2 of the second amplifier A2, and outputs it as a stabilized signal. When the output voltage Vout1 of the first amplifier A1 is larger than the reference voltage Vref, the output voltage Vout2 of the second amplifier A2 becomes + Vsat, which is applied to the D flip- When input, a stabilized high-level signal is output. On the other hand, when the output voltage Vout1 of the first amplifier A1 is smaller than the reference voltage Vref, the output voltage Vout2 of the second amplifier A2 becomes -Vsat, The stabilized low level signal is output.
The AND gate AND outputs the high level signal as the output signal when all of the input signals are at the high level and outputs the low level signal in the other case. Therefore, the output signal Vout1 of the first amplifier A1 The fifth switch SW5 is turned on in a period in which the sensing capacitance Cf, the parasitic capacitance Cp and the compensating capacitance Cc are initialized to be larger than the reference voltage Vref and the delta capacitance Ce ) To the first input (N3) of the first amplifier (A1).
When the fifth switch SW5 is turned on and the delta capacitance Ce is connected to the first input N3 of the first amplifier A1, the delta capacitance Ce is applied to the first amplifier A1, Sharing the charge capacitance Cfb of the capacitor Cfb. Since charges are accumulated in the feedback capacitance Cfb due to charge sharing between the sensing capacitance Cf, the parasitic capacitance Cp, the compensation capacitance Cc and the feedback capacitance Cfb, As the switch SW5 is turned on, part of the charge stored in the feedback capacitance Cfb is transferred to the delta capacitance Ce.
The charge sharing between the sensing capacitance Cf, the parasitic capacitance Cp, the compensation capacitance Cc and the feedback capacitance Cfb and the charge sharing between the delta capacitance Ce and the feedback capacitance Cfb, The output voltage Vout1 of the first amplifier A1 can be reduced because the delta capacitance Ce is involved in the overall charge sharing phenomenon even if it is performed at a different time.
After the output voltage Vout1 of the first amplifier A1 is reduced, the charge is again accumulated in the feedback capacitance Cfb, and the output voltage Vout1 of the first amplifier A1 rises again.
The saturation phenomenon of the first amplifier A1 can be prevented as the output voltage Vout1 of the first amplifier A1 is reduced under a certain condition. The magnitude of the feedback capacitance Cfb and the capacitance of the delta capacitance Ce It is possible to accurately determine the width to be lowered by the delta capacitance Ce when the output voltage Vout1 of the integrating
According to an embodiment of the present invention, since the output signal of the
FIG. 6 is a timing chart for explaining the operation of the fingerprint detecting device circuit shown in FIG. 5, and FIG. 7 is a graph showing a change in the output voltage of the first amplifier when no sensing capacitance exists.
Hereinafter, the operation of the fingerprint detecting apparatus according to the embodiment will be described with reference to FIG. 5 to FIG.
In Fig. 6, CLK indicates a level change of a clock signal for controlling the operation of the D flip-flop D. Fig. And the D flip-flop D operates when the clock signal CLK is at a high level. INIT represents the level change of the reset control signal INIT which controls the ON / OFF operation of the reset switch SWr connected between both ends of the feedback capacitance Cfb of the first amplifier A1, The reset switch SWr is turned on. PH1 and PH2 denote levels of the first control signal PH1 and the second control signal PH2 and are switches SW1 and SW2 controlled by the control signals PH1 and PH2 at high level, , SW3 are turned on.
7, PH1, PH2, and INIT represent periods in which the first control signal PH1, the second control signal PH2, and the reset control signal INIT are switched to the high level and maintained, respectively.
The logic value (LV) shown at the bottom of the graph of FIG. 7 represents the output signal of the AND gate (AND) of the
First, in the first period T1, the reset control signal INIT is switched to the high level. Thereby, the reset switch SWr is turned on, and the amount of charge remaining in the feedback capacitance Cfb of the first amplifier A1 can be discharged and initialized.
At this time, the potentials of the first input terminal N3 and the output terminal N5 of the first amplifier A1 become equal to the potential of the reference voltage Vref like the potential of the second input terminal N4. On the other hand, since one of the two input signals INIT and PH2 of the OR gate OR is a high level signal, the output signal of the OR gate OR becomes a high level signal, whereby the fourth switch SW4 is turned on State, and the amount of charge remaining in the delta capacitance Ce is also discharged and initialized.
Since the first control signal PH1 and the second control signal PH2 are maintained at a low level in the first period T1, the first through third switches SW1, SW2, and SW3 and the sixth switch And the AND gate AND which receives the first control signal PH1 as an input signal also outputs a low level signal. Therefore, the fifth switch SW5 is also kept in the off state. The circuit on the left side including the
In the second period T2, the reset control signal INIT is switched to the low level and the first control signal PH1 is switched to the high level. At this time, the first switch SW1 and the second switch SW2 are turned on. As the first switch SW1 is turned on, the sensing capacitance Cf and the parasitic capacitance Cp are connected to the ground potential. Further, as the second switch SW2 is switched to the ON state, the potential across the compensating capacitance Cc is kept equal to the potential of the power supply voltage Vcc, and can be set to the initial state for subsequent charge sharing have. The third switch SW3 and the sixth switch SW6 are still kept in the OFF state so that the feedback capacitance Cfb of the first amplifier A1 maintains the physical quantity in the first section T1. Thus, the output voltage Voutl of the first amplifier A1 can still be maintained equal to the magnitude of the reference voltage Vref.
On the other hand, since the OR gate OR outputs a high level signal, the fourth switch SW4 maintains the ON state.
In the third period T3, the first control signal PH1 is switched to the low level and the second control signal PH2 is switched to the high level. At this time, the first and second switches SW1 and SW2 are turned off, and one of the two input signals INIT and PH2 of the OR gate OR becomes a high level, And the fourth switch SW4 is turned on. Since the output signal LV of the AND gate AND becomes low level 0, the fifth switch SW5 is kept in the OFF state, so that the delta capacitance Ce does not affect the entire circuit operation do. On the other hand, as the third switch SW3 and the sixth switch SW6 are turned on, the left and right circuits based on the third switch SW3 are interconnected.
This causes charge sharing phenomenon between the sensing capacitance Cf, the parasitic capacitance Cp, the compensation capacitance Cc, and the feedback capacitance Cfb.
The sum of the amounts of charge charged in the sensing capacitance Cf and the parasitic capacitance Cp can be regarded as being equal to the sum of the amounts of charges supplied from the compensation capacitance Cc and the feedback capacitance Cfb, .
Therefore, the output voltage Vout1 of the first amplifier A1 can be expressed as follows.
In Equation (2)
If the magnitude of the power supply voltage Vcc supplied to one end of the compensating capacitance Cc is set to twice the magnitude of the reference voltage Vref, that is, if Vcc = 2 · Vref in Equation 2, Can be arranged.
Here, if the magnitude of the parasitic capacitance Cp and the magnitude of the compensating capacitance Cc are the same, that is, Cp = Cc, Equation (3) can be summarized as follows.
That is, if the magnitude of the power supply voltage Vcc is twice the magnitude of the reference voltage Vref and the magnitude of the compensating capacitance Cc is appropriately selected to be equal to the magnitude of the parasitic capacitance Cp, The influence of the parasitic capacitance Cp on the output voltage Vout1 of the transistors A1 and A1 can be removed.
If the magnitude of the parasitic capacitance Cp and the magnitude of the compensating capacitance Cc are completely equal to each other, assuming that there is no contact of the subject (i.e., Cf = 0), then even in the third period T3, The output voltage Vout1 of the transistor A1 maintains the same magnitude as the reference voltage Vref.
In the fourth period T4, the first control signal PH1 is again switched to the high level and the second control signal PH2 is switched to the low level. The sensing capacitance Cf, the parasitic capacitance Cp, and the compensation capacitance Cc are initialized as the first control signal PH1 is switched to the high level. As the second control signal PH2 is switched to the low level, the third switch SW3 and the sixth switch SW6 are turned off and the sensing capacitance Cf, the parasitic capacitance Cp, The charge sharing between the compensating capacitance Cc and the feedback capacitance Cfb is interrupted.
Since the output voltage Vout1 of the first amplifier A1 is greater than the reference voltage Vref, the output voltage Vout2 of the second amplifier A2 has a value of + Vsat, The output signal of the D flip-flop D of the flip-
The fourth switch SW4 is switched to the OFF state and the fifth switch SW5 is switched to the ON state so that the delta capacitance Ce is connected to the first input terminal N3 of the first amplifier A1 The charge sharing between the delta capacitance Ce and the feedback capacitance Cfb is achieved.
The amount of charge Q1 charged in the feedback capacitance Cfb before the fifth switch SW5 is turned on can be expressed as follows.
The sum Q2 of the amounts of charge stored in the delta electrostatic capacitance Ce and the feedback electrostatic capacity Cfb after the fifth switch SW5 is turned on can be expressed as follows. Here, Vout1 'represents the output voltage of the first amplifier A1 when the fifth switch SW5 is turned on and then reaches the steady state.
According to the charge conservation law, Q 1 = Q 2 and Vcc = 2Vref, so using this can be summarized as follows for Vout 1 '.
Substituting Equation (3) into Equation (7), the following equation is derived.
Referring to Equation (8), as the fifth switch SW5 is turned on, the delta capacitance Ce also has the same effect as that involved in charge sharing in the third period T3, The output voltage Vout1 of the transistor A1 is decreased in proportion to the magnitude of the delta capacitance Ce.
After the fifth period T5, a period in which the first control signal PH1 and the second control signal PH2 are alternately switched to the high level (hereinafter referred to as a "cycle") is repeated and the reset control signal INIT) is kept at a low level continuously. In this process, if the output voltage Vout1 of the first amplifier A1 is smaller than the reference voltage Vref, the output signal LV of the AND gate AND is kept at the low level 0 and the delta capacitance Ce do not serve to lower the output voltage Vout1 of the first amplifier A1.
While the cycle is repeated, the output signal (Vout2) of the second amplifier (A2) is input to the output section (115).
The decimation filter DF of the
The second amplifier A2 generates a different output voltage Vout2 corresponding to + Vsat or -Vsat depending on whether the output voltage Vout1 of the first amplifier A1 exceeds the reference voltage Vref, The + Vsat value as the output voltage Vout2 of the second amplifier A1, in proportion to the number of times that the output voltage Vout1 of the first amplifier A1 exceeds the reference voltage Vref during the same number of cycles, The number of times of outputting is also increased.
Thus, by integrating the output voltage Vout2 of the second amplifier A2 through the decimation filter DF during a certain number of cycles, the magnitude of the sensing capacitance Cf can be grasped as a digitized value do.
When the cycle is repeated a predetermined number of times, the reset control signal INIT is again switched to the high level and the operation is repeated from the first section T1 described above.
In the embodiment of the present invention, since external electrodes for applying a driving signal are not provided, a current path leaked to an external environment or a subject is removed when a driving signal is applied, and accurate fingerprint sensing results can be obtained.
In addition, by outputting a digital signal in the sensing driver itself, noise interference in the analog signal transmission path can be prevented, and the circuit design can also be simplified.
It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.
The scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.
100: sensor array
110, 110a, 110b, 110c: fingerprint sensing element
111, 111a, 111b: sensing electrodes
112, 112a and 112b: parasitic capacitance capacitors
113, 113a, and 113b:
114, 114a and 114b:
115, 115a, and 115b:
116, 116a, 116b: delta part
Claims (12)
Each of the fingerprint sensing elements,
A sensing electrode for forming a sensing capacitance in relation to a subject;
An integrating unit for continuously accumulating a value proportional to the sensing capacitance to generate an output voltage;
A comparing unit comparing the output voltage of the integrating unit with a reference voltage; And
And an output unit for integrating the output voltage of the comparison unit for a predetermined period and outputting the result as a digital signal.
And a delta unit for subtracting the output voltage of the integrating unit when the output voltage of the integrating unit exceeds the reference voltage.
The delta unit,
And a delta electrostatic capacity for sharing the charge with the feedback capacitance of the integrating unit and subtracting the output voltage of the integrating unit when the output voltage of the integrating unit exceeds the reference voltage.
The delta unit,
Further comprising an AND gate for generating a control signal for connecting the delta capacitance to the input of the amplifier while the sensing electrode is initialized when the output voltage of the integrator exceeds a reference voltage.
The delta unit,
And a D flip-flop for stabilizing the output voltage of the comparator and providing the input signal to the AND gate.
The delta unit,
Further comprising an OR gate for generating a control signal for initializing the delta capacitance in a period in which the feedback capacitance of the amplifier is initialized or in a period in which the sensing electrode is initialized.
Further comprising a compensating capacitance compensating an amount of charge charged in the parasitic capacitance formed in the sensing electrode while the sensing electrode is connected to the integrating unit.
And an external device for determining the magnitude of the sensing capacitance, which is proportional to the number of times the output voltage of the integrating unit exceeds the reference voltage for a predetermined interval based on the output signal of the output unit.
Wherein at least one second sensing electrode adjacent to the first sensing electrode of the first fingerprint sensing device to be subjected to the fingerprint sensing operation is supplied with the same potential as the potential of the first sensing electrode synchronously.
Wherein the sensing electrodes except for the first sensing electrode and the second sensing electrode are all connected to the ground potential.
Initializing a sensing electrode included in the fingerprint sensing device and forming a sensing capacitance in relation to the subject;
Connecting the sensing electrode to an input terminal of an amplifier included in the integrating unit so that a value proportional to the sensing capacitance is accumulated in an output voltage of the amplifier; And
And determining the magnitude of the sensing capacitance based on an output signal of an output unit that generates a digital signal proportional to the number of times the output voltage value of the integrating unit exceeds the reference voltage.
In the initialization step,
And subtracting the output voltage value of the integrating unit when the output voltage value of the integrating unit exceeds the reference voltage.
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| KR1020150149120A KR20170048705A (en) | 2015-10-27 | 2015-10-27 | Fingerprint detecting apparatus and driving method thereof |
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| KR1020150149120A KR20170048705A (en) | 2015-10-27 | 2015-10-27 | Fingerprint detecting apparatus and driving method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7496733B2 (en) | 2019-10-24 | 2024-06-07 | 三星電子株式会社 | Method for generating a fingerprint image and fingerprint sensor - Patents.com |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP7496733B2 (en) | 2019-10-24 | 2024-06-07 | 三星電子株式会社 | Method for generating a fingerprint image and fingerprint sensor - Patents.com |
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