KR20170028227A - Magnetoresistive random access device and method of manufacturing the same - Google Patents

Abstract

A magnetoresistive memory device includes a lower electrode formed on a substrate, an MTJ structure disposed on the lower electrode, and a mask structure disposed on the MTJ structure and including a top electrode and a sidewall capping pattern surrounding the top electrode sidewall, . The MTJ structure includes a lower magnetic pattern, a tunnel barrier pattern, and an upper magnetic pattern.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a magnetoresistive memory device,

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a magnetoresistive random access memory (MRAM) device and a manufacturing method thereof.

Each cell of the magnetoresistive memory element includes a resistive structure in which a lower electrode, a MTJ structure, and an upper electrode are sequentially stacked. However, the materials included in the MTJ structure are not easily etched, so that an electrical failure may occur in the MTJ structure during the etching process.

An object of the present invention is to provide a magnetoresistive memory element having excellent electrical characteristics.

Another object of the present invention is to provide a method of manufacturing the above-described magnetoresistive memory element.

According to exemplary embodiments of the present invention, a magnetoresistive memory device includes a lower electrode formed on a substrate, a 7MTJ structure provided on the lower electrode, and a lower electrode formed on the upper electrode and the MTJ structure, And a sidewall capping pattern surrounding the top electrode sidewalls.

In exemplary embodiments, the top electrode is in contact with the center of the top surface of the MTJ structure, and the sidewall capping pattern is in contact with an edge of the top surface of the MTJ structure.

In exemplary embodiments, the top electrode may have a wider top width than a bottom width.

In exemplary embodiments, the upper electrode may have a constant width at the bottom and a gradually increased width at the top.

In exemplary embodiments, the maximum width of the top electrode may be equal to or less than the width of the top of the MTJ structure.

In exemplary embodiments, the sidewall capping pattern may comprise an insulating material.

In exemplary embodiments, the sidewall capping pattern may comprise silicon nitride, silicon oxynitride, or silicon oxide.

In exemplary embodiments, the upper electrode may include at least one selected from the group consisting of tungsten, titanium, titanium nitride, tantalum, tantalum nitride, and iron.

In exemplary embodiments, the bottom surface of the mask structure may have the same size as the top surface of the MTJ structure.

In exemplary embodiments, the mask structure may cover the top surface of the MTJ structure.

In exemplary embodiments, the bottom width of the mask structure may be wider than the top width.

In exemplary embodiments, the mask structure may have a constant width at the bottom and a gradually reduced width at the top.

In exemplary embodiments, the mask structure has a planar top surface, and the area of the top electrode exposed to the planar top surface of the structure may be wider than the area of the sidewall capping pattern.

In exemplary embodiments, the MTJ structure may be stacked with a lower magnetic pattern, a tunnel barrier pattern, and an upper magnetic pattern.

In exemplary embodiments, a barrier metal pattern may be further included between the MTJ structure and the mask structure.

In exemplary embodiments, a barrier metal pattern surrounding the upper electrode bottom may be further included between the upper electrode and the sidewall capping pattern.

According to an aspect of the present invention, there is provided a magnetoresistive memory device comprising: an interlayer insulating film formed on a substrate and including a conductive pattern; A lower electrode and an MTJ structure; and a mask structure on the MTJ structure, the mask structure including an upper electrode and a sidewall capping pattern surrounding the upper electrode sidewall, and a wiring electrically connected to the upper electrode.

In exemplary embodiments, a conformal capping insulating film may be further included on the interlayer insulating film upper surface and the lower electrode, the MTJ structure, and the surface of the mask structure.

In order to achieve the above-described object, a method of manufacturing a magnetoresistive memory device according to exemplary embodiments includes forming a lower electrode film and an MTJ film on a substrate. An etch mask comprising a preliminary top electrode on the MTJ film and a preliminary sidewall capping pattern on the sidewall of the preliminary top electrode is formed. Then, the MTJ film and the lower electrode film are anisotropically etched using the etching mask to form a lower electrode, an MTJ structure, an upper electrode, and a sidewall capping pattern.

In exemplary embodiments, a mold pattern including holes is formed on the MTJ film to form the etch mask. Forming a redundant sidewall capping pattern having a smaller width on the sidewalls inside the hole than on the lower portion. Then, a preliminary upper electrode is formed on the preliminary sidewall capping pattern to fill the hole and make contact with the MTJ film.

In exemplary embodiments, the mold pattern may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

In exemplary embodiments, the preliminary sidewall capping pattern may comprise an insulating material having an etch selectivity with the mold pattern.

In exemplary embodiments, the preliminary sidewall capping pattern may comprise silicon oxide, silicon nitride, or silicon oxynitride.

In exemplary embodiments, a conformal capping film is formed on the sidewalls, the bottom, and the top surface of the mold pattern in the first holes to form the preliminary sidewall capping pattern. The capping film formed on the bottom surface of the first holes and on the top surface of the mold pattern is anisotropically etched.

In exemplary embodiments, the capping layer may be formed by atomic layer deposition or chemical vapor deposition.

In exemplary embodiments, a preliminary upper electrode film filling the inside of the holes is formed on the upper surface of the preliminary sidewall capping pattern and the mold pattern to form the preliminary upper electrode. The preliminary upper electrode film is planarized to expose the upper surface of the mold pattern.

In exemplary embodiments, after forming the preliminary upper electrode, the process may further include a step of removing the mold pattern.

In exemplary embodiments, the mold pattern may be removed through an isotropic etching process.

In the exemplary embodiments, the process of etching the MTJ film and the lower electrode film may include ion beam etching, sputter etching, or RF (radio-frequency) etching.

In exemplary embodiments, after the MTJ film is formed, a barrier metal film can be formed.

In exemplary embodiments, a barrier metal film surrounding the bottom of the preliminary upper electrode may be formed between the preliminary upper electrode and the preliminary side wall capping pattern.

A method of manufacturing a magnetoresistive memory device according to exemplary embodiments for achieving the above-described object forms a lower electrode film, an MTJ film, and a mold film on a substrate. The mold film is partially etched to form a mold pattern including a hole exposing a part of the MTJ film. Thereby forming a preliminary sidewall capping pattern on the inner wall of the hole. A preliminary upper electrode filling the inside of the hole is formed on the preliminary sidewall capping pattern and the MTJ film. The mold pattern is removed. The MTJ film and the lower electrode film are anisotropically etched using the preliminary upper electrode and the preliminary sidewall capping pattern as an etch mask to form a lower electrode, an MTJ structure, an upper electrode, and a sidewall capping pattern.

In exemplary embodiments, a mold film is formed on the MTJ film to form the mold pattern. Holes are formed in the mold film through a photo etching process.

In an exemplary embodiment, the MTJ film includes a stacked lower magnetic film, a tunnel barrier film, and an upper magnetic film, and the MTJ structure may include a stacked lower magnetic pattern, a tunnel barrier pattern, and an upper magnetic pattern. have

In exemplary embodiments, the preliminary sidewall capping pattern is formed to have a smaller width at the top than at the bottom, so that the inside of the hole in which the preliminary sidewall capping pattern is formed has a top width that is wider than the bottom width have.

In order to achieve the above-described object, there is provided a method of manufacturing a magnetoresistive memory element according to exemplary embodiments, wherein an interlayer insulating film including a conductive pattern is formed on a substrate. A lower electrode film and an MTJ film are sequentially formed on the interlayer insulating film. An etch mask comprising a preliminary top electrode on the MTJ film and a preliminary sidewall capping pattern on the sidewall of the preliminary top electrode is formed. The MTJ film and the lower electrode film are anisotropically etched using the etch mask to form a mask structure including the lower electrode, the MTJ structure, and the upper electrode and the sidewall capping pattern sequentially stacked on the conductive pattern. Then, a wiring electrically connected to the upper electrode is formed.

In exemplary embodiments, a conformally capping insulating film may be formed on the surface of the interlayer insulating film upper surface and the lower electrode, the MTJ structure, and the mask structure.

In the fabrication of the magnetoresistive memory device according to the exemplary embodiments, the MTJ film and the lower electrode film are etched using an etch mask including a preliminary upper electrode and a preliminary sidewall capping pattern on the sidewall of the preliminary upper electrode. Accordingly, when the MTJ film is etched, generation of conductive etch by-products from the preliminary upper electrode can be reduced. Therefore, the short failure of the MTJ structure due to the conductive etch by-products can be reduced.

1A and 1B are a cross-sectional view and a perspective view for explaining a magnetoresistive memory element according to exemplary embodiments.
FIGS. 2 to 12 are cross-sectional views and plan views for explaining a method of manufacturing a magnetoresistive memory element according to exemplary embodiments. FIG.
13 to 18 are cross-sectional views illustrating a method of manufacturing a magnetoresistive memory element according to exemplary embodiments.
19 is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments.
20 is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments.
21 is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments.
22 to 28 are cross-sectional views for explaining a method of manufacturing a magnetoresistive memory element.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, And should not be construed as limited to the embodiments described in the foregoing description.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

1A is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments. 1B is a perspective view of a variable resistance structure in a magnetoresistive memory element according to exemplary embodiments.

1A and 1B, the magnetoresistive memory device may include an interlayer insulating film 102 formed on a substrate 100 and a contact plug 104 which contacts the substrate through the interlayer insulating film 102 . A variable resistance structure 129 may be provided on the interlayer insulating layer 102 in contact with the upper surface of the contact plug 104. The variable resistor structure 129 may include a lower electrode 106a, an MTJ structure 114a, an upper electrode 126b, and a sidewall capping pattern 122b.

The substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, GaSb, and the like. According to some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

Although not shown, various elements such as a transistor, a diode, a source / drain layer, a source line, a word line, and the like can be formed on the substrate 100.

The contact plug 104 may include, for example, a metal such as tungsten, titanium, or tantalum, a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, or doped polysilicon.

The lower electrode 106a may have a larger lower surface than the upper surface of the contact plug 104 while completely covering the upper surface of the contact plug 104. [ The lower electrode 106a may be formed using a metal or a metal nitride. The lower electrode 106a may include at least one of a metal such as tungsten, titanium, tantalum, or the like, or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, or the like. And may further include a barrier metal film (not shown) on the lower electrode 106a.

The MTJ structure 114a may have a structure in which a first magnetic pattern 108a, a tunnel barrier pattern 110a, and a second magnetic pattern 112a are stacked.

The MTJ structure 114a may be provided on the lower electrode 106a to completely cover the upper surface of the lower electrode 106a. The lower surface of the MTJ structure 114a may have substantially the same area as the upper surface of the lower electrode 106a.

In the exemplary embodiments, the stack structure of the lower electrode 106a and the MTJ structure 114a may have vertical sidewalls. In the exemplary embodiments, the laminated structure of the lower electrode 106a and the MTJ structure 114a may have sloped sidewalls and may have a trapezoidal shape in cross section.

In the exemplary embodiments, the first magnetic pattern 108a may be provided as a fixed film structure with a fixed magnetization direction, for example.

In an exemplary embodiment, the first magnetic pattern 108a may include a fixed pattern, a lower ferromagnetic pattern, an antiferromagnetic coupling spacer pattern, and an upper ferromagnetic pattern. In this case, the fixed pattern may include, for example, at least one of manganese iron (FeMn), manganese iridium (IrMn), manganese platinum (PtMn), manganese oxide (MnO), manganese sulfide (MnS), tellurium manganese (FeF2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), chromium As shown in FIG. The upper and lower ferromagnetic patterns may be formed to include a ferromagnetic material including, for example, at least one of iron (Fe), nickel (Ni), and cobalt (Co). The antiferromagnetic coupling spacer pattern may be formed to include at least one of, for example, ruthenium (Ru), iridium (Ir), or rhodium (Rh).

In the exemplary embodiments, the second magnetic pattern 112a may be provided as a free layer whose magnetization direction is variable. In this case, the second magnetic pattern 112a may include a ferromagnetic material such as iron (Fe), cobalt (Co), nickel (Ni), chrome (Cr), platinum (Pt) The second magnetic pattern 112a may further include boron (B) or silicon (Si). These may be used alone or in combination of two or more. For example, the second magnetic pattern 112a may include a composite material such as CoFe, NiFe, FeCr, CoFeNi, PtCr, CoCrPt, CoFeB, NiFeSiB, CoFeSiB,

The tunnel barrier pattern 110a may be disposed between the first and second magnetic patterns 108a and 112a. Accordingly, the first and second magnetic patterns 108a and 112a may not directly contact each other.

In the exemplary embodiments, the tunnel barrier pattern 110a may include a metal oxide having an insulating property. For example, the tunnel barrier pattern 110a may include magnesium oxide (MgOx) or aluminum oxide (AlOx).

In the exemplary embodiments, the stacking structure of the MTJ structure 114a is not limited. The MTJ structure 114a has been described in which the free layer is disposed above the pinned layer. However, in another embodiment, the free film may be disposed below the immobilizing film.

The upper electrode 126b may be provided on the central portion of the MTJ structure 114a to cover only a portion of the upper surface of the MTJ structure 114a.

The top electrode 126b may have a top width that is wider than a bottom width. The maximum width of the upper electrode 126b may be equal to or less than the width of the top of the MTJ structure 114a.

In an exemplary embodiment, the lower portion of the upper electrode 126b may have a constant second width, and the upper portion of the upper electrode 126b may have a width that is wider than the second width. The width of the upper portion of the upper electrode 126b may be gradually increased.

In some exemplary embodiments, the width of the upper electrode 126b may gradually increase from the bottom to the top.

The upper electrode 126b may be provided as part of a hard mask in an etching process for forming the MTJ structure 114a and the lower electrode 106a.

The upper electrode 126b may be formed using a metal or a metal nitride. The upper electrode may comprise at least one of a metal such as, for example, tungsten, titanium, tantalum, iron or the like or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride and the like. In an exemplary embodiment, the top electrode may comprise tungsten.

The sidewall capping pattern 122b may be formed to surround the sidewalls of the upper electrode 126b on the MTJ structure 114a. The side wall capping pattern 122b may cover an edge of the MTJ structure 114a.

The sidewall capping pattern 122b may include an insulating material. The sidewall capping pattern 122n may be provided as part of the hard mask in an etching process for forming the MTJ structure 114a and the lower electrode 106a. In an exemplary embodiment, the sidewall capping pattern 122b may comprise silicon nitride, silicon oxynitride, or silicon oxide.

The mask structure 128a including the upper electrode 126b and the sidewall capping pattern 122b may have a shape covering the upper surface of the MTJ structure 114a. The lower surface of the mask structure 128a may have substantially the same area as the upper surface of the MTJ structure 114a.

The lower portion of the mask structure 128a may be wider than the upper portion.

In an exemplary embodiment, the lower portion of the mask structure 128a may have a constant third width, and the upper portion of the mask structure 128a may have a width that is narrower than the third width. The width of the upper portion of the mask structure 128a may be gradually reduced.

In some exemplary embodiments, the mask structure 128a can be progressively reduced in width from the bottom to the top.

In an exemplary embodiment, the exposed area of the upper electrode 126b on the upper surface of the mask structure 128a may be wider than the exposed area of the sidewall capping pattern 122b. In an exemplary embodiment, only the upper electrode 126b may be exposed on the upper surface of the mask structure 128a. The side wall capping pattern 122b may be exposed to the side wall of the mask structure 128a.

The MTJ structure 114a and the lower electrode 106a may be formed using the mask structure 128a as an etch mask. Since the upper electrode 126b is not exposed to the side wall of the mask structure 128a, the exposed area of the upper electrode 126b may be reduced. Accordingly, the generation of conductive etch by-products generated by the upper electrode 126b during the etching process is reduced, and the etching by-products are redeposited on the side walls of the patterned MTJ structure 114a and the lower electrode 106a, The second magnetic patterns 108a and 112a can be prevented from being short-circuited.

FIGS. 2 to 12 are cross-sectional views and plan views for explaining a method of manufacturing a magnetoresistive memory element according to exemplary embodiments. FIG.

Figs. 2 to 4, Figs. 6 to 10 and 12 are sectional views, and Figs. 5 and 11 are plan views.

Referring to FIG. 2, an interlayer insulating film 102 is formed on a substrate 100, and a contact plug 104 is formed to penetrate the interlayer insulating film 102 to contact an upper surface of the substrate 100.

The interlayer insulating film 102 may be formed to include an oxide such as, for example, silicon oxide. The interlayer insulating layer 102 may be formed through a chemical vapor deposition process, an atomic layer deposition process, or a spin coating process.

The contact plug 104 penetrates the interlayer insulating layer 102 to form a contact hole exposing the upper surface of the substrate 100. A conductive layer is formed on the substrate 100 and the interlayer insulating layer 102 to fill the contact hole, And then planarizing the upper surface of the conductive film until the upper surface of the interlayer insulating film 102 is exposed.

The lower electrode film 106, the MTJ film 114, and the mold film 116 can be sequentially formed on the interlayer insulating film 102 and the contact plug 104.

The lower electrode film 106 may be formed using a metal or a metal nitride.

The MTJ layer 114 may include a first magnetic layer 108, a tunnel barrier layer 110, and a second magnetic layer 112.

The first magnetic layer 108 may include, for example, a pinning layer, a lower ferromagnetic film, an antiferromagnetic coupling spacer film, and an upper ferromagnetic film. At this time, the fixed film may be formed of, for example, FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2, (FeF2), iron chloride (FeCl2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), chromium can do. The upper and lower ferromagnetic films may be formed to include a ferromagnetic material including at least one of iron (Fe), nickel (Ni), and cobalt (Co), for example. The antiferromagnetic coupling spacer film may comprise at least one of, for example, ruthenium (Ru), iridium (Ir) or rhodium (Rh).

The tunnel barrier film 110 may include, for example, aluminum oxide or magnesium oxide.

The second magnetic layer 112 may be provided as a free layer and may include a ferromagnetic material including at least one of iron (Fe), nickel (Ni), and cobalt (Co), for example.

The mold film 116 may include an upper electrode and a sidewall capping film to be formed later, and a material having an etch selectivity, respectively. It may also include a material that can be easily etched by an isotropic etching process.

In an exemplary embodiment, the mold film 116 may comprise silicon oxide. As another example, the mold film 116 may include silicon nitride or silicon oxynitride. The mold layer 116 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

The mold film 116 may be provided as a mold pattern for forming the upper electrode. Accordingly, the mold film 116 may be formed to have a height equal to or higher than the height of the target upper electrode.

Referring to FIG. 3, a photoresist pattern 118 is formed on the mold film 116.

Specifically, a photoresist film is coated on the mold film 116, and the photoresist pattern 118 is formed through an exposure and development process. The photoresist pattern 118 may include holes 120 exposing a portion where the upper electrode is to be formed. The bottom surface of the holes 120 may overlap the top surface of the contact plug 104.

Referring to FIGS. 4 and 5, the mold film 116 is anisotropically etched using the photoresist pattern 118 as an etch mask to form a mold pattern 116a. Thereafter, the photoresist pattern 118 is removed. That is, the mold pattern 116a may be formed through a photolithography process.

The mold pattern 116a may include first holes 120a formed from the photoresist pattern 118. [ An upper surface of the MTJ layer 114 may be exposed on a bottom surface of the first holes 120a.

In an exemplary embodiment, the size of the interior of the first holes 120a may be the same as the size of the mask structure including the top electrode and the sidewall capping pattern.

Referring to FIG. 6, the capping layer 122 is conformally formed along the sidewalls and the bottom surface of the first hole 120a and the top surface of the mold pattern 116a.

The capping layer 122 may include an insulating material. The capping layer 122 may be provided as part of the hard mask in the process of etching the lower MTJ layer 114. Accordingly, the capping layer 122 may include a material having an etch selectivity with the MTJ layer 114. In addition, the capping layer 122 may include a material having the etch selectivity with the mold pattern 116a.

In an exemplary embodiment, when the mold pattern 116a comprises silicon oxide, the capping layer 122 may comprise silicon nitride or silicon oxynitride. In an exemplary embodiment, when the mold pattern 116a comprises silicon nitride or silicon oxynitride, the capping layer 122 may comprise silicon oxide. The capping layer 122 may be formed by an atomic layer deposition process or a chemical vapor deposition process.

Referring to FIG. 7, the capping layer 122 is anisotropically etched to form a preliminary sidewall capping pattern 122a on the sidewalls of the first holes. Further, the preliminary sidewall capping patterns 122a may form second holes 124 whose inner width is narrower than the first holes 120a.

In the anisotropic etching process, the capping layer 122 formed on the upper surface of the mold pattern 116a and the bottom surface of the first hole 120a may be etched. Therefore, the upper surface of the MTJ layer 114 may be exposed on the bottom surface of the second holes 124. The preliminary sidewall capping pattern 122a may have a ring shape in plan view.

In the anisotropic etching process, the capping films formed on the upper sidewalls of the first holes 120a may be partially etched. Therefore, the preliminary sidewall capping pattern 122a may have a top width narrower than a bottom width.

In an exemplary embodiment, the bottom of the preliminary sidewall capping pattern 122a may have a constant first width, and the top of the preliminary sidewall capping pattern 122a may have a width less than the first width. The width of the upper portion of the preliminary sidewall capping pattern 122a may be gradually reduced.

In some exemplary embodiments, the width of the preparatory sidewall capping pattern 122a may be gradually reduced from bottom to top.

Accordingly, the upper width of the second holes 124 may be wider than the lower width. In an exemplary embodiment, the lower portion of the second hole 124 may have a constant second width, and the upper portion of the second hole 124 may have a width that is wider than the second width. The width of the upper portion of the second hole 124 may be gradually increased. Therefore, the second hole 124 may have the widest width at the top.

In some exemplary embodiments, the second holes 124 may be gradually increased in width from the bottom to the top.

8, an upper electrode film 126 filling the inside of the second hole 124 is formed on the upper surface of the mold pattern 116a, the preliminary sidewall capping pattern 122a, and the upper surface of the MTJ film 114 .

The upper electrode film 126 may be provided as a part of the hard mask in the process of etching the lower MTJ film 114 and the lower electrode film 106.

The upper electrode film 126 may be formed using a metal or a metal nitride. The upper electrode film 126 may include at least one of a metal such as tungsten, titanium, tantalum, iron or the like or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, or the like. In an exemplary embodiment, the upper electrode film 126 may comprise at least tungsten.

The upper electrode film 126 may be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.

Referring to FIG. 9, the upper electrode film 126 is planarized to expose the upper surface of the mold pattern 116a. The planarization process may include a chemical mechanical polishing and / or an etchback process. Thus, a preliminary mask structure 128 including a preliminary upper electrode 126a and a preliminary sidewall capping pattern 122a is formed. The preliminary mask structure 128 may be in direct contact with the MTJ film 114.

The preliminary upper electrode 126a may have the same shape as the second hole. Therefore, the upper width of the preliminary upper electrode 126a may be wider than the lower width.

In an exemplary embodiment, the lower portion of the preliminary upper electrode 126a may have a constant second width, and the upper portion of the preliminary upper electrode 126a may have a width wider than the second width. The width of the upper portion of the preliminary upper electrode 126a may be gradually increased. Therefore, the uppermost portion of the preliminary upper electrode 126a may have the widest width.

In some exemplary embodiments, the width of the preliminary upper electrode 126a may gradually increase from the bottom to the top.

Referring to FIGS. 10 and 11, the mold pattern 116a is removed. The removal process may include an isotropic etching process.

In an exemplary embodiment, if the mold pattern 116a comprises silicon oxide, it may be removed through a wet etch process using an etchant containing hydrofluoric acid. If the mold pattern 116a includes silicon nitride or silicon oxynitride, it may be removed through a wet etching process using an etchant containing at least one of hydrofluoric acid, phosphoric acid, and sulfuric acid.

Therefore, the upper surface of the MTJ layer 114 may be exposed to a portion where the preliminary mask structure 128 is not formed. The preliminary mask structure 128 may be provided as a hard mask for etching the MTJ film 114. As described, the preliminary mask structure 128 may be formed through a damascene process.

In the upper surface of the preliminary mask structure 128, the exposed area of the preliminary upper electrode 126a may be wider than the exposed area of the preliminary sidewall capping pattern 122a. In addition, the preliminary upper electrode 126a may not be exposed on the sidewall of the preliminary mask structure 128.

Referring to FIG. 12, the MTJ film 114 and the lower electrode film 106 are sequentially subjected to anisotropic etching using the preliminary mask structure 128 as an etching mask. Thus, a lower electrode 106a, an MTJ structure 114a, an upper electrode 126b, and a sidewall capping pattern 122b that are in contact with the contact plug 104 are formed. That is, a mask structure 128a including the upper electrode 126b and the side wall capping pattern 122b surrounding the side walls of the upper electrode 126b may be formed on the MTJ structure 114a.

The anisotropic etching process may include a dry etching process such as ion beam etching, sputter etching, and RF (radio-frequency) etching. In an exemplary embodiment, the MTJ film 114 and the lower electrode film 106 can be effectively etched by performing the ion beam etching process.

However, since the ion beam etching process electrically accelerates ions or the like and impinges on the corneal epithelium, surface atoms of the corneal epithelium can be etched by the collision of the ions. Therefore, during the anisotropic etching process, the upper sidewall of the spare side wall capping pattern 122a may be partially etched by the ion bombardment. However, the preliminary upper electrode 126a is exposed on the upper surface of the preliminary mask structure 128, and the exposed area of the preliminary side wall capping pattern 122a may be smaller than the exposed area of the preliminary upper electrode 126a . In addition, the top width of the spare side wall capping pattern 122a may be narrower than the bottom width. Therefore, in the anisotropic etching process, the ions mainly collide with the preliminary upper electrode 126a having a wide exposed area, and since the preliminary upper electrode has a higher strength than the preliminary side wall capping pattern 122a, The preliminary sidewall capping pattern 122a may not be excessively removed, damaged or collapsed. Thus, the underlying corneal epithelium can be etched using the preliminary mask structure 128.

During the etching process, the first etch by-products generated by the etched preliminary sidewall capping pattern 122a may be redeposited on the sidewalls of the etched MTJ layer 114. However, since the preliminary sidewall capping pattern 122a is formed of an insulating material, electrical failure due to redeposition of the first etch byproduct may not occur.

In addition, when performing the anisotropic etching process, the sidewall of the preliminary upper electrode 126a may be exposed only to the upper surface of the preliminary upper electrode 126a without being exposed to the outside. Therefore, the exposed area of the preliminary upper electrode 126a is greatly reduced. Accordingly, the amount of the second etching by-product having conductivity, which is generated by partially etching the preliminary upper electrode 126a during the anisotropic etching process, can be reduced. Therefore, the electrical failure caused by the second etching by-product being re-deposited on the sidewall of the partially etched MTJ layer 114 can be reduced.

In the exemplary embodiment, the etch process partially etches the upper edge of the preliminary mask structure 128 to form a mask structure 128a including the upper electrode 126b and the sidewall capping pattern 122b. Can be formed. The lower portion of the mask structure 128a may be wider than the upper portion.

 In an exemplary embodiment, the lower portion of the mask structure 128a may have a constant third width, and the upper portion of the mask structure 128a may have a width that is narrower than the third width. The width of the upper portion of the mask structure 128a may be gradually reduced.

In some exemplary embodiments, the mask structure 128a can be progressively reduced in width from the bottom to the top.

In an exemplary embodiment, the top electrode 126b may have a top width that is wider than a bottom width. In an exemplary embodiment, the lower portion of the upper electrode 126b may have a constant second width, and the upper portion of the upper electrode 126b may have a width that is wider than the second width. The width of the upper portion of the upper electrode 126b may be gradually increased.

In some exemplary embodiments, the width of the upper electrode 126b may gradually increase from the bottom to the top.

In an exemplary embodiment, the sidewall capping pattern 122b may have a top width that is narrower than a bottom width. In an exemplary embodiment, the bottom of the sidewall capping pattern 122b may have a constant first width, and the top of the sidewall capping pattern 122b may be narrower than the first width. The width of the upper portion of the sidewall capping pattern 122b may be gradually reduced.

In some exemplary embodiments, the sidewall capping pattern 122b may be gradually reduced in width from the bottom to the top.

In an exemplary embodiment, the area of the upper electrode 126b exposed on the upper surface of the mask structure 128a may be wider than the area of the sidewall capping pattern 122b. In an exemplary embodiment, only the upper electrode 126b may be exposed on the upper surface of the mask structure 128a. The side wall capping pattern 122b may be exposed to the side wall of the mask structure 128a.

13 to 18 are cross-sectional views illustrating a method of manufacturing a magnetoresistive memory element according to exemplary embodiments.

The method of manufacturing a magnetoresistive memory element described below is similar to the method described with reference to Figures 2 to 12, except that some of the film is additionally deposited.

Referring to FIG. 13, an interlayer insulating film 102 is formed on a substrate 100, and a contact plug 104 is formed to penetrate the interlayer insulating film 102 and contact the upper surface of the substrate 100.

The lower electrode film 106, the MTJ film 114, the etching stopper film 130, and the mold film 116 can be sequentially formed on the interlayer insulating film 102 and the contact plug 104.

In an exemplary embodiment, the etch stop layer 130 may comprise an insulating material. For example, the etch stop layer 130 may include silicon nitride or silicon oxynitride. In an exemplary embodiment, the etch stop layer 130 may be formed to a thickness of 10 to 300 ANGSTROM so that the etch stop layer 130 can be easily etched through a subsequent etching process.

Referring to FIG. 14, a photoresist pattern including holes is formed on the mold film 116 (FIG. 13). The mold film 116 is anisotropically etched using the photoresist pattern as an etch mask to form a mold pattern 116a. The mold pattern 116a may include first holes 120a. The upper surface of the etch stop layer 130 may be exposed on the bottom surface of the first holes 120a.

Referring to FIG. 15, a conformal capping layer (not shown) is formed along the sidewalls and bottom of the first hole 120a and the upper surface of the mold pattern 116a. The process of forming the capping film may be the same as that described with reference to FIG.

The capping layer is anisotropically etched and then anisotropically etched the etch stop layer 130 to form a preliminary sidewall capping pattern 122a on the sidewalls of the mold pattern 116a and the preliminary sidewall capping pattern 116a, A pre-etching stopper film pattern 130a is formed under the pattern 122a. Second holes 124 having a narrower inner width than the first holes 120a are formed by the preliminary sidewall capping pattern 122a and the preliminary etching stopper film pattern 130a. The MTJ layer 114 may be exposed at the bottom of the second holes 124.

In an exemplary embodiment, the preliminary sidewall capping pattern 122a and the pre-etch stop film pattern 130a may be formed of the same insulating material, for example, silicon nitride.

16, the second hole 124 is formed on the upper surface of the mold pattern 116a, the preliminary sidewall capping pattern 122a, the pre-etching stopper film pattern 130a, and the MTJ film 114, An upper electrode film (not shown) is formed. Thereafter, the upper electrode film is planarized so that the upper surface of the mold pattern 116a is exposed. Thus, a preliminary mask structure 128 including the preliminary upper electrode 126a and the preliminary side wall capping pattern 122a is formed. The preliminary upper electrode 126a may be in direct contact with the upper surface of the MTJ film 114.

The above-described processes may be the same as those described with reference to Figs. 8 and 9. Fig.

Referring to FIG. 17, the mold pattern 116a is removed. The removal process may include an isotropic etching process. The MTJ film 114 may be covered with the preliminary etching stopper film pattern 130a and the preliminary mask structure 128.

Referring to FIG. 18, the exposed preliminary etching stopper film pattern 130a is anisotropically etched using the preliminary mask structure 128 as an etching mask to form an etching stopper film pattern 130b. Subsequently, the MTJ film 114 and the lower electrode film 106 are anisotropically etched in order. Thus, a variable resistance structure (not shown) including the lower electrode 106a, the MTJ structure 114a, the upper electrode 126b, the sidewall capping pattern 122b, and the etch stop film pattern 130b that is in contact with the contact plug 104 129a can be formed.

That is, the etching stopper film pattern 130b may be formed under the side wall capping pattern 122b. The etch stop layer pattern 130b may surround the upper electrode 126b. Thus, the etch stop layer pattern 130b may be used as part of the sidewall capping pattern of the mask structure 128a. For example, the mask structure 128a may include the upper electrode 126b, the sidewall capping pattern 122b And the etching stopper film pattern 130b.

In the exemplary embodiment, when the sidewall capping pattern 122b and the etch stop film pattern 130b are formed of the same material, the magnetoresistance memory device shown in Figs. 1A and 1B can be manufactured.

19 is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments.

19 is substantially the same as or similar to the magnetoresistive memory element described with reference to FIGS. 1A and 1B, except that the barrier pattern 140 is provided between the MTJ structure 114a and the mask structure 128a. Therefore, detailed description of the repeated configuration will be omitted.

19, the magnetoresistive memory device includes an interlayer insulating film 102 formed on a substrate 100 and a contact plug 104 penetrating the interlayer insulating film 102 and contacting the substrate 100 . A variable resistance structure 129b may be provided on the interlayer insulating layer 102 in contact with the upper surface of the contact plug 104. [ The variable resistor structure 129b may include a lower electrode 106a, an MTJ structure 114a, a barrier pattern 140, an upper electrode 126b, and a sidewall capping pattern 122b.

The lower electrode 106a and the MTJ structure 114a may be the same as those described with reference to FIGS. 1A and 1B. In addition, the mask structure 128a including the upper electrode 126b and the sidewall capping pattern 122b may be the same as that described with reference to Figs. 1A and 1B.

The upper surface of the barrier pattern 140 is covered with the upper electrode 126b and the upper surface of the upper electrode 126b and the side wall capping pattern 122b are formed on the barrier pattern 140, It is possible to have a larger area than the lower surface of the lower surface. That is, the bottom surface of the upper electrode 126b may be formed at the central portion of the upper surface of the barrier pattern 140. [

In an exemplary embodiment, the barrier pattern 140 may comprise titanium, titanium nitride, tantalum, tantalum nitride.

The resistance memory element may be formed through the following process.

First, an interlayer insulating film is formed on a substrate, and a contact plug penetrating the interlayer insulating film and in contact with the upper surface of the substrate is formed. The lower electrode film, the MTJ film, the barrier film, and the mold film may be sequentially formed on the interlayer insulating film and the contact plug. That is, the interlayer insulating film, the contact plug, the lower electrode film, the MTJ film, and the mold film can be formed in the same manner as described with reference to FIG. However, after the MTJ film is formed, an additional barrier film may be further formed.

Thereafter, the same processes as those described with reference to FIGS. 3 and 4 are performed to form a mold pattern on the barrier film. That is, the barrier film may be exposed on the bottom surface of the mold pattern. Therefore, in the subsequent process, the upper electrode and the sidewall capping pattern formed in the first holes of the mold pattern may be brought into contact with the barrier film.

Thereafter, the same process as described with reference to Figs. 5 to 12 can be performed to fabricate the resistive memory device shown in Fig.

20 is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments.

20 is similar or similar to the magnetoresistive memory element described with reference to FIGS. 1A and 1B except that the barrier pattern 125 is provided along the sidewalls and bottom of the upper electrode 126b. Therefore, detailed description of the repeated configuration will be omitted.

Referring to FIG. 20, the magnetoresistive memory device may include an interlayer insulating film 102 formed on a substrate 100 and a contact plug 104 penetrating the interlayer insulating film 102 and contacting the substrate. A variable resistance structure 129c may be provided on the interlayer insulating layer 102 in contact with the upper surface of the contact plug 104. [ The variable resistor structure 129c may include a lower electrode 106a, an MTJ structure 114a, an upper electrode 126b, a barrier pattern 125, and a sidewall capping pattern 122b. The mask structure 128b may include an upper electrode 126b, a barrier pattern 125, and a sidewall capping pattern 122b.

The lower electrode 106a and the MTJ structure 114a may be the same as those described with reference to FIGS. 1A and 1B. In addition, the upper electrode 126b and the sidewall capping pattern 122b may be the same as those described with reference to Figs.

The barrier pattern 125 may be provided along the sidewalls and the bottom of the upper electrode 126b. The barrier pattern 125 may be provided between the sidewall of the upper electrode 126b and the sidewall capping pattern 122b and between the bottom of the upper electrode 126b and the MTJ structure 114a.

In an exemplary embodiment, the barrier pattern 125 may comprise titanium, titanium nitride, tantalum, tantalum nitride.

The above-mentioned magnetoresistive memory element can be manufactured by the following method.

First, the processes described with reference to FIGS. 2 to 7 are performed in the same manner.

Thereafter, a conformal barrier film is formed on the upper surface of the mold pattern 116a, the preparatory sidewall capping pattern 122a, and the upper surface of the MTJ film 114. An upper electrode film filling the inside of the third hole is formed on the barrier film. The process of forming the upper electrode film is the same as that described with reference to Fig.

Since the upper electrode film is formed on the barrier film, a barrier film pattern may be formed along the side walls and the bottom of the upper electrode formed in the subsequent process.

Subsequently, the magnetoresistance memory element shown in FIG. 20 can be formed by performing the same process as described with reference to FIGS. 9 to 12.

21 is a cross-sectional view illustrating a magnetoresistive memory element according to exemplary embodiments.

Referring to FIG. 21, a substrate 200 having a first region and a second region is provided. The first region may be a cell region in which magnetoresistive memory cells are formed. The second region may be located in the periphery of the first region, and may be a ferry region for forming ferrier circuits.

The substrate 200 of the first and second regions may be divided into an active region and a field region.

In the first region, the active regions may be regularly arranged with an isolated island shape. The first transistors 216 may be provided in the respective active regions. For example, two first transistors 216 may be formed in each of the active regions including two first gates 211, and a central region of the active region may be formed in a common first source region ( 212, and both edge portions of the active region may be provided to the first drain regions 214. [0034] FIG. The first transistor 216 may be a buried gate type transistor formed in the trench 204 formed in the substrate. The first gate 211 includes a first gate insulating layer pattern 206, a first gate electrode 208 and a first hard mask pattern 210 located in the trench 204 formed in the substrate 200 . The first gate 211 may have a line shape extending along the first direction.

As another example, the first transistor 216 may be a planar transistor formed on the surface of the substrate 200 by a first gate 211.

A source line 232 extending in contact with the first source regions 212 may be provided. The source line 232 may extend along the first direction. The source line 232 may comprise at least one of, for example, a metal such as tungsten, titanium, tantalum or the like or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, or the like.

A second transistor 218 may also be provided on the substrate 200 of the second region to form ferrier circuits. The second transistor 218 may be a planar transistor. For example, the second transistor 218 may include a second gate 225 and a second source / drain region 226 formed on a substrate 200 of a second region. The second gate 225 may include a second gate insulating layer pattern 220, a second gate electrode 222, and a second hard mask pattern 224.

A first interlayer insulating film 230 is provided on the substrate 200 of the first and second regions. The first interlayer insulating layer 230 may sufficiently cover the source line 232 and the first and second transistors 216 and 218. The first interlayer insulating film 230 may have a flat upper surface. Therefore, the upper surface of the first interlayer insulating film 230 may be located higher than the upper surface of the source line 232. For example, the first interlayer insulating layer 230 may include a first lower interlayer insulating layer 230a and a second lower interlayer insulating layer 230b. The source line 232 may be provided through the first lower interlayer insulating layer 230a.

And a contact plug 234 penetrating the first interlayer insulating film 230 of the first region and contacting the first drain regions 214, respectively. That is, the contact plugs 234 may be formed through the first interlayer insulating layer 230. The upper surface of the contact plugs 234 may be higher than the upper surface of the source line 232.

A pad pattern 236 may be provided on each of the contact plugs 234. In addition, an insulating film pattern 238 may be provided between the pad patterns 236. The pad patterns 236 may be disposed when direct contact between the contact plug 234 and the variable resistance structure 129 is difficult. Therefore, when the contact plug 234 and the variable resistance structure 129 can be in direct contact with each other, the pad pattern 236 may not be provided.

A variable resistance structure 129 may be provided on each of the pad patterns 236.

In an exemplary embodiment, the variable resistance structure 129 may have the same structure as that described with reference to FIG. As another example, the variable resistance structure may have the same structure as the variable resistance structure of FIG. 19 or the variable resistance structure of FIG.

The variable resistor structure 129 may include a lower electrode 106a, an MTJ structure 114a, an upper electrode 126b, and a sidewall capping pattern 122b. The variable resistance structure includes the upper electrode 126b and the sidewall capping pattern 122b provided in the mask structure 128a so that the first and second magnetic patterns 108a and 112a of the MTJ structure 114a are short- Can be reduced.

An insulating capping pattern 240a may be formed on the upper surface of the insulating film pattern 238 and the sidewalls of the variable resistor structure 129. The insulating capping pattern 240a may not be formed on the upper surface of the variable resistance structure 129. [ The insulating capping pattern 240a may include, for example, silicon nitride.

An upper interlayer insulating film 242 may be provided on the insulating capping pattern 240a to cover the variable resistor structure 129. [

The upper interlayer insulating film 242 may include silicon oxide.

A bit line 250 is provided which penetrates the upper interlayer insulating film 242 and contacts the upper surface of the variable resistance structure 129. The bit line 250 may extend in a second direction perpendicular to the first direction while contacting the plurality of upper electrodes 126b. A plurality of bit lines 250 may be provided in parallel with each other.

The bit line 250 may have a structure in which a barrier metal pattern 246 and a metal pattern 248 are stacked. The barrier metal pattern 246 may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The metal pattern 248 may include copper, tungsten, aluminum, and the like.

The upper surface of the bit line 250 and the upper surface of the upper interlayer insulating film 242 may be substantially planar. In some embodiments, the bit line 250 is disposed in the upper interlayer insulating layer 242 and the bit line 250 on the upper interlayer dielectric layer 242 and the upper portion of the variable resistance structures 129 A via plug may be further disposed in the upper interlayer insulating film 242 to connect the electrodes 126b

Although not shown, an interlayer insulating film covering the upper interlayer insulating film 242 and the bit line 250 may be further provided.

22 to 28 are cross-sectional views for explaining a method of manufacturing a magnetoresistive memory element.

22, an element isolation layer 202 is formed on a substrate 200 to divide the substrate 200 into an active region and a field region. The substrate 200 may be divided into a first region where memory cells are formed and a second region where peripheral circuits are formed. The device isolation layer 202 may be formed through a shallow trench isolation (STI) process. The active regions may be regularly arranged with isolated island shapes.

First transistors 216 are formed on the substrate 200 of the first region. In the isolated active region, two first transistors 216 may be formed. For example, the first transistors 216 may be buried gate type transistors. In order to form the first transistors 216, a mask pattern is formed on the substrate 200, a line-shaped trench 204 extending in a first direction by etching the substrate using the mask pattern, . Two trenches 204 may be formed in each active region. A first gate 211 including a first gate insulating layer pattern 206, a first gate electrode 208 and a first hard mask pattern 210 is formed in the trenches 204. In addition, impurities are implanted into the active regions on both sides of the first gate 211 to form the first source region 212 and the first drain region 214, respectively. The first source region may be provided as a common source region to the two first transistors 216.

In the present embodiment, the first transistors 216 are described as buried gate transistors, but the present invention is not limited thereto. For example, the first transistors may be planar gate type transistors.

The second transistor 218 included in the peripheral circuit is formed on the substrate of the second region. For example, the second transistor 218 may be a transistor of a planar gate type. In order to form the second transistor 218, a second gate insulating film, a second gate electrode film, and a second hard mask pattern 224 are formed on the substrate 200. The second gate insulating film pattern and the second gate electrode film are etched using the second hard mask pattern 224 to form the second gate insulating film pattern 220 and the second gate electrode 222. A second gate 225 including the second gate insulating film pattern 220, the second gate electrode 222 and the second hard mask pattern 224 may be formed. Further, the second gate 225 ) Impurity is implanted into the active regions on both sides to form the second source / drain regions 226, respectively.

Referring to FIG. 23, a first lower interlayer insulating film 230a covering the first and second transistors 216 and 218 is formed on the substrate 200 of the first and second regions. Thereafter, the planarization process may be performed such that the upper surface of the first lower interlayer insulating film 230a is flat. The planarization process may include a chemical mechanical polishing or an etchback process.

A portion of the first lower interlayer insulating film 230a of the first region is etched to form first openings 231 exposing the surfaces of the first source regions 212. [ The first openings 231 may have a shape extending in the first direction. A first conductive layer is formed and planarized in the first openings 231 to form source lines 232 in contact with the first source regions 212. The source lines 232 may be formed to include at least one of, for example, a metal such as tungsten, titanium, tantalum, or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, or the like.

A second lower interlayer insulating film 230b is formed on the first lower interlayer insulating film 230a and the source lines 232. [ Since the upper surface of the first lower interlayer insulating film 230a is flat, the second lower interlayer insulating film 230b may have a flat upper surface. The first and second lower interlayer insulating films 230a and 230b may be formed of silicon oxide.

Second openings 233 are formed through the first and second lower interlayer insulating films 230a and 230b of the first region to expose the first drain regions 214, respectively. A second conductive layer is formed and planarized in the second openings 233 to form contact plugs 234 which are in contact with the first drain regions 214, respectively. The contact plugs 234 may be formed to include at least one of, for example, a metal such as tungsten, titanium, tantalum, or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, and the like.

Accordingly, a first interlayer insulating film 230 including first and second lower interlayer insulating films 230a and 230b is formed on the substrate 200 of the first and second regions. The contact plugs 234 and the source lines 232 are formed in the first interlayer insulating layer 230 of the first region. The upper surfaces of the contact plugs 234 may be located higher than the upper surface of the source lines 232.

Referring to FIG. 24, a pad film is formed on the first interlayer insulating film 230. The pad film may be formed to include at least one of a metal such as tungsten, titanium, tantalum, or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, and the like. The pad film is etched to form a pad pattern 236 which contacts the contact plugs 234, respectively.

An insulating film pattern 238 filling the space between the pad patterns 236 is formed. The insulating film pattern 238 may be formed using silicon nitride or silicon oxide.

Alternatively, the pad pattern 236 may be formed through a damascene process. That is, the pad pattern 236 may be formed by first forming an insulating film pattern 238 including an opening in a portion where the pad pattern 236 is to be formed, and forming a pad film in the opening and planarizing the pad film.

Referring to FIG. 25, an island-shaped variable resistance structure 129 is formed to contact the pad patterns 236, respectively. The variable resistor structure 129 may include a lower electrode 106a, an MTJ structure 114a, an upper electrode 126b, and a sidewall capping pattern 122b.

In an exemplary embodiment, the variable resistance structure may be formed in the same manner as the variable resistance structure shown in Figs. 1A and 1B. In this case, the variable resistance structure may be formed through the same process as described with reference to FIGS. 2 to 12.

As another example, the variable resistance structure may be formed in the same manner as the variable resistance structure shown in FIG. As another example, the variable resistance structure may be formed in the same manner as the variable resistance structure shown in FIG.

Referring to FIG. 26, an insulating capping layer 240 is formed on the insulating layer pattern 238 and the variable resistance structure 129. An upper interlayer insulating film 242 is formed on the insulating capping layer 240.

The insulating capping layer 240 may be conformally formed along the surfaces of the variable resistance structures 129 and may not be buried between the variable resistance structures 129. The insulating capping layer 240 may include silicon nitride, silicon oxynitride, or the like.

The upper interlayer insulating film 242 may include silicon oxide. In an exemplary embodiment, the upper interlayer insulating film 242 may further include a step of planarizing the surface so as to have a flat upper surface.

Referring to FIG. 27, the upper interlayer insulating layer 242 and a portion of the insulating capping layer 240 are etched to form a groove 244 for forming a bit line. The groove 244 may have a shape extending in a second direction perpendicular to the first direction. In some embodiments, the grooves 244 may be formed in plurality,

In the etching process, the insulating capping layer 240 formed on the upper electrode 126b is removed to form an insulating capping pattern 240a. Therefore, the upper electrode 126b may be exposed on the bottom surface of the groove 244.

Referring to FIG. 28, a bit line 250 is formed in the groove 244. The bit line may extend in a second direction. The bit line 250 may be formed by forming a barrier metal film on sidewalls and bottom surfaces of the groove 244, forming a metal film on the barrier metal film to fill the groove 244, and planarizing the metal film. The barrier metal film may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The metal film may include copper, tungsten, aluminum, and the like. Thus, the bit line 250 may include a barrier metal pattern 246 and a metal pattern 248. The bit line 250 may contact the upper electrode 126b.

A groove 242 is not formed in the upper interlayer insulating film 242 and a via plug is formed in the upper interlayer insulating film 242 so that the bit line 250 on the upper interlayer insulating film 242 And the upper electrodes 126b of the variable resistance structures 129 may be connected. In other embodiments, a plurality of bit lines 250 may be formed in the grooves 244, respectively, or may be formed on the upper interlayer insulating film 242, or may be disposed in the first direction have

Thereafter, although not shown, an interlayer insulating film covering the upper interlayer insulating film 242 and the bit line 250 can be further formed.

The magnetoresistance memory device of each embodiment of the present invention can be used as a memory included in an electronic product such as a mobile device, a memory card, a computer, and the like.

100, 200: substrate 102: interlayer insulating film
104, 234: a contact plug 106a: a lower electrode
108a: first magnetic pattern 110a: tunnel barrier pattern
112a: second magnetic pattern 114a: MTJ structure
116a: Mold pattern 122b, 132a: Side wall capping pattern
126b: upper electrode 128a: mask structure
129, 129a, 129b: Variable resistance structure
140: barrier pattern 212: first source region
214: first drain region 216: first transistor
218: second transistor 230: first interlayer insulating film
232: source line 236: pad pattern
240a: Insulating capping pattern 242: Upper interlayer insulating film
250: bit line

Claims (20)

A lower electrode formed on a substrate;
An MTJ structure provided on the lower electrode; And
And a sidewall capping pattern disposed on the MTJ structure, the sidewall capping pattern surrounding the upper electrode and the upper electrode sidewall. The magnetoresistive memory element according to claim 1, wherein the upper electrode has an upper width larger than a lower width. The magnetoresistive memory element according to claim 1, wherein the upper electrode has a constant width at a lower portion and a width gradually increases at an upper portion. 2. The magnetoresistive memory element of claim 1, wherein the sidewall capping pattern comprises an insulating material. 5. The magnetoresistive memory element of claim 4, wherein the sidewall capping pattern comprises silicon nitride, silicon oxynitride, or silicon oxide. The magnetoresistive memory element according to claim 1, wherein the upper electrode comprises at least one selected from the group consisting of tungsten, titanium, titanium nitride, tantalum, tantalum nitride, and iron. 2. The magnetoresistive memory element of claim 1, wherein the bottom surface of the mask structure has the same size as the top surface of the MTJ structure and covers the top surface of the MTJ structure. 2. The magnetoresistive memory element of claim 1, wherein the bottom width of the mask structure is wider than the top width. 9. The magnetoresistive memory element of claim 8, wherein the mask structure has a constant width at the bottom and a progressive decrease in width at the top. 2. The device of claim 1, wherein the mask structure has a planar top surface, wherein an area of the top electrode exposed on a planar top surface of the structure is greater than an area of the sidewall capping pattern. The magnetoresistive memory element of claim 1, further comprising a barrier metal pattern between the MTJ structure and the mask structure. 2. The magnetoresistive memory element of claim 1, further comprising a barrier metal pattern surrounding the top electrode bottom between the top electrode and the sidewall capping pattern. Forming a lower electrode film, MTJ film on the substrate;
Forming an etch mask comprising a preliminary upper electrode on the MTJ film and a preliminary sidewall capping pattern on the sidewall of the preliminary upper electrode; And,
Wherein the MTJ film and the lower electrode film are anisotropically etched using the etching mask to form the lower electrode, the MTJ structure, the upper electrode, and the sidewall capping pattern. 14. The method of claim 13, wherein forming the etch mask comprises:
Forming a mold pattern including holes on the MTJ film;
Forming a preliminary sidewall capping pattern on the sidewalls inside the hole, the preliminary sidewall capping pattern having a lower width than the bottom; And,
And forming a preliminary upper electrode on the preliminary sidewall capping pattern, filling the hole and contacting the MTJ film. 15. The method of claim 14, wherein the preliminary sidewall capping pattern comprises an insulating material having an etch selectivity with the mold pattern. 15. The method of claim 14, wherein forming the preliminary sidewall capping pattern comprises:
Forming a conformally capping film on sidewalls, bottoms, and top surfaces of the mold patterns in the first holes; And,
And anisotropically etching the capping film formed on the bottom surface of the first holes and the top surface of the mold pattern. 15. The method of claim 14, wherein forming the preliminary upper electrode comprises:
Forming a preliminary upper electrode film filling the inside of the holes on the upper surface of the preliminary sidewall capping pattern and the mold pattern; And,
And planarizing the preliminary upper electrode film so that the upper surface of the mold pattern is exposed. 15. The method of claim 14, further comprising removing the mold pattern through an isotropic etching process after forming the preliminary upper electrode. Forming, on the substrate, an interlayer insulating film including a conductive pattern therein;
Sequentially forming a lower electrode film and an MTJ film on the interlayer insulating film;
Forming an etch mask comprising a preliminary upper electrode on the MTJ film and a preliminary sidewall capping pattern on the sidewall of the preliminary upper electrode;
Anisotropically etching the MTJ layer and the lower electrode layer using the etch mask to form a mask structure including a lower electrode, an MTJ structure, an upper electrode, and a sidewall capping pattern sequentially stacked on the conductive pattern; And,
And forming a wiring electrically connected to the upper electrode. 20. The method of claim 19, further comprising forming a conformally capping insulating film on the upper surface of the interlayer insulating film and the surface of the lower electrode, the MTJ structure, and the mask structure.

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