KR20170020414A - Semiconductor device - Google Patents

Abstract

A semiconductor device is disclosed. The disclosed semiconductor device includes a buffer layer and a plurality of nitride semiconductor layers on a substrate, at least one masking layer and at least one intermediate layer between the plurality of nitride semiconductor layers. Thereby, the present invention reduces defect density and tension stress.

Description

Semiconductor device

To a semiconductor device with reduced defect density and tensile stress.

Sapphire is often used as a substrate for forming a nitride semiconductor device. However, the sapphire substrate is expensive, hard, difficult to manufacture, and low in electric conductivity. When the sapphire substrate is epitaxially grown at a large diameter, it is difficult to fabricate the sapphire substrate in a large area due to warpage of the substrate itself at a high temperature due to low thermal conductivity. To overcome these limitations, a nitride-based semiconductor device utilizing a silicon substrate instead of a sapphire substrate has been developed. Since the silicon substrate has higher thermal conductivity than the sapphire substrate, the warpage of the substrate is not large even at the growth temperature of the nitride film grown at a high temperature, so that the growth of a large diameter film is possible. However, when a nitride thin film is grown on a silicon substrate, dislocation density increases due to lattice constant mismatch between the substrate and the thin film, and cracks are generated due to inconsistency of the thermal expansion coefficient. Therefore, a method for reducing the defect density and a method for preventing cracks have been extensively studied. However, when the defect density is decreased, a tensile stress is generated incidentally to reduce the defect density, while the cracks are increased or the cracks are decreased, but the defect density is increased. As described above, it is difficult to satisfy both of the reduction of defect density and the reduction of cracks in the growth of a nitride thin film on a silicon substrate.

A semiconductor device with reduced defect density and tensile stress is provided.

A semiconductor device according to an aspect of the present invention includes: a plurality of nitride semiconductor layers; At least one masking layer disposed between the plurality of nitride semiconductor layers; And at least one intermediate layer disposed between the plurality of nitride semiconductor layers on the at least one masking layer to compensate for the tensile stress.

The plurality of nitride semiconductor layers may be formed of a nitride containing gallium.

The plurality of nitride semiconductor layers may be formed of Al _x In _y Ga _{1 -xy} N (0? X, y? 1, x + y <1).

The at least one masking layer may be formed of silicon nitride or titanium nitride.

The at least one intermediate layer is _{Al x0 In y0 Ga 1 -x0- y0} N (0≤x0, y0≤1, x0 + y0≤1), step-graded _{Al x In y Ga 1 -x- y} N (0≤x , y≤1, x + y≤1), Al x1 In y1 Ga 1 -x1- y1 N / Al x2 In y2 Ga 1 -x2- y2 N (0≤x1, x2, y1, y2≤1, x1 ≠ x2 or y1? y2) superlattice, and compressive stress can be applied to the upper nitride semiconductor layer.

A substrate may be further provided under the plurality of nitride semiconductor layers.

The substrate may comprise a silicon substrate or a silicon carbide substrate.

At least one buffer layer may be further provided between the substrate and the plurality of nitride semiconductor layers.

The at least one buffer layer may comprise a nucleation layer.

The nucleation layer may be formed of AlN.

The at least one buffer layer may be formed of Al _x In _y Ga _{1 -x- y} N (0? X, y? 1, x + y? 1).

The at least one buffer layer may have a step-graded structure or a superlattice structure.

_Wherein the at least one buffer layer comprises a step graded Al _x In _y Ga _{1 -x- y} N (0? X, y? 1, x + y? 1) or Al _x1 In _y1 Ga _{1 -x1- y1} N / Al _x2 In _{y2 Ga 1 -x2- y2 N (0≤x1} , x2, y1, y2≤1, x1 ≠ x2 or y1 ≠ y2) second may be formed of a lattice.

The at least one masking layer and the at least one intermediate layer may be constructed in pairs.

At least one intermediate layer may be further disposed under the at least one masking layer.

The at least one intermediate layer may be formed of Al _x Ga _{1 -x} N (0.4 <x <1).

A semiconductor device according to another aspect of the present invention includes: a first nitride semiconductor layer; A second nitride semiconductor layer; A third nitride semiconductor layer; A masking layer between the first nitride semiconductor layer and the second nitride semiconductor layer; And an intermediate layer between the second nitride semiconductor layer and the third nitride semiconductor layer.

The first, second, and third nitride semiconductor layers may be formed of a nitride containing gallium.

A semiconductor device according to another aspect of the present invention includes: a silicon-based substrate doped with a p-type impurity; A buffer layer formed on the silicon substrate; And a nitride laminate formed on the buffer layer.

The silicon-based substrate may be a silicon substrate or a silicon carbide substrate.

The p-type impurity may include at least one selected from B, Al, Mg, Ca, Zn, Cd, Hg and Ga.

The p-type impurity may be boron (B).

The doping concentration of the p-type impurity is about 5 × 10 ¹⁷ / cm ³ To 10 &lt; ²⁰ &gt; / cm &lt; ³ &gt;.

The doping concentration of the p-type impurity is about 10 ¹⁸ / cm ³ To 5 x 10 &lt; ¹⁹ &gt; / cm &lt; ³ &gt;.

The doping concentration of the p-type impurity can be determined such that the resistivity of the silicon-based substrate is approximately 1? Cm or less.

The nitride layered body may include a plurality of nitride semiconductor layers; At least one masking layer disposed between the plurality of nitride semiconductor layers; And at least one intermediate layer provided between the plurality of nitride semiconductor layers.

A method of fabricating a semiconductor device according to an aspect of the present invention includes: preparing a silicon-based substrate doped with a p-type impurity; Forming a buffer layer on the silicon substrate; And forming a nitride laminate on the buffer layer.

In the embodiment of the present invention, the defect density can be reduced at the interface between the buffer layer and the first nitride semiconductor layer before the masking layer, and the masking layer can be formed on the first nitride semiconductor layer to enhance the reduction in defect density. By sufficiently reducing the defect density before the interlayer, even if the defect density is increased due to the use of the intermediate layer, the effect of reducing the defect density by the masking layer can be maintained or reduced. Further, tensile stress can be compensated by the intermediate layer to prevent the occurrence of cracks. Further, by regulating the composition and thickness of the intermediate layer to reduce or eliminate defect regeneration caused by the intermediate layer, a nitride semiconductor layer having a low defect density without cracks can be grown even in a structure using only one intermediate layer.

The semiconductor device according to the embodiment of the present invention can grow the nitride semiconductor layer to a desired thickness by reducing both lattice defects and tensile stress when the nitride semiconductor layer is grown on the silicon substrate or the silicon carbide substrate. It is also possible to manufacture wafers with a large diameter by using a silicon substrate or a silicon carbide substrate. A semiconductor device according to an embodiment of the present invention may be applied to a light emitting diode, a Schottky diode, a laser diode, a field effect transistor, a power device, or the like.

1A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
1B is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
2A is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
2B is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
3A shows a nitride stack with a masking layer and an intermediate layer, and an SEM image.
Figure 3b shows an OM image of the nitride stack shown in Figure 3a.
4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
8A to 8C show cracks generated in the GaN nitride semiconductor layer when Al composition of the AlxGa1-xN intermediate layer is changed.
9 illustrates an example in which a semiconductor device according to an embodiment of the present invention is applied to a light emitting device.
FIG. 10 shows a schematic structure of a semiconductor device according to an embodiment.
11 shows a schematic structure of a semiconductor device according to another embodiment.
12 is a view for defining a bow of a wafer.
FIG. 13 shows an example of a light emitting device using the semiconductor device of FIG.
14 is a graph comparing bow characteristics generated on a wafer with respect to the light emitting device of the comparative example and the light emitting device of the embodiment.
15A to 15E are views for explaining a semiconductor device according to an embodiment and a method for manufacturing another element using the same.
16A to 16F are views illustrating a semiconductor device according to another embodiment and a method of manufacturing another device using the same.
17A to 17D are views for explaining a method of manufacturing a semiconductor device according to still another embodiment.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements, and the sizes and thicknesses of the respective elements may be exaggerated for convenience of explanation. On the other hand, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

A semiconductor device according to an embodiment of the present invention includes a plurality of nitride semiconductor layers and may include at least one masking layer between the plurality of nitride semiconductor layers. And at least one intermediate layer on top of the nitride semiconductor layer above the at least one masking layer. In the following, what is referred to as "upper" or "upper" The nitride semiconductor layer may be structurally or functionally distinguishable from a semiconductor device comprising a stack of a plurality of semiconductor layers. For example structurally, as the top or bottom layer of each of the masking layer or intermediate layer, and can be distinguished by functionally having different growth characteristics and compositions, or by having different doping concentrations or doping types.

1A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

The semiconductor device 10 shown in FIG. 1A may include a substrate 11, and a plurality of nitride semiconductor layers on the substrate 11. FIG. The plurality of nitride semiconductor layers may include, for example, a first nitride semiconductor layer 12, a second nitride semiconductor layer 14, and a third nitride semiconductor layer 16. At least one masking layer 13 may be provided between the plurality of nitride semiconductor layers. At least one intermediate layer 15 may be provided between the plurality of nitride semiconductor layers on the masking layer 13. The intermediate layer 15 can compensate for the relative tensile stress due to the nitride semiconductor layer grown on the masking layer 13.

The substrate 11 may be removed during or after fabrication of the semiconductor device. 1B shows a semiconductor device 10 'from which the substrate 11 has been removed.

2A and 2B illustrate an example in which at least one buffer layer is provided on a substrate 21. In this case, FIG. 2A shows an example having one buffer layer 22, and FIG. 2B shows an example having two buffer layers. Referring to FIG. 2B, the at least one buffer layer may include, for example, a first buffer layer 22 'and a second buffer layer 23'. The at least one buffer layer is AlN, AlGaN, step-graded _{Al x In y Ga 1-xy} N (0≤x, y≤1, x + y≤1), Al x1 In y1 Ga 1 -x1- y1 N / Al _x2 In _y2 Ga _{1 -x2- y2} N (0? x1, x2, y1, y2? 1, x1? x2 or y1? y2, x1 + y1? 1, x2 + y2? And may be formed of a material containing any one of them.

A plurality of nitride semiconductor layers may be formed on the at least one buffer layer, at least one masking layer may be interposed between the plurality of nitride semiconductor layers, and at least one intermediate layer may be formed. For example, a first nitride semiconductor layer 24 is arranged on the first and second buffer layers 22 'and 23', and a masking layer 25 is formed on the first nitride semiconductor layer 24 Lt; / RTI &gt; A second nitride semiconductor layer 26 is arranged on the masking layer 25 and an intermediate layer 27 is arranged on the second nitride semiconductor layer 26 and a third nitride semiconductor layer 26 is formed on the intermediate layer 27. [ Layer 28 may be arranged. The at least one buffer layer 22, 22 ', or 23' may reduce dislocation due to mismatch of lattice constants between the substrate 21 and the first nitride semiconductor layer 24, To prevent cracks generated due to the cracks. Meanwhile, the first buffer layer 22 'may serve as a nucleation layer. The first buffer layer 22 'serving as a nucleation layer may be formed of, for example, AlN. The nucleation layer prevents the melt-back phenomenon caused by the reaction between the substrate and the nitride semiconductor layer, and can act to wet the second buffer layer 23 'or the first nitride semiconductor layer to be grown thereafter have. In the growth step of the nucleation layer, an Al source is initially injected to prevent the substrate from being firstly exposed to ammonia and nitriding. For example, a nucleated growth layer may have a size of tens to hundreds of nanometers.

A dislocation loop may be formed at the interface between the second buffer layer 23 'and the first nitride semiconductor layer 24 to reduce the dislocation density. When the second buffer layer 23 'is formed of, for example, Al _x Ga _{1 - x} N (0 _{? X} ? 1), the Al composition may have a composition having a single composition or sequentially decreasing. For example, the Al composition can be sequentially reduced step-by-step with Al _{0 .7} Ga _{0 .3} N -> Al _{0 .5} Ga _{0 .5} N -> Al _{0 .3} Ga _{0 .7} N. In this case, the lattice mismatching and the thermal expansion coefficient mismatching between the buffer layer and the nitride semiconductor layer are reduced stepwise, so that the compressive stress can be effectively generated during the epitaxial growth and the tensile stress generated during cooling can be reduced. In addition, bending of the threading dislocation can be induced to reduce defects. As the thickness of the buffer layer increases, compressive stress relaxation of the first nitride semiconductor layer can be reduced, and defects can be reduced. The thickness of the buffer layer may be several hundred nanometers to several micrometers thick. Meanwhile, the substrate 21 may be removed during or after fabricating the semiconductor device. Alternatively, when the substrate 21 is removed, the buffer layer may be removed together. It is possible for the substrate to be removed or the substrate and the buffer layer to be removed in the semiconductor laminate structure described below, and a detailed description thereof will be omitted.

The substrate 11 (21) may be formed of a material containing silicon. That is, the substrates 11 and 21 may be silicon-based substrates. For example, the substrate may comprise a silicon (Si) substrate or a silicon carbide (SiC) substrate. The silicon substrate may be, for example, a (111) surface. The substrates 11 and 21 may be cleaned using sulfuric acid, water, hydrofluoric acid, deionized water, or the like. The cleaned substrate is free from impurities such as metals and organic substances and the natural oxide film, and the surface of the substrate can be terminated with hydrogen to become suitable for epitaxial growth.

The plurality of nitride semiconductor layers may be formed of a nitride containing gallium, for example, as a layer to be grown on the substrate 11 (21). The plurality of nitride semiconductor layers may be formed of Al _x In _y Ga _{1 -xy} N (0? X, y? 1, x + y <1). For example, the plurality of nitride semiconductor layers may be formed of a material including any one of GaN, InGaN, and AlInGaN. Alternatively, the plurality of nitride semiconductor layers may be formed of a nitride containing no aluminum.

The masking layers 13 and 25 may be formed of silicon nitride (SiNx) or titanium nitride (TiN). For example, a SiNx masking layer can be formed using SiH ₄ (silane) and ammonia gas. The masking layer is formed at a level that can partially cover the nitride layer at random, rather than completely covering the nitride semiconductor layer in a planar manner so that the nitride semiconductor layer is not exposed. Accordingly, the region where the nitride semiconductor layer is exposed is determined according to the degree that the masking layer covers the nitride semiconductor layer, and the initial island growth pattern of the nitride semiconductor layer grown thereon may be changed. For example, when increasing the masking area of SiNx and reducing the area of the exposed nitride semiconductor layer, the density of the initial islands of the nitride semiconductor layer to be grown on the masking layer decreases while the size of the relatively integrated island Can be increased. In this case, the thickness of the nitride semiconductor layer to be coalesced can also be increased.

The defect density is reduced by the masking layers 13 and 25 because the masking layer masks the threading dislocation directly or the effect of masking the island facet of the second nitride semiconductor layer 14 26 ). &Lt; / RTI &gt; The coalescence thickness and defect density of the second nitride semiconductor layers 14 and 26 may be varied depending on growth conditions such as temperature, pressure, V / III source ratio and the like. The growth conditions of the SiNx masking layer and the second nitride semiconductor layer are selected, for example, under conditions that the surface pit density due to the penetration transition can be 5E8 / cm ² or less in the flattened state of the complete incorporation .

On the other hand, the first nitride semiconductor layer 24 can receive compressive stress from the second buffer layer 23 'having a relatively small lattice size. This compressive stress can be gradually relaxed as the thickness of the nitride semiconductor layer becomes thicker. When the masking layer 25 is provided between the first and second nitride semiconductor layers 12 and 24 and between the two nitride semiconductor layers 14 and 26, The compressive stress that is decoupled and transferred to the second nitride semiconductor layers 14 and 26 can be cut off. In addition, the second nitride semiconductor layers 14 and 26 undergo initial island growth, and relative tensile stresses may be generated during the process of coalescence of the islands. As a result, the first nitride semiconductor layer is subjected to a strong compressive stress by the buffer layer, while the second nitride semiconductor layer on the masking layer is subjected to a weaker compressive stress or tensile stress due to stress decoupling and coalescence. When the thickness of the layer having a relatively small compressive stress exceeds the critical point, cracks are generated in the thin film during cooling, so that as the thickness of the second nitride semiconductor layer is increased, the possibility of cracking increases. Therefore, the thickness of the second nitride semiconductor layer can be selected under such conditions that cracks are not generated and the defect density is also reduced.

 Reducing the combined thickness of the second nitride semiconductor layer while maintaining the thickness of the masking layer may be a method of reducing the defect density and preventing cracks. For this purpose, it is possible to control the growth conditions of the second nitride semiconductor layer, for example, by increasing the growth temperature, lowering the growth pressure, or increasing the V / III source ratio, Can be used.

However, even if the growth condition of the second nitride semiconductor layer is controlled, when the thickness of the second nitride semiconductor layer is increased to about 2um or more and cooled to room temperature, the difference in thermal expansion coefficient between the substrate and the second nitride semiconductor layer A crack can be generated because the tensile stress can not be controlled. According to the embodiment of the present invention, at least one intermediate layer 15 (27) can be arranged on the second nitride semiconductor layer 14 (26) to compensate the tensile stress generated during cooling of the nitride semiconductor layer . When the third nitride semiconductor layers 16 and 28 are formed on the intermediate layers 15 and 27, the third nitride semiconductor layers 16 and 28 may have a high compressive stress. The compressive stress of the third nitride semiconductor layers 16 and 28 compensates for the weak compressive stress or tensile stress of the second nitride semiconductor layer 26, thereby reducing the cracks.

The plurality of nitride semiconductor layers may be selectively undoped or doped. The nitride semiconductor layer in the last upper layer among the plurality of nitride semiconductor layers may be doped with n-type or p-type, and the remaining nitride semiconductor layers may be undoped. Alternatively, the nitride semiconductor layer adjacent to the at least one masking layer may be undoped. The third nitride semiconductor layers 16 and 28 may be formed of, for example, a n-type or p-type doped conductive nitride layer. Alternatively, the third nitride semiconductor layers 16 and 18 may have a two-layer structure of an undoped layer and a doped layer. The third nitride semiconductor layers 16 and 28 may have a thickness of 2 um or more and a doping concentration of 3E18 / cm ³ or more, for example, considering the current spreading of the semiconductor device.

FIG. 3A is a conceptual view showing an experimental group stack and an SEM sectional photograph showing an effect of an embodiment of the present invention, and FIG. 3B is an optical microscope (OM) image of a surface.

FIG. 3A is an example of the semiconductor device shown in FIG. 2B, in which a SiNx masking layer is disposed between a first u-GaN nitride semiconductor layer and a second u-GaN nitride semiconductor layer, the _x N intermediate layer is arranged _- Al _x Ga ₁ between the u-GaN third nitride semiconductor layer. An n-GaN layer may be provided on the third nitride semiconductor layer.

Referring to the OM (Optical Microscope) image of FIG. 3B, even if the third nitride semiconductor layer 28 is formed on the intermediate layer 27 with a thickness of 4 μm or more and the Si doping concentration is 3E18 cm ^-3 or more, And the defect density can be kept as low as 5.3E8 cm ^{- 2} when measuring the defect density. This shows in advance that the density of the threading dislocations reaching the intermediate layer through the SiNx masking layer is reduced to prevent the occurrence of cracks by retarding or reducing the relaxation of the compressive stress applied by the intermediate layer.

On the other hand, when u-GaN is used for the second nitride semiconductor layer and n-GaN is used for the third nitride semiconductor layer in the structure including only the masking layer (SiNx) on the u-GaN first nitride semiconductor layer, The defect density decreased to 3.1E8 cm ^-2. However, due to the tensile stress caused by the dislocation bending due to the increase of the tensile stress and the Si n-doping occurring on the islanding phase on the masking layer, Cracks can occur.

Alternatively, in the structure including only the intermediate layer (Al x Ga 1-x N) between the two nitride semiconductor layers (n GaN and u GaN) without the masking layer, the defect density is as high as about 7.7E8 cm ^-2 . The reason why the defect density is high may be that there is no defect reduction effect due to the masking layer. However, cracks are not generated on the surface of the thin film due to the compressive stress application effect of the intermediate layer.

In the semiconductor multilayer structure, an AlN layer as a core layer growth, and the buffer layer to the step grade _{(step-graded) Al x Ga} 1 - was used _{- X N (X N g-} Al x Ga 1).

 In the OM photograph of the structure having only the middle layer, cracks are not observed on the surface of the thin film, but internal cracks in the form of hatches are observed inside the thin film, but such internal cracks are not observed in FIG. As a result, by effectively reducing the threading dislocations before the interlayer insertion through the masking layer to increase the stress compensation effect by the interlayer, the defect density can be reduced and the tensile stress can be reduced. Here, a decrease in defect density can be expected when the masking layer is formed on the aluminum-containing nucleation layer or the buffer layer. However, when the masking layer is formed on the nitride semiconductor layer as in the embodiment of the present invention, . When the masking layer is provided on the buffer layer, it is difficult to sufficiently reduce the defect density in the previous step of the interlayer since the dislocation bending effect occurring between the buffer layer and the nitride semiconductor layer can not be utilized. In this structure, it is difficult to obtain a sufficient stress compensation effect even if the intermediate layer is inserted. Therefore, a multi-layered intermediate layer may be required for stress compensation. However, in such a case, defects may be regenerated and crystallinity may be deteriorated by the multilayer intermediate layer. Therefore, defects reduced by the masking layer can be increased again, and it may be required to finally provide a masking layer in order to compensate for the defect. However, the thickness of the nitride nitride semiconductor layer to be grown on the final masking layer must be limited, and therefore the doping concentration and thickness of the n-type conductive nitride semiconductor layer can be reduced. In this way, even if the masking layer and the intermediate layer are provided, it is difficult to satisfy both the reduction of the defect density and the compensation of the tensile stress when the masking layer is provided on the buffer layer.

Meanwhile, the substrate, the buffer layer and the nitride semiconductor layer used below are substantially the same as those described with reference to Figs. 1A, 1B, 2A, and 2B, and therefore detailed description thereof will be omitted.

4 shows a semiconductor device 30 according to another aspect of the present invention. The semiconductor device 30 shown in FIG. 4 includes a plurality of nitride semiconductor layers on a substrate 31, and one or more pairs of a masking layer and an intermediate layer may be alternately arranged between the plurality of nitride semiconductor layers. The semiconductor device 30 may include at least one buffer layer 32 and 33 on the substrate 31 and a plurality of nitride semiconductor layers thereon. The plurality of nitride semiconductor layers may include first to fifth nitride semiconductor layers 34, 36, 38, 40, and 42. A first masking layer 35 is provided between the first nitride semiconductor layer 34 and the second nitride semiconductor layer 36 and a second masking layer 35 is formed between the second nitride semiconductor layer 36 and the third nitride semiconductor layer 38 A second intermediate layer 37 is provided and a second masking layer 39 is provided between the third and fourth nitride semiconductor layers 38 and 40. The fourth and fifth nitride semiconductor layers 40 and 40 And the second intermediate layer 41 may be provided between the fifth nitride semiconductor layers 42. For example, when a pair of the SiNx masking layer and the AlxGa1-xN intermediate layer is repeatedly laminated twice, the defect density can be further reduced and the crystallinity can be further increased by the two masking effects. For example, the defect density can be reduced to 3E8 / cm ² or less, and the half widths of the XRD GaN (002) and (102) peaks can have a crystallinity of 230 arcsec and 310 arcsec or less, respectively. Here, when the SiNx masking layer and the AlxGa1-xN intermediate layer are repeated, a nitride semiconductor layer with a lower defect density can be obtained.

5 includes at least one buffer layer 52 and 53 on a substrate 51 and a first nitride semiconductor layer 54 on the at least one buffer layer 52 and 53, And a masking layer 55 may be provided on the first nitride semiconductor layer 54. The at least one buffer layer 52 and 53 may be optional, and the at least one buffer layer may include a nucleation layer. A plurality of intermediate layers may be provided on the masking layer 55. The plurality of intermediate layers may include first to third intermediate layers 57, 59 and 61. A second nitride semiconductor layer 56 is provided on the masking layer 55 and a first intermediate layer 57, a third nitride semiconductor layer 58 and a second intermediate layer 59 , A fourth nitride semiconductor layer 60, a third intermediate layer 61, and a fifth nitride semiconductor layer 62 may be provided. FIG. 5 shows an example in which a pair of masking layers and at least one intermediate layer are further provided on the intermediate layer.

6 includes at least one buffer layer 72 and 73 on a substrate 71 and a first nitride semiconductor layer 74 on the at least one buffer layer 72 and 73, . A first intermediate layer 75 is provided on the first nitride semiconductor layer 74 and a second nitride semiconductor layer 76, a masking layer 77 and a third nitride semiconductor layer 78 ), A second intermediate layer 79, and a fourth nitride semiconductor layer 80 may be provided. FIG. 6 shows an example in which a pair of masking layers and at least one intermediate layer below the intermediate layer are further provided. Here, although one intermediate layer is provided below the masking layer 77, a plurality of intermediate layers may be further provided.

By providing at least one intermediate layer before the masking layer 77, the compressive stress can be refreshed to increase the compressive stress, thereby completely or partially replacing the role of the buffer layer. Therefore, the at least one buffer layer 72, 73 may be optional. In the semiconductor device 70 shown in Fig. 6, for example, the use of the aluminum-containing buffer layer having a relatively slow growth rate can be minimized, and the throughput can be improved.

The semiconductor device 100 shown in FIG. 7 includes a first region 110 in which at least one masking layer is interposed between a plurality of nitride semiconductor layers, and a second region 110 in which at least one And a second region 120 in which an intermediate layer is inserted. At least one buffer layer 102 (103) may be provided between the substrate 101 and the first region 110.

For example, the first region 110 may include a first nitride semiconductor layer 111a, a first masking layer 112a, a second nitride semiconductor layer 111b, a second masking layer 112b, A layer 111c and a third masking layer 112c. The second region 120 includes a fourth nitride semiconductor layer 121a, a first intermediate layer 122a, a fifth nitride semiconductor layer 121b, a second intermediate layer 122b, a sixth nitride semiconductor layer 121c, 3 intermediate layer 122c. However, the present invention is not limited thereto, and it is also possible to provide two masking layers, two intermediate layers, one masking layer, and two intermediate layers.

 The first region 110 and the second region 120 may be alternately stacked one or more times. The seventh nitride semiconductor layer 150 may be further formed on the finally deposited second region 120 and the seventh nitride semiconductor layer 150 may be doped n or p. Alternatively, the seventh nitride semiconductor layer 150 may have a two-layer structure of an undoped layer and a doped layer.

Meanwhile, the composition of the intermediate layer used in the semiconductor device according to the embodiment of the present invention can be adjusted to reduce or prevent the compressive stress relaxation that can be caused in the intermediate layer while maintaining the reduced defect density by the masking layer. This will be described by taking the semiconductor element 20 shown in FIG. 2B as an example. The intermediate layer 27 may have a large lattice mismatch with the third nitride semiconductor layer 28 to apply compressive stress to the third nitride semiconductor layer 28. For example, the third nitride semiconductor layer 28 may be formed of gallium nitride (GaN), and the intermediate layer 27 may be formed of Al _x Ga _{1 - x} N. The intermediate layer 27 may have a thickness in the range of 10-100 nm to have a relaxed grating size. When the thickness of the intermediate layer 27 is too thin, the relaxation of the lattice size of the intermediate layer 27 is not likely to occur, so that the compressive stress due to the lattice difference can not be effectively applied to the upper nitride semiconductor layer to be grown thereafter. Is too thick, the intermediate layer itself is subjected to tensile stress by the lower nitride semiconductor layer, and a crack can be formed. On the other hand, it is possible to control the compressive stress relaxation due to the lattice mismatch by changing the Al composition of the intermediate layer. If the Al composition is too high to cause excessive lattice mismatch by the intermediate layer, dislocations may occur to relax the stress. In this case, the effect of reducing the defect by the masking layer can be canceled.

8A to 8C are OM images showing cracks generated in the GaN semiconductor layer when the Al composition of the AlxGa1-xN intermediate layer is changed. 8A shows that when the AlGaN intermediate layer has an Al composition of 40%, the AlGaN intermediate layer can not apply a sufficient compressive stress and cracks are generated. On the other hand, the defect density was ~ 5E18 cm ^-2, which was not significantly increased compared with the structure using only the masking layer. FIG. 8B shows that cracks are not generated when the AlGaN intermediate layer has an Al composition of 60%. At this time, the defect density is maintained at ~ 5E18 cm ^-2 . FIG. 8C shows that when AlN having a 100% Al composition is used as the intermediate layer, the defect density increases to as low as about E9 / cm ² , thereby relaxing the compressive stress and generating a crack.

According to the above results, it can be seen that there is an Al composition which can exhibit a stress compensation effect and at the same time inhibit dislocation generation. For example, the AlxGa1-xN intermediate layer may have a range of 0.4 < x < 1. The AlxGa1-xN intermediate layer may have a thickness in the range of 10 to 100 nm. According to these results, for example, even in a structure including at least one buffer layer, a masking layer, a nitride semiconductor layer and an AlxGa1-xN intermediate layer (0.4 < x < 1) on a substrate while maintaining a reduction in defect density due to the masking layer The stress compensation effect by the intermediate layer can be obtained.

In the semiconductor device according to the embodiment of the present invention, the masking layer is disposed on the nitride semiconductor layer. In this structure, it is difficult to transmit the threading dislocation of the first nitride semiconductor layer to the second nitride semiconductor layer, thereby reducing the defect density , And then the application of the compressive stress by the intermediate layer can be further facilitated.

In the embodiment of the present invention, the defect density can be reduced at the interface between the buffer layer and the first nitride semiconductor layer before the masking layer, and the masking layer can be formed on the first nitride semiconductor layer to enhance the reduction in defect density. Even if the defect density is increased due to the use of the intermediate layer by sufficiently reducing the defect density before the intermediate layer, the effect of reducing the defect density by the masking layer can be maintained or reduced. Further, tensile stress can be compensated by the intermediate layer to prevent the occurrence of cracks. Further, by regulating the composition and thickness of the intermediate layer to reduce or eliminate defect regeneration caused by the intermediate layer, a nitride semiconductor layer having a low defect density without cracks can be grown even in a structure using only one intermediate layer. For example, the semiconductor element (20), without cracks the nitride semiconductor layer satisfying the 4E8 / cm ² or less defect density and thickness and 4E18 / cm ³ or more n doping concentration of at least 3.4um to the intermediate layer shown in Fig. 2b can do. At this time, the half widths of the XRD GaN (002) and (102) peaks were 280 arcsec and 350 arcsec or less, respectively.

The semiconductor device according to the embodiment of the present invention can grow the nitride semiconductor layer to a desired thickness by reducing both lattice defects and tensile stress when the nitride semiconductor layer is grown on the silicon substrate or the silicon carbide substrate. It is also possible to manufacture wafers with a large diameter by using a silicon substrate or a silicon carbide substrate. A semiconductor device according to an embodiment of the present invention may be applied to a light emitting diode, a Schottky diode, a laser diode, a field effect transistor, a power device, or the like.

9 illustrates an example in which a semiconductor device according to an embodiment of the present invention is applied to a light emitting device. 9 includes a plurality of nitride semiconductor layers on a substrate 221, at least one masking layer between the plurality of nitride semiconductor layers, and at least one intermediate layer on top of the masking layer can do. For example, the plurality of nitride semiconductor layers may include a first nitride semiconductor layer 224, a second nitride semiconductor layer 226, and a third nitride semiconductor layer 228. A masking layer 225 is disposed between the first and second nitride semiconductor layers 224 and 226 and an intermediate layer is formed between the second and third nitride semiconductor layers 226 and 228. [ 227 may be disposed. The third nitride semiconductor layer 228 may be doped to a first type, for example, n-type. The first and second nitride semiconductor layers 224 and 226 may be either undoped or doped. An active layer 229 may be formed on the third nitride semiconductor layer 228 and a fourth nitride semiconductor layer 230 may be formed on the active layer 229. [ The fourth nitride semiconductor layer 230 may be doped to a second type, for example, p-type.

At least one buffer layer may be provided between the substrate 221 and the first nitride semiconductor layer 224. The at least one buffer layer may include, for example, a first buffer layer 222 and a second buffer layer 223. Meanwhile, the substrate 221 may be removed during or after fabricating the semiconductor device. Alternatively, the substrate 221, the first buffer layer 222, and the second buffer layer 223 may be removed together.

 10 shows a schematic configuration of a semiconductor device according to an embodiment. The semiconductor device 300 may include a silicon-based substrate 310, a buffer layer 340, and a nitride layered structure 350.

The silicon substrate 310 is formed by doping a substrate with a high concentration of p-type impurities. As the substrate, a silicon substrate or a silicon carbide substrate may be employed. As the silicon-based substrate 310, for example, a wafer in which a p-type impurity is highly doped can be used. Alternatively, the p-type impurity is not doped, or a silicon wafer which is doped at a low concentration is purchased and doped with a p-type impurity by a process such as implantation, and then the p-type impurity is doped at a high concentration. As the p-type impurity, for example, B, Al, Mg, Ca, Zn, Cd, Hg, Ga and the like can be used. The doping concentration may be about 10 &lt; ¹⁷ &gt; / cm &lt; ³ &gt; or more and may be different depending on the kind of the impurity. For example, when the p-type impurity is boron (B), the doping concentration is approximately 5 × 10 ¹⁷ / cm ³ To about 10 ²⁰ / cm ³ Range. &Lt; / RTI &gt; Alternatively, the doping concentration is approximately 10 ¹⁸ / cm ³ To 5 x 10 &lt; ¹⁹ &gt; / cm &lt; ³ &gt;. The doping concentration was 5 × 10 ¹⁷ / cm ³ It is difficult to show a bow reduction effect. When the doping concentration exceeds 10 ²⁰ / cm ³ , it is difficult to form a silicon substrate in the form of a single crystal. Alternatively, the doping concentration can be determined so that the specific resistance of the silicon-based substrate 310 is 1 cm m or less.

The buffer layer 340 is provided for securing the thin film quality of the nitride layered body 350 to be grown on the dissimilar substrate and is dislocated due to lattice constant mismatch between the silicon based substrate 310 and the nitride layered body 350. [ And to suppress generation of cracks due to inconsistency of the thermal expansion coefficient. The buffer layer 340 may include at least one buffer layer, and may have a layer acting as a nucleation layer. As the buffer layer 340, a multi-layer structure of AlN, SiC, Al ₂ O ₃ , AlGaN, AlInGaN, AlInBGaN, AlBGaN, GaN, XY or a combination thereof may be employed. X may be Ti, Cr, Zr, Hf, Nb or Ta, and Y may be nitrogen (N) or boron (B, B ₂ ).

The nitride layered structure 350 may include at least one GaN-based compound semiconductor layer. The nitride layered structure 350 may include, for example, a plurality of nitride semiconductor layers. The nitride layered structure 350 may include a plurality of nitride semiconductor layers, at least one masking layer provided between the plurality of nitride semiconductor layers, and at least one intermediate layer provided between the plurality of nitride semiconductor layers. The nitride layered structure 350 may have the structure shown in, for example, FIG. 1B. However, it is not limited thereto and may have various nitride laminated structures.

The nitride semiconductor layer may include, for example, a cladding layer. Alternatively, the nitride semiconductor layer may include n-GaN doped with an n-type impurity or p-GaN doped with a p-type impurity. Or u-GaN that is not doped with the impurity. When the nitride semiconductor layer is doped with a predetermined impurity, the semiconductor device 300 can be used as a template for forming a light emitting device. When the nitride semiconductor layer is not doped, it can be used as a template for forming a power device and can also be used as a template for forming a light emitting device.

11 shows a schematic configuration of a semiconductor device 302 according to another embodiment. The semiconductor device 302 may include a silicon-based substrate 312, a buffer layer 340, and a nitride stack 350, to which a p-type impurity is heavily doped. This embodiment differs from the embodiment of FIG. 1 in the impurity doping mode of the silicon-based substrate 312. The p-type impurity doped in the silicon-based substrate 312 is mainly distributed on the surface side of the silicon-based substrate 312. The silicon-based substrate 312 may be formed by preparing a general silicon substrate, that is, a silicon wafer in which impurities are not doped or doped with impurities at a low concentration, and doping the p-type impurity by ion implantation have. Other components are substantially the same as the embodiment of Fig. 10, and similarly, they can be used as templates for forming various semiconductor elements such as a light emitting element, a power element, and the like.

In the above embodiments, the silicon substrate 310 doped with the p-type impurity at a high concentration is employed as the substrate in order to reduce the warpage of the substrate during the manufacturing process of the semiconductor devices 300 and 302, It usually appears as a bow measured at the wafer level. The bow of the silicon-based substrate 310 (312) in the semiconductor devices 100, 102 300 and 302 of the embodiment can be made to be about 100 μm or less based on the 2 "diameter disc shape.

12 is a view for defining a bow of a wafer. The amount of deflection of the substrate during the process can be defined as a bow measured at the wafer level. Here, the wafer W refers to a substrate and a thin film formed on the substrate. Such a bow appears because the thermal expansion coefficients of the substrate and the thin film formed on the substrate are different. When the wafer W is cooled to room temperature after the high temperature process required for thin film growth, the degree of shrinkage varies depending on the difference in the coefficient of thermal expansion, and thus the wafer W is warped. At this time, the distance between the position of the most protruding from the thickness direction of the wafer W and the most curved position is referred to as a bow. The bow can be increased in proportion to the square of the diameter D of the wafer W under the same conditions. Therefore, as the substrate of a large diameter is used, the bow becomes larger. The bow shown on the wafer W in the figure is shown in a concave form, but this is illustrative and may vary depending on the thermal expansion rate of the substrate, the thin film, the high temperature during the process, and the stress conditions.

In this embodiment, silicon substrates 310 and 312 doped with p-type impurities at a high concentration are used as the substrate, which is intended to reduce the occurrence of the above-described bow.

 When a general silicon substrate was used, a bow of several tens to several hundreds of microns was observed in a convex shape after the growth of the nitride semiconductor film, and this was analyzed by plastic deformation of the silicon substrate. Generally, since the coefficient of thermal expansion of the silicon substrate is smaller than the coefficient of thermal expansion of the semiconductor film formed on the silicon substrate, the nitride semiconductor film shrinks more than the silicon substrate upon cooling to room temperature, so that a bow of a concave shape may occur. (GPa) compressive stress is applied to compensate for the tensile stress generated in the semiconductor film in the high-temperature process for growth. To cause plastic deformation. That is, at room temperature, the silicon substrate having a brittle property is in a ductile state at a high temperature, and excessive stress applied to the silicon substrate in this condition causes plastic deformation of the silicon substrate. In this case, even after the high temperature and stress conditions are removed, the silicon substrate may not return to its original shape and may have a convex bow.

 However, when silicon substrates 310 and 312 doped with a p-type impurity at a proper level or higher are used, the occurrence of such bow can be reduced. These results were confirmed from the following examples and experimental results thereof.

FIG. 13 shows the structure of the light emitting device 400 using the semiconductor device 300 of FIG. The light emitting device 400 may include a silicon substrate 410, a buffer layer 440, a nitride layer 450, an n-type semiconductor layer 460, an active layer 470, and a p-type semiconductor layer 480. The positions of the n-type semiconductor layer 460 and the p-type semiconductor layer 480 may be reversed. The buffer layer 440 includes a first buffer layer 441 and a second buffer layer 442. The nitride layer 450 includes a first nitride semiconductor layer 453, a masking layer 454, a second nitride semiconductor layer 455, an intermediate layer 456, and a third nitride semiconductor layer 457. Here, the third nitride semiconductor layer 457 may be omitted.

The concrete configuration related to the experimental results to be described below is as follows. The silicon substrate 410 is a substrate doped with boron (B) at a concentration of about 10 ¹⁹ / cm ³ in Si (111), and the substrate has a resistivity of about 0.007? Cm. The first buffer layer 441 is a nucleation layer, and may be formed of AlN. The second buffer layer 442 may be formed of AlGaN. The first nitride semiconductor layer 453, the second nitride semiconductor layer 455 and the third nitride semiconductor layer 457 are formed of GaN, the masking layer 454 is formed of SiN, the intermediate layer 456 is formed of SiN, AlGaN. &Lt; / RTI &gt; The n-type semiconductor layer 460 may be formed of n-GaN, the p-type semiconductor layer 480 may be formed of p-GaN, and the active layer 470 may be formed of a multiple quantum well structure of GaN / InGaN.

The luminescent characteristics of the light emitting device 400 of the example and the comparative example were measured, and the results are as follows. In the comparative example, boron (B) was doped to a concentration of 4 x 10 ¹⁶ / cm ³ , and the specific resistance of the substrate was ^15? Cm when a general silicon substrate was used instead of the silicon substrate 410 doped with a high concentration of impurities.

wavelength Comparative Example Example Average (nm) 449 448 Standard deviation (nm) 5.54 3.31 Uniformity (%) 1.2 0.7

Table 1 shows that in the embodiment where the light emitting device 400 is manufactured using the silicon substrate 410, the standard deviation of the emission wavelength is smaller than that of the comparative example and the uniformity is also improved.

In the light emitting structure employing the multiple quantum well structure of GaN / InGaN, the scattering of the emission wavelength is related to the uniformity of the In composition. In this structure, the emission wavelength is controlled by adjusting the mole fraction of In in the InGaN layer. For example, as the mole fraction of In increases, the emission wavelength can be shifted to the long wavelength band. The result of the above-described embodiment in which scattering of the emission wavelength is reduced means that the In composition is uniformly formed in the InGaN layer in growing the multiple quantum well structure. This is because the wafer bow in the template state for forming the multiple quantum well structure is reduced Because. When the bow of the wafer is large, the temperature distribution of the substrate becomes non-uniform, which may cause the composition of In to form the multiple quantum well structure to become uneven.

FIG. 14 is a graph comparing bow characteristics generated on a wafer with respect to the light emitting device of the comparative example and the light emitting device 400 of the embodiment. Referring to the graph, the wafer bow of the comparative example using a general silicon substrate has a size of about 80 μm to 120 μm according to the direction, whereas the wafer bow of the embodiment is very small, about several micrometers, irrespective of the direction.

15A to 15E are views for explaining a semiconductor device according to the embodiment and a method of manufacturing another element using the same.

As shown in FIG. 15A, a silicon substrate 310 doped with a p-type impurity at a high concentration is prepared. As the p-type impurity, B, Al, Mg, Ca, Zn, Cd, Hg, Ga and the like can be used. As the substrate, a silicon substrate or a silicon carbide (SiC) substrate can be used. The silicon-based substrate 310 of this type can be formed by p-type impurity doping combined with silicon ingot growth. The doping concentration is about 5 × 10 ¹⁷ / cm ³ To 10 ²⁰ / cm ³ , or from about 10 ¹⁸ / cm ³ to 5 × 10 ¹⁹ / cm ³ . Alternatively, the doping concentration can be determined so that the resistivity of the silicon-based substrate 310 is approximately 1? Cm or less.

Next, as shown in FIG. 15B, a buffer layer 340 is formed on the silicon substrate 310. Buffer layer 340 may be formed of _{AlN, SiC, Al 2 O 3} , AlGaN, AlInGaN, AlInBGaN, AlBGaN, GaN, multi-layered structure consisting of a single layer or a combination of XY. Here, X may be Ti, Cr, Zr, Hf, Nb or Ta, and Y may be nitrogen (N) or boron (B, B ₂ ).

Next, as shown in FIG. A nitride layered body 350 is formed on the buffer layer 340. The nitride layered structure 350 may include a GaN-based compound semiconductor layer. The nitride layered body 350 may be doped with a predetermined impurity if necessary. For example, n-type impurities may be doped and used as a template for manufacturing a light emitting device, or may be used as a template for manufacturing a power device without doping with an impurity.

The buffer layer 340 and the nitride layered body 360 may be formed according to a general semiconductor manufacturing process, for example, by a metal organic chemical vapor deposition (MOCVD) process. The total thickness of the buffer layer 340 and the nitride layered body 350 is determined so that the defect density is not more than a proper level, and can be set to about 3 m or more. In consideration of a difference in thermal expansion coefficient between the silicon substrate 310, the buffer layer 340 and the nitride layered body 350, stresses that can cancel the stress generated upon cooling to room temperature after the high temperature process, The stacked body 350 can be applied upon growth. For example, when the thermal expansion coefficient of the buffer layer 340 and the nitride layered structure 350 is greater than the thermal expansion coefficient of the silicon substrate 310, compressive stress is applied in a high temperature process .

The semiconductor device 300 shown in Fig. 15C can be used as a template for forming various semiconductor devices. For example, as shown in Fig. 15D, an element layer DL can be formed over the nitride layered body 350. [ The element layer DL may be composed of a plurality of thin film layers made of a material suitable for a device to be manufactured. For example, a LED device, a power device such as a HEMT (High Electron Mobility Transistor), an LD (Laser Diode) device, or the like. Next, the silicon substrate 310 can be separated as shown in FIG. 15E. As the separation process, a wet etching process may be used together with a polishing process, or a dry etching process may be used, but the present invention is not limited thereto.

16A to 16F are views illustrating a semiconductor substrate according to another embodiment and a method for manufacturing another element using the same.

The substrate 310 'is prepared as shown in FIG. 16A. As the substrate 310 ', a silicon substrate, a silicon carbide (SiC) substrate, or the like can be used.

Next, a p-type impurity such as B, Al, Mg, Ca, Zn, Cd, Hg, Ga or the like is doped to the substrate 310 'at a high concentration and an ion implantation process . According to this process, as shown in FIG. 16B, the silicon-based substrate 312 can be formed in a form mainly distributed on the side closer to the surface of the p-type impurity. Next, the processes of FIGS. 16C to 16F are substantially the same as the processes described in FIGS. 15B to 15E. That is, the buffer layer 340, the nitride layered structure 350, and the element layer DL may be formed. Then, the silicon-based substrate 312 can be separated.

By using the silicon-based substrate 310 doped with the p-type impurity at a predetermined level or more in the above-described manufacturing process, the plastic deformation of the substrate hardly occurs even after the step of adding high temperature and stress, And a good film quality is realized. In addition, the manufactured semiconductor elements 300 and 302 can be used as templates for manufacturing various light emitting elements or power elements of good quality.

For example, a method of manufacturing a light emitting device on such a template will be described with reference to FIGS. 17A to 17D.

17A illustrates a process of isolating a wafer on which a light emitting device layer is grown on a template and then depositing a dielectric material capable of serving as a chip passivation and a CBL (current blocking layer) And shows a patterned structure. More specifically, a buffer layer 440, a nitride laminate 450, an n-type semiconductor layer 460, an active layer 470, and a p-type semiconductor layer 480 are formed on a silicon substrate 410 doped with a p- And a PL layer PL and a CBL layer CBL made of a dielectric material may be formed in a predetermined pattern. A buffer layer (440), a nitride laminated body (450) may be employed a configuration of the buffer layer (440), a nitride laminated body (450) described in Figure 10 or Figure 13; A metal layer 490 having a p-ohmic contact function and a reflection function can be deposited on the p-type semiconductor layer 480 and the CBL layer CBL.

17B shows bonding the submount 510 over the structure as shown in FIG. 17A. As the submount 510, a Si (100) substrate can be used. A bonding metal layer 520 for bonding may be formed on one surface of the submount 510. The bonding metal layer 520 and the metal layer 490 may be eutectic bonded at about 300 ° C or higher.

Next, as shown in FIG. 17C, the silicon substrate 410 may be removed by a grinding process and a wet or dry etching process. 17C, the submount 550 is depicted below, contrary to FIG. 17B.

As shown in FIG. 17D, a texturing process may be performed to increase the light-emitting efficiency of the active layer 470 on the surface from which the silicon-based substrate 410 is removed. Next, the textured buffer layer 440 and a portion of the nitride layered body 450 are etched to expose the n-type semiconductor layer 460 and an n-ohmic contact is formed on the exposed n-type semiconductor layer 460. [ The metal layer 550 may be formed. In addition, by forming the electrode layer 530 for voltage application on the lower surface of the submount 510, the vertical light emitting device 600 can be manufactured as shown in FIG. 17D.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it should be understood that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims. It will be appreciated that embodiments are possible. Accordingly, the true scope of the present invention should be determined by the appended claims.

10, 20, 30, 50, 70, 100,
11, 21, 31, 51, 71,
24, 26, 28, 34, 36, 38, 40, 42, 54, 56, 58, 60, 62, 74, 76, 78, 80,
22, 23, 32, 33, 52, 53, 72, 73, 102, 103,
13, 25, 35, 39, 55, 75, 112a, 112b, 112c, 225,
127, 37, 41, 57, 61, 77, 79, 122a, 122b, 122c, 227,
229.. . The active layer

Claims (16)

A first nitride semiconductor layer;
A masking layer directly above the first nitride semiconductor layer;
A second nitride semiconductor layer directly over the masking layer;
An intermediate layer on the second nitride semiconductor layer;
And a third nitride semiconductor layer on the intermediate layer,
Wherein the first nitride semiconductor layer, the second nitride semiconductor layer, and the third nitride semiconductor layer contain gallium,
The first nitride semiconductor layer and the second nitride semiconductor layer are formed of the same elements,
The intermediate layer is made of Al _x In _y Ga _{1 -x0-} y0N (0 <x0, y0 <1, x0 + y0 <1), step grades Al _x In _y Ga _1-xy N (0 = x, y = _{+ y = 1), Al x1} In y1 Ga 1 -x1- y1 N / Al x2 In y2 Ga 1 -x2- y2 N (0 = x1, x2, y1, y2 = 1, x1 ≠ x2 or y1 ≠ y2) And a superlattice, and applies compressive stress to the upper nitride semiconductor layer. The method according to claim 1,
Wherein the first, second, and third nitride semiconductor layers are formed of Al _x In _y Ga _{1 -xy} N (0? X, y? 1, x + y <1). The method according to claim 1,
Wherein the masking layer comprises silicon nitride or titanium nitride. The method according to claim 1,
And a substrate is further provided on one surface of the first nitride semiconductor layer. 5. The method of claim 4,
Wherein the substrate comprises a silicon substrate or a silicon carbide substrate. 6. The method of claim 5,
And at least one buffer layer is further provided between the substrate and the first nitride semiconductor layer. The method according to claim 6,
_Wherein the at least one buffer layer is made of Al _x In _y Ga _{1 -x- y} N (0? X, y? 1, x + y? 1). The method according to claim 6,
Wherein the at least one buffer layer has a step-graded structure or a superlattice structure. 9. The method of claim 8,
_Wherein the at least one buffer layer comprises a step graded Al _x In _y Ga _{1 -x- y} N (0? X, y? 1, x + y? 1) or Al _x1 In _y1 Ga _{1 -x1- y1} N / Al _x2 In _{y2 Ga 1 -x2- y2 N (0≤x1} , x2, y1, y2≤1, x1 ≠ x2 or y1 ≠ y2) second semiconductor elements are formed in a lattice. 10. The method according to any one of claims 1 to 9,
Wherein the intermediate layer is a first intermediate layer and includes at least one fourth nitride semiconductor layer on one surface of the first nitride semiconductor layer and at least one second nitride semiconductor layer between the first nitride semiconductor layer and the at least one fourth nitride semiconductor layer, Further comprising an intermediate layer. 10. The method according to any one of claims 1 to 9,
Wherein the intermediate layer is a first intermediate layer,
At least one fourth nitride semiconductor layer between the first intermediate layer and the third nitride semiconductor layer and at least one second intermediate layer between the third nitride semiconductor layer and the at least one fourth nitride semiconductor layer, device. 10. The method according to any one of claims 1 to 9,
Wherein the masking layer is a first masking layer,
Wherein a second masking layer, a fourth nitride semiconductor layer, a second intermediate layer, and a fifth nitride semiconductor layer are sequentially stacked at least once on one surface of the third nitride semiconductor layer. 10. The method according to any one of claims 1 to 9,
And the third nitride semiconductor layer is doped with n-type. 14. The method of claim 13,
And a fourth nitride semiconductor layer doped with p-type impurities are stacked on the third nitride semiconductor layer. The method according to claim 6,
Wherein the substrate is a substrate doped with a p-type impurity. 16. The method of claim 15,
Wherein a doping concentration of the p-type impurity is determined such that a specific resistance of the substrate is 1? Cm or less.

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