KR20170016582A - Memory apparatus using a plurality of power source and system including the same - Google Patents
Memory apparatus using a plurality of power source and system including the same Download PDFInfo
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- KR20170016582A KR20170016582A KR1020150109846A KR20150109846A KR20170016582A KR 20170016582 A KR20170016582 A KR 20170016582A KR 1020150109846 A KR1020150109846 A KR 1020150109846A KR 20150109846 A KR20150109846 A KR 20150109846A KR 20170016582 A KR20170016582 A KR 20170016582A
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- data
- power supply
- memory device
- power
- external voltage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The memory device may include first to third pads respectively to provide first to third power supplies to the internal circuit. The first pad may receive the first external voltage to provide the first power. The second and third pads may each receive a second external voltage in common, the second pad may provide the second power, and the third pad may provide the third power.
Description
The present invention relates to a semiconductor device, and more particularly, to a memory device using a plurality of power sources and a system including the same.
A typical semiconductor system may include a processor and a memory device in communication with the processor. The processor and the memory device are connected to each other via a data bus, and can perform data communication while transmitting and receiving data through the data bus. The processor may include a transmitting circuit for transmitting data to the memory device and a receiving circuit for receiving data transmitted from the memory device. Likewise, the memory device may include a transfer circuit for transferring data to the processor and a receive circuit for receiving data from the processor.
A recent technology trend is to develop a semiconductor system that can communicate faster, while consuming less power. The voltage level of the power source used by the processor or memory for data communication is getting lower and the amount of data transmitted at the same time is increasing.
Embodiments of the present invention can provide a memory device capable of separating a power source of a data transmission circuit and a power source of a data reception circuit, and a system including the same.
In addition, embodiments of the present invention can provide a memory device capable of separating a power source of a data transfer circuit, a power source of a data receiving circuit, and a power source of a peripheral circuit, and a system including the same.
A memory device according to an embodiment of the present invention includes a first pad receiving a first external voltage to provide a first power source; A second pad receiving a second external voltage to provide a second power supply; And a third pad receiving the second external voltage to provide a third power source.
A memory device according to an embodiment of the present invention includes a data transmitter for outputting data using a first power source received through a first pad; A data receiver for receiving data using a second power source received via a second pad; A parallelizer for generating data output through the transmitter from data stored in the memory device using a third power source received via a third pad; And a parallelizer for aligning data received via the data receiver using the third power source.
A system according to an embodiment of the present invention includes a processor; A power management device for providing first and second external voltages; And a memory device in communication with the processor and operating using the first external voltage as a first power source and the second external voltage as a second and a third power source, A first pad connecting an external voltage to the first power supply line; A second pad connecting the second external voltage to a second power supply line; And a third pad connecting the second external voltage to the third power supply line.
Embodiments of the present invention can improve the operation reliability of a memory device and a system that operate at high speed.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a system according to an embodiment of the present invention; FIG.
FIG. 2 is a view showing a configuration of a system according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a configuration of a system according to an embodiment of the present invention;
4 is a diagram illustrating a configuration of a memory device according to an embodiment of the present invention.
1 is a diagram showing a configuration of a
The power management integrated
The power management integrated
The
The
The
2 is a diagram showing a configuration of a
The power management integrated
The
The
The
The
3 is a diagram showing a configuration of a
The
The
The plurality of stacked
4 is a diagram showing a configuration of a
In FIG. 4, the peripheral circuit may include a
4, the
The
In FIG. 4, the
The
The
The
The
The
It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.
Claims (20)
A second pad receiving a second external voltage to provide a second power supply; And
And a third pad receiving the second external voltage to provide a third power supply.
Wherein the first to third power supply lines are not connected to each other within the memory device, the first to third power supply lines providing the first to third power supplies to the internal circuits of the memory device, respectively.
Wherein a level of the first external voltage is lower than a level of the second external voltage and a voltage level of the first power source is lower than a voltage level of the second and third power sources.
A first circuit operating using the first power supply;
A second circuit operating using the second power supply; And
And a third circuit operating using the third power supply.
Wherein the first circuit includes a data transmitter for outputting data to an external device.
And the second circuit includes a data receiver for receiving data from an external device.
Wherein the third circuit comprises peripheral circuitry for providing data stored in the memory device to the data transmitter or for storing data received via the data receiver in the memory device.
A data receiver for receiving data using a second power source received via a second pad;
A parallelizer for generating data output through the transmitter from data stored in the memory device using a third power source received via a third pad; And
And a parallelizer for aligning data received via the data receiver using the third power source.
And a data transfer driver for driving the output of the serializer to the data transmitter, wherein the data transfer driver operates using the second power supply.
Further comprising a reference voltage generator for generating a reference voltage using the second power supply,
Wherein the data receiver differentially amplifies the reference voltage and the data to receive the data.
Wherein the first pad receives a first external voltage to provide the first power source and the second and third pads commonly receive a second external voltage to provide the second and third power sources, respectively.
Wherein the level of the first external voltage is lower than the level of the second external voltage.
A data strobe transmitter for transmitting a read data strobe signal using the first power source; And
And a data strobe receiver for receiving the write data strobe signal using the second power supply.
A data strobe tree for adjusting the timing of the write data strobe signal and outputting the strobe tree to the parallelizer; And
Further comprising a data strobe generating unit for generating the read data strobe signal,
Wherein the data strobe tree and the data strobe generator each operate using the third power source.
Further comprising a strobe transfer driver for driving the read data strobe signal to output the data strobe signal to the data strobe transmitter,
Wherein the strobe transfer driver is operable to receive the third power supply.
A power management device for providing first and second external voltages; And
And a memory device in communication with the processor, the first external voltage being used as a first power source, and the second external voltage being used as a second and a third power source,
The memory device comprising: a first pad connecting the first external voltage to a first power supply line;
A second pad connecting the second external voltage to a second power supply line; And
And a third pad coupling the second external voltage to a third power supply line.
Wherein the first external voltage has a lower level than the second external voltage.
The memory device comprising: a first circuit receiving and operating the first power supply from the first power supply line;
A second circuit receiving and operating the second power supply from the second power supply line; And
And a third circuit receiving and operating the third power supply from the third power supply line.
The first circuit comprising a data transmitter for outputting data stored in the memory device to the processor,
And the second circuit includes a data receiver for receiving data transmitted from the processor.
The third circuit comprising peripheral circuitry for providing data stored in the memory device to the data transmitter or for storing data received via the data receiver in the memory device.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150109846A KR20170016582A (en) | 2015-08-04 | 2015-08-04 | Memory apparatus using a plurality of power source and system including the same |
US14/950,260 US9721623B2 (en) | 2015-08-04 | 2015-11-24 | Memory apparatus using plurality of power sources and system including the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020150109846A KR20170016582A (en) | 2015-08-04 | 2015-08-04 | Memory apparatus using a plurality of power source and system including the same |
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KR20170016582A true KR20170016582A (en) | 2017-02-14 |
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KR1020150109846A KR20170016582A (en) | 2015-08-04 | 2015-08-04 | Memory apparatus using a plurality of power source and system including the same |
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US (1) | US9721623B2 (en) |
KR (1) | KR20170016582A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2017111798A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | High retention time memory element with dual gate devices |
US10128215B1 (en) | 2016-02-16 | 2018-11-13 | Darryl G. Walker | Package including a plurality of stacked semiconductor devices having area efficient ESD protection |
US10607977B2 (en) * | 2017-01-20 | 2020-03-31 | Google Llc | Integrated DRAM with low-voltage swing I/O |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100245276B1 (en) * | 1997-03-15 | 2000-02-15 | 윤종용 | Burst mode random access memory device |
JP4408500B2 (en) * | 1999-11-18 | 2010-02-03 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
US6518794B2 (en) * | 2000-04-24 | 2003-02-11 | International Business Machines Corporation | AC drive cross point adjust method and apparatus |
JP3927788B2 (en) * | 2001-11-01 | 2007-06-13 | 株式会社ルネサステクノロジ | Semiconductor device |
KR100609039B1 (en) * | 2004-06-30 | 2006-08-10 | 주식회사 하이닉스반도체 | Input/output line circuit |
JP2008011446A (en) | 2006-06-30 | 2008-01-17 | Toshiba Corp | Semiconductor integrated circuit |
JP5288391B2 (en) * | 2007-05-24 | 2013-09-11 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
US8559558B2 (en) | 2010-02-08 | 2013-10-15 | Micron Technology, Inc. | Reference voltage generator for single-ended communication systems |
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2015
- 2015-08-04 KR KR1020150109846A patent/KR20170016582A/en unknown
- 2015-11-24 US US14/950,260 patent/US9721623B2/en active Active
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US20170040041A1 (en) | 2017-02-09 |
US9721623B2 (en) | 2017-08-01 |
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