KR20170016582A - Memory apparatus using a plurality of power source and system including the same - Google Patents

Memory apparatus using a plurality of power source and system including the same Download PDF

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Publication number
KR20170016582A
KR20170016582A KR1020150109846A KR20150109846A KR20170016582A KR 20170016582 A KR20170016582 A KR 20170016582A KR 1020150109846 A KR1020150109846 A KR 1020150109846A KR 20150109846 A KR20150109846 A KR 20150109846A KR 20170016582 A KR20170016582 A KR 20170016582A
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South Korea
Prior art keywords
data
power supply
memory device
power
external voltage
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KR1020150109846A
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Korean (ko)
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송근수
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에스케이하이닉스 주식회사
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Priority to KR1020150109846A priority Critical patent/KR20170016582A/en
Priority to US14/950,260 priority patent/US9721623B2/en
Publication of KR20170016582A publication Critical patent/KR20170016582A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The memory device may include first to third pads respectively to provide first to third power supplies to the internal circuit. The first pad may receive the first external voltage to provide the first power. The second and third pads may each receive a second external voltage in common, the second pad may provide the second power, and the third pad may provide the third power.

Figure P1020150109846

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory device using a plurality of power sources,

The present invention relates to a semiconductor device, and more particularly, to a memory device using a plurality of power sources and a system including the same.

A typical semiconductor system may include a processor and a memory device in communication with the processor. The processor and the memory device are connected to each other via a data bus, and can perform data communication while transmitting and receiving data through the data bus. The processor may include a transmitting circuit for transmitting data to the memory device and a receiving circuit for receiving data transmitted from the memory device. Likewise, the memory device may include a transfer circuit for transferring data to the processor and a receive circuit for receiving data from the processor.

A recent technology trend is to develop a semiconductor system that can communicate faster, while consuming less power. The voltage level of the power source used by the processor or memory for data communication is getting lower and the amount of data transmitted at the same time is increasing.

Embodiments of the present invention can provide a memory device capable of separating a power source of a data transmission circuit and a power source of a data reception circuit, and a system including the same.

In addition, embodiments of the present invention can provide a memory device capable of separating a power source of a data transfer circuit, a power source of a data receiving circuit, and a power source of a peripheral circuit, and a system including the same.

A memory device according to an embodiment of the present invention includes a first pad receiving a first external voltage to provide a first power source; A second pad receiving a second external voltage to provide a second power supply; And a third pad receiving the second external voltage to provide a third power source.

A memory device according to an embodiment of the present invention includes a data transmitter for outputting data using a first power source received through a first pad; A data receiver for receiving data using a second power source received via a second pad; A parallelizer for generating data output through the transmitter from data stored in the memory device using a third power source received via a third pad; And a parallelizer for aligning data received via the data receiver using the third power source.

A system according to an embodiment of the present invention includes a processor; A power management device for providing first and second external voltages; And a memory device in communication with the processor and operating using the first external voltage as a first power source and the second external voltage as a second and a third power source, A first pad connecting an external voltage to the first power supply line; A second pad connecting the second external voltage to a second power supply line; And a third pad connecting the second external voltage to the third power supply line.

Embodiments of the present invention can improve the operation reliability of a memory device and a system that operate at high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a system according to an embodiment of the present invention; FIG.
FIG. 2 is a view showing a configuration of a system according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a configuration of a system according to an embodiment of the present invention;
4 is a diagram illustrating a configuration of a memory device according to an embodiment of the present invention.

1 is a diagram showing a configuration of a system 1 according to an embodiment of the present invention. In Figure 1, the system 1 schematically shows a configuration for providing power to components of an electronic device. The system 1 may include a power supply 110 and a power management integrated circuit 120. The power supply 110 may convert AC power supplied from the outside into DC power so that the power supply 110 can be stably used in the system 1. [ In addition, various types of batteries may be used as a power source such as the power supply 110. [

The power management integrated circuit 120 may receive power from the power supply 110. The power management integrated circuit 120 may be coupled to various devices. For example, the power management integrated circuit 120 may be coupled to a system IC, such as an application processor (AP) 131, a data storage device 132, and a memory device 133. The power management integrated circuit 120 converts the power applied from the power supply 110 into a power suitable for use in each of the devices 131, 132, and 133, and supplies the converted power to each device .

The power management integrated circuit 120 may include a microcontroller 121 and a plurality of modules 122, 123, 124. The microcontroller 121 may include information about a power source suitable for use in the devices 131, 132, 133, and may store and execute a sequence or algorithm for generating the appropriate power source. The plurality of modules 122, 123 and 124 may be connected to the respective devices 131, 132 and 133 and may include a voltage regulator or the like for supplying power to the respective devices 131, 132 and 133 .

The microcontroller 121 may include a register 125 for storing the sequence or algorithm, and the register 125 may include an embedded nonvolatile memory. The register 125 stores power information of the devices 131, 132 and 133, a sequence performed by the microcontroller 121, and / or trimming information of the plurality of modules 122, 123 and 124 .

The application processor 131, the data storage device 132 and the memory device 133 may be components of an electronic device, for example, a smart phone, a tablet PC, a netbook, a personal wireless communication device, Portable multimedia devices, and the like. The application processor 131, the data storage device 132, and the memory device 133 may receive power from the power management integrated circuit 120 and operate. The application processor 131 may execute an operating system in the electronic device and perform various computing functions. The memory device 133 may be a system memory that stores information on an operating system, stores data processed by the application processor 131, and stores data generated as a result of the operation. The memory device 133 may function as a data buffer for storing data according to the control of the application processor 131 or for transmitting the stored data to the application processor 131. [ The memory device 133 may include volatile memory devices such as static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), and may also include a read only memory (ROM), a programmable ROM (PROM) Volatile memory devices such as electrically erasable and programmable ROM (EEPROM), electrically programmable ROM (EPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM And may include one or more. The data storage device 132 may be a solid state drive including a plurality of flash memories.

The memory device 133 may operate by receiving at least two different power sources. The memory device 133 may receive first and second external voltages VDD1 and VDD2 from the power management integrated circuit 120 as a power source. The level of the first external voltage VDD1 may be different from the level of the second external voltage VDD2. For example, the level of the first external voltage VDD1 may be different from the level of the second external voltage VDD2. Level. ≪ / RTI > The memory device 133 may utilize the first and second external voltages VDD1 and VDD2 as various power sources.

2 is a diagram showing a configuration of a system 2 according to an embodiment of the present invention. In FIG. 2, the system 2 may include a memory controller 210, a power management integrated circuit 220, and a memory device 230. The memory controller 210 may control the memory device 230 and may communicate with the memory device 230. The memory controller 210 may transmit and receive data DQ for data communication with the memory device 230 and may transmit and receive a data strobe signal DQS. The memory controller 210 may also provide a command signal CMD, an address signal ADD, and a clock signal CLK to control the operation of the memory device 230.

The power management integrated circuit 220 may supply power necessary for operation of the memory device 230. The power management integrated circuit 220 may supply the first and second external voltages VDD1 and VDD2 to the memory device 230. [ The memory device 230 may operate by receiving the first and second external voltages VDD1 and VDD2 having different voltage levels. In one embodiment, the memory controller 210 and the power management integrated circuit 220 may be independent components. In one embodiment, the memory controller 210 and the power management integrated circuit 220 may be components included in one processor device.

The memory device 230 may include a plurality of pads. The plurality of pads may be bonded to the packaging ball when the memory device 230 is packaged. The memory device 230 may receive various signals and power through a plurality of pads. In FIG. 2, the memory device 230 may include first to third power pads 231, 232, and 233. The first power pad 231 may receive the first external voltage VDD1 from the power management integrated circuit 220. [ The second power pad 232 may receive the second external voltage VDD2 from the power management integrated circuit 210. [

The memory device 230 may be coupled to the memory controller 210 via other pads. The memory device 230 may include a data pad 234 to transmit and receive data DQ to and from the memory controller 210. The memory device 230 may further include a data strobe pad 235 for transmitting and receiving the data strobe signal DQS to the memory controller 210. [ The memory device 230 may further include a pad 236 for receiving a command signal CMD, an address signal ADD and a clock signal CLK from the memory controller 210.

The memory device 230 may use the first external voltage VDD1 received by the first power source pad 231 as the first power source VDDQL. The memory device 230 may use the second external voltage VDD2 received by the second power pad 232 as a second power source VDDQRX. Also, the memory device 230 may use the second external voltage VDD2 received by the third power pad 233 as the third power VDDP. The first to third power source pads 231, 232, and 233 may be connected to the first to third power source lines 241, 242, and 243, respectively. The first to third power lines 241, 242, and 243 may be power meshes disposed in the memory device 230, and the first to third power lines 241, 242, And can be connected to different internal circuits. The first power supply line 241 may be a power supply mesh for supplying the first power supply VDDQL and the second power supply line 242 may be a power supply mesh for supplying the second power supply VDDQRX, 3 power supply line 243 may be a power supply mesh for supplying the third power supply VDDP. The first to third power supply lines 241, 242, and 243 may be separated without being connected to each other.

The memory device 230 may include various internal circuits for storing data transmitted from the memory controller 210 and for outputting stored data. In FIG. 2, the memory device 230 may include first through third circuits 251, 252, and 253. The first circuit 251 may operate by receiving the first power supply VDDQL through the first power supply line 241. The second circuit 252 may operate by receiving the second power supply VDDQRX through the second power supply line 242. The third circuit 243 may operate by receiving the third power supply VDDP through the third power supply line 253. Although not shown, the first to third circuits 251, 252, and 253 may operate by receiving the ground voltage in addition to the first to third power sources VDDQL, VDDQRX, and VDDP, respectively. The ground voltage may be connected through another power supply pad.

3 is a diagram showing a configuration of a system 3 according to an embodiment of the present invention. In FIG. 3, the system 3 may include a substrate 310, a processor 320, and a memory device 330. The substrate 310 may be a silicon substrate and may be an interposer providing a signal path between the processor 320 and the memory device 330. The signal path may include an electrical connection path, such as a metal layer or a silicon through vias. In addition, the substrate 310 may include any logic circuitry to form various signal paths to enable the processor 320 and the memory device 330 to perform mutual data communication with one another. The substrate 310 may be electrically connected to an external device through a package ball 340 such as a ball grid array, a bump ball, a C4 bump, or the like. The external device may be a host device connected to the system 3. In addition, the substrate 310 may be electrically connected to the processor 320 and the memory device 330 via micro bumps 350. The system 3 may be implemented in the form of a system in package, a system on chip, a flip-chip package, or a multi-chip package. And may be implemented in the form of a package on package when a plurality of packages are included.

The processor 320 receives a request from the host device and generates data DQ, a data strobe signal DQS, a command signal CMD, an address signal ADD, and the like to be transmitted to the memory device based on the request. And a clock signal (CLK). The processor 320 may control the write and / or read operations of the memory device 330. During a write operation, the processor 320 may provide data DQ, a data strobe signal DQS, a command signal CMD, an address signal ADD, and a clock signal CLK to the memory device 330 have. During a read operation, the processor 320 provides a command signal CMD, an address signal ADD and a clock signal CLK to the memory device 330, To provide data DQ and data strobe signal DQS. In FIG. 3, the processor 320 exemplifies the command signal CMD, the address signal ADD, and the clock signal CLK as signals for controlling the memory device 330, but is not limited thereto. Any signal necessary for operation of the memory device 330, such as a chip select signal, may be included in the signal for controlling the memory device 330. [

The memory device 330 may be a stacked memory device comprising a plurality of stacked chips 331, 332, 333, 334. The plurality of stacked chips 331, 332, 333 and 334 may be memory chips, and the plurality of stacked chips 331, 332, 333 and 334 may be connected to each other via through vias 360 and microbumps 370 And can be electrically connected. The plurality of stacked chips 331, 332, 333, and 334 may have a data storage space, such as a memory bank, for storing data transmitted from the processor 320.

The plurality of stacked chips 331, 332, 333, and 334 receive the first and second external voltages VDD1 and VDD2 and operate using at least three power sources. The first external voltage VDD1 may be received through the first package ball 341 and may be supplied to the first power pad 351. The second external voltage VDD2 may be received through the second package ball 342 and supplied to the second and third power pads 352 and 353, respectively. As described above, the first to third power supply pads 351, 352, and 353 may be micro-bumps. The first power source pad 351 may supply the first power source VDDQL to the plurality of the stacked chips 331, 332, 333 and 334 and the second power source pad 352 may supply the first power source VDDQL to the plurality of stacked chips 331, The third power supply pad 353 may supply the third power supply VDDP to the plurality of stacked chips 331, 332, 333, and 334 . The first to third power supplies VDDQL, VDDQRX and VDDP may be supplied to the plurality of stacked chips 331, 332, 333, and 334 through the through vias 360 and the microbumps 370.

4 is a diagram showing a configuration of a memory device 4 according to an embodiment of the present invention. In FIG. 4, the memory device 4 may be connected to an external device via a data bus and a data strobe bus. The external device may be the processor or the memory controller shown in Figs. The memory device 4 may include a data transmitter DQTX 411, a data receiver DQRX 412 and peripheral circuitry. The data transmitter 411 and the data receiver 412 may be connected between the data bus and the peripheral circuit. The data transmitter 411 may transmit data stored in the memory device 4 to an external device via the data bus. The data receiver 412 may receive data transmitted from the external device via the data bus.

In FIG. 4, the peripheral circuit may include a serializer 413 and a parallelizer 414. In Fig. 2, only a part of the configuration of the peripheral circuit is shown, and the peripheral circuit may include more logic circuits for storing or outputting data. The serializer 413 may convert the parallel data stored in the memory bank of the memory device 4 and transmitted through the data transmission line into serial data and output the converted data to the data transmitter 411 . The serializer 413 may be, for example, a circuit such as a pipe latch for outputting serial data as serial data. The parallelizer 414 may output the serial data received through the data receiver 412 as parallel data. The parallelizing unit 414 may convert the serial data into the parallel data. The data converted by the parallelizing unit 414 may be stored in the memory bank through the data transmission line of the memory device 4. [ The parallelizing unit 414 may be, for example, a data aligning circuit for outputting serial data as parallel data.

4, the data transmitter 411 may correspond to the first circuit 251 of FIG. 2, the data receiver 412 may correspond to the second circuit 252, and the serializer 413 And the parallelizing unit 414 may correspond to the third circuit 253. The data transmitter 411 may operate by receiving the first power VDDQL and the data receiver 412 may operate by receiving the second power VDDQRX. The parallelizing unit 414 can operate by receiving the third power supply VDDP. The voltage levels of the second and third power sources VDDQRX and VDDP may be substantially equal to each other and the voltage level of the first power source VDDQL may be higher than the voltage levels of the second and third power sources VDDQRX and VDDP Can be low.

The data transmitter 411 may be a transmission circuit for transmitting a signal swinging to a low level, that is, low swing data. The data transmitter 411 may be an N-over-N driver that drives the data bus according to a level of data to be output using the first power source VDDQL having a relatively low voltage level. When the memory device 4 and the processor are performing high speed and low power communication, the data receiver 412 must be able to correctly receive the low swing signal. The data receiver 412 may be a receiving circuit for receiving low swing data. Accordingly, the data receiver 412 can receive the data transmitted through the data bus 411 by receiving the second power supply VDDQRX having a voltage level higher than the power of the data transmitter 411.

In FIG. 4, the data receiver 412 can receive data by differentially amplifying a signal transmitted through the data bus with a reference voltage VREFQ. The reference voltage VREFQ may have an intermediate level of the low swing data transmitted through the data bus, for example. The memory device 4 may further include a reference voltage generator 415. The reference voltage generator VREFQ may operate using the second power supply VDDQRX. The reference voltage generator 415 may generate the reference voltage VREFQ from the second power source VDDQRX.

The memory device 4 may further include a data transfer driver 416. The data transfer driver 416 may be connected between the serializer 413 and the data transmitter 411. The data transfer driver 416 may drive the output of the serializer 413 and output the data to the data transmitter 411. For example, the data transfer driver 416 may include a pull-up and pull-down driver, amplifies the serial data output from the serializer 413, and outputs the amplified signal to the data transmitter 411 . The data transfer driver 416 may operate by receiving the second power supply VDDQRX.

The memory device 4 may further include a data strobe transmitter (DQSTX) 421 and a data strobe receiver (DQSRX) 422. The data strobe transmitter 421 and the data strobe receiver 422 may be connected to the external device through a data strobe bus. The data strobe transmitter 421 may transmit a read data strobe signal RDQS generated in the memory device in a read operation to the external device via the data strobe bus. The data strobe receiver 422 may receive a write data strobe signal WDQS transmitted from the external device via the data strobe bus in a write operation. The data strobe transmitter 421 may configure a data transmission circuit together with the data transmitter 411 and may operate using the same power source as the data transmitter 411. The data strobe transmitter 421 may operate by receiving the first power VDDQL. The data strobe receiver 422 may configure a data receiving circuit together with the data receiver 412 and may operate using the same power source as the data receiver 412. The data strobe receiver 422 may operate by receiving the second power supply VDDQRX.

The memory device 4 may further include a data strobe generator 423 and a data strobe signal tree (DQS tree) 424. The data strobe generating unit 423 may generate the read data strobe signal RDQS in a read operation. The read data strobe signal RDQS may be a signal synchronized with data output through the serializer 413 and the data transmitter 411 in a read operation. The data strobe signal tree 424 may adjust the timing of the write data strobe signal WDQS received via the data strobe receiver 422. The data strobe signal tree 424 may provide a timed write data strobe signal to the parallelizer 414. The parallelizing unit 414 may transmit the data aligned by the parallelizing unit 414 to the data transmission line and the memory bank in synchronization with the timing data of the write data strobe signal. The data strobe generator 423 and the data strobe signal tree 424 may be included in a peripheral circuit. The data strobe generator 423 and the data strobe signal tree 424 may operate by receiving the third power supply VDDP.

The memory device 4 may further include a strobe transfer driver 425. The strobe transmission driver 425 may be connected between the data strobe generator 423 and the data strobe transmitter 421. The strobe transmission driver 425 may drive the data strobe signal RDQS output from the data strobe generator 423 to output the data strobe signal to the data strobe transmitter 421. For example, the strobe transmission driver 425 may include a pull-up and pull-down driver, amplifies the read data strobe signal RDQS output from the data strobe generating unit 423, And output it to the strobe transmitter 421. The strobe transmission driver 425 may operate by receiving the third power supply VDDP.

The memory device 4 according to an embodiment of the present invention can be configured to use a suitable power source in accordance with the operating characteristics of the internal circuit. The data transmitter 411 and the data strobe transmitter 421 of the memory device 4 can transmit data and data strobe signals swinging to a low level respectively using the first power source VDDQL. Thus, the memory device 4 can be used in a system for high speed and low power communication. The data receiver 412 and the data strobe receiver 422 of the memory device 4 may also receive data and data strobe signals, respectively, using the second power supply VDDQRX. Accordingly, the data receiver 412 and the data strobe receiver 422 amplify the data and data strobe signals swinging to a low level to the voltage level of the second power supply VDDQRX, respectively, To be received. Furthermore, the memory device 4 allows the peripheral circuits other than the circuit for data transmission and reception to operate using the third power supply (VDDP), thereby reducing noise or voltage drop So that the effect does not affect the circuit for data transmission and reception.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (20)

A first pad receiving a first external voltage to provide a first power supply;
A second pad receiving a second external voltage to provide a second power supply; And
And a third pad receiving the second external voltage to provide a third power supply. The method according to claim 1,
Wherein the first to third power supply lines are not connected to each other within the memory device, the first to third power supply lines providing the first to third power supplies to the internal circuits of the memory device, respectively. The method according to claim 1,
Wherein a level of the first external voltage is lower than a level of the second external voltage and a voltage level of the first power source is lower than a voltage level of the second and third power sources. The method according to claim 1,
A first circuit operating using the first power supply;
A second circuit operating using the second power supply; And
And a third circuit operating using the third power supply. 5. The method of claim 4,
Wherein the first circuit includes a data transmitter for outputting data to an external device. 6. The method of claim 5,
And the second circuit includes a data receiver for receiving data from an external device. The method according to claim 6,
Wherein the third circuit comprises peripheral circuitry for providing data stored in the memory device to the data transmitter or for storing data received via the data receiver in the memory device. A data transmitter for outputting data using a first power source received via a first pad;
A data receiver for receiving data using a second power source received via a second pad;
A parallelizer for generating data output through the transmitter from data stored in the memory device using a third power source received via a third pad; And
And a parallelizer for aligning data received via the data receiver using the third power source. 9. The method of claim 8,
And a data transfer driver for driving the output of the serializer to the data transmitter, wherein the data transfer driver operates using the second power supply. 9. The method of claim 8,
Further comprising a reference voltage generator for generating a reference voltage using the second power supply,
Wherein the data receiver differentially amplifies the reference voltage and the data to receive the data. 9. The method of claim 8,
Wherein the first pad receives a first external voltage to provide the first power source and the second and third pads commonly receive a second external voltage to provide the second and third power sources, respectively. 12. The method of claim 11,
Wherein the level of the first external voltage is lower than the level of the second external voltage. 9. The method of claim 8,
A data strobe transmitter for transmitting a read data strobe signal using the first power source; And
And a data strobe receiver for receiving the write data strobe signal using the second power supply. 14. The method of claim 13,
A data strobe tree for adjusting the timing of the write data strobe signal and outputting the strobe tree to the parallelizer; And
Further comprising a data strobe generating unit for generating the read data strobe signal,
Wherein the data strobe tree and the data strobe generator each operate using the third power source. 15. The method of claim 14,
Further comprising a strobe transfer driver for driving the read data strobe signal to output the data strobe signal to the data strobe transmitter,
Wherein the strobe transfer driver is operable to receive the third power supply. A processor;
A power management device for providing first and second external voltages; And
And a memory device in communication with the processor, the first external voltage being used as a first power source, and the second external voltage being used as a second and a third power source,
The memory device comprising: a first pad connecting the first external voltage to a first power supply line;
A second pad connecting the second external voltage to a second power supply line; And
And a third pad coupling the second external voltage to a third power supply line. 17. The method of claim 16,
Wherein the first external voltage has a lower level than the second external voltage. 18. The method of claim 17,
The memory device comprising: a first circuit receiving and operating the first power supply from the first power supply line;
A second circuit receiving and operating the second power supply from the second power supply line; And
And a third circuit receiving and operating the third power supply from the third power supply line. 19. The method of claim 18,
The first circuit comprising a data transmitter for outputting data stored in the memory device to the processor,
And the second circuit includes a data receiver for receiving data transmitted from the processor. 20. The method of claim 19,
The third circuit comprising peripheral circuitry for providing data stored in the memory device to the data transmitter or for storing data received via the data receiver in the memory device.
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