KR20170012019A - Method for optimizing parallel matrix multiplication in a system supporting multiple CPU and multiple GPU - Google Patents

Abstract

A multi-process computing method and a computing system are provided. The computing method for a multi-process in the computing system estimates a block size to be distributed in a plurality of graphic processing units (GPU) connected to a central processing unit (CPU), and performs matrix product calculation having the block size estimated in a memory of each of the plurality of GPUs. The estimated block size is a value estimated through machine learning based on the number of the plurality of GPUs connected to the CPU, and a size of a matrix obtained through the matrix product calculation of the plurality of GPUs.

Description

[0001] The present invention relates to a computing method in a computing environment supporting a plurality of CPUs and a plurality of GPUs,

The present disclosure relates to computer processing techniques, and more particularly, to a method and system for providing parallel matrix multiplication in a computing environment comprising a plurality of CPUs (Central Processing Unit) and a plurality of GPUs (Graphics Processing Unit) .

As the demand for processing large amounts of data such as Big Data increases, there is a growing demand for computing environments using multiple CPUs and multiple GPUs. Therefore, there is a need for a computation method for speeding up numerical computation in a system composed of a multi-CPU and a multi-GPU. The GPU uses a large number of cores in parallel to simultaneously perform computations on large amounts of data, greatly speeding up computations.

Conventionally, when data is exchanged between a plurality of GPUs in a computing environment including a plurality of GPUs and a plurality of CPUs, operation data generated by operations performed in each GPU includes a QuickPath Interconnect (QPI) Channels, and the like.

In addition, when processing large amounts of data, a large scale matrix multiplication is used. Conventionally, various techniques for block decomposition of a matrix have been proposed in a system in which multi processes are implemented. On the other hand, in the system using multi-GPU, development of technology for optimal block separation of matrices is an early stage. Therefore, there is a need for a method of finding an optimum block size that can improve the matrix operation speed in a system using a multi-GPU.

SUMMARY OF THE INVENTION The object of the present disclosure is to provide a method and system for estimating an optimal block size through machine learning to speed up parallel operations in a plurality of GPUs connected to a CPU.

In order to achieve the above object, a computing system for a multi-process according to an embodiment of the present disclosure includes a first CPU (Core Processing Unit) and a first memory A computing system for a multi-process according to an embodiment of the present disclosure includes a CPU (Central Processing Unit), a central processing unit (CPU) A GPU (Graphics Processing Unit) connected to the CPU through a connector, and a memory included in each of the plurality of GPUs, wherein each of the plurality of GPUs is connected to a designated block Wherein the designated block size is determined based on a number of GPUs connected to the CPU and a size of a square matrix obtained through the matrix multiplication of the plurality of GPUs The value is estimated using a machine learning based.

In order to achieve the above object, a computing method for a multiprocess according to an embodiment of the present disclosure includes estimating a block size to be distributed to a plurality of GPUs connected to a CPU through a connector, And performing a matrix multiplication operation with the estimated block size in a memory of each of a plurality of GPUs, wherein the estimated block size is determined by the number of GPUs connected to the CPU and the matrix product of the plurality of GPUs Is a value estimated using the machine learning based on the size of the square matrix obtained through the operation.

The data processing method according to embodiments of the present disclosure can provide high performance computing (HPC) by performing high-speed parallel computation through a plurality of GPUs in a computing system including a plurality of GPUs connected to a CPU .

1 is a simplified block diagram of a computing system, in accordance with one embodiment of the present disclosure;
2 is a detailed block diagram of a computing system, in accordance with an embodiment of the present disclosure;
Figure 3 is a simplified block diagram of a computing system, in accordance with an embodiment of the present disclosure;
2 is a detailed block diagram of a computing system, in accordance with an embodiment of the present disclosure;
3 is a flow diagram illustrating a method of operation in a plurality of GPUs, in accordance with one embodiment of the present disclosure;
Figure 4 illustrates a method of operation in a plurality of GPUs, in accordance with embodiments of the present disclosure;
5 is a flow chart illustrating a method for estimating an optimal block size through machine learning, in accordance with one embodiment of the present disclosure;
Figure 6 is a graph showing execution time according to block size, in accordance with one embodiment of the present disclosure; and
7 is a table showing results of estimating the optimal block size according to an embodiment of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS The terminology used herein will be briefly described, and the present disclosure will be described in detail.

Although the terms used in this disclosure have taken into account the functions in this disclosure and have made possible general terms that are currently widely used, they may vary depending on the intent or circumstance of the person skilled in the art, the emergence of new technologies and the like.

Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Accordingly, the terms used in this disclosure should be defined based on the meaning of the term rather than on the name of the term, and throughout the present disclosure.

The embodiments of the present disclosure are capable of various transformations and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that it is not intended to limit the scope of the specific embodiments but includes all transformations, equivalents, and alternatives falling within the spirit and scope of the disclosure disclosed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the embodiments of the present invention,

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by terms. Terms are used only for the purpose of distinguishing one component from another.

The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprise", "comprising" and the like are used to specify that there is a stated feature, number, step, operation, element, component, or combination thereof, But do not preclude the presence or addition of features, numbers, steps, operations, components, parts, or combinations thereof.

In this disclosure, "module" or "module " performs at least one function or operation, and may be implemented in hardware or software or a combination of hardware and software. Also, a plurality of " modules "or a plurality of" parts "may be implemented as at least one processor (not shown) integrated into at least one module, except" module " .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. In order that the present disclosure may be more fully understood, the same reference numbers are used throughout the specification to refer to the same or like parts.

1 is a simplified block diagram of a computing system, in accordance with one embodiment of the present disclosure; 1, the computing system 10 includes a plurality of CPUs (Central Processing Units) 110 and 210, a plurality of CPUs 110 and 210, and a plurality of memories 130 and 230, And a plurality of connectors 120, 220 that connect to the connectors 140, 150, 240, 250.

The system 10 may be, for example, a supercomputer comprising a plurality of CPUs and a plurality of GPUs. In addition, the system 10 may be a computing system that includes one CPU and a plurality of GPUs. The system 10 may be embodied in one electronic device, such as a computer or the like.

Each of the CPUs 110 and 210 may be a chipset including a system memory. Each GPU 140, 150, 240, 250 may be a special purpose processor for processing graphics data such as video games and the like. For example, the GPU may be, but is not limited to, an NVIDA ^TM GPU.

The connectors 120 and 220 are connected to a plurality of GPUs 140, 150, 240 and 250 connected to the connectors 120 and 220 through buses which are a plurality of network interfaces, 130, and 230 and the CPUs 110 and 210, respectively.

May be, for example, connectors 120, 220 are bridge-type (bridged) host interface, a PCI Express (Peripheral component interconnect express, PCIe ^TM) Root Complex (root complex) from the system. For the convenience of description, a computing system implemented with a PCIe ^TM system will be described in the present disclosure, but the present invention is not limited thereto. The term " root complex " as used in this disclosure may mean " connector. &Quot;

According to one embodiment of the present disclosure, a plurality of first GPU (Graphics Processing Unit) GPU1 140 and GPU2 150 are connected via a first connector 120 to a first CPU ) 110 and the first memory 130. [ The plurality of second GPUs GPU3 240 and GPU 250 may be connected to the second CPU 210 and the second memory 230 via a second connector 220. [ Also, the first CPU 110 and the second CPU 210 can communicate through communication paths connecting the CPUs 110 and 210, respectively.

According to one embodiment of the present disclosure, each of a plurality of first GPUs 140, 150 may generate a first computational data by performing a first computation based on address information stored in memory of each other. In addition, each of the second GPUs 240 and 250 can generate the second calculation data by performing the second calculation based on the address information stored in the memory of the second GPU 240 and the second GPU 240. The first calculation data and the second calculation data can be exchanged through a communication path.

For example, each of the GPUs 140 and 150, which is a plurality of first GPUs commonly connected to the first connector 120, performs an operation and generates first calculation data, The GPUs 240 and 250, which are a plurality of connected second GPUs, may each perform an operation to generate second operation data.

As another example, the GPU1 140 and the GPU2 150 connected to the first connector 120 may share one switch shown in Fig. In addition, the GPU1 140 and the GPU2 150 may be connected to different switches and connected to one first connector 120, respectively.

If GPU1 (140) and GPU2 (150) is connected to a different switch connected to the first connector (120), GPU1 (140) and GPU2 (150) are connected to each other via a bus, such as the NVIDIA Lane ^TM (NVIDIA Lane ^TM) It is possible. At this time, the GPU1 140 and the GPU2 150 can directly perform mutual address information request through the connected bus without passing through the first connector 120, thereby performing calculation.

The operation method of the GPU3 240 and the GPU4 250 connected to the second connector 220 corresponds to the operation method of the GPU1 140 and the GPU2 150 connected to the first connector 120, do.

Although two GPUs 140, 150, 240, and 250 are shown connected to the connectors 120 and 220 in FIG. 1, the connectors 120 and 220 may be connected to two or more GPUs . Also, in the computing system 10, the plurality of CPUs 110 and 210 may each include one or more connectors 120 and 220, but the computing system 10 includes connectors of the plurality of CPUs 110 and 210 It may include a CPU that does not.

The plurality of first GPUs 140 and 150 and the plurality of second GPUs 240 and 250 may each include a memory. In addition, the operations performed on each GPU may be a parallel matrix multiplication operation performed to cause the other GPUs to be accessed based on the addresses stored in the memory of each GPU. The parallel matrix multiplication of the GPU can be performed in the memory of each GPU.

In one embodiment of the present disclosure, the target address of GPU2 150, which is at least one GPU of each GPU 140, 150, 240, 250, is coupled to GPU2 150, The exchange of computational data between the GPU2 150 and the GPU2 150 and the GPU3 240 connected to the other connector 220 is performed via a communication path interconnecting the CPU1 110 and the CPU2 210 .

For example, the communication path may be, but is not limited to, Hyper Transport (HT) or QuickPath Interconnect (QPI).

The plurality of first GPUs 140 and 150 and the plurality of second GPUs 240 and 250 may be connected to the respective connectors 120 and 220 through a switch. A plurality of switches connected to the first connector 120 and the second connector 220 may be provided. The switches connecting the connectors 120 and 220 and the plurality of GPUs 140, 150, 240, and 250 will be described with reference to FIG.

At least one of the plurality of GPUs 140, 150, 240, and 250 connected to the CPUs 110 and 120 may be a master, and the remaining GPUs may be slaves. For example, when four GPUs are connected to the first CPU 110, one of the four GPUs may be a master and the remaining three may be slaves. The master GPU can construct a database in the memory of the master GPU or in the host memory of the CPU, the size of the input matrix of each GPU, the number of GPUs connected to the CPU, and the block size for matrix multiplication in a plurality of GPUs.

According to one embodiment of the present disclosure, a master GPU can estimate an optimal block size by which a plurality of GPUs can perform a shortest matrix multiplication operation using machine learning based on data stored in a database. The method of estimating the optimal block size will be described in detail in FIGS.

2 is a detailed block diagram of a computing system, in accordance with one embodiment of the present disclosure; Referring to FIG. 2, the computing system 10 may include a plurality of CPUs, such as a first CPU 110 and a second CPU 210. Each of the CPUs 110 and 210 may be connected to the first route complex 120 and the second route complex 220 via the PCIe ^TM bus, respectively. The first contains the root complex 120 and the second root complex 220 includes a plurality of PCIe ^TM device downstream ports (PCIe ^TM device downstream port) (270) and can be accessed in each memory (130 and 230).

Each root complex 120, 220 can communicate with a plurality of GPU-connected PCIe ^TM switches 160, 260 via a PCIe ^TM bus. Root complex through the PCIe ^TM device downstream ports 270, one of which is PCIe and PCIe ^TM device upstream port (PCIe ^TM device upstream port) (280) of the PCIe ^TM switch (160, 260) ^TM bus (120, 220) Communication can be performed.

The PCIe ^TM switch 106 and 260 includes a plurality of PCIe ^TM device downstream ports 270 and the PCIe ^TM device downstream port 270 includes a PCIe ^TM device upstream port 280 of one GPU 140 and 150 ) And the PCIe ^TM bus. Each of the GPUs 140, 150, 240, and 250 may include GPU memories 140-1, 150-1, 240-1, and 250-1. Each GPU 140, 150, 240, 250 can access the memory 140-1, 150-1, 240-1, 250-1 of each GPU via a PCIe ^TM bus. The memory 140-1, 150-1, 240-1, and 250-1 of each GPU can perform a large number of parallel matrix multiplication operations.

For example, the plurality of CPUs 110 and 210 constituting the computing system 10 may be interconnected through a QuickPath Interconnect (QPI).

However, the configuration of the computing system 10 shown in FIG. 2 is only one embodiment for explaining the present disclosure, but is not limited thereto, and can be variously implemented.

Figure 3 is a flow diagram illustrating a method of operation in a plurality of GPUs, in accordance with one embodiment of the present disclosure;

In step S310, a parallel matrix multiplication operation is performed on each of a plurality of GPUs connected to each of the root complexes constituting the computing system 10. [ The parallel matrix multiplication operation is accessed in the memory of another GPU based on the address stored in the memory of each GPU, and can be performed in each memory of the GPU.

For example, a parallel matrix multiplication operation performed on the GPU may be a square matrix of C = AxB. In this case, A may be an input matrix NxN of the first GPU, B may be an input matrix NxN of the second GPU, and C may be a square matrix NxN according to a parallel matrix multiplication operation of the first GPU and the second GPU . Specifically, C (i) may be a row vector of an NxN square matrix and the following function.

Here, | B | is is (belong to) a block in a row of the matrix (blocks), S _i is the i-th GPU, A (i) belonging to the S _i | of the GPU included in / S, S is a CPU | B The number, B (i, j), may be | B | / S and | B | / S may be sub-blocks of B (i).

Conventionally, when a GPU includes a plurality of CPUs and each CPU performs a parallel matrix multiplication operation in a computing system 10 including a plurality of GPUs, a CPU You must exchange B (j) with another CPU. Therefore, there is a problem that the speed of the calculation is lowered.

According to one embodiment of the present disclosure, a matrix multiplication operation of a plurality of GPUs may be performed in the memory of each GPU. In addition, matrix multiplication operations of a plurality of GPUs are performed first among GPUs connected to a common root complex. Therefore, the GPU operation method according to the present embodiment of the present invention can improve the operation speed because it does not have to pass the communication path such as QPI every time when the operation is performed in the GPU as in the prior art.

In step S330, operation data exchange between a plurality of GPUs connected to different root complexes among a plurality of GPUs constituting the computing system 10 is performed. A parallel matrix multiplication operation in the GPU can be accessed to another GPU based on the address stored in the memory of each GPU. Thus, the target address of at least one GPU of a plurality of GPUs coupled to a common root complex may be one of a plurality of GPUs coupled to other root complexes.

For example, when a plurality of root complexes are connected to a common CPU, the target address of at least one of the plurality of GPUs connected to the common root complex is one of a plurality of GPUs connected to another root complex connected to a common CPU . At this time, each GPU does not pass a communication path such as QPI, and can exchange computation data generated as a result of computation in a common CPU. Therefore, the operation speed can be improved as compared with the conventional art.

In step S350, GPU operation data exchange between a plurality of CPUs constituting the computing system 10 is performed. As described above in step S330, the target address of at least one of the plurality of GPUs coupled to the common root complex may be one of a plurality of GPUs connected to the other root complexes.

For example, the target address of the first GPU coupled to the first root complex of the first CPU may be in the memory of the second GPU coupled to the second root complex of the second CPU. At this time, the first GPU performs the first calculation data acquired from the plurality of first GPUs of the first CPU and the second calculation data acquired from the plurality of second GPUs of the second CPU through the communication path such as QPI .

4 is a diagram illustrating a method of operation in a plurality of GPUs, in accordance with embodiments of the present disclosure.

Referring to Figure 4, a thin line 410 is computed on a plurality of GPUs (GPU1 and GPU2, GPU3 and GPU4, GPU5 and GPU6, GPU7 and GPU8) connected via a common root complex and a common switch Lt; / RTI > A plurality of GPUs (GPU1 and GPU2, GPU3 and GPU4, GPU5 and GPU6, GPU7 and GPU8) can perform parallel matrix multiplication based on address information stored in the memory of each GPU to generate operation data. Each GPU can exchange generated computation data.

For example, GPU1 and GPU2 may be connected via a bus such as a PCIe ^TM bus, and GPU1 and GPU2 may directly access each memory to perform operations. GPU3 and GPU4, GPU5 and GPU6, and GPU7 and GPU8, respectively, can perform operations in the same manner as the calculation methods of GPU1 and GPU2.

The dot line 420 illustrates the exchange of data in a plurality of GPUs (GPU1 and GPU4, GPU2 and GPU3, GPU5 and GPU8, GPU6 and GPU7) connected to a common root complex via different switches.

For example, the GPU 1 may exchange data with the first route complex or the GPU 4 via the PCIe ^TM bus to the first switch. GPU2 and GPU3, GPU5 and GPU8, GPU6 and GPU7, respectively, can exchange data in the same way as data exchange between GPU1 and GPU3.

The thick line 430 shows the exchange of data between a CPU and a plurality of GPUs that do not share a root complex.

A communication path such as a QPI that interconnects the first CPU and the second CPU via a PCIe ^TM bus connecting each device (CPU, root complex, switch, memory, GPUs) of the computing system 10 So that data exchange with the GPU 8 can be performed. GPU4 can exchange data using GPU5 and QPI communication path. When GPU1 and GPU8, GPU4, and GPU5 exchange data with each other, each GPU can pass through a switch, a root complex, and a CPU connected through a PCIe ^TM bus.

Each root complex can receive an access request from each GPU to memory associated with each root complex. The root complex can receive the results of data exchange between multiple GPUs on behalf of the CPU and store the results in memory (included) connected to the root complex. The root complex can transfer the data exchange result of a plurality of GPUs to the CPU, and the CPU can store the received data in the host memory included in the CPU.

That is, conventionally, the GPU data could be exchanged using the QPI by the number of GPUs included in the computing system 10 (the embodiment of FIG. 4: 8), but the method according to the embodiment of the present disclosure is not applicable to the computing system 10 QPI can be used by the number of CPUs (the embodiment of FIG. Accordingly, the data exchange method between a plurality of GPUs according to the embodiments of the present disclosure described above can significantly improve the computation speed of graphics processing by greatly reducing the number of QPI use times compared to the conventional method.

5 is a flow chart illustrating a method for estimating optimal block size through machine learning, in accordance with one embodiment of the present disclosure.

For example, a plurality of GPUs may perform parallel matrix multiplication using a programming model such as NVDIA CUDA ^TM . However, this is only one embodiment for explaining the present disclosure, but is not limited thereto.

In operation S510, the computing system 10 may construct a database for estimating an optimal block size in a parallel matrix multiplication of a plurality of GPUs connected to one CPU.

The computing system 10 may split an input matrix of a square matrix by matrix multiplication of a plurality of GPUs into a plurality of blocks. The computing system 10 may distribute a plurality of separate blocks to a master GPU and a slave GPU, respectively. Therefore, when the optimal block size to be distributed to each GPU is extracted from the input square matrix, the operation speed of a plurality of GPUs can be optimized.

The computing system 10 can determine one of the plurality of GPUs included in one CPU as a master and the remaining GPUs as a slave. The computing system 10 may store the number (n) of GPUs included in one CPU, the input matrix size (s) of each GPU, and the block size (b) of the square matrix as a database. The database may be the memory of the master GPU or it may be the big data store of the computing system 10. In step S520, the computing system 10 may perform the steps of, for example, Deep Learning In block matrix decomposition, the block size is calculated by multiplying the execution time of the GPU by the parallel matrix multiplication using multiple GPUs. run time. Therefore, it is possible to estimate the optimum block size and shorten the data processing time through the GPU.

6 is a graph showing execution time according to a block size, according to an embodiment of the present disclosure;

As described in FIG. 3, for example, it may be a square matrix C = AxB according to the matrix multiplication operation in two GPUs. In this case, A may be an NxN matrix of the first GPU, B may be an NxN matrix of the second GPU, and C may be a square matrix of NxN, which is a parallel multiplication matrix of an A matrix and a B matrix.

FIG. 6 is a graph showing a matrix multiplication rate according to a block size using a random matrix multiplication of 10,000 x 10,000 (AxB) square matrix using four GPUs.

Referring to FIG. 6, when the number of blocks is small (# of Block), it means that the block size of the square matrix is relatively largely decomposed, meaning that a lot of data is allocated in one block. At this time, since the amount of operation data in a plurality of GPUs processed in one block increases, the input matrix operation processing time can be reduced. However, when the number of blocks is too small, the block size of the square matrix is decomposed too much, so that the amount of operation data in the GPU is excessively increased, and the input matrix operation processing time can be increased.

Also, when the number of blocks (# of Block) is large, it means that the block size of the square matrix is relatively small, meaning that the number of block data exchanges increases between a plurality of GPUs. Therefore, as the number of data exchanges between a plurality of GPUs increases, the input matrix multiplication processing time in a plurality of GPUs may increase.

For example, in FIG. 6, if the number of blocks of the square matrix is decomposed into about 50, the number of blocks may be optimal. At this time, the data may be distributed evenly among a plurality of GPUs. Thus, the rate of input matrix computation can have an optimal value.

According to one embodiment of the present disclosure, when a square matrix C is decomposed into a plurality of blocks in a square matrix C = AxB in a parallel matrix multiplication operation using a plurality of GPUs described in FIG. 3, a parallel matrix multiplication operation a function for estimating an optimal block size (b *) for a parallel matrix multiplication may use b * = g (n, s). Where n is the size of the square matrix and s is the number of GPUs that perform operations on one CPU. The function g may be a function of inferring the optimal block size (b *) using machine learning and regression analysis such as deep running.

Regression analysis is an analytical method that measures fitness between two variables for observed continuous variables. As an example, a Gaussian process regression may be used. Data analysis through machine learning using an artificial neural network can also provide statistically high accuracy. In this disclosure, Gaussian regression analysis was applied to estimate the optimal block size, but this is not an exhaustive list.

For example, machine learning such as deep learning can extract hidden key values from a database, such as Big Data. In Deep Neural Networks (DNN), input values can be computed, training is repeated, and key values obtained from training can be deduced.

According to one embodiment of the present disclosure, the input value to the deep neural network (DNN) may be the size (n) of the square matrix in the square matrix C = AxB, the number of GPUs connected to the CPU (s) . At this time, the testing function for extracting the optimal block size (b *) may be b * = arg _b min f (s, n, b). Here, f (n, s, b) may be the execution time of the parallel matrix multiplication function f . The system 10 can extract the function b * = g (n, s) using the deep learning machine learning method and the regression analysis based on the values (n, s, b) input to the DNN. Thus, the system 10 can infer the h-dimensional vector, which is the number of hidden nodes in the DNN.

7 is a table showing results of estimating the optimal block size according to an embodiment of the present disclosure.

According to one embodiment of the present disclosure, a database can be created by logging the function f (n, s, b). As described above, n may be the size of the input matrix of the GPU, s may be the number of GPUs included in the CPU, and b may be the block size in matrix multiplication. For example, n may be an input matrix of size 4,000 (4k), 8,000 (8k), 16,000 (16k). s can be the number of 2, 3, 4, etc. GPUs. b may be in the range of 1k, 2k, 4k, 8k, and 16k. For example, one CPU includes two GPUs, a square matrix input through two GPUs is 16,000 (16k), and an input square matrix is divided into blocks of 4,000 (4k) x 4,000 (4k) decomposed and distributed to each GPU.

The table of Fig. 7 shows the mean and standard deviation of the parameters of the function f (n, s, b) obtained by repeating matrix multiplication 10 times. The results of each item in the table are the mean and standard deviation of the function f (n, s, b) performed more than 5 times at a specific s, n, b value (the numbers in parentheses are the standard deviations, )to be. The numbers in circles in the table indicate the average values at n, s, and b obtained from the optimal block size (b *). Based on the data obtained from the table, the computing system 10 may generate metadata and apply a Gaussian process regression to the metadata values.

Accordingly, when a parallel matrix multiplication operation is performed in a plurality of GPUs included in a CPU, a parallel matrix is divided into a plurality of blocks based on block decomposition in a plurality of GPUs, , And a matrix having an optimal block size for a plurality of GPUs can be distributed by estimating an optimal block size. At this time, neural network machine learning and regression analysis (e.g., Gaussian process regression) can be used to estimate the optimal block size.

According to one embodiment of the present disclosure described above, machine learning can be used to estimate an optimal block size to be distributed to a plurality of GPUs. Accordingly, high-speed parallel computing is performed through a plurality of GPUs connected to the CPU, thereby providing High Performance Computing (HPC).

Meanwhile, the above-described method can be implemented in a general-purpose digital computer that can be created as a program that can be executed by a computer and operates the program using a computer-readable recording medium. In addition, the structure of the data used in the above-described method can be recorded on a computer-readable recording medium through various means. The computer-readable recording medium includes a storage medium such as a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), optical reading medium (e.g., CD ROM,

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, disclosure methods should be considered from an illustrative point of view, not from a restrictive point of view. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

10: Computing System
110: first CPU, 210: second CPU
120: first connector (root complex) 220: second connector (root complex)
130: first memory 23: second memory
140: first GPU, 150: second GPU, 240: third GPU, 250: fourth GPU

Claims (12)

In a computing system for multi-process,
A CPU (Central Processing Unit);
A plurality of GPU (Graphics Processing Unit) connected to the CPU, and
And a memory included in each of the plurality of GPUs,
Each of the plurality of GPUs performing a matrix multiplication with a designated block size in the memory of each GPU,
Wherein the designated block size is a value estimated using machine learning based on a number of GPUs connected to the CPU and a size of a square matrix obtained through the matrix multiplication of the plurality of GPUs. The method according to claim 1,
Wherein one of the plurality of GPUs is a master and the remaining GPUs are slaves, and the master GPU stores the input matrix size of each of the plurality of GPUs, the number of the plurality of GPUs, and the block size in a memory of the master GPU as a database Building a computing system. 3. The method of claim 2,
The master GPU includes:
And divides the square matrix into the estimated block size to distribute to the master GPU and the slave GPU. The method according to claim 1,
The testing function for extracting the optimum block size (b *) using the machine learning is b * = arg _b min f (s, n, b)
Where b * is the optimal block size, f (n, s, b) is the execution time of the parallel matrix multiplication function f , s is the number of GPUs connected to the CPU, n is the size of the input square matrix, Sized computing system. 5. The method of claim 4,
Wherein the function for estimating the block size for performing the shortest matrix through the machine learning comprises:
b * = g (n, s)
Where g is a function that deduces an optimal block size (b *) using machine learning and regression analysis. The method according to claim 1,
And a network interface connecting each of the plurality of GPUs,
The matrix multiplication operation may include:
Wherein each of the plurality of GPUs is accessed through a memory of a different GPU through the network interface based on an address stored in a memory of each of the plurality of GPUs. A computing method for a multiprocess,
Estimating a block size to be distributed to a plurality of GPUs connected to the CPU; And
Performing a matrix multiplication operation with the estimated block size in a memory of each of the plurality of GPUs,
Wherein the estimated block size is a value estimated using machine learning based on a number of GPUs connected to the CPU and a size of a square matrix obtained through the matrix multiplication of the plurality of GPUs. 8. The method of claim 7,
One of the plurality of GPUs is a master and the remaining GPUs are slaves,
Wherein the estimating step comprises:
Constructing a database of the input matrix size of each of the plurality of GPUs, the number of the plurality of GPUs, and the block size in a memory of the master GPU. 9. The method of claim 8,
Wherein the master GPU further comprises splitting the square matrix into the estimated block size and distributing the square matrix to the master GPU and the slave GPU. 8. The method of claim 7,
The testing function for extracting the optimum block size (b *) using the machine learning is b * = arg _b min f (s, n, b)
Where b * is the optimal block size, f (n, s, b) is the execution time of the parallel matrix multiplication function f , s is the number of GPUs connected to the CPU, n is the size of the input square matrix, Size computing method. 11. The method of claim 10,
Wherein the function for estimating the block size for performing the shortest matrix through the machine learning comprises:
b * = g (n, s)
Where g is a function of inferring an optimal block size (b *) using machine learning and regression analysis. 8. The method of claim 7,
And a network interface connecting each of the plurality of GPUs,
The matrix multiplication operation may include:
Wherein each of the plurality of GPUs is accessed and stored in a memory of a different GPU through the network interface based on an address stored in a memory of each of the plurality of GPUs.

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