KR20170009660A - Non-volatile memory device based on variable resistance - Google Patents

Abstract

The present invention relates to a nonvolatile memory element using a resistance change. According to an embodiment of the present invention, provided is a nonvolatile memory element including: at least one first wire structure including a first surface layer of an aluminum oxide in at least one part; and at least one second wire structure including a second surface layer of a carbon inclusion, touching the first surface layer of the aluminum oxide, in at least one part. A reversible electrochemical reaction product is generated or eliminated between carbon of the carbon inclusion and the aluminum oxide, on a contact interface between the second surface layer of the second wire structure and the first surface layer of the first wire structure depending on a current or potential applied to the first and second wire structures. The nonvolatile memory element has at least two resistance levels in order to control the size of the current, flowing along the first and second wire structures, according as the reversible electrochemical reaction product is generated or eliminated.

Description

[0001] The present invention relates to a non-volatile memory device,

The present invention relates to a memory device, and more particularly, to a nonvolatile memory device using a resistance change.

2. Description of the Related Art In recent years, the nonvolatile memory market is rapidly expanding as demand for portable digital applications such as digital cameras, MP3 players, personal digital assistants (PDAs), and mobile phones increases. As a programmable nonvolatile memory device, a NAND flash memory is a typical example. A nonvolatile memory device that can replace the nonvolatile memory device has been attracting attention as a resistive memory device (ReRAM) using a variable resistor whose resistance value changes reversibly.

It is possible to realize a low power memory device in which the cell configuration can be simplified since the physical property of the resistance value of the variable resistor can be used as a data state itself and low power driving is possible. However, since a typical resistive memory element is fabricated by a lamination structure of metal-insulator-metal (MIM), a high-temperature oxidation process is required to form the insulator layer. Such a high-temperature oxidation process makes it difficult to apply a polymer device which is difficult to process at a high temperature, and thus becomes a limiting factor for a new application such as a flexible device. As an alternative, a low temperature process using the solution-based wet coating of the insulating layer has been proposed. However, such a wet process is difficult to obtain a reliable and uniform insulating layer, and its application to practical nonvolatile memory devices is limited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which has two or more resistance value levels reversibly changing without a complicated insulating layer formation process by a high- And to provide a volatile memory device.

According to an aspect of the present invention, there is provided a nonvolatile memory device comprising: at least one first wiring structure having a first surface layer of aluminum oxide on at least a part thereof; And at least one second wiring structure having a second surface layer of a carbon-containing material in contact with the first surface layer of the aluminum oxide at least in part, wherein at least one of the first wiring structure and the second surface structure has a potential or current , A reversible electrochemical reaction product is generated or extinguished between the aluminum oxide and the carbon of the carbon-containing layer at the contact interface between the first surface layer of the first wiring structure and the second surface layer of the second wiring structure. At least two resistance levels may be provided to control the magnitude of the current flowing along the first and second wiring structures according to the generation or disappearance of the reversible electrochemical reaction product.

In one embodiment, at least one of the first wiring structure and the second wiring structure may have a linear structure. The first wiring structure may include an underlying aluminum layer or aluminum core, the aluminum layer and the aluminum oxide on the aluminum core, and the second wiring structure may include carbon fibers.

The aluminum layer may be formed by wet coating, electrolytic plating, and electroless plating. Either one of the first wiring structure and the second wiring structure may have a planar structure. The first wiring structure having the planar structure may have an aluminum film, an aluminum foil or an aluminum sheet structure.

And the other of the first wiring structure and the second wiring structure may have a linear structure. The aluminum oxide may be a natural oxide film. The reversible electrochemical reaction product may comprise an aluminum carbon oxide. The aluminum carbon oxide may include any one of Al ₄ O ₄ C, and Al ₂ OC, or a mixture thereof. Preferably, the aluminum carbon oxide may include Al ₄ O ₄ C, the non-volatile memory device has a low resistance level when the Al ₄ O ₄ C is generated, and the Al ₄ O ₄ C And has a high resistance level when it is destroyed. The set voltage of the nonvolatile memory element is in the negative bias region and the reset voltage is in the positive bias region.

The first wiring structure and the second wiring structure may have a woven structure, a weave, a nonwoven fabric, or a combination structure thereof. Wherein one of the first wiring structure and the second wiring structure surrounds the other or surrounds the other.

A support may be further provided to be coupled to at least one of the first wiring structure and the second wiring structure to maintain contact between the first wiring structure and the second wiring structure.

The first wiring structure and the second wiring structure may be embedded in the support. At least one of the first wiring structure and the second wiring structure may be coupled to the support by threading the support. The support may comprise a fabric, a nonwoven fabric, a flexible insulating sheet or a combination thereof. In one embodiment, the first and second wiring structures form a memory cell array, and peripheral circuits for driving the memory cell array can be mounted in the support. The first wiring structure and the second wiring structure may be flexible.

According to one embodiment, there is provided a non-volatile memory device comprising a memory cell that provides a resistance level of at least two as a result of the generation or dissipation of a reversible electrochemical reaction product between an aluminum oxide layer and a carbon layer in contact with the aluminum oxide layer. May be provided.

According to an embodiment of the present invention, after forming the contact interface by contacting the first surface layer of the aluminum oxide of the first wiring structure and the second surface layer of the carbon containing material of the second wiring structure to each other, Volatile memory device in which a resistance value level of at least two can be provided without forming a different kind of insulating layer such as another oxide film between the wiring structures by forming a reversible electrochemical reaction product on the contact interface Can be provided.

Figures 1A-1C illustrate unit cells of non-volatile memory devices according to various embodiments of the present invention.
FIG. 2A is a block diagram of a non-volatile memory device according to another embodiment of the present invention, and FIG. 2B is a perspective view illustrating the memory cell array of FIG. 2A.
3A and 3B are perspective views showing a memory cell array according to an embodiment of the present invention.
4A and 4B are perspective views showing a memory cell array according to another embodiment of the present invention.
5A is a graph showing electric characteristics of a current-voltage of a non-volatile memory device including a first wiring structure of an aluminum film having a contact interface and a second wiring structure of carbon fibers according to an embodiment of the present invention, and FIG. 5B Is a graph showing the cycle reliability of the non-volatile memory device of FIG. 5A.
FIG. 6 is a graph showing a composition change due to an electrochemical reaction by voltage driving at a contact interface between a first wiring structure, which is an aluminum film, and a second wiring structure, which is a carbon fiber.
Figs. 7A to 7D are graphs showing Al2p peaks in an initial state (Initial), a set state (SET), and a reset state (RESET) only in contact with an aluminum film (Al reference), an aluminum film as reference values by XPS analysis.
8A to 8D are graphs showing C1s peaks of an Al film, Al film, Initial state, SET state and Reset state RESET, respectively, as reference values.
9 is a block diagram illustrating an electronic system including a non-volatile memory device in accordance with one embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, The present invention is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

Like numbers refer to like elements in the drawings. Also, as used herein, the term "and / or" includes any and all combinations of any of the listed items.

The terms used herein are used to illustrate the embodiments and are not intended to limit the scope of the invention. Also, although described in the singular, unless the context clearly indicates a singular form, the singular forms may include plural forms. Also, the terms "comprise" and / or "comprising" used herein should be interpreted as referring to the presence of stated shapes, numbers, steps, operations, elements, elements and / And does not exclude the presence or addition of other features, numbers, operations, elements, elements, and / or groups.

Reference herein to a layer formed "on" a substrate or other layer refers to a layer formed directly on top of the substrate or other layer, or may be formed on intermediate or intermediate layers formed on the substrate or other layer Layer. ≪ / RTI > It will also be appreciated by those skilled in the art that structures or shapes that are "adjacent" to other features may have portions that overlap or are disposed below the adjacent features.

As used herein, the terms "below," "above," "upper," "lower," "horizontal," or " May be used to describe the relationship of one constituent member, layer or regions with other constituent members, layers or regions, as shown in the Figures. It is to be understood that these terms encompass not only the directions indicated in the Figures but also the other directions of the devices.

As used herein, the term "at least one wiring structure" refers to conductors that are individually accessible or grouped and accessible. The conductors have a linear structure or an area structure, and the term linear structure refers to a structure having an appropriate aspect ratio that can linearly expand linearly one-dimensionally to make point contact or line contact with other structures. The term planar structure refers to a structure having a suitable area that is two-dimensionally extended to make line contact with the linear structure.

The linear structure is not limited to one extending in one direction, and it is possible to perform various extending directions such as bending, bending, rotating, winding, spiraling, meandering, lapping, twisting, or a combination thereof. Likewise, the planar structure is not limited to being flatly extended, and it is possible to manipulate various extending directions such as bending, bending, twisting, curling, overlapping, folding, or bending. This operation enables nonvolatile memory devices according to embodiments of the present invention to be applied to wearable devices and electronic devices requiring a change in shape.

In the following, embodiments of the present invention will be described with reference to cross-sectional views schematically illustrating ideal embodiments (and intermediate structures) of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein. In addition, reference numerals of members in the drawings refer to the same members throughout the drawings.

1A-1C illustrate unit cells 10A, 10B, and 10C of non-volatile memory devices in accordance with various embodiments of the present invention.

1A, a nonvolatile memory device 10A includes a first wiring structure 1A and a second wiring structure 2 in contact with the first wiring structure 1A. The first wiring structure 1A may have a planar structure, and a planar structure is illustrated in Fig. The planar structure may be, for example, a film.

The second wiring structure 2 may have a linear structure, and a linear structure is exemplified. The linear structure may be, for example, wire or fiber. In another embodiment, the second wiring structure 2 is not limited to the straight line structure, but may be formed by a variety of extending directional structures such as bending, bending, rotating, winding, spiraling, meandering, overlapping, twisting, Lt; / RTI > Even the second wiring structure 2 may thread or surround the first wiring structure 1A. Or vice versa.

The second wiring structure 2 can be in line contact with the first wiring structure 1A and the contact interface CI defined by this line contact can have a width or length of several nm to several mu m, Whereby a memory cell can be defined. The present invention is not limited to the width or length of the contact interface CI.

Electrical signals can be input and output to and from these wiring structures 1A and 2 and the wiring structures 1A and 2 are electrically connected to each other by the line contact between the wiring structures 1A and 2, Can be provided. In one embodiment, the first wiring structure 1A may be a planar structure having a surface layer 1s of aluminum oxide. The surface layer 1s of the aluminum oxide may be formed on the whole or part of the first wiring structure 1A.

Such a planar structure may be, for example, an aluminum film having a surface layer 1s as a natural oxide film, or a composite film in which an aluminum layer is formed on the base of the aluminum oxide. The composite film may be a planar structure on which the aluminum layer is coated on a flexible substrate such as a resin-based material such as polyimide, rayon, yarn, fabric, cotton, paper, or a nonwoven fabric. The coating of the aluminum layer may be formed by an atomic layer deposition process capable of sputtering or a low temperature process or a wet coating or electrolytic or electroless plating in which an aluminum precursor suitable for a solvent is dissolved and dispersed for coating, It is not.

The second wiring structure 2 is a linear structure including a carbon-containing surface layer 2s in contact with the surface layer 1s of the aluminum oxide. The carbon-containing material may include amorphous carbon or crystalline carbon, and may be a graphene or carbon nanotube coating material. In one embodiment, the second wiring structure 2 may be provided with a conductive or non-conductive fiber core and a carbon-containing layer 2s coated on at least a part of the fiber core. The conductive or non-conductive fiber core may include a metal, a conductive polymer, a laminated structure thereof, or a mixture thereof, but the present invention is not limited thereto. In another embodiment, the second wiring structure 2 may be made of a single structure of carbon fibers. In this case, the carbon-containing layer 2s may be provided by the surface of the carbon fiber itself.

When the first wiring structure 1A and the second wiring structure 2 form a contact interface CI, a variable voltage or current signal is applied between the first wiring structure 1A and the second wiring structure 2 A reversible electrochemical reaction product is generated in the contact interface CI of the line-contacted wiring structures 1A and 2 while the current I flows through the first wiring structure 1A and the second wiring structure 2 Or may be destroyed.

According to the embodiment of the present invention, two or more resistance value levels may be provided in the conductive path by the first wiring structure 1A and the second wiring structure 2 in accordance with generation or disappearance of the reversible electrochemical reaction product Quot; 0 "or" 1 ", for example, to such a resistance value level, information can be stored and a nonvolatile memory element can be provided. The change of the reversible electrochemical reaction product and the resistance value level will be described later with reference to FIG. 5A.

Referring to FIG. 1B, the nonvolatile memory element 10B includes a first wiring structure 1B and a second wiring structure 2 in contact with the first wiring structure 1B. The first wiring structure 1B may have a linear structure, and a linear structure is exemplified. As described with reference to Fig. 1A, the second wiring structure 2 may have a linear structure, and a linear structure is exemplified. As described above, the first and second wiring structures 1B and 2 are not limited to the straight line structure and may be formed of various elongate members such as a bent, bent, rotated, rolled, spirally, meandering, overlapping, Lt; RTI ID = 0.0 > directional < / RTI >

The first wiring structure 1B and the second wiring structure 2 cross each other and make point contact. The contact interface CI defined by this point contact can have a width and a length of several nanometers to several micrometers, and the present invention is not limited thereto.

Electrical signals can be input and output to and from the wiring structures 1B and 2 and the wiring structures 1B and 2 are electrically connected to each other by point contact between the wiring structures 1B and 2, . In one embodiment, the first wiring structure 1B may be a linear structure having a surface layer 1s of aluminum oxide. The linear structure may be, for example, an aluminum wire having a surface layer 1s as a natural oxide film, or a composite fiber having an aluminum layer formed on the base of the aluminum oxide. For example, the composite fiber may be formed by wet or dry coating the aluminum layer on a conductive or non-conductive polymer fiber core, and a natural oxide layer may be formed on the aluminum layer. Alternatively, the first wiring structure 1 may be provided by forming an aluminum layer on the carbon fiber core.

Referring to Fig. 1C, the nonvolatile memory element 10C includes a first wiring structure 1C and a second wiring structure 2 in contact with the first wiring structure 1C. The first wiring structure 1C may have a planar structure. The first wiring structure 1C may be bendable, as shown in Fig. 1C. However, the embodiment of the present invention is not limited thereto, and the first wiring structure 1C can be operated in various expansion directions such as bending, bending, twisting, curling, overlapping, folding, or bending.

The second wiring structure 2 may have a linear structure as described above with reference to Figs. 1A and 1B, and a linear structure is exemplified. However, the first and second wiring structures 1C and 2 are not limited to a straight line structure, and may be formed of various types of elongated directionally bent, Structure.

The first wiring structure 1B and the second wiring structure 2 cross each other and make line contact. The contact interface CI defined by this line contact may have a width of several nanometers to several micrometers, and the present invention is not limited thereto.

1C, the first wiring structure 1A, 1B, 1C and the second wiring structure 2 can be bent, bent, rotated, or bent as long as the contact interface CI is maintained. In the embodiments described above with reference to Figs. 1A to 1C, It is possible to manipulate the winding, the spiral, the meander, the ply, the twine, or the combination so that the flexible element can be provided. Although not shown, the first wiring structure and the second wiring structure may have a planar structure having a mutual contact interface, and the flexible element may be provided by allowing the movement of the movement as long as the contact interface is maintained .

FIG. 2A is a block diagram of a non-volatile memory device 100 according to another embodiment of the present invention, and FIG. 2B is a perspective view showing the memory cell array MA of FIG. 2A.

2A, a non-volatile memory device 100 may include a memory cell array MA, a row decoder 120, a read / program circuit 130, and a column decoder 140. The memory cell array 110 may be coupled to the row decoder 120 via word lines WL ₁ , WL ₂ , ..., WL _{n -1} , WL _n . The memory cell array 110 may be coupled to the read / program circuit 130 via bit lines BL ₁ , BL ₂ , ..., BL _n-1 , BL _n .

Word lines _{(WL 1, WL 2, ...} , WL n -1, WL n) and the word lines at least one group of the _{(WL 1, WL 2, ...} , WL n -1, WL n) is the above-described The first wiring structure and the other group may be the second wiring structure. Referring to FIG. 2B, the first wiring structure includes first wiring structures 1 having a linear structure having a surface layer of aluminum oxide and at least one carbon fiber layer 1 having contact with the surface layer of the aluminum oxide, The second wiring structures 2 having a linear structure such as the second wiring structure 2 are exemplified.

The plurality of memory cells MC includes a reversible electrochemical reaction product which is generated and extinguished in accordance with the magnitude of the electrical signal at the contact interface between the first and second wiring structures 1 and 2 as a memory element . Since the memory cells are formed by mutual contact of these wiring structures without any other material layer between the first wiring structures and the second wiring structures, the structure is simple, and the first and second wiring structures are formed in the flexible abnormal memory cell array It is possible to provide a nonvolatile memory device which is easily deformable, bending, wrinkling, folding, bending, or a combination thereof so as to be free from molding or change in shape. For example, the first wiring structures 1 and the second wiring structures 2 may have a structure, for example, a spiral structure in which one group surrounds another group or encapsulates one group.

Referring again to FIG. 2A, a plurality of memory cells in the row direction connected to the respective word lines WL ₁ , WL ₂ , ..., WL _{n -1} , WL _n may constitute a logical page, WL ₁ , WL ₂ , ..., WL _{n -1} , WL _n ) may be determined by the storage capacity of the memory cell. The plurality of memory cells MC have a two-dimensional arrangement in which the memory cell array MA is formed, but it may have a three-dimensional structure by an operation such as bending or bending for example. In another example, one or more memory cell arrays MA may be vertically stacked to provide a three-dimensional structure.

The row decoder 120 may select any one of the word lines of the selected memory block. The row decoder 120 may apply a word line voltage (V _WL ) from a voltage generator (not shown) to the word line of the selected memory block. The row decoder 120 outputs a program voltage V _PGM and a verify voltage V _VFY to the selected word line and a ground or pass voltage V _PASS to the unselected word line Unselected WL . If desired, a switching element such as a transistor may be coupled to the memory cell for cell selection.

The memory cell array MA can be addressed by the bit lines BL ₁ , BL ₂ , BL ₃ , ..., BL _n via the column decoder 140. The read / program circuit 130 can receive data transmitted from the outside through the column decoder 140 or output data to the outside.

The read / program circuit 130 may include a page buffer and may operate as a sense amplifier or as a program driver depending on the mode of operation. In this specification, the read / program circuit, or page buffer, may be used interchangeably in equivalent terms, and one does not exclude the other. In a program operation, the read / program circuit 130 receives data from an external circuit and transfers the bit line voltage corresponding to the data to be programmed to the bit line of the memory cell array MA. During the read operation, the read / program circuit 130 can read the data stored in the selected memory cell through the bit line, latch the read data, and output it to the outside.

The read / program circuit 130 may perform a verify operation in response to a program operation of the memory cell in response to a transfer signal transmitted from the control circuit 170, And output it as a page buffer signal. In one embodiment, the read operation of read / program circuit 130 may be performed by charge integration using bit line parasitic capacitors. The charge integration is performed through a current sensing circuit and can detect the program state of the memory cell.

The pass / fail verify circuit 150 verifies, for example, according to the ISPP operating method, that the memory cells have reached a desired level each time the program loop count is increased. If the memory cell has a desired threshold voltage, that is, a target value, the program and program verify operation for the memory cell is determined by the program path. However, if the memory cell does not reach the desired threshold voltage, Circuit 150 may generate a count signal (not shown). The path / path validation circuit 150 may determine whether the program is successful or not, and may pass the result to the control circuit 170.

The counter 160 counts the number of erase operations performed on the memory cell. In another embodiment, the control circuit 170 receives the number of erase operations counted by the counter 160 when the erase operation is performed a plurality of times, and when the erase operation is repeated a certain number of times, Operation can be performed. The erase operation can be performed simultaneously by the entire memory cells on a block-by-block basis.

The control circuit 170 performs transmission control of data and sequence control of recording (or programming) / erasing / reading operations of data in response to the command CMD. The control circuit 170 includes a row decoder 120, a read / write circuit 130, a column decoder 140, a pass / fail detector 150, and a column decoder 150 to perform a pulse program and a verify operation in accordance with, for example, And the counter 160, as shown in FIG.

The control circuit 170 can determine whether to end or continue the program operation with reference to the pass / fail of the program transmitted from the pass / fail detector 150. [ When receiving the result of the program fail (Fail) from the pass / fail verification circuit 150, the control circuit 170 generates a voltage generator (not shown) for generating V _PGM and V _VFY to advance the subsequent program loop And the page buffer 130, respectively. As such, the control circuit 170 can receive the sequence number of the program loop to advance the program according to the increasing number of program loops. Conversely, if the control circuit 170 is provided with the result of the program pass, the program operation for the selected memory cells will end.

In various designs, the memory cell array MA and the control circuit 170 can be integrated in the same chip or arranged in different chips. In another embodiment, peripheral circuits for driving the memory cell array MA are formed of a semiconductor chip by silicon processing, and the memory cell array MA may be formed separately as shown in FIG. 2B. This memory cell array MA makes it possible to maintain a stable coupling between the first wiring structure and the second wiring structure in a suitable support as described later with reference to FIG. 3A. Also, the peripheral circuits may be mounted on the support.

3A and 3B are perspective views showing a memory cell array according to an embodiment of the present invention.

3A and 3B, the memory cell array MA includes a first wiring structure 1 and a second wiring structure 2 in order to enhance the contact state of the first wiring structure 1 and the second wiring structure 2, And a support 20 coupled to at least one of the first and second substrates 2 and 3. 3A, the support 20 may be coupled to the wiring structures 1 and 2 in such a manner as to contact one surface of either the first wiring structure 1 or the second wiring structure 2. [ In Fig. 3B, the first wiring structure 1 and the second wiring structure 2 are buried in the support 20, for example.

The support 20 has a planar structure but may have another three-dimensional shape. In one embodiment, the support 20 may be a fabric, a nonwoven fabric, a flexible insulating sheet, or a combination thereof, although the present invention is not limited thereto. The contact state of the first wiring structure 1 and the second wiring structure 20 is maintained by the operation of bending or bending the memory cell array MA by the coupling of the supporting body 20 to the flexible non- Can be implemented.

4A and 4B are perspective views showing a memory cell array according to another embodiment of the present invention.

Referring to FIG. 4A, the first wiring structure 1 and the second wiring structure 2 may have a weaving structure that intersects each other. Such a woven structure is exemplary, and various woven fabrics, such as interlocking, by application of nonwoven fabrication process techniques, may provide a memory cell array having a variety of weaves, nonwoven fabrics, or a combination thereof.

4B, a support 20 may be further provided which is joined to these wiring structures 1 and 2 for enhancing the contact state of the first wiring structure 1 and the second wiring structure 2. In this case, the first wiring structure 1 and the second wiring structure 2 can be coupled to the support 20 by threading the upper surface and the lower surface of the support 20. In another embodiment, as described above with reference to Fig. 3B, the support may be formed in a manner that the first wiring structure 1 and the second wiring structure 2 are buried in contact with the first wiring structure and the second wiring structure .

5A is a graph showing electric characteristics of a current-voltage of a non-volatile memory device including a first wiring structure of an aluminum film having a contact interface and a second wiring structure of carbon fibers according to an embodiment of the present invention, and FIG. 5B Is a graph showing the cycle reliability of the non-volatile memory device of FIG. 5A.

Referring to FIG. 5A, the second wiring structure is grounded, and a current change obtained by sweeping a voltage signal varying from negative to positive direction with respect to the first wiring structure is measured. In step 1 (S1) in which the first negative voltage is swept, the non-volatile memory device is in a high resistance state, and when the voltage gradually increases, a set operation of changing the resistance value from about -2 V to about 2 V in step 2 (S2) It happens. This set operation can occur within a range of about -1 V to -3 V through control of the contact interface. However, this is only exemplary and the set operation can occur in the negative bias region.

Thereafter, in step 4 (S4) in which the magnitude of the negative voltage gradually decreases and the magnitude of the positive voltage gradually increases in step 3 (S3), the nonvolatile memory device maintains a low resistance state and the voltage gradually increases A reset operation that changes from a high voltage state of about 2.7 V or more to a high resistance state occurs in step S5 (S5). As with the normal operation, the reset operation can take place within the range of 1 V to 4 V through control of the contact interface. However, this is only exemplary and it will be possible to cause a reset operation to occur in the positive bias region through the interface control. In step 5 (S6) where the voltage is reduced again, the nonvolatile memory element maintains a high resistance state.

The programming and erasing operations of the nonvolatile memory element can be performed using the set operation and the reset operation obtained by appropriate voltage signals applied between the first wiring structure and the second wiring structure. The low resistance state by the set operation and the high resistance state by the reset operation may be discriminated by sensing the magnitude of the current flowing by applying an appropriate read voltage between the first wiring structure and the second wiring structure.

Referring to FIG. 5B, for a nonvolatile memory device according to an embodiment of the present invention, a resistance value after a set operation and a reset operation at 0.5 V has been read. It is confirmed that the difference in size between the low resistance state (LRS) and the high resistance state (HRS) is maintained at 102 or more even when the number of times of repetition is 100 or more. Thus, according to the embodiment of the present invention, A nonvolatile memory element can be obtained.

FIG. 6 is a graph showing a composition change due to an electrochemical reaction by voltage driving at a contact interface between a first wiring structure, which is an aluminum film, and a second wiring structure, which is a carbon fiber. The composition analysis was performed using energy dispersive x-ray spectroscopy (EDS). The X axis is a component value of the aluminum film as a reference value. The compositional changes of carbon and oxygen after the resistance change of initial state, initial state (SET) and reset state (RESET) of aluminum film were analyzed.

Referring to FIG. 6, a change in composition of carbon and oxygen occurs at a contact interface between the first wiring structure and the second wiring structure by voltage driving. It can be seen that the carbon content is high and the oxygen content is decreased in the set state. Conversely, in the reset state, the content of carbon is decreased and the content of oxygen is increased.

In order to understand the phenomenon occurring at the contact interface between aluminum and carbon, we refer to the phase change diagram depending on the composition between the two materials. The reaction of formula 1 below in which aluminum carbooxide is formed by the reaction of aluminum oxide and carbon may occur. At this time, oxygen vacancies may be generated together with the aluminum carbon oxides.

[Formula 1]

2Al ₂ O ₃ + 3C ↔ Al ₄ O ₄ C + 2CO (g) ↑

Generation of the aluminum oxide and the calculation of the free energy change in the ambient temperature of between carbon reaction product the formation of the _{Al 4 O 4 C <Al 2} O 3 <Al 2 OC <Al 4 to C ₃ compounds Al ₄ O ₄ C oxygen vacancies And it is understood that the resistance value is changed.

The compound Al ₄ O ₄ C is formed in the set driving, the conductivity is increased by the generated oxygen vacancy, and the low resistance state (LRS) is induced. In the reset driving, the oxygen vacancy disappears and the high resistance state (HRS) do. XPS (X-ray photoelectron spectroscopy) analysis was performed as follows for the analysis of the components in detail.

7A to 7D show Al2p peaks in an Al film, Al film, Initial state, SET state, and Reset state RESET as reference values by XPS analysis, and Figs. FIG. 8D shows the C1s peak of the Al film as the reference value, the state (Initial) only in contact with the aluminum film, the SET state, and the reset state RESET.

Referring to FIGS. 7A to 7D, it can be deduced that an Al-O bond is increased to form an aluminum oxide in a reset state at an Al2p peak, and referring to FIGS. 8A to 8D, a CO- And it can be deduced that an aluminum nitride carbon oxide is formed. The result shows that the formation of oxygen vacancies by the formation of aluminum carboxides by the three-bias at the contact interface between the carbon layer and the aluminum oxide reduces the resistance, and in the case of the reset bias, the resistance increases due to the reverse reaction .

9 is a block diagram illustrating an electronic system 1000 including a non-volatile memory device in accordance with one embodiment of the present invention.

9, an electronic system 1000 includes a controller 1010, an input / output device (I / O) 1020, a storage device 1030, an interface 1040 and a bus 1050 . The controller 1010, the input / output device 1020, the storage device 1030 and / or the interface 1040 may be coupled to each other via the bus 1050. [

The controller 1010 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1020 may include a keypad, a keyboard, or a display device. The storage device 1030 can store data and / or instructions, and the storage device 1030 can include the three dimensional non-volatile memory device described herein.

In some embodiments, the storage device 1030 may have a hybrid structure that further includes other types of semiconductor memory devices (e.g., a DRAM device and / or an Slam device). The interface 1040 may perform the function of transmitting data to or receiving data from the communication network. The interface 1040 may be in wired or wireless form. To this end, the interface 1040 may comprise an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1000 is an operation memory for improving the operation of the controller 1010, and may further include high-speed DRAM and / or Slam.

The electronic system 1000 may be a flexible device and may be a wearable device such as, for example, a smart garment, a smart hat, a smart shoe or a smart watch. However, the present invention is not limited thereto and may be applied to other personal digital assistant (PDA) portable computers, tablet PCs, wireless phones, mobile phones, A digital music player, a memory card, or any electronic product capable of transmitting and / or receiving information in a wireless environment.

Although the embodiments described above mainly disclose memory elements, they are exemplary and those skilled in the art will appreciate that the variable resistors according to embodiments of the present invention may be implemented as fuse and anti-fuse, or on / off switching elements of a logic circuit such as an FPGA Can also be applied.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

Claims (21)

At least one first wiring structure having at least a first surface layer of aluminum oxide on at least a part thereof; And
And at least one second wiring structure having a second surface layer of carbon-containing material at least partly in contact with the first surface layer of the aluminum oxide,
Wherein the first interconnection structure and the second interconnection structure are formed on the contact interface between the first surface layer of the first interconnection structure and the second surface layer of the second interconnection structure in accordance with the electric potential or current applied to the first interconnection structure and the second interconnection structure, A reversible electrochemical reaction product is generated or extinguished between carbons of the carbon-containing layer,
Wherein at least two resistance levels are provided so that a magnitude of a current flowing along the first wiring structure and the second wiring structure is controlled in accordance with generation or disappearance of the reversible electrochemical reaction product. The method according to claim 1,
Wherein at least one of the first wiring structure and the second wiring structure has a linear structure. The method according to claim 1,
Wherein the first wiring structure comprises an underlying aluminum layer or an aluminum core and the aluminum oxide and the aluminum oxide on the aluminum core,
Wherein the second wiring structure includes carbon fibers. The method of claim 3,
The aluminum layer is wet-coated, electrolytically plated, and electrolessly plated. The method according to claim 1,
Wherein one of the first wiring structure and the second wiring structure has a planar structure. 6. The method of claim 5,
Wherein the first wiring structure having the planar structure has an aluminum film, an aluminum foil or an aluminum sheet structure. 6. The method of claim 5,
And the other of the first wiring structure and the second wiring structure has a linear structure. The method according to claim 1,
Wherein the aluminum oxide is a natural oxide film. The method according to claim 1,
Wherein the reversible electrochemical reaction product comprises an aluminum carbon oxide. 10. The method of claim 9,
Wherein the aluminum carbon oxide comprises any one of Al ₄ O ₄ C, and Al ₂ OC, or a mixture thereof. 10. The method of claim 9,
Wherein the aluminum carbon oxide comprises Al ₄ O ₄ C,
And has a low resistance level when the Al ₄ O ₄ C is generated and a high resistance level when the Al ₄ O ₄ C disappears. The method according to claim 1,
Wherein the set voltage of the non-volatile memory element is within a negative bias region and the reset voltage is within a positive bias region. The method according to claim 1,
Wherein the first wiring structure and the second wiring structure have a woven structure, a woven structure, a nonwoven fabric, or a combination structure thereof. The method according to claim 1,
Wherein one of the first wiring structure and the second wiring structure surrounds the other or surrounds the other. The method according to claim 1,
Further comprising a support coupled to at least one of the first wiring structure and the second wiring structure to maintain contact between the first wiring structure and the second wiring structure. 16. The method of claim 15,
Wherein the first wiring structure and the second wiring structure are embedded in the support. 16. The method of claim 15,
Wherein at least one of the first wiring structure and the second wiring structure is coupled to the support by threading the support. 16. The method of claim 15,
Wherein the support comprises a fabric, a nonwoven fabric, a flexible insulating sheet, or a combination thereof. 16. The method of claim 15,
Wherein the first and second wiring structures form a memory cell array,
And a peripheral circuit for driving the memory cell array is mounted in the support. The method according to claim 1,
Wherein the first wiring structure and the second wiring structure are flexible. A memory cell providing a resistance level of at least two as a result of generation or dissipation of a reversible electrochemical reaction product between the aluminum oxide layer and the carbon layer contacting the aluminum oxide layer.

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