KR20160140512A - Decoder and memory controller including the same - Google Patents

Abstract

The present invention relates to a decoder and a memory controller including the same. According to an embodiment of the present invention, a decoder includes a syndrome calculator for generating syndrome values from a received codeword, wherein the syndrome calculator includes multipliers and adders configured to input the codeword by a bit group unit having a plurality of bits in parallel and performs a serial operation for each of the inputted bit groups in parallel so as to generate the syndrome values. Accordingly, the present invention can minimize the complexity of a decoder structure.

Description

[0001] DECODER AND MEMORY CONTROLLER INCLUDING THE SAME [0002]

The present invention is directed to a decoder and a memory controller including the decoder. More particularly, the present invention relates to a decoder and a memory controller including the decoder and the memory controller. And a syndrome calculator capable of generating the syndrome values, and a memory controller including the decoder.

Generally, when it is desired to minimize the complexity in designing a decoder, the multiplier is designed to repeatedly use one resource such as an adder every clock. In addition, when high speed processing is required in designing a decoder, it is designed to be capable of simultaneously processing necessary operations for one clock by using a multiplier and an adder.

However, when both complexity minimization and high-speed processing are required, a structured method or structure is not proposed, and in some cases, the subblocks have been designed to be serialized or parallelized.

As for BCH (Bose-Chaudhuri-Hoquenbhem) decoder, scalability is limited because there is no structured structure capable of freely adjusting serial / parallel degree, efficiency is low and it is difficult to guarantee optimal structure for the purpose There was a problem. Especially, the problem of BCH code which has to perform polynomial division is problematic with respect to the syndrome operation step which is not easy to be flexible serialization or parallelization.

Technical Solution According to an aspect of the present invention, there is provided a decoder and a memory controller including the decoder. The decoder includes a plurality of bit groups, each of which includes a plurality of bits, And a syndrome calculator capable of generating the syndrome values, and a memory controller including the same.

A decoder according to an aspect of the technical idea of the present invention includes a syndrome calculator for generating syndrome values from a received codeword and the syndrome calculator is operable to convert the codeword into a plurality of bits, And multipliers and adders for receiving the syndrome values in units of bit groups included therein and generating the syndrome values by performing a serial operation on each of the bit groups input in parallel.

In some embodiments, the plurality of bits contained in each of the bit groups included in the codeword may be input via the adders.

In some embodiments, each of the bit groups includes at least three or more bits, and the multipliers may include accumulative multipliers, each of which is disposed between the adders.

In some embodiments, the accumulative multipliers may cumulatively multiply Galois Field elements having the same value.

In some embodiments, the syndrome calculator further includes a register for temporarily storing processing data for a bit group for which serial operation is completed, when the serial operation for any one of the bit groups is completed .

In some embodiments, the multipliers may include a unit multiplier that multiplies a unit Galois field element for the group of bits for which the serial operation is complete.

In some embodiments, the syndrome calculator further comprises a first switch between the register and the unit multiplier, wherein the first switch is turned off before the serial operation of the first bit group among the bit groups is completed off of the first bit group, and may be controlled to be turned on after the serial operation of the first bit group is completed.

In some embodiments, the syndrome calculator further comprises a second switch located at an output of the syndrome calculator, wherein the second switch is turned off before serial operation on all of the bit groups is completed, And may be controlled to be turned on after serial operation on all of the groups is completed.

In some embodiments, the decoder includes a key equation solver that generates an error locator polynomial based on the syndrome values, a chien search block that finds an error locus based on the error locator polynomial, And an error correction block for correcting the error of the received data based on the error position and outputting the corrected received data.

The memory controller according to an aspect of the technical idea of the present invention may include the decoder.

A method and an apparatus according to an embodiment of the present invention may be implemented in parallel by a bit group unit including a plurality of bits and performing serial operation on each of bit groups input in parallel to generate the syndrome values The complexity of the decoder structure can be minimized while speeding up the decoding process.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a block diagram of a decoder in accordance with an embodiment of the present invention.
FIG. 2 is a diagram showing an embodiment of the syndrome calculator shown in FIG. 1. FIG.
3 is a block diagram of a memory system in accordance with one embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. However, it should be understood that the technical idea of the present invention is not limited to the specific embodiments but includes all changes, equivalents, and alternatives included in the technical idea of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0029] In the following description of the present invention, a detailed description of known technologies will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, numerals (e.g., first, second, etc.) used in the description of the present invention are merely an identifier for distinguishing one component from another.

Also, in this specification, when an element is referred to as being "connected" or "connected" with another element, the element may be directly connected or directly connected to the other element, It should be understood that, unless an opposite description is present, it may be connected or connected via another element in the middle.

It should be noted that the terms such as " unit, "" to, "" Or a combination of hardware and software.

It is to be clarified that the division of constituent parts in this specification is merely a division by each main function of each constituent part. That is, two or more constituent parts to be described below may be combined into one constituent part, or one constituent part may be divided into two or more functions according to functions that are more subdivided. In addition, each of the constituent units described below may additionally perform some or all of the functions of other constituent units in addition to the main functions of the constituent units themselves, and that some of the main functions, And may be carried out in a dedicated manner.

Hereinafter, embodiments according to the technical idea of the present invention will be described in detail.

1 is a block diagram of a decoder in accordance with an embodiment of the present invention.

Referring to FIG. 1, according to an embodiment, a decoder 100 may be implemented as a Bose-Chaudhuri-Hoquenbhem (BCH) decoder.

The decoder 100 includes a data buffer 110, a syndrome calculator 120, a key equation solver 130, a chien search block 140, and an error correction block an error correcting block 150 may be included.

The data buffer 110 may temporarily store the received codeword R (x) and provide it to the error correction block 150.

Syndrome calculator 120 generates syndrome values S (x) based on the received codeword R (x). If there is no error in the received codeword R (x), the syndrome values S (x) all have a value of "0 ", and if there is an error in the received codeword R (x) (S (x)) includes a value other than "0 ".

The codeword R (x) stored in the data buffer 110 can be output from the decoder 100 without additional error correction if the syndrome values S (x) all have a value of "0".

Syndrome values S (x) are passed to the key equation solver 130 for error correction if the syndrome values S (x) include a value other than "0".

The concrete structure of the syndrome calculator 120 according to the embodiment of the present invention will be described in detail with reference to FIG.

The key equation solver 130 may generate an error locator polynomial (? (X)) based on the received syndrome values S (x) and pass it to the Chien search block 140.

According to an embodiment, the key equation solver 130 may be implemented using a Berlekamp-Massey algorithm, a step-by-step algorithm, an Euclidean algorithm, or a modified Euclidean algorithm modified Euclidean algorithm) to generate an error locator polynomial (∧ (x)).

The quench search block 140 may calculate error locations and generate an error polynomial E (x), based on the error locator polynomial (∧ (x)) delivered from the key equation solver 130 have. The search query block 140 may pass the generated error polynomial E (x) to the error correction block 150.

The error correction block 150 corrects the error of the received codeword R (x) buffered from the data buffer 110 based on the error polynomial E (x) delivered from the CHN search block 140 , The error-corrected code word C (x) can be output.

FIG. 2 is a diagram showing an embodiment of the syndrome calculator shown in FIG. 1. FIG.

1 and 2, the syndrome calculator 120 receives a received codeword R (x) in parallel on a bit group basis and performs a serial operation on each of the bit groups input in parallel And may include multipliers 122-1 through 122-4 and adders 124-1 through 124-4 that generate syndrome values S _i .

2, a syndrome calculator 120 calculates a syndrome R (x) of a received codeword R (x) in accordance with the following equation: < EMI ID = May be input in parallel in units of bit groups including at least two or more bits.

According to the embodiment, when the received codeword R (x) is not divided by the number of bits of the bit group (for example, if it consists of a group of 3 bits), a value of "0 & Bit groups may be formed.

Hereinafter, the calculation process of the syndrome values (S _i ) will be described together to understand the concept of the bit group of the code word (R (x)).

Syndrome values (S _i ) can be basically obtained according to [Equation 1] below.

[Equation 1]

= R₀ + R₁αⁱ + R₂α²ⁱ +… + R_N-1α^i(N-1) S _i =

= R ₀ R ₁ + R ₂ α ⁱ + α ²ⁱ + ... + R _N-1 ? ^{I (N-1)}

For parallel processing of the syndrome values (S _i), [formula 1] to obtain the syndrome values (S _i) can be modified as [Equation 2].

[Equation 2]

S _i = (((R _{N- 1} ? ³ⁱ _N- ²ⁱ + R ₂ α R + _N- α ⁱ + ₃ R _{4 N-)} α ⁴ⁱ + (R _{5 N-} α ³ⁱ _N- α ²ⁱ + R ₆ R + _{7 N-} α ⁱ + _{N-R 8))} α + ... ⁴ⁱ⁾ α ⁴ⁱ + α ³ⁱ R ₃ + R ₂ α ²ⁱ + α ⁱ + R ₁ R ₀

That is, the code word R (x) may be divided into unit groups including a plurality of bits and input in parallel. For example, if the code word R (x) is divided into 4 bit groups, the first bit group includes R _N-4, R _N-3 , R _N-2 , R _N-1 , The group includes R _N-8 , R _N-7 , R _N-6 and R _{N- 5} , and the last bit group may include R _0, R ₁ , R ₂ , and R ₃ .

The structure of the syndrome calculator 120 of FIG. 2 according to the embodiment of the present invention can be utilized when the syndrome values S _i are obtained according to Equation (2).

The syndrome calculator 120 includes a plurality of adders 124-1 to 124-4, a plurality of multipliers 122-1 to 122-4, a register 126 and switches SW1 and SW2 .

Each of the bits included in each of the bit groups included in the code word R (x) may be input through a plurality of adders 124-1 to 124-4.

When each of R _N-4, R _N-3 , R _N-2 and R _{N-1 of the} first bit group is input to each of adders 124-1 through 124-4 _, A serial operation on R _N-3 , R _N-2 , R _N-1 can be performed.

The first switch SW1 may be controlled in a turn-off state before the serial operation of the first bit group is completed.

R _N-1 of the first group of bits is input to the first adder 124-1, a first cumulative multiplier 122-2 Royce field element (Galois Field element) to go by α ⁱ haejyeoseo the product, _N- R ₁ α ⁱ can be output.

First accumulation multiplier 122-2 output _N- R ₁ α ^i, the second adder haejyeoseo (124-2), a first bit group of _{N-R 2} is further input to a, R _N-1 α ⁱ + R of _N-2 can be output.

Second accumulation by the multiplier 122-3, a second adder (124-2) outputs the _N- R ₁ α ⁱ + R Royce field element go to the _N-2, α ⁱ is multiplied, R _N-1 of α ²ⁱ + R _N-2 ? ^I can be output.

Second cumulative multiplier 122-3 output _N- R ₁ α ²ⁱ + α ⁱ R _{2 N-} is a third adder (124-3) haejyeoseo the first bit of the group R _N-3 are further input to, the R _{N- 1} ? ²ⁱ + ^RN _{- 2} ? ^I + _RN-3 can be output.

The third cumulative multiplier by a (122-4), the third field element Royce go to the output of ^{_{R N- 1 α 2i + R N-}} 2 α i + R N-3 of the adder (124-3) is multiplied by α ⁱ RN _{- 1} ? ³ⁱ + ^RN _{- 2} ? ²ⁱ + ^RN _-3 ? ^I can be output.

The third cumulative multiplier (122-4) outputs the _{N- 1} α ³ⁱ + R _N- R ₂ α ²ⁱ + α ⁱ is R _N-3 of the first group of bits input to the fourth adder (124-4) of _N R _-4 can be added so that ^RN _{- 1} ? ³ⁱ + ^RN _{- 2} ? ²ⁱ + ^RN _-3 ? ^I + _RN-4 can be output.

A second switch (SW2) is previously turned to series operation for all of the bit group is completed - because it is controlled to the OFF state, the fourth adder (124-4), an output of the _N R _{- 1} α R ³ⁱ + _{N- ^{2 α 2i + R N-3}} α i + R N- 4 , may be stored is input to register 126 via a loop (loop). The data input to the register 126 may be output again according to the timing at which the second bit group is input.

When the serial operation of the first bit group is completed, the first switch SW1 can be controlled to be turned on.

When each of the RN _-8, RN _-7 , RN _-6 , and RN _-5 of the second bit group is input to each of the adders 124-1 through 124-4, A serial operation on R _N-8, R _N-7 , R _N-6 , and R _N-5 of the second bit group may be performed.

A unit multiplier 122-1 is added to RN _-1 ? ³ⁱ + ^RN _{- 2} ? ²ⁱ + ^RN _-3 ? ^I + RN _-4 as a result of serial operation on the first bit group stored in the register 126, (R _N-1 ? ³ⁱ + R _N-2 ? ²ⁱ + R _N-3 ? ^I + R _N-4 )? ⁴ⁱ is multiplied by the Galois field element? ⁴ⁱ .

Then, the second bit group and the remaining bit groups input in parallel as in the first bit group are subjected to serial operation by the multipliers 122-2 to 122-4 and the adders 124-1 to 124-4 (((RN _{- 1} ? ³ⁱ ) from the fourth adder 124-4 ^{_{+ R N-2 α 2i +}} R N- 3 α i + R N- 4) α 4i + (R N- 5 α 3i ^{_{+ R N- 6 α 2i + R}} N- 7 α i + R N-8)) α 4i _{^{+?) α 4i + R 3}} α 3i R ₂ R ₁ + α ²ⁱ + α ⁱ + R ₀ value is output, at this time the second switch (SW1) is turned on, while the output value of the fourth adder (124-4) converter 120, the output of the syndrome As shown in FIG.

That is, the accumulative multipliers 122-2 to 122-4 are disposed between the adders 124-1 to 124-4, and the accumulative multipliers 122-2 to 122-4 and the adders 124-1 To 124-4 may perform a serial operation on each of the bit groups input in parallel, and the bit group may include a codeword R (x) divided for processing through a serial operation after being input in parallel, Lt; / RTI > of bits.

When the bit group is composed of two bits, since the number of accumulative multipliers can be made to be one, when the bit group is composed of four or more bits, the accumulative multipliers 122-2 to 122-4 cumulatively add the Galois field elements So as to simplify the structure of the syndrome calculator 120. FIG.

According to an embodiment, the accumulative multipliers 122-2 through 122-4 may cumulatively multiply a galois field element having the same value, e.g., [alpha] ⁱ .

According to the embodiment, the unit multiplier 122-1 multiplies the bit group for which the serial operation is completed by the Galois field element having a constant value, and the size of the Galois field element multiplied by the unit multiplier 122-1 is May be determined according to the size of the bit group. For example, when the bit group is composed of 4 bits, the unit multiplier 122-1 multiplies? ⁴ⁱ , and when the bit group is composed of 8 bits, the unit multiplier 122-1 can multiply? ⁸ⁱ .

According to an embodiment, when the received codeword R (x) is input in parallel in units of a bit group including at least three or more bits, the syndrome calculator 120 may include two or more accumulative multipliers to obtain a more efficient structure Can be implemented.

According to another embodiment, when the syndrome calculator 120 receives the received codeword R (x) in parallel in units of bit groups including 2? N (n is a natural number of 2 or more) bits, The code word (R (x)) is divided into a bit group unit while including multipliers, so that a more efficient structure can be realized.

3 is a block diagram of a memory system in accordance with one embodiment of the present invention.

1 through 3, the memory system 200 may include a host 210, a memory device 220, and a memory controller 230.

According to an embodiment, the memory system 200 may be implemented as an electronic device or a portable device. The portable device may be implemented as a cellular phone, a smart phone, or a tablet PC.

The host 210 may send a request to the memory controller 230 to read data required for internal process processing or to store data according to a process result.

The memory device 220 may store data managed by the host 210 and may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, an MRAM (magnetic RAM), a spin transfer (MRAM), conductive bridging RAM (CBRAM), FeRAM (ferroelectric RAM), PRAM (phase change RAM), resistive RAM (RRAM), nanotube RRAM a polymer memory RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronics memory device, or an insulator resistance change memory. , A random access memory (RAM) as a volatile memory, for example, a dynamic random access memory (DRAM), or a static random access memory (SRAM), but the scope of the present invention is not limited thereto.

The memory controller 230 can control the transmission / reception of data between the host 210 and the memory device 220. The memory controller 230 may include an interface 232, an encoder 234, and a decoder 236.

The interface 232 may interface signal transmission / reception between the host 210 and the memory controller 230.

The encoder 234 may encode the data received from the host 210 and output it to the memory device 220.

According to an embodiment, the decoder 236 of FIG. 3 may be implemented in the same manner as the decoder 100 of FIG. The decoder 236 can check the error of the data R (x) output from the memory device and correct the error and transmit the corrected data C (x) to the host 210 via the interface 232 .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Various modifications and variations are possible.

100, 236: decoder
110: data buffer
120: Syndrome Calculator
130: Key equation solver
140: Chien Search Block
150: error correction block
200: Memory system
210: Host
220: memory device
230: Memory controller

Claims (10)

And a syndrome calculator for generating syndrome values from the received codeword,
The syndrome calculator includes:
A decoder for receiving the codeword in units of bit groups including a plurality of bits in parallel and multipliers and adders for generating the syndrome values by performing a serial operation on each of the bit groups input in parallel, decoder.
The method according to claim 1,
Wherein the plurality of bits contained in each of the bit groups included in the codeword are input through the adders.
3. The method of claim 2,
Each of the bit groups comprising at least three or more bits,
The multipliers,
Wherein each of the adders comprises cumulative multipliers disposed between the adders.
The method of claim 3,
The accumulative multipliers are operable,
And cumulatively multiplies Galois Field elements having the same value with each other.
5. The method of claim 4,
The syndrome calculator includes:
Further comprising a register for temporarily storing processing data for a bit group in which a serial operation is completed, when a serial operation for any one of the bit groups is completed.
6. The method of claim 5,
The multipliers,
And a unit multiplier for multiplying the unit group field element with the bit group for which the serial operation has been completed.
The method according to claim 6,
The syndrome calculator includes:
Further comprising a first switch between the register and the unit multiplier,
The first switch is turned off before the serial operation of the first bit group among the bit groups is completed and is turned on after the serial operation of the first bit group is completed. Controlled.
8. The method of claim 7,
The syndrome calculator includes:
Further comprising a second switch located at the output of the syndrome calculator,
Wherein the second switch is turned off before the serial operation for all of the bit groups is completed and is turned on after the serial operation for all of the bit groups is completed.
The method according to claim 1,
The decoder includes:
A key equation solver for generating an error locator polynomial based on the syndrome values;
A chien search block for finding an error position based on the error locator polynomial; And
And an error correction block for correcting the error of the received data based on the error position and outputting the corrected received data.
A memory controller comprising the decoder of claim 1.

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