KR20160129407A - Fan-out package, Package-On-Package and manufacturing method thereof - Google Patents

Fan-out package, Package-On-Package and manufacturing method thereof Download PDF

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Publication number
KR20160129407A
KR20160129407A KR1020150061525A KR20150061525A KR20160129407A KR 20160129407 A KR20160129407 A KR 20160129407A KR 1020150061525 A KR1020150061525 A KR 1020150061525A KR 20150061525 A KR20150061525 A KR 20150061525A KR 20160129407 A KR20160129407 A KR 20160129407A
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South Korea
Prior art keywords
metal
semiconductor chip
package
contact
wiring layer
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KR1020150061525A
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Korean (ko)
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KR101691099B1 (en
Inventor
곽형국
이현우
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하나 마이크론(주)
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Priority to KR1020150061525A priority Critical patent/KR101691099B1/en
Priority to PCT/KR2015/008702 priority patent/WO2016175394A1/en
Publication of KR20160129407A publication Critical patent/KR20160129407A/en
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Publication of KR101691099B1 publication Critical patent/KR101691099B1/en

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A fan-out POP manufacturing method of the present invention includes the steps of: preparing an individual semiconductor chip comprising a contact metal; preparing a sacrifice substrate comprising an interconnect metal; mounting the individual semiconductor chip on the sacrifice substrate in a face-up shape such that the contact metal and the interconnect metal face the same direction; molding a protective member on the contact metal and the interconnect metal; exposing one side of the contact metal and one side of the interconnect metal by planarizing the protective member; and rewiring a top side for electrically connecting the contact metal and the interconnect metal to the outside. According to the configuration of the present invention, a process can be simplified and a yield rate can be improved.

Description

팬 아웃 패키지, 팬 아웃 POP 패키지 및 그 제조 방법 {Fan-out package, Package-On-Package and manufacturing method thereof}Fan-out package, fan-out POP package, and manufacturing method thereof

본 발명은, 파인 피치에 대응되고 방열 특성이 우수한 팬 아웃 패키지, 팬 아웃 POP 패키지 및 그 제조 방법에 관한 것으로, 특히 기존 팬 아웃 웨이퍼 레벨 패키지 공정에 있어서 몰딩 공정 후 이용되어 오던 비아 형성(via drilling) 및 비아 충진(via filling) 공정이 생략됨으로써, 공정 조건이 단순화 되고 수율 개선이 기대되며, 솔더 볼 공정 혹은 메탈 포스트 공정을 통하여 상하부 패키지 리드선을 형성하거나, 반도체 다이에 형성되는 접속단자를 메탈 스터드 범프 공정이나 메탈 필러 공정을 통하여 형성함으로써 리스크를 저감하는 팬 아웃 POP 패키지 및 그 제조 방법에 관한 것이다.The present invention relates to a fan-out package, a fan-out POP package and a method of manufacturing the same that are compatible with fine pitches and have excellent heat dissipation characteristics. More particularly, the present invention relates to a fan- And the via filling process is omitted, the process conditions are simplified and the yield is expected to be improved. The upper and lower package leads can be formed through the solder ball process or the metal post process, or the connection terminals formed on the semiconductor die can be connected to the metal stud The present invention relates to a fan-out POP package and a method of manufacturing the fan-out POP package.

일반적으로 반도체 패키지는 인쇄회로기판(Printed Circuit Board, PCB) 상에 반도체 칩이 실장되는 구조를 갖는다. 가령, 다수의 메모리 반도체 칩과 로직 반도체 칩이 동일한 기판 상에 적층될 때 전체 사이즈가 증가되는 경향이 있기 때문에, 패키지의 사이즈를 줄이기 위하여, 반도체 칩들을 상하로 적층하는 패키지 온 패키지(POP) 기술이 제공되고 있다.In general, a semiconductor package has a structure in which a semiconductor chip is mounted on a printed circuit board (PCB). For example, when a plurality of memory semiconductor chips and logic semiconductor chips are stacked on the same substrate, the total size tends to increase. Therefore, in order to reduce the size of the package, a package on package (POP) technique Are provided.

그런데, 이러한 팬 아웃 패키지 온 패키지(POP)는 상하부 패키지를 전기적으로 연결하는 비아 콘택 혹은 리드선이 요구되는데, 종래의 이러한 비아 콘택은 비아 성형 공정(via drilling process), 및 비아 충진 공정(metal filling process)을 통해서 구현될 수 있다. However, such a fan-out package-on-package (POP) requires a via contact or a lead wire for electrically connecting the upper and lower packages. The conventional via contact is a via drilling process and a metal filling process ). ≪ / RTI >

그러나 이러한 비아 콘택 형성을 위한 비아 성형 공정이나 비아 충진 공정은 다음과 같은 문제점이 있다.However, the via forming process and the via filling process for forming the via contact have the following problems.

가령, 비아 성형 공정 시 비아 홀 사이드 부분의 RA 값을 관리하기 곤란하고, 비아 성형을 위한 드릴링(drilling) 공정을 위하여 드릴링 설비가 요구되며, 비아에 메탈을 충진(filling)하기 위하여 여러 증착 장비 기타 충진 설비가 필요하게 된다. For example, it is difficult to control the RA value of the via hole side in the via forming process, and drilling equipment is required for the drilling process for via formation. In order to fill the via with metal, A filling facility is required.

공개특허 10-2008-0022452≪ RTI ID = 0.0 &

따라서 본 발명은 상기한 바와 같은 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 팬 아웃 하부 패키지와 팬 아웃 상부 패키지를 연결하는 콘택 공정을 몰딩 공정 후 비아 형성 및 충진 공정을 이용하지 않는 팬 아웃 패키지, 팬 아웃 POP 패키지 및 그 제조 방법을 제공하는 것이다.SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a method of manufacturing a fan- Out fan package, a fan-out POP package, and a manufacturing method thereof.

전술한 바와 같은 목적을 달성하기 위한 본 발명의 특징에 따르면, 본 발명의 팬 아웃 패키지 온 패키지는, 재배선층, 상기 재배선층과 스터드 콘택을 통해 전기적으로 연결되는 반도체 칩, 상기 반도체 칩의 외곽의 상기 반도체 칩과 실질적으로 동일한 평면 에 배치되고, 일측이 상기 재배선층을 통해 외부와 전기적으로 연결되는 인터커넥터, 및 상기 재배선층 상에 형성되고, 볼 마운트(ball mount) 되는 상기 인터커넥터의 타측을 노출시키는 보호부재를 포함한다.According to an aspect of the present invention, there is provided a fan-out package on package including a re-wiring layer, a semiconductor chip electrically connected to the re-wiring layer through a stud contact, An interconnector which is disposed on substantially the same plane as the semiconductor chip and whose one side is electrically connected to the outside through the re-wiring layer; and an inter-connector which is formed on the re-wiring layer and which is ball- And a protective member which exposes the protective member.

본 발명의 다른 특징에 의하면, 본 발명의 팬 아웃 POP 제조 방법은, 콘택 메탈이 구비된 개별 반도체 칩을 준비하는 단계, 인터커넥터 메탈이 구비된 희생 기판을 준비하는 단계, 상기 콘택 메탈과 상기 인터커넥터 메탈이 동일한 방향을 향하도록, 상기 개별 반도체 칩을 상기 희생 기판에 페이스 업(face up) 형태로 마운트 하는 단계, 상기 콘택 메탈과 상기 인터커넥터 메탈에 보호부재를 몰딩하는 단계, 상기 보호부재를 평면화하여 상기 콘택 메탈의 일측과 상기 인터커넥터 메탈의 일측을 노출시키는 단계, 및 상기 콘택 메탈과 상기 인터커넥터 메탈을 외부와 전기적으로 연결하는 탑 사이드 재배선하는 단계를 포함한다.According to another aspect of the present invention, there is provided a fan-out POP manufacturing method comprising the steps of preparing an individual semiconductor chip provided with a contact metal, preparing a sacrificial substrate provided with an interconnect metal, Mounting the discrete semiconductor chips face up on the sacrificial substrate so that the connector metal faces in the same direction; molding a protective member on the contact metal and the interconnect metal; Exposing one side of the contact metal and one side of the interconnecting metal, and a top side re-wiring step of electrically connecting the contact metal and the interconnecting metal to the outside.

위에서 설명한 바와 같이, 본 발명의 구성에 의하면 다음과 같은 효과를 기대할 수 있다.As described above, according to the configuration of the present invention, the following effects can be expected.

첫째, 몰딩 공정 후속으로 콘택 비아 형성 및 충진 공정이 원천적으로 생략되기 때문에, 파인 피치가 개선되고, 패키지의 신뢰성이 강화되는 효과가 있다.First, since the formation of the contact via and the filling process are basically omitted after the molding process, the fine pitch is improved and the reliability of the package is enhanced.

둘째, 패키지 공정 전반에 걸쳐 미러 웨이퍼를 희생 기판으로 사용하여 마운트 공정이 실시되기 때문에, 열처리 공정에도 불구하고 열팽창으로 인하여 뒤틀림 현상이 최소화되는 효과가 기대된다. Second, because the mounting process is performed using the mirror wafer as a sacrificial substrate throughout the entire packaging process, the twist phenomenon is expected to be minimized due to thermal expansion despite the heat treatment process.

셋째, 반도체 칩을 희생 기판에 페이스-업 마운트 함에 있어서, 다이 접착 테이프(DAF)를 이용하기 때문에, 후속 몰딩 공정이나 그라인딩 공정 시 반도체 칩이 희생 기판으로 움직이는 것을 잡아주며, 특히 재배선 공정 시 접점이 단락되는 것을 방지하여 수율 저하를 막아줄 수 있다.Third, since the die bonding tape (DAF) is used in the face-up mounting of the semiconductor chip to the sacrificial substrate, the semiconductor chip can be moved to the sacrificial substrate during the subsequent molding process or grinding process. Thereby preventing a reduction in the yield.

도 1은, 본 발명에 의한 팬 아웃 POP 패키지 구성의 일 실시예를 나타내는 단면도.
도 2는, 본 발명에 의한 팬 아웃 POP 패키지 구성의 다른 실시예를 나타내는 단면도.
도 3a 내지 도 3d는, 본 발명에 의한 반도체 칩의 제조 공정을 나타내는 단면도들.
도 4a 및 도 4b는, 본 발명에 의한 희생 기판의 제조 공정을 나타내는 단면도들.
도 5a 내지 도 5c는, 본 발명에 의한 희생 기판 상에 반도체 칩을 마운트 하는 제조 공정을 나타내는 단면도들.
도 6a 및 도 6b는, 본 발명에 의한 탑 사이드 재배선 제조 공정을 나타내는 단면도들.
도 7은, 본 발명에 의한 듀얼 사이드 재배선 제조 공정을 나타내는 단면도.
도 8은, 본 발명에 의한 팬 아웃 POP 패키지 제조 방법을 나타내는 순서도.1 is a sectional view showing an embodiment of a fan-out POP package configuration according to the present invention;
2 is a cross-sectional view showing another embodiment of a fan-out POP package configuration according to the present invention;
3A to 3D are cross-sectional views illustrating a manufacturing process of a semiconductor chip according to the present invention.
4A and 4B are cross-sectional views showing a manufacturing process of a sacrificial substrate according to the present invention.
5A to 5C are cross-sectional views illustrating a manufacturing process for mounting a semiconductor chip on a sacrificial substrate according to the present invention.
6A and 6B are cross-sectional views illustrating a top side rewiring process according to the present invention.
7 is a sectional view showing a dual side rewiring process according to the present invention.
8 is a flowchart showing a method of manufacturing a fan-out POP package according to the present invention.

본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해 질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려 주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 도면에서 층 및 영역들의 크기 및 상대적인 크기는 설명의 명료성을 위해 과장된 것일 수 있다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Brief Description of the Drawings The advantages and features of the present invention, and how to achieve them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

본 명세서에서 기술하는 실시예들은 본 발명의 이상적인 개략도인 평면도 및 단면도를 참고하여 설명될 것이다. 따라서 제조 기술 및/또는 허용 오차 등에 의해 예시도의 형태가 변형될 수 있다. 따라서 본 발명의 실시예들은 도시된 특정 형태로 제한되는 것이 아니라 제조 공정에 따라 생성되는 형태의 변화도 포함하는 것이다. 따라서 도면에서 예시된 영역들은 개략적인 속성을 가지며, 도면에서 예시된 영역들의 모양은 소자의 영역의 특정 형태를 예시하기 위한 것이고, 발명의 범주를 제한하기 위한 것은 아니다.Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are produced according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

이하, 상기한 바와 같은 구성을 가지는 본 발명에 의한 팬 아웃 패키지 온 패키지의 바람직한 실시예를 첨부된 도면을 참고하여 상세하게 설명한다.Hereinafter, preferred embodiments of the fan-out package on package according to the present invention will be described in detail with reference to the accompanying drawings.

도 1을 참조하면, 본 발명의 팬 아웃 패키지(100)는, 재배선층(RDL), 재배선층(RDL)과 스터드 콘택(102)을 통해 전기적으로 연결되는 반도체 칩(110), 반도체 칩(110)의 외곽에서 실질적으로 동일한 평면에 배치되고 일측이 재배선층(RDL)을 통해 외부와 전기적으로 연결되는 인터커넥터(120), 재배선층(RDL) 상에 형성되어 반도체 칩(110)과 인터커넥터(120)를 보호하되 인터커넥터(120)의 타측을 노출시키는 보호부재(130), 및 재배선층(RDL)의 접속부재(140)를 포함한다.1, a fan-out package 100 according to the present invention includes a semiconductor chip 110 electrically connected to a redistribution layer RDL, a redistribution layer RDL and a stud contact 102, a semiconductor chip 110 An interconnector 120 which is disposed on substantially the same plane at the outer periphery of the rewiring layer RDL and whose one side is electrically connected to the outside through a rewiring layer RDL, And a connecting member 140 of the rewiring layer RDL to protect the other end of the interconnection 120 from being exposed.

여기서 인터커넥터(120)는 보호부재(130)의 에폭시 몰딩 컴파운드(EMC) 공정에 앞서 볼 마운트(ball mount) 공정을 통하여 형성된다.Here, the interconnector 120 is formed through a ball mount process prior to the epoxy molding compound (EMC) process of the protection member 130.

도 2를 참조하면, 본 발명의 팬 아웃 POP 패키지(200)는, 일방 패키지가 타방 패키지 상부에 적층되는 패키지 온 패키지(Package On Package) 타입이다. 이러한 POP 패키지(200)는, 팬 아웃 하부 패키지(100a), 팬 아웃 상부 패키지(100b), 및 하부 패키지(100a)의 외곽에 구비되어 한 쌍의 패키지(100a,100b)를 연결하는 상하부 인터커넥터(120)를 포함한다.Referring to FIG. 2, the fan-out POP package 200 of the present invention is a package-on-package type in which one-side packages are stacked on top of the other. The POP package 200 includes a fan-out lower package 100a, a fan-out upper package 100b, and upper and lower interconnecting connectors 100a and 100b, which are provided on the outer sides of the lower package 100a and connect the pair of packages 100a and 100b. (120).

본 발명은 인터커넥터(120)가 비아 공정(via process)을 통하여 형성되지 않는 것이 특징이다. 본 발명의 인터커넥터(120)는 솔더 볼(solder ball) 공정이나 구리(Cu) 기타 메탈 포스트(metal post) 공정을 통하여 형성될 수 있다.The present invention is characterized in that the interconnector 120 is not formed via a via process. The interconnector 120 of the present invention may be formed through a solder ball process or a copper (Cu) other metal post process.

하부 패키지(100a)는, 하부 반도체 칩(110a), 하부 반도체 칩(110a) 일면의 탑 사이드 재배선층(RDLa), 하부 반도체 칩(110a) 타면의 듀얼 사이드 재배선층(RDLb), 탑 사이드 재배선층(RDLa)과 듀얼 사이드 재배선층(RDLb) 사이에 충진되는 하부 보호부재(130a), 탑 사이드 재배선층의 접속부재(140a), 및 듀얼 사이드 재배선층의 접속부재(140b)를 포함한다. The lower package 100a includes a lower semiconductor chip 110a, a top side re-wiring layer RDLa on one surface of the lower semiconductor chip 110a, a dual side re-wiring layer RDLb on the other surface of the lower semiconductor chip 110a, A lower protective member 130a to be filled between the dual side rewiring layer RDLa and the dual side rewiring layer RDLb, a connecting member 140a of the top side rewiring layer and a connecting member 140b of the dual side rewiring layer.

상부 패키지(100b)는, 듀얼 사이드 재배선층의 접속부재(140b)와 와이어 본딩되는 하나 이상의 상부 반도체 칩(110b), 상부 반도체 칩(110b)을 보호하는 상부 보호부재(130b)를 포함할 수 있다.The upper package 100b may include one or more upper semiconductor chips 110b to be wire-bonded to the connecting member 140b of the dual side re-wiring layer and an upper protective member 130b to protect the upper semiconductor chip 110b .

하부 반도체 칩(100a)은 로직(logic) 반도체를 포함할 수 있고, 상부 반도체 칩(100b)은 메모리(memory) 반도체를 포함할 수 있다.The lower semiconductor chip 100a may include a logic semiconductor, and the upper semiconductor chip 100b may include a memory semiconductor.

전술한 바와 같이 본 발명의 상하부 패키지 연결용 인터커넥터(120)는 하부 패키지(100a) 공정 시 형성되는 것이 특징이다.As described above, the upper and lower package interconnecting interconnector 120 of the present invention is formed during the process of lower package 100a.

한편, 하부 반도체 칩(110a)과 하부 재배선층(RDLa)은 스터드 콘택(102)에 의하여 전기적으로 연결되는데 스터드 콘택(102)은 스터드 범프 공정, 구리(Cu) 기타 메탈 필터 공정, 혹은 솔더 볼 공정을 통하여 형성되는 특징이 있다.The lower semiconductor chip 110a and the lower rewiring layer RDLa are electrically connected by the stud contact 102. The stud contact 102 may be formed by a stud bump process, As shown in FIG.

이하, 본 발명에 의한 팬 아웃 패키지 온 패키지(POP)의 제조 방법을 도면을 참조하여 설명한다.Hereinafter, a method of manufacturing a fan-out package on package (POP) according to the present invention will be described with reference to the drawings.

도 3a 내지 도 3d를 참조하여, 반도체 칩 제조 공정을 설명한다.3A to 3D, a semiconductor chip manufacturing process will be described.

반도체 기판을 준비하는 단계(S10); Preparing a semiconductor substrate (S10);

도 3a를 참조하면, 반도체 기판(S)을 준비한다. 이때 반도체 기판(S)은 스트립 형태(strip-type)의 웨이퍼(wafer)를 포함한다. 반도체 기판(S)(혹은 웨이퍼라 한다.)의 일면에 반도체 기판용 패드(Sp)(혹은 웨이퍼 패드라 한다.)를 형성한다. 패드(Sp)는 재배선 공정을 통하여 형성될 수 있다.Referring to FIG. 3A, a semiconductor substrate S is prepared. At this time, the semiconductor substrate S includes a strip-type wafer. A semiconductor substrate pad Sp (or a wafer pad) is formed on one surface of a semiconductor substrate S (or a wafer). The pad Sp may be formed through a rewiring process.

반도체 기판용 패드 상에 콘택 메탈을 본딩하는 단계(S12); The step of bonding the metal contact pad on the semiconductor substrate (S12);

도 3b를 참조하면, 메탈 스터드 범프 본딩 공정(metal stud bump bonding process)이나 솔더 볼 공정(solder ball process)을 통하여 반도체 기판용 패드(Sp) 상에 콘택 메탈(Sc)을 형성한다. 콘택 메탈(Sc)은 후술하는 노출 공정을 거쳐 스터드 콘택(102)을 형성하게 된다.Referring to FIG. 3B, a contact metal Sc is formed on a semiconductor substrate pad Sp through a metal stud bump bonding process or a solder ball process. The contact metal Sc forms the stud contact 102 through the exposure process described below.

반도체 기판의 타면에 접착 테이프를 라미네이팅 하는 단계(S14); Laminating an adhesive tape to the other surface of the semiconductor substrate (S14);

도 3c를 참조하면, 다이 접착용 필름 기타 접착 테이프(Die Attached Film: DAF)를 일정한 두께로 도포하고 라미네이팅(lamination process) 한다. 콘택 메탈 본딩 공정(S12) 이전에 접착 테이프(DAF)의 라미네이팅 공정(S14)이 먼저 실시될 수 있다.Referring to FIG. 3C, a die attach film or other adhesive tape (Die Attached Film: DAF) is applied to a predetermined thickness and lamination process is performed. The laminating step S14 of the adhesive tape DAF may be performed before the contact metal bonding step S12.

반도체 기판을 절단하여 개별 반도체 칩으로 분리하는 단계(S16); Cutting the semiconductor substrate into separate semiconductor chips (S16);

도 3d를 참조하면, 싱글레이션 공정(singulation process)을 통하여 반도체 기판(S)을 개별 반도체 칩(110)으로 절단하는 공정이 실시될 수 있다.Referring to FIG. 3D, a process of cutting the semiconductor substrate S into individual semiconductor chips 110 through a singulation process can be performed.

이로써, 반도체 기판용 패드(Sp) 상에 콘택 메탈(Sc)이 본딩되는 개별 반도체 칩(도 1의 110)이 준비된다.Thus, an individual semiconductor chip (110 in FIG. 1) to which the contact metal Sc is bonded is prepared on the semiconductor substrate pad Sp.

도 4a 및 도 4b를 참조하여, 희생 기판의 제조 공정을 설명한다.The manufacturing process of the sacrificial substrate will be described with reference to Figs. 4A and 4B.

희생 기판을 준비하는 단계(S20); Preparing a sacrificial substrate (S20);

도 4a를 참조하면, 희생 기판(M)은 미러 웨이퍼(mirror wafer)를 포함할 수 있다. 희생 기판(M)을 준비하고 희생 기판(M)의 일면에 희생 기판용 패드(Mp)를 형성한다. 패드(Mp)는 재배선 공정을 통하여 형성될 수 있다. 본 발명의 패키지 공정은 반도체 칩(110a)이 희생 기판(M) 상에 형성되기 때문에, 고온 공정 시 열팽창에 따른 휨(warpage) 현상이 최소화되는 효과가 있다.Referring to FIG. 4A, the sacrificial substrate M may include a mirror wafer. A sacrificial substrate M is prepared and a sacrificial substrate pad Mp is formed on one surface of the sacrificial substrate M. [ The pad Mp may be formed through a rewiring process. Since the semiconductor chip 110a is formed on the sacrificial substrate M, the packaging process of the present invention has the effect of minimizing the warpage due to thermal expansion during the high temperature process.

희생 기판용 패드 상에 인터커넥터 메탈을 본딩하는 단계(S22); The step of bonding the interconnect metal on the sacrificial substrate pads (S22);

도 4b를 참조하면, 솔더 볼 공정이나 메탈 포스트 공정을 통하여 희생 기판용 패드(Mp) 상에 인터커넥터 메탈(Mc)을 형성한다. 인터커넥터 메탈(Mc)을 후술하는 솔더 볼 공정을 거쳐 비아 성형 공정 및 비아 충진 공정을 대신하는 상하부 인터커넥터(도 1 및 도 2의 120)를 형성하게 된다. Referring to FIG. 4B, the interconnect metal Mc is formed on the sacrificial substrate pad Mp through a solder ball process or a metal post process. The interconnect metal Mc is then subjected to a solder ball process, which will be described below, to form upper and lower interconnects 120 (FIGS. 1 and 2) in place of the via forming process and the via filling process.

도 5a 내지 도 5c를 참조하여, 희생 기판 상에 반도체 칩을 마운트 하는 제조 공정을 설명한다.A manufacturing process of mounting a semiconductor chip on a sacrificial substrate will be described with reference to Figs. 5A to 5C.

반도체 기판용 패드 상에 콘택 메탈이 구비된 개별 반도체 칩을 희생 기판용 패드 상에 인터커넥터 메탈이 구비된 희생 기판에 페이스 업( face up ) 형태로 마운트 하는 단계(S30); Face up (face on an individual semiconductor chip, the contact metal is provided on the semiconductor substrate pads on the sacrificial substrate having a pad interconnect metal sacrificial substrate the method comprising mounting a up) type (S30);

도 5a를 참조하면, 접착 테이프(DAF)를 이용하여 각 반도체 칩(110)을 희생 기판(M) 상에 고정할 수 있다. 이때 접착 테이프(DAF)에 의하여 희생 기판(M) 상에 고정된 반도체 칩(110a)은 후술하는 몰딩 공정 혹은 평면화 공정에 의하더라도 움직이지 않고 고정되어 후술하는 재배선 공정 시 수율 감소를 최소화 할 수 있다.Referring to FIG. 5A, each semiconductor chip 110 can be fixed on the sacrificial substrate M using an adhesive tape DAF. At this time, the semiconductor chip 110a fixed on the sacrificial substrate M by the adhesive tape DAF is fixed without moving even if it is subjected to a molding process or a flattening process, which will be described later, have.

희생 기판 상에 보호부재를 몰딩하는 단계(S32); On the sacrificial substrate Molding the protective member (S32);

도 5b를 참조하면, 반도체 기판용 패드(Sp)에 본딩되는 콘택 메탈(Sc)과, 희생 기판용 패드(Mp)에 본딩되는 인터커넥터 메탈(Mc) 상에 에폭시 몰딩 컴파운드(EMC)를 증착한다. 에폭시 몰딩 컴파운드(EMC)는 콘택 메탈(Sc)과 인터커넥터 메탈(Mc)이 커버될 정도로 보호부재(130a)가 도포될 수 있다.5B, an epoxy molding compound (EMC) is deposited on the contact metal Sc to be bonded to the semiconductor substrate pad Sp and the interconnector metal Mc to be bonded to the sacrificial substrate pad Mp . The epoxy molding compound (EMC) can be coated with the protective member 130a so that the contact metal Sc and the inter-connector metal Mc are covered.

보호부재를 그라인딩 하여 평면화 하는 단계(S34); The protective member The step of grinding to flatten (S34);

도 5c를 참조하면, 콘택 메탈(Sc)과 인터커넥터 메탈(Mc)이 노출될 때까지 평면화 공정을 계속하여 실시한다. 이와 같은 평면화 공정을 통하여 노출된 콘택 메탈(Sc)과 인터커넥터 메탈(Mc)은 결과적으로 스터드 콘택(도 1 및 도 2의 102)과 인터커넥터(도 1 및 도 2의 120)를 형성하게 된다.Referring to FIG. 5C, the planarization process is continued until the contact metal Sc and the interconnect metal Mc are exposed. The exposed contact metal Sc and the interconnect metal Mc through the planarization process result in the formation of the stud contact (102 in FIGS. 1 and 2) and the interconnect (120 in FIGS. 1 and 2) .

도 6a 및 도 6b를 참조하여, 탑 사이드 재배선 제조 공정을 설명한다.6A and 6B, a top side rewiring process will be described.

스터드 콘택과 인터커넥터를 외부와 전기적으로 연결하는 탑 사이드 재배선 단계(S40); Stud A top side re-wiring step (S40) for electrically connecting the contacts and the inter-connector to the outside ;

도 6a를 참조하면, 탑 사이드 재배선 공정 결과, 인터커넥터(120)를 통하여 타 패키지(도 2의 100b)를 외부와 전기적으로 연결하고, 스터드 콘택(102)을 통하여 반도체 칩(도 2의 110a)을 외부와 전기적으로 연결하는 탑 사이드 재배선(RDLa)을 설치한다. 그리고 탑 사이드 재배선 접속부재(140a)를 형성한다.Referring to FIG. 6A, as a result of the topside rewiring process, another package (100b in FIG. 2) is electrically connected to the outside through the interconnector 120 and the semiconductor chip 110a (RDLa) for electrically connecting the topside rewiring line (RDLa) to the outside. Then, the top side redistributive line connecting member 140a is formed.

희생 기판을 반도체 칩으로부터 제거하는 단계(S42); Removing the sacrificial substrate from the semiconductor chip (S42);

도 6b를 참조하면, 희생 기판(M)을 그라인딩하여 희생 기판(M)을 보호부재(130a)에서 제거한다. 그라인딩 공정을 통하여 희생 기판용 패드(Mp)와 접착 테이프(DAF)가 제거됨으로써, 반도체 칩(110a)과 인터커넥터 메탈(Mc)이 노출되어 타 패키지(도 2의 100b)와 전기적으로 연결될 수 있다. Referring to FIG. 6B, the sacrificial substrate M is grinded to remove the sacrificial substrate M from the protective member 130a. The sacrificial substrate pad Mp and the adhesive tape DAF are removed through the grinding process so that the semiconductor chip 110a and the interconnector metal Mc are exposed and can be electrically connected to another package 100b in FIG. .

도 7을 참조하여, 듀얼 사이드 재배선 제조 공정을 설명한다.Referring to Fig. 7, the dual side re-wiring manufacturing process will be described.

스터드 콘택과 인터커넥터를 타 패키지와 전기적으로 연결하는 듀얼 사이드 재배선 단계(S50); Stud A dual side rearrangement step (S50) of electrically connecting the contact and the interconnection to the other package ;

도 7을 참조하면, 희생 기판(M)이 제거되어 인터커넥터 메탈(Mc)이 노출된 영역으로 인터커넥터(120)를 통하여 타 패키지(도 2의 100b)와 전기적으로 연결되는 듀얼 사이드 재배선(RDLb) 및 접속부재(140b)를 설치할 수 있다.7, the sacrificial substrate M is removed to form a dual side rewiring line (not shown) electrically connected to another package (100b in FIG. 2) through the interconnector 120 to the exposed region of the interconnector metal Mc RDLb and a connecting member 140b.

이상에서 살펴본 바와 같이, 본 발명은 팬 아웃 패키지 온 패키지에서 상하부 패키지를 연결하는 콘택을 몰딩 공정 후 비아 형성 및 충진 공정을 이용하지 않고 솔더 볼 공정이나 범프 공정 등을 이용함으로써 수율을 개선하는 구성을 기술적 사상으로 하고 있음을 알 수 있다. 이와 같은 본 발명의 기본적인 기술적 사상의 범주 내에서, 당업계의 통상의 지식을 가진 자에게 있어서는 다른 많은 변형이 가능할 것이다.As described above, the present invention provides a structure for improving the yield by using a solder ball process, a bump process, or the like without using a via forming process and a filling process after a molding process for connecting the upper and lower packages in a fan- It can be seen that it is technological thought. Many other modifications will be possible to those skilled in the art, within the scope of the basic technical idea of the present invention.

100: 패키지 102: 스터드 콘택
110: 반도체 칩 120: 인터커넥터
130: 보호부재 140: 접속부재
RDL: 재배선층 S: 반도체 기판
Sp: 반도체 기판용 패드 Sc: 콘택 메탈
DAF: 접착 테이프 M: 희생 기판
Mp: 희생 기판용 패드 Mc: 인터커넥터 메탈100: Package 102: Stud contact
110: semiconductor chip 120: interconnect connector
130: protective member 140: connecting member
RDL: re-wiring layer S: semiconductor substrate
Sp: Pad for semiconductor substrate Sc: Contact metal
DAF: adhesive tape M: sacrificial substrate
Mp: Pad for sacrificial substrate Mc: Interconnector metal

Claims (9)

재배선층;
반도체 칩;
상기 반도체 칩을 보호하는 보호부재; 및
상기 보호부재로부터 일부가 노출됨으로써, 상기 재배선층과 상기 반도체 칩을 전기적으로 연결하는 스터드 콘택을 포함하여 구성되는 것을 특징으로 하는 팬 아웃 패키지.A rewiring layer;
A semiconductor chip;
A protective member for protecting the semiconductor chip; And
And a stud contact electrically connecting the re-wiring layer and the semiconductor chip by partially exposing the protective member. 제 1 항에 있어서,
상기 반도체 칩의 외곽의 상기 반도체 칩과 실질적으로 동일한 평면 에 배치되고, 일측이 상기 재배선층을 통해 외부와 전기적으로 연결되는 인터커넥터를 더 포함하여 구성되는 것을 특징으로 하는 팬 아웃 패키지.The method according to claim 1,
Further comprising: an inter-connector disposed on a substantially same plane as the semiconductor chip outside the semiconductor chip and having one side electrically connected to the outside through the re-wiring layer. 제 2 항에 있어서,
상기 스터브 콘택은 메탈 스터드 범프 혹은 솔더 볼을 포함하고,
상기 인터커넥터는 솔더 볼 혹은 메탈 포스트를 포함하는 것을 특징으로 하는 팬 아웃 패키지.3. The method of claim 2,
Wherein the stub contact includes a metal stud bump or a solder ball,
Wherein the interconnector comprises a solder ball or a metal post. 콘택 메탈이 구비된 개별 반도체 칩을 준비하는 단계;
인터커넥터 메탈이 구비된 희생 기판을 준비하는 단계;
상기 콘택 메탈과 상기 인터커넥터 메탈이 동일한 방향을 향하도록, 상기 개별 반도체 칩을 상기 희생 기판에 페이스 업(face up) 형태로 재배열 하는 단계;
상기 콘택 메탈과 상기 인터커넥터 메탈이 외부로 노출되지 않도록 보호부재를 몰딩하는 단계;
상기 보호부재를 연마하여 상기 콘택메탈과 상기 인터커넥터메탈의 상부를 노출시키는 단계; 및
상기 콘택 메탈과 상기 인터커넥터 메탈을 외부와 전기적으로 연결하는 상부 재배선 및 접속부재 형성 단계를 포함하는 것을 특징으로 하는 팬 아웃 POP 패키지 제조 방법.Preparing an individual semiconductor chip provided with a contact metal;
Preparing a sacrificial substrate provided with interconnect metal;
Rearranging the individual semiconductor chips in a face up form on the sacrificial substrate so that the contact metal and the interconnect metal are oriented in the same direction;
Molding the protection member so that the contact metal and the interconnect metal are not exposed to the outside;
Polishing the protective member to expose an upper portion of the contact metal and the interconnect metal; And
And forming an upper wiring and a connection member electrically connecting the contact metal and the interconnecting metal to the outside. 제 4 항에 있어서,
상기 반도체 칩을 준비하는 단계는,
웨이퍼 일면에 패드를 형성하는 단계;
상기 웨이퍼 패드 상에 상기 콘택 메탈을 본딩하는 단계;
상기 웨이퍼의 타면에 접착 테이프를 라미네이팅하는 단계; 및
상기 웨이퍼를 절단하여 상기 개별 반도체 칩으로 분리하는 단계를 포함하고,
상기 콘택 메탈을 본딩하는 단계는,
메탈 스터드 범프 본딩 공정, 혹은 솔더 볼 공정을 통하여 상기 웨이퍼 패드 상에 콘택 메탈이 마운트 되는 것을 특징으로 하는 팬 아웃 POP 패키지 제조 방법.5. The method of claim 4,
The step of preparing the semiconductor chip includes:
wafer Forming a pad on one surface;
Bonding the contact metal on the wafer pad;
Laminating an adhesive tape on the other side of the wafer; And
And separating the wafer into the individual semiconductor chips,
The step of bonding the contact metal comprises:
Wherein the contact metal is mounted on the wafer pad through a metal stud bump bonding process or a solder ball process. 제 4 항에 있어서,
상기 희생 기판을 준비하는 단계는,
상기 희생 기판에 패드를 형성하는 단계; 및
상기 희생 기판용 패드 상에 상기 인터커넥터 메탈을 본딩하는 단계를 포함하고,
상기 인터커넥터 메탈을 본딩하는 단계는,
솔더 볼 공정이나 메탈 포스트 공정을 통하여 상기 희생 기판용 패드 상에 인터커넥터 메탈이 마운트 되는 것을 특징으로 하는 팬 아웃 POP 패키지 제조 방법.5. The method of claim 4,
Wherein preparing the sacrificial substrate comprises:
Forming a pad on the sacrificial substrate; And
Bonding the interconnect metal to the sacrificial substrate pad,
Wherein the step of bonding the interconnect metal comprises:
Wherein the interconnection metal is mounted on the pad for the sacrificial substrate through a solder ball process or a metal post process. 제 4 항에 있어서,
상기 희생 기판을 상기 반도체 칩으로부터 제거하여 상기 콘택 메탈의 타측과 상기 인터커넥터 메탈의 타측을 노출하는 단계; 및
상기 콘택 메탈과 상기 인터커넥터 메탈을 타 패키지와 전기적으로 연결하는 듀얼 사이드 재배선하는 단계를 더 포함하는 것을 특징으로 하는 팬 아웃 POP 패키지 제조 방법.5. The method of claim 4,
Removing the sacrificial substrate from the semiconductor chip to expose the other side of the contact metal and the other side of the interconnect metal; And
Further comprising a dual side re-routing step of electrically connecting the contact metal and the interconnecting metal to another package. 하부 패키지;
상부 패키지; 및
상기 하부 패키지에 구비되어 상기 상하부 패키지를 연결하는 인터커넥터를 포함하고,
상기 인터커넥터는, 솔더 볼 공정 혹은 메탈 포스트 공정을 통하여 형성되고,
상기 하부 패키지는,
탑 사이드 재배선층;
상기 탑 사이드 재배선층과 스터드 콘택을 통해 전기적으로 연결되는 하부 반도체 칩;
상기 하부 반도체 칩의 외곽에 배치되고 일측이 상기 탑 사이드 재배선층을 통해 외부와 전기적으로 연결되는 인터커넥터;
상기 탑 사이드 재배선층 상에 형성되고, 상기 인터커넥터의 타측을 노출시키는 하부 보호부재; 및
상기 탑 사이드 재배선층의 접속부재를 포함하는 것을 특징으로 하는 팬 아웃 POP 패키지.Lower package;
An upper package; And
And an interconnector provided in the lower package for connecting the upper and lower packages,
The interconnector is formed through a solder ball process or a metal post process,
Wherein the lower package comprises:
A topside rewiring layer;
A lower semiconductor chip electrically connected to the top side re-wiring layer through a stud contact;
An interconnection disposed at an outer side of the lower semiconductor chip and having one side electrically connected to the outside through the top side re-wiring layer;
A lower protective member formed on the top side re-wiring layer and exposing the other side of the interconnector; And
And a connection member of the top side re-wiring layer. 제 8 항에 있어서,
상기 상부 패키지는,
상기 인터커넥터의 타측과 전기적으로 연결되는 듀얼 사이드 재배선층;
상기 듀얼 사이드 재배선층의 접속부재;
상기 듀얼 사이드 재배선층의 접속부재와 전기적으로 연결되는 하나 이상의 상부 반도체 칩; 및
상기 상부 반도체 칩을 보호하는 상부 보호부재를 포함하는 것을 특징으로 하는 팬 아웃 POP 패키지.
9. The method of claim 8,
Wherein the upper package comprises:
A dual side re-wiring layer electrically connected to the other side of the interconnector;
A connecting member of the dual side re-wiring layer;
At least one upper semiconductor chip electrically connected to the connection member of the dual side re-wiring layer; And
And an upper protective member for protecting the upper semiconductor chip.
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