KR20160119844A - Transistor using piezoresistor as channel, and electronic circuit - Google Patents

Abstract

A source (14) for injecting the carrier into the piezoresistor; a drain (16) for receiving the carrier from the piezoresistor; and a resistor (16) provided to surround the piezoresistor There is provided a transistor including a piezoelectric body 12 for applying pressure to a piezo resistor and a gate 18 for applying a voltage to the piezoelectric body so that the piezoelectric body applies pressure to the piezo resistor.

Description

[0001] TRANSISTOR USING PIEZORESISTOR AS CHANNEL, AND ELECTRONIC CIRCUIT [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and an electronic circuit, and more particularly to a transistor and an electronic circuit using a piezo resistor as a channel.

Patent Document 1 discloses a transistor in which a piezo resistor is used as a channel and a piezoelectric body for applying pressure to the piezoresistor is provided at the gate.

U.S. Patent No. 8159854

However, in the transistor disclosed in Patent Document 1, a pressure is applied from the piezoelectric body gate to the piezo resistor channel using a supporting structure made of a high-strength-strength material (hereinafter, the piezoelectric body and the gate are collectively referred to as a piezoelectric body gate). For this reason, the pressure application efficiency is not sufficient, and the integration becomes difficult. Also, if the source and the drain are interchanged, the characteristics change. For this reason, it is difficult to use the transistor of Patent Document 1 in a circuit making the source and the drain equivalent.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a piezoelectric resonator capable of effectively applying pressure from a piezoelectric gate to a piezo resistor channel without using a device (transistor) It is an object of the present invention to provide a transistor and an electronic circuit which are possible. Another object of the present invention is to provide a transistor and an electronic circuit capable of interchanging a source and a drain.

The present invention relates to a piezoelectric resonator comprising a piezo resistor which carries a carrier, a source for injecting the carrier into the piezo resistor, a drain for receiving the carrier from the piezoresistor, and a piezoelectric element And a gate for applying a voltage to the piezoelectric body so that the piezoelectric body applies pressure to the piezo resistor.

In the above structure, the gate may be provided so as to surround the piezoelectric body, and the piezoelectric body may be configured to be dielectric-polarized in a direction from the piezo resistor toward the gate or from the gate toward the piezoresistor.

In the above configuration, the plurality of gates may be provided in a direction parallel to the conduction direction of the carrier conducting the channel in the piezoresistor, and the piezoelectric body may be dielectric polarized in the parallel direction.

In the above configuration, the piezoelectric body may be provided so as to surround the piezo resistor from all directions orthogonal to the conduction direction of the carrier.

In the above structure, the piezoelectric body may be provided so as to surround the piezo resistor from a direction orthogonal to the conduction direction of the carrier.

In the above arrangement, it is preferable that the piezoelectric resonator is provided with a supporting member formed on the substrate and supporting the piezo resistor, wherein the upper surface of the piezo resistor is curved and the piezoelectric member surrounds the upper surface of the piezo resistor and the side surface of the support .

In the above configuration, the height of the support may be larger than the width of the piezo resistor.

In the above configuration, the material of the support may have the same structure as the material of the piezo resistor.

In the above configuration, the material of the support may be different from the material of the piezo resistor.

In the above structure, the source and the drain are symmetrical with respect to a plane between the source and the drain in the piezoresistor, and the piezoresistor, the piezoelectric body, and the gate are formed on the intermediate surface It can be a symmetrical structure.

The present invention is a circuit comprising: a circuit connected between a first power supply and a second power supply; and one of the source and the drain is connected to the first power supply, and the other of the source and the drain is connected to the circuit And a transistor which is connected to a power supply terminal of the transistor and to which a signal for interrupting power supplied to the circuit is input to the gate.

And a nonvolatile element that stores data stored in the bistable circuit in a nonvolatile manner and restores nonvolatilely stored data in the bistable circuit, The circuit may be a bistable circuit.

In the above configuration, the nonvolatile element may be connected between the node in the bistable circuit and the control line.

The present invention is an electronic circuit characterized by comprising a nonvolatile element and a nonvolatile memory cell including the transistor in which the source or the drain is connected in series with the nonvolatile element as the transistor.

The present invention is the transistor described above, wherein the transistor is provided with first and second transistors complementary to each other, wherein the dielectric polarization directions of the piezoelectric bodies of the first and second transistors are opposite to each other, Is a direction in which the piezoelectric body can apply pressure to the piezo resistor when a voltage or a negative voltage is applied to the piezo resistor.

The present invention relates to a semiconductor device comprising: a piezo resistor which conducts a carrier in a first direction; a source which injects the carrier into the piezo resistor; a drain which receives the carrier from the piezo resistor; A piezoelectric body for applying pressure to the piezo resistor, and a gate for applying a voltage to the piezo resistor so as to apply pressure to the piezo resistor.

(Effects of the Invention)

According to the present invention, it is possible to provide a transistor and an electronic circuit capable of effectively applying pressure to a piezo resistor channel from a piezoelectric gate, and capable of switching a source and a drain, without using a device (transistor) supporting structure by a high- . Alternatively, it is possible to provide a transistor and an electronic circuit capable of switching the source and the drain.

1 is a cross-sectional view of a transistor according to a first comparative example.
2 is a perspective view of a transistor according to the first embodiment.
Fig. 3 (a) is a perspective sectional view of the first-type transistor according to the first embodiment, Fig. 3 (b) is a cross-sectional view, and Fig. 3 (c) is a circuit symbol.
Fig. 4A is a perspective sectional view of the second-type transistor according to the first embodiment, Fig. 4B is a cross-sectional view, and Fig. 4C is a circuit symbol.
5 (a) to 5 (f) are schematic diagrams of a transistor according to a modification of the first embodiment.
6 (a) and 6 (b) show the sizes used in the simulations of the first embodiment and the first comparative example, respectively. Source, drain, gate and metal contacts are not shown for simplicity.
Figs. 7 (a) and 7 (b) are diagrams showing α for L _PE in Example 1 and Comparative Example 1, respectively.
Figs. 8 (a) and 8 (b) are diagrams showing α for I _PR in Example 1 and Comparative Example 1, respectively.
9 (a) and 9 (b) are diagrams showing drain current (I _D ) with respect to the drain voltage (V _D ) in Example 1 and Comparative Example 1, respectively.
10 (a) and 10 (b) are _views showing S for L _PE in Example 1 and Comparative Example 1, respectively.
11 (a) and 11 (b) are diagrams showing S for I _PR in Example 1 and Comparative Example 1, respectively.
Figs. 12 (a) to 12 (c) are diagrams showing the output voltage versus time of the ring oscillator. Fig.
13 (a) and 13 (b) are block diagrams of an electronic circuit according to the second embodiment.
14 is a circuit diagram of an electronic circuit according to the third embodiment.
15 is a circuit diagram of an electronic circuit according to a modification of the third embodiment.
16 (a) is a circuit diagram of a nonvolatile memory cell according to a fourth embodiment, and FIG. 16 (b) is a cross-sectional perspective view.
17A to 17F are circuit diagrams (1) showing an electronic circuit according to a fifth embodiment.
18 (a) to 18 (f) are circuit diagrams (part 2) showing an electronic circuit according to a fifth embodiment.
Figs. 19 (a) to 19 (c) are cross-sectional views of a transistor according to a sixth embodiment and modifications thereof.
FIG. 20A is a perspective sectional view of a transistor according to a seventh embodiment, and FIGS. 20B and 20C are cross-sectional views.
21 (a) is a cross-sectional view of a transistor according to a modification 1 of the seventh embodiment, and Fig. 21 (b) is a cross-sectional view.
22 (a) is a perspective sectional view of a transistor according to a modification 2 of the seventh embodiment, and Figs. 22 (b) and 22 (c) are sectional views.
23 is a cross-sectional view of a transistor according to a modification 3 of the seventh embodiment.
FIG. 24A is a diagram showing drain characteristics using simulation 2, and FIG. 24B is a diagram showing drain characteristics in which simulations 1 and 2 are compared.
25 is a diagram showing transfer characteristics of an inverter circuit.
26A and 26B are diagrams showing butterfly curves of the bistable circuits in the simulations 1 and 2, respectively.
27 is a block diagram of an electronic circuit according to the eighth embodiment.

Recent CMOS (Complementary Metal Oxide Semiconductor) logic systems such as microprocessors and System on a Chip (SoC) have been developed by combining transistor miniaturization and high performance. Such compatibility is largely due to the improvement of the current driving ability based on the miniaturization of the transistor and the high density integration. However, the power consumption increases with the miniaturization of the transistor (the update of the technology node). This increase in power consumption is a serious problem that limits the performance of the logic system and the integration density of the transistors. Further, in a mobile device such as a smart phone, which is one of important applications in recent CMOS logic systems, the power consumption of the logic system is also one of the factors determining the battery usage time.

The lowering of the power supply voltage in the CMOS logic system is one of the effective means for lowering the power consumption of the CMOS logic system. However, lowering the voltage significantly degrades the operating frequency (speed) of the logic system. In addition, the lowering of the voltage significantly deteriorates the resistance to the change of the device. The main cause of the problem caused by lowering the power supply voltage is deterioration of the current driving ability of the transistor. Therefore, a "high sensitivity" transistor capable of driving a larger current with a smaller input voltage has been actively developed. In addition, the ratio of the dynamic power to the static power with respect to the total power consumption in the low voltage operation decreases with the driving voltage, and the static power increases. Therefore, a transistor having sufficiently low leakage (subthreshold leakage) is required even in a low-voltage operation. From the above viewpoint, several new devices have been researched and developed. However, even if the current driving ability is high, there are many devices with large leakage and many devices with low leakage current driving ability.

It is possible to expect a considerable reduction in the power consumption in the region of the ultra low voltage having the power supply voltage of about 0.2V. However, in the conventional CMOS technology, when such an ultra-low voltage operation is performed, deterioration of the circuit performance due to deterioration of the current driving capability is severe, which is difficult to use. Such deterioration of circuit performance is difficult to fundamentally solve with any semiconductor material as long as the semiconductor is used for the channel. The metal channel has a low resistance and is likely to realize a high current driving capability even at a low voltage. However, if metal channels are used, it is in principle difficult to lower the leakage sufficiently. Therefore, it is considered to use a material for metal-insulator transition which can form two states of low resistance in metal and high resistance in insulator, for the channel of the transistor. These transistors are considered suitable devices for ultra-low voltage driving. In recent years, a new transistor called a piezoelectronic transistor (PET) has been proposed, which uses a piezoresistor having a large piezo effect as its gate and a piezoresistive effect as a channel causing a metal-insulator transition under pressure as a channel Document 1).

1 is a cross-sectional view of a transistor (PET) according to Comparative Example 1. Fig. Comparative Example 1 is an example in which the structure of Patent Document 1 is applied. As shown in Fig. 1, a piezoresistor 10 is provided between the source 14 and the drain 16. The piezoelectric body 12 is provided below the source 14 (on the side opposite to the piezoresistor 10). A gate 18 is provided under the piezoelectric body 12. The stacked body from the gate 18 to the drain 16 is supported by a support structure 20 made of a high-strength-strength material. When a voltage is applied between the source 14 and the gate 18, the piezoelectric body 12 is displaced. As a result, pressure is applied from the piezoelectric body 12 to the piezo resistor 10.

In PET, a piezoresistive element 10, which undergoes a metal-insulator transition by pressure, is used for the channel. The resistance of the piezo resistor 10 on the metal phase at the time of on-state is very low, and a large current driving capability can be expected. The resistance change rate with respect to the pressure of the piezo resistor is large, and the channel resistance at the time of off can be made very high. Therefore, a sufficient ON / OFF current ratio can be expected. Further, by reversing the direction of dielectric polarization of the piezoelectric body 12 in PET, it is possible to realize operations such as p-channel operation and n-channel operation in the MOSFET. Therefore, a circuit using a complementary transistor such as a CMOS circuit can be configured.

In order to realize a high current driving capability and a sharp subthreshold characteristic in PET, it is required to use a piezoelectric body 12 having a large piezoelectric effect. Not only the characteristics of the piezoelectric body 12 but also the structure of the device capable of applying pressure to the piezoelectric body efficiently from the piezoelectric body 12 becomes very important. In the PET proposed so far, a supporting structure of a device such as a support structure 20 made of a high-yield strength material or the like is used to apply pressure to the piezo resistor. This support structure is not suitable for high-density integration of integrated circuits. In addition, there is a possibility that performance degradation due to various parasitic elements caused by the presence of the support structure 20 may occur. Further, such a supporting structure is not suitable for applying a pressure from the piezoelectric body 12 to the channel made of the piezo resistor with high efficiency. Therefore, it is important to realize a device structure capable of efficiently applying pressure to a channel without using the supporting structure of such a device in PET.

In the embodiments described below, PET having a device structure suitable for an integrated circuit can be realized without using the supporting structure of the device. Further, it is possible to realize PET having a structure capable of applying a high-efficiency pressure from the piezoelectric gates to the piezo resistor channel. The device structure PET can realize high current drive capability and steep subthreshold characteristics. In addition, it is possible to realize a power gating circuit using low impedance of PET and a memory circuit and logic circuit of low power consumption using high-speed operation under PET at low voltage.

Example 1

Example 1 is an example of PET. 2 is a perspective view of a transistor according to the first embodiment. Fig. 3 (a) is a perspective sectional view of the first-type transistor according to the first embodiment, Fig. 3 (b) is a cross-sectional view, and Fig. 3 (c) is a circuit symbol. Fig. 4A is a perspective sectional view of the second-type transistor according to the first embodiment, Fig. 4B is a cross-sectional view, and Fig. 4C is a circuit symbol.

As shown in Figs. 2 to 4 (c), the central axis in the piezoresistor 10 is defined as the z-axis and the radial direction is defined as the r-direction. The piezo resistor 10 has a cylindrical shape. At both ends of the piezo resistor 10, a source 14 and a drain 16 are provided. The source 14 injects a carrier (for example, electrons) into the piezoresistor 10. The drain 16 receives the carrier from the piezoresistor 10. The carrier conducts in the piezo resistor 10 in the direction from the source 14 to the drain 16. The conduction direction of the carrier is the z direction. A metal contact layer 15 is formed between the source 14 and the piezo resistor 10 and a metal contact layer 17 is formed between the drain 16 and the piezoresistor 10. The metal contact layers 15 and 17 are in contact with the piezoelectric body 12 and are used to apply a gate voltage to the piezoelectric body 12 effectively when the piezo resistor 10 is an insulating phase. It is preferable that the metal contact layers 15 and 17 have a low Young's modulus so that pressure is effectively applied to the piezo resistor 10. [ The piezoelectric body 12 is provided so as to surround the piezoresistor 10. The piezoelectric body 12 has a donut shape. A gate 18 is provided around the piezoelectric body 12.

As shown in Figs. 3A and 3B, the dielectric polarization direction 22 of the piezoelectric substance 12 in the first-type transistor 11a is -r direction. For example, when a positive voltage is applied between the gate 18 and the source 14 with respect to the source 14, the piezoelectric body 12 applies pressure to the piezoresistor 10. As a result, the piezo resistor 10 becomes a metal phase. Thus, the carrier is conducted from the source 14 to the drain 16. If no voltage is applied between the gate 18 and the source 14, no pressure is applied to the piezoresistor 10 and the piezoresistor 10 is isolated. As a result, conduction of carriers from the source 14 to the drain 16 is cut off. Thus, the piezoresistor 10 turns on (becomes a metal phase) when the positive side voltage is applied to the gate 18 with the source 14 as a reference, in the first type transistor 11a. This operation can be regarded as equivalent to the operation of the n-channel FET in the MOSFET. Thus, the first-type transistor 11a is referred to as an n-channel for convenience and is represented by a circuit symbol as shown in Fig. 3 (c). In Fig. 3 (c), the source S corresponds to the source 14, the drain D corresponds to the drain 16, and the gate G corresponds to the gate 18, respectively.

As shown in Figs. 4 (a) and 4 (b), the dielectric polarization direction 22 of the piezoelectric substance 12 in the second-type transistor 11b is in the + r direction. For example, when a negative voltage is applied between the gate 18 and the source 14 with respect to the source 14, pressure is applied to the piezoresistor 10. As a result, the piezo resistor 10 becomes a metal phase. If no voltage is applied between the gate 18 and the source 14, no pressure is applied to the piezoresistor 10, and the piezoresistor 10 is isolated. As a result, conduction of carriers from the source 14 to the drain 16 is cut off. As described above, when the negative voltage is applied to the gate 18 with the source 14 as a reference, the piezoresistor 10 turns on (becomes a metal phase) in the second-type transistor 11b. This operation can be regarded as equivalent to the operation of the p-channel FET in the MOSFET. Therefore, the second type transistor 11b is referred to as a p-channel for convenience and is indicated by a circuit symbol as shown in Fig. 4 (c).

As described above, the n-channel and the p-channel of PET in the following description are the same as the operation of the n-channel FET of the MOSFET, not the carrier for conducting the channel of the piezoresistor 10, Operation or the like.

5 (a) to 5 (f) are schematic diagrams of a transistor according to a modification of the first embodiment. Figs. 5A and 5C are cross-sectional views, Figs. 5B and 5D are sectional views, and Figs. 5E and 5F are circuit symbols. As shown in Figs. 5 (a) and 5 (b), in the transistor 11c, the dielectric polarization direction of the piezoelectric body 12 is the -z direction. Gates 18a and 18b are provided so as to face the z direction of the piezoelectric body 12. [ The piezoelectric body 12 can apply pressure to the piezo resistor 10 by applying a positive voltage between the gate 18a and the gate 18b with respect to the gate 18b.

As shown in Figs. 5 (c) and 5 (d), in the transistor 11d, the dielectric polarization direction of the piezoelectric body 12 is the z direction. The piezoelectric body 12 can apply pressure to the piezo resistor 10 by applying a negative voltage between the gate 18a and the gate 18b with respect to the gate 18b. Therefore, the transistor 11c and the transistor 11d are complementary to each other.

In Figs. 5 (e) and 5 (f), G1 corresponds to the gate 18a, and G2 corresponds to the gate 18b. For example, when G2 is connected to a reference voltage (or a source or the like) such as ground, G2 may not be described but may be represented by a circuit symbol as shown in Figs. 3 (c) and 4 (c). Hereinafter, G2 is assumed to be the same potential as the source, and the description thereof is omitted.

In the first embodiment, the gate 18 is provided so as to surround the piezoelectric body 12. The piezoelectric body 12 is dielectric-polarized outward or inward (for example, radially within the piezo resistor 10). In the modification of the first embodiment, a plurality of gates 18a and 18b are provided in parallel to the z direction on the surface of the piezoelectric body 12 opposed to the z direction (that is, the surface perpendicular to the z direction). The piezoelectric body 12 is dielectric-polarized in the z direction. Thus, the dielectric polarization direction of the piezoelectric body 12 is appropriately set. The complementary transistor can be easily formed by orienting the dielectric polarization direction in the piezoelectric body 12 in the opposite direction.

In the first embodiment and its modifications, the piezoelectric body 12 surrounds the piezo resistor 10 and applies pressure to the piezo resistor 10 from the surroundings. Therefore, the supporting structure of the device as in Comparative Example 1 may not be used. The piezo resistor 10 and the piezoelectric body 12 have been described as cylindrical and donut-shaped. However, the shapes of the piezo resistor 10 and the piezoelectric body 12 are not limited to these. For example, the piezo resistor 10 may be a polygonal column such as a quadrangular column. In addition, the angle of the polygonal column may be rounded. In this case, in the first embodiment, the direction of the dielectric polarization in the piezoelectric body 12 is the direction from the piezoresistor 10 to the gate 18 or from the gate 18 to the piezoresistor 10. In the modified example of the first embodiment, the dielectric polarization direction is the z direction. In order to uniformly apply pressure to the piezoresistor 10, it is preferable that the piezoresistor and the piezoelectric body 12 are rotationally symmetric with respect to the z-axis.

The metal contacts 15 and 17 are formed while being in contact with the piezoelectric body 12 in the first embodiment and the modification thereof (when the metal contacts 15 and 17 are formed in the modified example) And the drain 16 may be used. In this case, the source 14 and the drain 16 may be in contact with the piezoelectric body 12. If the source 14 and the drain 16 are made of a material having a low Young's modulus (for example, a material having a Young's modulus equal to that of the piezo resistor 10 or smaller than the piezo resistor 10) And the drain 16 and the piezoelectric body 12 may be in contact with each other. 3 (b), 4 (a), 4 (b), 5 (a) to 5 (d) when the Young's modulus of the source 14 and the drain 16 is large, It is preferable to form a gap between the source 14 and the drain 16 and the piezoelectric body 12 as shown in Fig. 5A to 5D, voids are formed between the source 14 and the drain 16 and the piezoelectric body 12, but voids are formed between the source 14 and the drain 16, It may be in contact with the piezoelectric body 12 when it is the same as the piezo resistor 10 or is smaller than the piezoresistor 10.

The piezoresistor 10 is made of a material having a piezoresistive effect in which the electrical resistance is changed by the applied mechanical pressure. It is preferable that the resistivity of the piezo resistor 10 is changed by 2 or more by applying pressure to the piezo resistor 10, more preferably by 4 or more, more preferably by 5 or more. As such a material, for example, SmSe, TmSe, SmS, Ca ₂ RuO ₄ , (Ca, Ba, SrRu) O ₃ , Ni (S _x Se _{1 -x} ) ₂ C, or (V _{1 -x} Cr _x ) ₂ O ₃ can be used for the piezoresistor 10.

The piezoelectric body 12 is made of a material having an inverse piezoelectric effect that is mechanically deformed by an applied voltage. As the material of the piezoelectric body 12, for example, the following ABC ₃ type perovskite structure materials can be used.

(Pb, M1) (Ti, M2) O 3,

(Bi, M1) (Zn, Ti, M2) O 3,

(Bi, M1) (Na, Ti, M2) O 3,

(K, M1) (Nb, M2) O 3,

(Li, M1) (Nb, M2) O 3,

(Li, M1) (Ta, M2) O 3,

or

(Na, M1) (Nb, M2) O 3

Here, M1 is Li, Ca, Ba, Sr, Bi, Pb or lanthanoid with a valence of 1-3. M2 is Zr, Hf, Mg / Nb, Mg / Ta, In / Sc and the like having a valence of 2-6.

As the material other than the perovskite structure material, the following can be used.

(Hf, M3) O ₂

Here, M3 is Sr, Si, Ba, Ca, Mg, Zr, Ce, Ti, Ge, Sn, Nb, Ta or lanthanoids.

PTZ (lead magnesium niobate-lead titanate), or PZN-PT (zinc niobate-titanate-lead zirconate-titanate lead zirconate titanate) is used as the material of the piezoelectric body 12, typically PZT (lead zirconate titanate), PSZT Lead) can be used. The source 14, the drain 16 and the gate 18 are conductors such as metal.

The metal contact layers 15 and 17 preferably have a low Young's modulus and low resistivity. As such materials, Al (68), Mg (65), Ag (76), Au (80), Pb (14), Ca (23), Sn (41) Can be used. The parentheses indicate the Young's modulus (GPa). For example, it is preferable that the Young's modulus of the metal contact layers 15 and 17 is about the same as that of the piezo resistor 10 or smaller than that of the piezo resistor 10.

The piezoelectric resistor 10, the piezoelectric body 12, the metal contact layers 15 and 17, and the source 14, the drain 16 and the gate 18 are formed by a sputtering method, a CVD (Chemical Vapor Deposition) As shown in FIG.

The transistor characteristics of Example 1 and Comparative Example 1 were simulated. The piezo resistor 10 is referred to as SmSe, and the piezoelectric substance 12 is referred to as PMT-PT.

6 (a) and 6 (b) show the sizes used in the simulations of the first embodiment and the first comparative example, respectively. For simplicity, the source, drain, gate, and metal contacts are not shown. As shown in Fig. 6 (a), in the first embodiment, the piezoelectric body 12 applies pressure to the piezo resistor 10. The thickness I _PR (corresponding to the radius) of the piezo resistor 10 in the r direction to which the pressure is applied, and the thickness L _PE of the pi electrode 12 in the r direction. The thickness h _PR of the piezoresistor 10 in the z direction, and the thickness H _PE of the piezoelectric body 12 in the z direction. and the distance R _PE from the z axis to the center of the piezoelectric body 12 in the r direction. The area of the surface of the piezoelectric resistor 12 that applies pressure to the piezo resistor 10 (that is, the surface where the piezoelectric resistor 12 and the piezo resistor 10 face each other) is larger than the area a _PR with respect to the piezoresistor 10, ) Is defined as A _PE . is a _PR = _PR 2πI h _PR, a _PR 2πI A _PE = H _PE. Therefore, the area ratio a _PR / A _PE = h _PR / H _PE .

As shown in Fig. 6 (b), the direction in which the piezoelectric body 12 applies pressure to the piezoresistor 10 in Comparative Example 1 is referred to as x direction. The thickness I _PR of the piezo resistor 10 in the x direction, and the thickness L _PE of the piezoelectric body 12 in the x direction. The area a _PR of the piezoresistor 10 facing the piezoresistor 10 facing the piezoresistor 10 and the area A _PE of the piezoresistor 12 is referred to as an area _PE .

By specifying the parameter of the size as described above, it is possible to compare the first embodiment and the first comparative example.

First of all, a coefficient? Representing the ratio of the pressure P to the piezoresistor 10 with respect to the gate voltage V _G applied to the gate 18 of the embodiment 1 and the comparative example 1 was calculated. P =? _{V G.} The larger coefficient? Indicates that the pressure is efficiently applied to the piezoresistor 10.

Figs. 7 (a) and 7 (b) are diagrams showing α for L _PE in Example 1 and Comparative Example 1, respectively. I _PR was fixed at 3 nm. A plurality of solid lines change a _PR / A _PE from 0.2 to 1.0 in 0.2 steps in the direction of the arrow. The drawings for Example 1 and Comparative Example 1 are also shown below. As shown in Fig. 7 (a), when a _PR / A _PE is small,? Is large. α does not depend much on L _PE . As shown in FIG. 7 (b), when a _PR / A _PE is small,? Is large. α becomes smaller as L _PE becomes larger.

Figs. 8 (a) and 8 (b) are diagrams showing α for I _PR in Example 1 and Comparative Example 1, respectively. L _PE was fixed at 40 nm. As shown in FIG. 8 (a), when a _PR / A _PE is small,? Is large. If I _PR is smaller, α is larger. As shown in FIG. 8 (b), when a _PR / A _PE is small,? Is large. If I _PR is smaller, α is larger.

Figure 7 (a) and 8 (a) and Fig. 7 (b), and when compared to 8 (b), for _{example, L PE = 40㎚, I PR} = 3㎚ and a _PR / A _PE = 0.4, the? Value in Example 1 is twice as large as that in Comparative Example 1. As described above, in the first embodiment, the pressure can be efficiently applied to the piezo resistor 10 as compared with the first comparative example. Thus, the current driving capability can be increased.

9 (a) and 9 (b) are diagrams showing drain current (I _D ) with respect to the drain voltage (V _D ) in Example 1 and Comparative Example 1, respectively. In Example 1, I _PR = 3 nm, L _PE = 40 nm, h _PR = 12 nm, H _PE = 30 nm and a _PR / A _PE = 0.4. In Comparative Example 1, I _PR = 3 nm, L _PE = 40 nm, a _PR = 100 nm ² , A _PE = 250 nm ² and a _PR / A _PE = 0.4. A plurality of solid lines indicate that the gate voltage (V _G ) is applied from 0 V to 0.2 V in 0.01 V steps.

As shown in Figs. 9 (a) and 9 (b), the drain current I _D of the first embodiment is three times larger than that of the first comparative example. As described above, in Example 1, the current driving capability is three times or more larger than that in Comparative Example 1.

Subthreshold slope S was then calculated. When the subthreshold slope S is small, the leakage current when the piezoresistor 10 is turned off by the gate 18 becomes small.

10 (a) and 10 (b) are _views showing S for L _PE in Example 1 and Comparative Example 1, respectively. I _PR was fixed at 3 nm. As shown in Fig. 10 (a), when a _PR / A _PE is small, S is small. S decreases with decreasing L _PE . As shown in Fig. 10 (b), when a _PR / A _PE is small, S is small. If L _PE is small, S is small.

11 (a) and 11 (b) are diagrams showing S for I _PR in Example 1 and Comparative Example 1, respectively. L _PE was fixed at 40 nm. As shown in Fig. 11 (a), when a _PR / A _PE is small, S is small. I _PR is small and S is small. As shown in Fig. 11 (b), when a _PR / A _PE is small, S is small. I _PR is small and S is small.

Figure 10 (a) and Figure 11 (a) and FIG. 10 (b), and when compared to 11 (b), for example, _{L PE = 40㎚, I PR =} 3㎚, a PR / A PE = 0.4 In Example 1, S is about 50 as compared with Comparative Example 1, which is lower than the threshold value (60 mV / decade) of the MOSFET at room temperature. On the other hand, S of Comparative Example 1 is about 100, which is twice as large as that of Example 1. As described above, in Embodiment 1, the subthreshold characteristic can be made steep as compared with Comparative Example 1. [ Therefore, the leakage current at the time of off can be suppressed.

From the viewpoint of? and S, it is preferable that a _PR / A _PE is small. For example, a _PR / A _PE is preferably smaller than 1, and more preferably about 0.6 or smaller.

Next, the oscillation frequency of the ring oscillator constituted by the inverter of five stages was calculated. The inverter was a complementary inverter using p-channel PET and n-channel PET. Figs. 12 (a) to 12 (c) are diagrams showing the output voltage versus time of the ring oscillator. Fig. Fig. 12 (a) shows the calculation results of the PET of Example 1. Fig. In the calculated PET, I _PR = 3 nm, L _PE = 10 nm, h _PR = 6 nm, H _PE = 30 nm and a _PR / A _PE = 0.2. The power supply voltage V _DD is 0.2V. Since the mechanical resonance phenomenon in response to the voltage application of the piezoelectric body 12 affects the oscillation frequency of the ring oscillator, the calculation is carried out by introducing this effect. Fig. 12 (b) and Fig. 12 (c) show calculation results in the case of using a FinFET of a 16 nm node, and power supply voltages V _DD = 0.5 V and 0.2 V, respectively.

As shown in Fig. 12 (a), the oscillation frequency is about 60 GHz even when V _DD = 0.2 V in the first embodiment. As shown in Fig. 12 (b), the FinFET has an oscillation frequency of about 25 GHz at V _DD = 0.5V. As shown in Fig. 12 (c), at V _DD = 0.2 V, the oscillation frequency is about 1.3 GHz. As described above, even if a FinFET, which is one of the fastest transistors currently operating, is used, the operation speed is drastically degraded if V _DD is reduced. On the other hand, in Embodiment 1, since the driving current capability is large, the oscillation frequency is high even if V _DD is small. There is a possibility that an oscillation frequency of about 100 GHz can be realized by V _DD = 0.2 V by optimizing the structure.

According to the first embodiment, the piezoelectric body 12 is provided so as to surround the piezoresistor 10. By applying a voltage to the gate 18, the piezoelectric body 12 applies pressure to the piezo resistor 10. As a result, the support structure is not required to be used as compared with Comparative Example 1. 7 (a) to 8 (b), pressure can be applied to the piezo resistor 10 with high efficiency as compared with Comparative Example 1. [ Therefore, the current driving capability can be increased. 10 (a) to 11 (b), the subthreshold characteristic can be improved as compared with Comparative Example 1. [ The piezoresistor 10 is turned into a metal phase by the pressure, so the on resistance is very low. Therefore, high-speed operation becomes possible even at a low power supply voltage (for example, 0.2 V or less) as shown in Fig. 12 (a).

1, the gate 18, the source 14, and the drain 16 are stacked in this order. Therefore, when a carrier flows from the source 14 toward the drain 16 And the case where the carrier flows from the drain 16 toward the source 14 is not equivalent (the current is different). As described above, the source 14 and the drain 16 are not symmetrical with respect to the gate 18. Therefore, when the source 14 and the drain 16 are interchanged to obtain the same characteristics, the voltage applied to the gate 18 is changed. Therefore, when the source 14 and the drain 16 are interchanged, the characteristics largely change.

In the first embodiment, the device structure can be configured such that the direction of the source 14 and the drain 16 with respect to the center of the channel is symmetrical. Since the source 14 and the drain 16 are equivalent to the gate 18, when the same voltage is applied to the gate 18 even when the source 14 and the drain 16 are interchanged, the same characteristics are obtained . Thus, even if the source 14 and the drain 16 are interchanged, the characteristics are hardly changed.

Example 2

Embodiment 2 is an example of a power gating circuit using the PET of Embodiment 1 as a power switch. 13 (a) and 13 (b) are block diagrams of an electronic circuit according to the second embodiment. As shown in Fig. 13 (a), the power gating circuit 100a has a p-channel PET 30b and a power domain circuit 32 as a power switch. The power domain circuit 32 is provided between the ground (GND), which is two power sources, and the power source V _DD . Power domain circuit 32 is supplied with power from ground (GND) and power supply V _DD . And a p-channel PET 30b is provided between the circuit 32 and the power supply V _DD . The source of the PET 30b is connected to the power supply V _DD and the drain thereof is connected to the circuit 32. [ A signal for controlling the power supplied to the circuit 32 is input to the gate. The node between the PET 30b and the circuit 32 becomes a virtual V _DD . The voltage of the potential difference between the virtual V _DD and the ground (GND) is applied to the circuit 32.

As shown in Fig. 13 (b), the power gating circuit 100b has an n-channel PET 30a and a power domain circuit 32 as a power switch. An n-channel PET 30a is provided between the ground (GND) and the circuit 32. The source of the PET 30a is connected to the ground GND and the drain thereof is connected to the circuit 32. [ A signal for controlling the power supplied to the circuit 32 is input to the gate. The node between the PET 30a and the circuit 32 becomes a virtual GND. The voltage of the potential difference between the power supply V _DD and the virtual GND is applied to the circuit 32. The PETs 30a and 30b are the transistors according to the first embodiment.

According to the second embodiment, the circuit 32 is connected between the power supply V _DD (first power supply) and the ground (GND) (second power supply). The source of the PET 30a or the PET 30b as the power switch is connected to the power supply V _DD or the ground (GND), and the drain is connected to the circuit 32. A signal for blocking power supplied to the circuit 32 is input to the gate. This signal is a signal that turns on or off the PET 30a or PET 30b.

Thus, in the power gating circuit of the second embodiment, the PET 30a or the PET 30b is used for the power switch of the power domain circuit. The on-resistance of the PET 30a or the PET 30b is low in metal. As a result, the voltage drop in the power switch can be suppressed to a very low level. 13 (a), the potential difference between the virtual power supply V _DD and the ground (GND), the potential difference between the power supply V _DD and the virtual ground (GND) in the power domain circuit 32, ) Can be easily increased. Therefore, the circuit performance of the power domain circuit 32 can be kept high. Therefore, a higher circuit performance can be obtained as compared with the case where a general MOSFET is used for a power switch. Further, the voltage drop can be concentrated on the power switch when the power supply is cut off, due to the cutoff characteristics of the PET 30a or the PET 30b due to the abrupt subthreshold characteristic and the large on / off ratio. Therefore, leakage of the power domain circuit 32 at the time of power shutdown can be suppressed to be small. Further, if the PET 30a or the PET 30b is formed in the multilayer wiring layer, the area overhead due to the power switch can be substantially eliminated. The power domain circuit 32 may be composed of conventional CMOS or PET (including complementary PET).

Example 3

Example 3 is an example in which PET according to Example 1 is used in a power switch of a nonvolatile bistable circuit. 14 is a circuit diagram of an electronic circuit according to the third embodiment. As shown in Fig. 14, the memory cell 101 has a bistable circuit 40 and nonvolatile elements MTJ1 and MTJ2 (nonvolatile memory element). The bistable circuit 40 voluntarily stores data. The nonvolatile elements MTJ1 and MTJ2 store the data stored in the bistable circuit 40 in a non-volatile manner and restore the data stored in the non-volatile state to the bistable circuit 40. [ The nonvolatile elements MTJ1 and MTJ2 are, for example, ferromagnetic tunnel junction elements.

The bistable circuit 40 has inverters 42 and 44. The inverter 42 has a p-channel FET m1 and an n-channel FET m2. The inverter 44 has a p-channel FET m3 and an n-channel FET m4. The inverter 42 and the inverter 44 are connected in a ring shape. The bistable circuit 40 is connected between the power supply V _DD and the ground. The power source V _DD is connected to the sources of the FETs m1 and m3, and the ground is connected to the sources of the FETs m2 and m4. The PET 30 (p-channel) which is a power switch is connected in series between the source of the FETs m1 and m3 and the power supply V _DD . The power supplied to the bistable circuit 40 can be cut off by turning off the PET 30.

The nodes to which the inverter 42 and the inverter 44 are connected are nodes Q and QB, respectively. The node Q and the node QB are mutually complementary nodes. The nodes Q and QB are connected to the input / output lines D and DB via the FET m5 and the FET m6, respectively. The gates of the FET m5 and the FET m6 are connected to the word line WL. Writing and reading of data to the bistable circuit 40 is performed in the same manner as in the conventional SRAM.

The FET m7 and the nonvolatile element MTJ1 are connected in series in the path 66 between the node Q and the control line CTRL and the node QB and the control line (N-channel) FET m8 and the nonvolatile element MTJ2 are connected in series in the path 66 between the non-volatile element MTJ1 and the non-volatile element MTJ2. One of the source and the drain of the FETs m7 and m8 is connected to the nodes Q and QB and the other of the source and the drain is connected to the nonvolatile elements MTJ1 and MTJ2. The gates of the FETs m7 and m8 are connected to the switch line SR. The FETs m7 and m8 may be connected between the nonvolatile elements MTJ1 and MTJ2 and the control line CTRL, respectively.

The storing operation of data from the bistable circuit 40 to the nonvolatile elements MTJ1 and MTJ2 is performed by turning the control lines CTRL to the high level and the low level in the ON state of the FETs m7 and m8. After the data is stored in the nonvolatile elements MTJ1 and MTJ2, the PET 30 is turned off. Thereby, power is not supplied to the bistable circuit 40, so that power consumption can be reduced.

The restoring operation of the data from the nonvolatile elements MTJ1 and MTJ2 to the bistable circuit 40 turns on the PET 30 with the control line CTRL set to the low level and the power is supplied to the bistable circuit 40 .

In the third embodiment, the nonvolatile elements MTJ1 and MTJ2 may be replaced with a ferromagnetic tunnel junction element, a variable resistance element used in a giant magnetoresistive (GMR) element, a ReRAM (Resistance Random Access Memory), or a PRAM The phase change element used can be used. The PET 30, which is a power switch, may be provided between the ground and the bistable circuit 40 as shown in Fig. 13 (b) of the second embodiment. In this case, PET is an n-channel PET and the FETs (m7 and m8) are p-channel. The number of nonvolatile elements is one, and a nonvolatile element may be connected between one node of the bistable circuit 40 and the control line.

An example of a master-slave flip-flop circuit will be described as a modification of the third embodiment. 15 is a circuit diagram of an electronic circuit according to a modification of the third embodiment. As shown in Fig. 15, the memory circuit 102 includes a D-latch circuit 102a and a D-latch circuit 102b. D latch circuit 102a includes a bistable circuit 40, pass gates 72 and 73, nonvolatile elements MTJ1 and MTJ2, and FETs m7 to m9. The pass gate 73 and the FET m9 are connected in parallel in the ring of the bistable circuit 40. [ The FET m7 and the nonvolatile element MTJ1 are connected in series between the node Q and the control line CTRL in the bistable circuit 40. [ The FET m8 and the nonvolatile element MTJ2 are connected in series between the node QB and the control line CTRL in the bistable circuit 40. [ The node Q becomes the QB signal through the inverter 61. The node QB becomes the Q signal through the inverter 62. The node Q is connected to the D latch circuit 102b through the pass gate 72. [

The D latch circuit 102b includes a bistable circuit 50 and pass gates 70 and 71. [ In the bistable circuit 50, inverters 52 and 54 are connected in a ring shape. The inverter 52 has a p-channel FET m11 and an n-channel FET m12. The inverter 54 has a p-channel FET m13 and an n-channel FET m14. A pass gate 71 is connected to the ring of the bistable circuit 50. Data D is input to the bistable circuit 50 through the inverter 60 and the pass gate 70. The clock signal CLK becomes the clock CB through the inverter 63 and becomes the clock C through the inverter 64. [ The clocks CB and C are input to the respective pass gates 70 to 73. (P-channel) PET 30 as a power switch is connected between the bistable circuits 40 and 50 and the power supply V _DD .

In the modification of the third embodiment, the nonvolatile elements MTJ1 and MTJ2 may use a GMR element, a variable resistance element used for the ReRAM, or a phase change element used for the PRAM, in addition to the ferromagnetic tunnel junction element. The PET 30, which is a power switch, may be provided between the ground and the bistable circuit 40. In this case, PET is an n-channel PET and the FETs (m7 and m8) are p-channel. The number of nonvolatile elements is one, and a nonvolatile element may be connected between one node of the bistable circuit 40 and the control line.

A problem when a MOSFET is used as a power switch corresponding to the PET 30 shown in Fig. 14 or Fig. 15 will be described. During the store operation, since a current flows through the nonvolatile element (MTJ1 or MTJ2), the impedance between the power supply V _DD and the ground is greatly lowered. For this reason, when a MOSFET is used as a power switch, the voltage drop in the MOSFET becomes large. Thereby, sufficient voltage is not applied to the bistable circuit 40 and the nonvolatile elements MTJ1 and MTJ2. Therefore, stable operation becomes difficult. Therefore, when a normal MOSFET is used for a power switch, a MOSFET having a very large channel width (or a plurality of MOSFETs) is used in order to apply a sufficient voltage to the memory cell. Therefore, problems such as an increase in cell area, complication of layout, and deterioration in performance (in practice, a power switch of a sufficient size can not be used due to restriction of cell area) arises.

On the other hand, in the third embodiment and its modifications, the PET 30 according to the first embodiment is used for the power switch. As a result, the current driving capability of the PET 30 is much larger than that of a MOSFET (including a high-performance transistor such as a FinFET), so that it is easy to suppress the voltage drop by the power switch to a small level do. Therefore, stable operation of the memory cell can be realized simply by introducing the power switch. Therefore, when the PET 30 is used for a power switch, the power gating of the nonvolatile bistable circuit can be realized without increasing the cell area, complicating the layout, and deteriorating the performance (PET can be formed in the multilayer wiring layer) .

A nonvolatile bistable circuit having a nonvolatile element for nonvolatilely storing data of the bistable circuit 40, as in the third embodiment and its modifications, includes a power switch (not shown) for supplying power to the bistable circuit 40, Is referred to as PET (30). As a result, the power gating of the nonvolatile bistable circuit can be realized without increasing the cell area, complicating the layout, and deteriorating the performance. Further, since the leakage current when the PET 30 is turned off is small, the standby power consumption when the bistable circuit 40 is shut off can be suppressed.

In the third embodiment and its modifications, the FETs m1 to m14 may be a MOSFET or a PET. In the path 66, a large current is used in the store operation. Therefore, by using PET as the FETs m7 and m8, the storage operation can be performed at a low voltage. When the FETs m7 and m8 are made of PET, the structure of FIG. 16 (b) of Embodiment 4 described later can be adopted. In addition, a plurality of nonvolatile memory power switches can be constituted by one or a plurality of PETs. For example, a power switch can be constructed using a smaller number of PETs than the number of nonvolatile memory cells.

Example 4

Embodiment 4 is an example in which PET is used for a nonvolatile memory cell. 16 (a) is a circuit diagram of a nonvolatile memory cell according to a fourth embodiment, and FIG. 16 (b) is a cross-sectional perspective view. 16 (a), the nonvolatile memory cell 104 includes a nonvolatile element 80 and a PET (90). A nonvolatile element 80 and a source and a drain of the PET 90 are connected in series between the source line SL and the bit line BL. The gate of the PET 90 is connected to the word line WL. In the nonvolatile element 80, a nonmagnetic layer 84 is formed between the free layer 82 made of a ferromagnetic metal and the pinned layer 86. In the ferromagnetic tunnel junction device, the nonmagnetic layer 84 is a tunnel insulating film, and in the giant magnetoresistance (GMR) device, the nonmagnetic layer 84 is a metal layer. The free layer 82 and the pinned layer 86 may be reversed.

A metal layer 81, a free layer 82, a nonmagnetic layer 84, a pinned layer 86, and a metal layer 87 are successively laminated on the drain 16 of the PET 90, as shown in Fig. 16 (b) . As described above, the nonvolatile element 80 can be laminated on the PET 90.

Spin Transfer Torque Current In the nonvolatile element 80 of the current drive type like the magnetization reversal type ferromagnetic tunnel junction element, a current flows at the time of data update. Thus, the nonvolatile memory cell 104 is composed of the PET 90 and the nonvolatile element 80 as in the fourth embodiment. This makes it possible to realize a nonvolatile memory cell operable even at a low voltage such as 0.5 V or less. This is because the on-resistance of the PET 90 is low, and it is possible to drive a sufficient current necessary for data update even in low-voltage driving. By using a GMR element having a ferromagnetic metal / nonmagnetic metal / ferromagnetic metal structure with lower resistance, a driveable nonvolatile memory cell at a lower voltage can be realized. In addition to the ferromagnetic tunnel junction element and the giant magnetoresistive (GMR) element, the nonvolatile element 80 may use a variable resistance element used in the ReRAM or a phase change element used in the PRAM.

Example 5

The fifth embodiment is an example in which PET is used for the logic circuit. 17 (a) to 18 (f) are circuit diagrams showing an electronic circuit according to a fifth embodiment. As shown in Figs. 17A and 17B, the inverter circuit 91 for outputting the NOT signal Y of the signal A includes one n-channel PET 97a and one p-channel PET 97b ). As shown in Figs. 17C and 17D, the NAND circuit 92 for outputting the NAND signal Y multiplied by the signals A and B includes two n-channel PETs 97a and two p- And a channel PET (97b). As shown in Figs. 17 (e) and 17 (f), the NOR circuit 93 for outputting the NOR signal Y of the sum of the signals A and B includes two n-channel PET 97a and two p- PET (97b).

As shown in Figs. 18A and 18B, the XOR circuit 94 for outputting the exclusive-OR (XOR) signal Y of the signals A and B includes one n-channel PET 97a, one p- A PET (97b), an inverter circuit (91), and a pass gate (98). The pass gate 98 may be composed of an n-channel PET 97a and a p-channel PET 97b. 18 (c) and 18 (d), the circuit 95 for outputting the signal A as the signal Y in synchronization with the signal B can be constituted by the inverter circuit 91 and the pass gate 98 . As shown in Figs. 18 (e) and 18 (f), the circuit 96 for sequentially outputting signals A and B in synchronism with the signal S as a signal Y includes two inverter circuits 91 and two paths And a gate 98.

In the logic circuit according to the fifth embodiment, the dielectric polarization directions 22 of the piezoelectric body 12 in the PET 97a (first transistor) and the PET 97b (second transistor) complementary to each other are opposite to each other, A direction in which the piezoelectric body 12 applies stress to the piezoresistor 10 when a positive voltage is applied to the gate 18 and a negative voltage is applied to the gate electrode 18 and the PET 97b on the basis of the source 14 . By using such PETs 97a and 97b, the same logic as the CMOS logic circuit can be realized with the same circuit configuration. (For example, a 3-input NAND or a 3-input NOR, etc.) such as a NOT circuit, an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, an XOR circuit, an XNOR circuit, (E.g., AND-OR-INV (AOI) or OR-AND-INV (OAI)), various latch circuits, various flip-flop circuits (e.g., DFF, RSFF, JKFF or TFF) (MUX) or the like can be constituted.

In addition, the PET 97a and the PET 97b are the same size, so that the same current can be secured. Therefore, it is not necessary to change the size of the n-channel FET and the p-channel FET like a CMOS logic circuit. Therefore, wiring and layout when a logic circuit or the like is mounted can be facilitated, and a desired effect such as reducing the area occupied by the circuit or reducing the signal propagation delay can be expected.

1, it is not equivalent when a carrier flows from the source 14 to the drain 16 and when the carrier flows from the drain 16 to the source 14 . On the other hand, in the first embodiment, the direction from the source 14 to the drain 16 and the direction from the drain 16 to the source 14 are equivalent. Thus, the pass gates 98 can be formed using the PETs 97a and 97b.

Example 6

Example 6 is another example of PET. Figs. 19 (a) to 19 (c) are cross-sectional views of a transistor according to a sixth embodiment and modifications thereof. As shown in Fig. 19 (a), in the PET according to the sixth embodiment, the source 14 is provided on the surface in the -y direction of the piezoresistor 10 and the drain 16 is provided on the surface in the + y direction . The piezoelectric body 12 is provided on the surface of the piezo resistor 10 in the -x direction. A gate 18 is provided on the surface of the piezoelectric body 12 in the -x direction. The support structure 20 supports the piezoelectric body 12 and the piezoresistor 10. A metal contact layer having a small Young's modulus shown in the first embodiment may be formed between the source 14 and the piezo resistor 10 and between the drain 16 and the piezo resistor 10. The surface of the source 14 and the drain 16 opposite to the piezoelectric body 12 (surface in the + x direction) may be in contact with the support structure 20. [

The carrier conducts in the y direction within the piezoresistor 10. The piezoelectric body 12 applies pressure to the piezoresistor 10 from the x direction. The relationship between the voltage between the source 14 and the gate 18 and the voltage between the drain 16 and the gate 18 remains the same even when the source 14 and the drain 16 are interchanged. Therefore, it is possible to make the currents almost equal when the carrier flows from the source 14 to the drain 16 and when the carrier flows from the drain 16 to the source 14. As a result, when the source 14 and the drain 16 are interchanged, the characteristics of the PET can be equivalent. Therefore, for example, PET according to the sixth embodiment can be used for a pass gate.

As shown in Fig. 19 (b), in the PET according to the first modification of the sixth embodiment, a support body 21 is provided between the source 14 and the drain 16 and the support structure 20. The support 21 is made of a resin such as polyimide and has a Young's modulus smaller than that of the piezoelectric body 12 and the piezo resistor 10. [

In the sixth embodiment shown in Fig. 19A, a gap is formed between the source 14 and the drain 16 and the support structure 20. This makes it difficult to form the source 14 and the drain 16. Further, the source 14 and the drain 16 become structurally unstable.

19B, the source 14 and the drain 16 are stabilized because the support 21 supports the source 14 and the drain 16, as shown in Fig. 19 (b). When the Young's modulus of the support body 21 is sufficiently small, the pressure of the piezoelectric body 12 is almost applied to the piezoresistive element 10. The support body 21 may be made of a porous material such as porous silica and the support body 21 may be crushed to form a gap after the source 14 and the drain 16 are formed.

19 (c), in the PET according to the second modification of the sixth embodiment, the source 14 and the drain 16 are connected to the support structure 20. Also, the source 14 and the drain 16 are drawn out to be supported by the support structure 20. As a result, the source 14 and the drain 16 are stabilized. The sixth embodiment and its modifications may be used for the electronic circuits of the second to fifth embodiments. Even if the metal contact layer is formed between the source 14 and the piezo resistor 10 and between the drain 16 and the piezo resistor 10, if the Young's modulus of the metal contact layer is small, It does not interfere with the application of pressure to the gasket 10.

In the comparative example 1, since the source 14 and the drain 16 are stacked in this order, the gate bias is changed when the source 14 is the drain 16. Therefore, when the source 14 and the drain 16 are interchanged, the characteristics of the PET are changed.

The voltage between the source 14 and the gate 18 and between the drain 16 and the gate 18 is higher than the voltage between the source 14 and the drain 16, It is the same. Further, the shapes of the source 14 and the drain 16 can be almost equivalent. Therefore, even if the source 14 and the drain 16 are interchanged, the characteristics do not change. For this reason, it is preferable that the source 14 and the drain 16 have a substantially symmetrical structure with respect to the intermediate surface between the source 14 and the drain 16 in the piezoresistor 10, It is preferable that the piezoelectric body 12 and the gate 18 are formed to be substantially symmetrical with respect to the intermediate surface between the source 14 and the drain 16 in the piezoresistor 10. Further, even if the areas a _PR and A _PE are made different from each other for reasons such as making the area a _PR smaller than A _{PE in} order to improve? And S, the above characteristics are maintained. Therefore, even when the source 14 and the drain 16 are interchanged, the characteristics of the PET are hardly changed.

Example 7

Example 7 is another example of PET. FIG. 20A is a perspective sectional view of a transistor according to a seventh embodiment, and FIGS. 20B and 20C are cross-sectional views. The broken lines in the piezo resistors 10, 14 and 16 are lines dividing the upper portions 10a, 14a and 16a and the supports 10b, 14b and 16b virtually. 20A to 20C, a direction from the source 14 to the drain 16 in the Y direction, a direction orthogonal to the Y direction in the surface direction of the substrate 25 in the X direction, 25) is referred to as the Z direction.

The piezo resistor 10, the source 14, and the drain 16 are formed on the substrate 25. The piezo resistor 10 has an upper portion 10a and a support portion 10b. The upper portion 10a has a semi-cylindrical shape. A source 14 and a drain 16 are provided at both ends of the piezoresistor 10 in the Y direction. The source 14 has an upper portion 14a corresponding to the upper portion 10a of the piezo resistor 10 and a support portion 16a corresponding to the support portion 10b of the piezoresistor 10. The drain 16 has an upper portion 16a corresponding to the upper portion 10a of the piezo resistor 10 and a support portion 16b corresponding to the support portion 10b of the piezoresistor 10. The supports 10b, 14b and 16b support the tops 10a, 14a and 16a, respectively. The carrier conducts in the Y direction within the piezoresistor 10. A metal contact layer 15 is formed between the source 14 and the piezo resistor 10 and a metal contact layer 17 is formed between the drain 16 and the piezoresistor 10. The piezoelectric body 12 is provided so as to surround the piezoresistor 10. A gate 18 is provided around the piezoelectric body 12.

The polarization direction 22 of the piezoelectric substance 12 in the first type transistor of the seventh embodiment is the direction of the piezo resistor 10 from the gate 18. [ The polarization direction 22 of the piezoelectric substance 12 in the second type transistor is opposite to the direction of the arrow 22 in Figs. 20 (a) to 20 (c) to be. The polarization direction of the piezoelectric body 12 covering the support portion 10b is not shown. Other configurations are the same as those in the first embodiment, and description thereof is omitted.

21 (a) is a cross-sectional view of a transistor according to a modification 1 of the seventh embodiment, and Fig. 21 (b) is a cross-sectional view. 21A and 21B, the metal contact layers 15 and 17 are not formed, and the source 14 and the drain 16 directly contact the piezoresistor 10. The source 14 and the drain 16 are in contact with the piezoelectric body 12. The rest of the configuration is the same as that of the seventh embodiment, and a description thereof will be omitted.

22 (a) is a perspective sectional view of a transistor according to a modification 2 of the seventh embodiment, and Figs. 22 (b) and 22 (c) are sectional views. As shown in Figs. 22 (a) to 22 (c), the gates 18a and 18b are provided on both sides of the piezoelectric body 12 in the y direction. The polarization direction 22 of the piezoelectric body 12 is -y direction or y direction. The other configuration is the same as that of the first modification of the seventh embodiment, and a description thereof will be omitted. Further, the metal contact layers 15 and 17 may be formed similarly to the seventh embodiment. Further, the source 14 and the drain 16 may be in contact with the piezoelectric body 12. At this time, the source 14 and the drain 16 do not contact the gates 18a and 18b.

23 is a cross-sectional view of a transistor according to a modification 3 of the seventh embodiment. As shown in Fig. 23, the support portion 10b has a trapezoidal cross-sectional shape. Other configurations are the same as those of the seventh embodiment and its modification examples 1 and 2, and description thereof is omitted.

The piezoelectric body 12 may be provided so as to surround the piezoresistor 10 from a part of the direction orthogonal to the conduction direction (Y direction) of the carrier, as in the seventh embodiment and its modifications. Compared with the case where the piezoelectric body 12 is provided so as to surround the piezo resistor 10 from all directions orthogonal to the conductive direction of the carrier as in the first embodiment, .

The pressure of the piezoelectric body 12 is not efficiently applied to the piezoresistor 10 in the case where only the upper portion 10a of the piezo resistor 10 is formed on the substrate 25. [ Therefore, a support portion 10b (support) for supporting the upper portion 10a is provided. The upper surface of the piezo resistor 10 is a curved surface and the piezoelectric member 12 is formed so as to surround the upper surface of the upper portion 10a of the piezo resistor 10 and the side surface of the support portion 10b. As a result, the pressure is effectively applied to the upper portion 10a. The XZ cross-sectional shape of the upper portion 10a is described as an example, but the XZ cross-sectional shape of the upper portion 10a may be a semi-elliptical shape, a part of a circle, a part of an ellipse, or a machine room shape. The supporting portion 10b may not be the piezo resistor 10. [ It is preferable that the Young's modulus and Poisson's ratio of the support portion 10b are the same as those of the piezo resistor 10 in order to efficiently apply pressure to the piezo resistor 10. [ Therefore, the material of the supporting portion 10b is preferably the same as that of the piezo resistor 10. The material of the support portion 10b may be different from the material of the piezo resistor 10.

Further, the supporting portions 14b and 16b may not be the source 14 and the drain 16, respectively. When the supporting portions 14b and 16b are in contact with the piezoelectric body 12, the supporting portions 14b and 16b are preferably made of a material having a low Young's modulus. From the viewpoint of the efficiency of the manufacturing process, the supporting portions 14b and 16b are preferably made of the same material as the source 14 and the drain 16. When the metal contact layers 15 and 17 are formed, the metal contact layers 15 and 17 are formed between the upper portion 10a and the upper portion 14a and between the upper portion 10a and the upper portion 16a It is good. It is preferable that the gate electrode 18 or the piezoelectric body 12 and the gate electrode 18 are provided apart from the substrate 25 so as not to cause electrical conduction to the substrate 25. [ When the supporting portions 10b, 14b and 16b are made of different materials from the upper portions 10a, 14a and 16a, the supporting portions 10b, 14b and 16b may be formed by machining the upper surface of the substrate 25, for example. That is, the materials of the supports 10b, 14b, and 16b may be the same as the material of the substrate 25. [

When the height of the support portion 10b is zero or low, no pressure is efficiently applied to the top portion 10a. The height of the support portion 10b is preferably equal to or larger than the width of the upper portion 10a of the piezo resistor.

The polarizing direction 22 of the piezoelectric body 12 is set such that the piezoelectric body 12 is arranged in the direction in which the piezoelectric body 10 surrounds the piezoelectric body 10 or in the opposite direction 12) and the piezoresistor 10 and the opposite direction). In this case, it operates in the same manner as in Fig. 3 (a) to Fig. 4 (b) of the first embodiment. The polarization direction 22 of the piezoelectric body 12 may be the propagation direction of the carrier or the opposite direction as in the modification 2 of the seventh embodiment. In this case, the operation is similar to that of the modification of the first embodiment shown in Figs. 5 (a) to 5 (f). The metal contact layers 15 and 17 may or may not be formed. The same materials as those of the first embodiment can be used for the respective materials of the transistors in the seventh embodiment and its modifications. The substrate 25 may be, for example, a silicon substrate. Transistors of the seventh embodiment and its modifications can be used for the electronic circuits of the second to fifth embodiments and its modifications.

In the simulations shown in Figs. 7 (a) to 11 (b), the pressure distribution in the piezoresistor 10 is considered to be substantially constant. This is true when the channel length of the piezoresistor 10 is short, or in the modified example of the first embodiment and the second modified example of the seventh embodiment. This simulation is called simulation 1. However, in Embodiments 1 and 7 and Modification 1 thereof, for example, when the channel length is increased to some extent or more, the pressure is gradually applied to the piezoresistor 10. Thus, the structure shown in Fig. 6 (a) was used and the pressure applied to the piezoresistor 10 gradually became a simulation. This simulation is called simulation 2. Each simulation can be applied to Embodiment 7 by using the effective cross-sectional area of the upper portion 10a of the piezoresistor 10.

FIG. 24A is a diagram showing drain characteristics using simulation 2, and FIG. 24B is a diagram showing drain characteristics obtained by comparing simulation 1 and simulation 2. FIG. I _PR = 3 nm, L _PE = 40 nm, h _PR = 12 nm, H _PE = 30 nm and a _PR / A _PE = 0.4. The gate voltage V _G is 0.02 V steps from 0 V to 0.2 V in the direction of the arrow. As shown in Fig. 24 (a), when the drain voltage V _D becomes high, the drain current I _D becomes saturated.

As shown in Fig. 24 (b), Simulation 1 and Simulation 2 coincide with each other with respect to the low drain voltage (V _D ). However, in the simulation 1, the drain current I _D does not saturate when the drain voltage V _D becomes high. In the simulation 2, the drain current I _D saturates. As described above, in the first and seventh embodiments, there is a possibility that the drain current I _D is saturated. The drain current I _D does not saturate in the structure similar to the modification of the embodiment 1, the modification example 2 of the embodiment 7, and the comparison example 1. Also in the sixth embodiment and its modifications, there is a possibility that the drain current I _D is saturated.

Next, transfer characteristics were simulated for the case of using the transistor of Example 7 as the PET 97a and 97b of the inverter circuit 91 shown in Fig. 17 (a) and 17 (b) . 25 is a diagram showing transfer characteristics of an inverter circuit. As shown in Fig. 25, in the simulation 2, the output voltage Vout is steeply changed with respect to the change of the input voltage Vin compared with the simulation 1. [

25, the butterfly curve in the bistable circuit in which the inverter circuit 91 is connected in the form of a loop is simulated. Figure 26 (a) and 26 (b) is a node (QB) for the voltage (V _Q) of the figure, and the node (Q) representing the butterfly curve of the bistable circuit in each simulated first and Simulation 2 Voltage (V _QB ). The dashed line represents the maximum square entering the aperture of the butterfly curve. The length of one side of this square is the noise margin. As shown in Fig. 26 (a), when the drain current is not saturated as in simulation 1, the noise margin is about 55 mV. As shown in Fig. 26 (b), when the drain current is saturated as in Simulation 2, the noise margin is about 77 mV. In this simulation example, the noise margin when the drain current saturates is 1.4 times that when the drain current is not saturated.

The polarization direction of the piezoelectric body 12 is set to the direction from the piezo resistor 10 to the gate 18 or from the gate 18 to the piezo resistor 10 as in the first and seventh embodiments. As a result, the drain current can be saturated as in the simulation 2. Therefore, the noise margin can be increased as shown in Fig. 26 (b).

Example 8

27 is a block diagram of an electronic circuit according to the eighth embodiment. In the electronic circuit, the microprocessor 110 has a power management unit 112, a nonvolatile SRAM array 114, and a power domain 116. The nonvolatile SRAM array 114 has a power switch 120. The power domain 116 has a power switch 120 and a nonvolatile flip flop 118. The power management unit 112 uses the power switch 120 of the non-volatile SRAM array 114 and the power domain 116 and powers off or de-energizes the power supplied to the non-volatile SRAM array 114 and power domain 116 Can be reduced.

The memory cell described in Embodiment 3 or Embodiment 4 can be used for the nonvolatile SRAM array 114. [ As a result, the nonvolatile SRAM array 114 can be driven at a low voltage. In addition, for example, when the power supply is interrupted, nonvolatile memory can be stored. The flip-flop circuit described in the modification of the third embodiment can be used as the nonvolatile flip-flop 118 in the power domain 116. [ As a result, the nonvolatile flip-flop 118 can be driven with a low voltage. Further, for example, when the power supply is interrupted, nonvolatile memory can be stored. As the logic circuit in the power domain 116, the logic circuit described in the fifth embodiment can be used. As a result, low-voltage driving is possible, and high-speed operation is possible as compared with a general CMOS circuit. The power switch described in the second embodiment can be used as the power switch 120. [ As a result, the voltage drop by the power switch 120 can be suppressed to a low level. Thus, the nonvolatile power gating of the low-voltage drive logic system, which is closer to the ideal state, becomes possible.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

10: Piezo resistor 10a:
10b: Support part 12:
14: source 16: drain
18: gate 22: dielectric polarization direction
30, 90: PET 32: circuit
80: Nonvolatile element

Claims (16)

A piezoresistive element through which the carrier conducts,
A source for injecting the carrier into the piezo resistor,
A drain for receiving the carrier from the piezo resistor,
A piezoelectric body provided so as to surround the piezo resistor and applying pressure to the piezoresistor,
And a gate for applying a voltage to the piezoelectric body so that the piezoelectric body applies pressure to the piezo resistor. The method according to claim 1,
The gate is provided so as to surround the piezoelectric body,
Wherein the piezoelectric body is dielectric-polarized in a direction from the piezo resistor to the gate or in a direction from the gate to the piezoresistor. The method according to claim 1,
The plurality of gates are provided in a direction parallel to the conduction direction of the carrier conducting the channel in the piezoresistor,
Wherein the piezoelectric body is dielectric-polarized in the parallel direction. 4. The method according to any one of claims 1 to 3,
Wherein the piezoelectric body is provided so as to surround the piezo resistor from all directions orthogonal to the conduction direction of the carrier. 4. The method according to any one of claims 1 to 3,
Wherein the piezoelectric body is provided so as to surround the piezo resistor from a direction orthogonal to the conduction direction of the carrier. 4. The method according to any one of claims 1 to 3,
And a support member formed on the substrate and supporting the piezo resistor,
The upper surface of the piezo resistor is a curved surface,
And the piezoelectric body surrounds the upper surface of the piezo resistor and the side surface of the support body. The method according to claim 6,
And the height of the support is larger than the width of the piezo resistor. 8. The method according to claim 6 or 7,
Wherein the material of the support is the same as the material of the piezo resistor. 8. The method according to claim 6 or 7,
Wherein the material of the support is different from the material of the piezo resistor. A piezo resistor which conducts carriers in a first direction,
A source for injecting the carrier into the piezo resistor,
A drain for receiving the carrier from the piezo resistor,
A piezoelectric body for applying pressure to the piezo resistor from a second direction intersecting the first direction,
And a gate for applying a voltage to the piezoelectric body so that the piezoelectric body applies pressure to the piezo resistor. 11. The method according to any one of claims 1 to 10,
Wherein the source and the drain are symmetrical with respect to a plane between the source and the drain in the piezoresistor,
Wherein the piezoresistor, the piezoelectric body and the gate are symmetrical with respect to the intermediate surface, respectively. A circuit connected between the first power source and the second power source,
The transistor according to any one of claims 1 to 11, wherein either the source or the drain is connected to the first power source, and the other of the source and the drain is connected to the power source terminal of the circuit And a transistor for inputting a signal for interrupting power supplied to said circuit to said gate. 13. The method of claim 12,
A bistable circuit for storing data,
And a nonvolatile element for storing the data stored in the bistable circuit in a nonvolatile manner and restoring the nonvolatile stored data in the bistable circuit,
Wherein the circuit is the bistable circuit. 14. The method of claim 13,
And said nonvolatile element is connected between a node in said bistable circuit and a control line. A nonvolatile element,
12. The electronic circuit according to any one of claims 1 to 11, comprising a nonvolatile memory cell including the transistor in which the source or the drain is connected in series with the nonvolatile element. 12. A transistor according to any one of claims 1 to 11, comprising first and second transistors complementary to each other,
Wherein a dielectric polarization direction of the piezoelectric body of the first and second transistors is opposite to each other and when a positive voltage or a negative voltage is applied to the gate on the basis of the source, the piezoelectric body can apply pressure to the piezo resistor Direction.

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