KR20160118555A - C-band CMOS Bidirectional Amplifier Using Switchable Matching Network - Google Patents

Abstract

Provided is a C-band CMOS bidirectional amplifier using a switchable matching circuit configured based on a common gate amplifier structure capable of switching a drain and a source of a transistor by switching a supplied voltage, wherein a bidirectional amplifier is manufactured by using a CMOS 65-nm process to simplify a system. The C-band CMOS bidirectional amplifier using a switchable matching circuit comprises: a central transmission path formed in a horizontal direction with a first port and a second port as a center; an amplification terminal formed between the first port and the second port and performing bidirectional amplification using a common gate circuit; and first and second conversion matching terminals formed between the first port and the amplification terminal and between the second port and the amplification terminal and converting the direction of a current to correspond to the amplification direction according to the directivity of the amplification terminal.

Description

[0001] C-band CMOS Bidirectional Amplifier Using Switchable Matching Network [

The present invention relates to a C-band CMOS bidirectional amplifier using a conversion matching circuit, and more particularly, to a bidirectional amplifier using a conventional HEMT process, which is easier to integrate and less expensive to manufacture, and a conversion matching circuit can automatically convert without bias adjustment To a C-band CMOS bidirectional amplifier.

Power amplifiers are widely used in communication systems, e.g., wireless telephone base stations and wireless telephones. In a wireless telephony system, a power amplifier typically amplifies a high frequency signal for transmission.

The main consideration in designing a power amplifier is its efficiency. In general, high efficiency is required to reduce the amount of power dissipated as heat. Moreover, the amount of power available in various applications such as satellite and portable wireless telephones may be limited. It is therefore important to increase the efficiency in the power amplifier, which is intended to increase the operating time or increase the capacity of the satellite or portable radiotelephone.

As the wireless communication system rapidly increases, the system integrated circuit is simplified, the weight is reduced, the performance efficiency is important, and a circuit capable of bi-directional amplification is being manufactured.

In particular, existing bi-directional amplifiers are mainly made of 3-5 family transistors. However, it has a problem that it is expensive to manufacture and is not easy to integrate with other circuits.

Published Japanese Patent Application No. 10-2001-0052234 (published Jun. 25, 2001)

Therefore, in order to solve the above-mentioned problems, the present invention has been made to provide a time-division bi-directional amplifier using a CMOS 65-nm process for simplifying the system and to change the drain and source of the transistor The present invention provides a C-band CMOS bidirectional amplifier using a conversion matching circuit configured based on a common gate amplifier structure capable of performing a C-band CMOS amplification.

Other objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, there is provided a C-band CMOS bidirectional amplifier using a conversion matching circuit. The C-band CMOS bidirectional amplifier includes a first port and a second port, An amplification stage which is configured between the first port and the second port and is capable of performing bi-directional amplification in a time-sharing manner by using a common gate circuit; and an amplification stage which is formed between the first port and the amplification stage, and between the second port and the amplification stage, And a first and second conversion matching stage for converting the direction of the matching current.

Preferably, the amplifier stage is connected to a DC control switch (DPDP switch) in a common gate structure, a first conversion matching stage and a second conversion matching stage are respectively connected to the drains, and first and second transistors M _A1) (characterized in that is comprises a first inductor (L _inter) which is connected between the M _A2) and said first and second transistors (M _{A1) (A2} M) increase the power gain.

Preferably, a resistor R _A and a capacitor C _ACG connected in parallel to each other are formed between the amplifier stage and the direct current control switch (DPDP switch) in a multi-stage common gate structure.

Preferably the first transform matching stage or second conversion matching stage is a third transistor (M _W1), and a power source (V _sw for applying a predetermined voltage to the gate of the third transistor (M _W1) that this amplifier stage and a drain connected ), and the third transistor (M _W1) and the power (V _sw) resistor connected in series between the (R _sW) and, on one side is a ground power supply (V _sw) and a resistor (R _sW) and connected in parallel a first capacitor (C _ACG) which with said third transistor in series between the source of the second inductor (L _SWIT1) and said first port and said transistor (M _W1) connecting the source and the drain of the (M _W1) a second capacitor (C ₁₎ through to, and the third transistor (M _W1) source and a second capacitor connected in parallel to the (C ₁₎ converting the matching stage (200a) to control the direction for the amplified direction of the (SPDP switch), a DC control switch (SPDP switch) and a DC control switch 3. The source of the transistor a first inductor (L ₁₎ and the direct-current control switch (SPDP switch) (400a) and the third transistor (M _W1) connected in series in the connection line connected with the source of the (M _W1) and And a third capacitor (C _ACG ) connected in parallel to a connection line to be connected.

Preferably, a constant voltage is applied to the gate of the third transistor M _W1 at a voltage of 1.3 V through a power source V _sw , and a voltage of a resistance connected in series between the third transistor M _W1 and the power source V _sw (R _SW ) has a resistance of 20 Kohm.

The C-band CMOS bidirectional amplifier using the conversion matching circuit according to the present invention as described above has the following effects.

First, this structure has an advantage that the input and output portions of the circuit can be designed symmetrically with respect to each other, so that both gains and phases can be equalized.

Second, it is easy to apply to a high-frequency phased array system, and has a small chip size by utilizing a structure capable of reusing a transistor.

Third, it is easier to integrate and less expensive to manufacture than the conventional HEMT process, and the conversion matching circuit can perform automatic conversion without bias control.

1 is a circuit diagram showing a configuration of a C-band CMOS bidirectional amplifier using a conversion matching circuit according to an embodiment of the present invention.
Fig. 2 is a graph showing the S parameter and the noise figure characteristic in the forward direction in the circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of Fig. 1. Fig.
Fig. 3 is a graph showing the reflection loss characteristic in the forward direction in the circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of Fig. 1
Fig. 4 is a graph showing the S parameter and the noise figure characteristic in the reverse direction in the circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of Fig. 1
Fig. 5 is a graph showing the reflection loss characteristic in the reverse direction in the circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of Fig. 1
Fig. 6 is a graph showing linearity characteristics in a circuit diagram showing a configuration of the C-band CMOS bidirectional amplifier of Fig. 1

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of a C-band CMOS bidirectional amplifier using the conversion matching circuit according to the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It is provided to let you know. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and are not intended to represent all of the technical ideas of the present invention. Therefore, various equivalents It should be understood that water and variations may be present.

1 is a circuit diagram showing a configuration of a C-band CMOS bidirectional amplifier using a conversion matching circuit according to an embodiment of the present invention.

As shown in Fig. 1, a central transmission line is formed in the horizontal direction around the first port and the second port, and is configured between the first port and the second port, and is used for time-division bi- directional amplification And an amplification stage 100 which is provided between the first port and the amplification stage 100 and between the second port and the amplification stage 100 so as to direct the direction of the current corresponding to the amplification direction according to the directionality of the amplification stage 100 And a first conversion matching stage 200a and a second conversion matching stage 200b.

At this time, the amplifier stage 100 is connected to the DC control switch (DPDP switch) 300 in a common gate structure, the first conversion matching stage 200a and the second conversion matching stage 200b are connected to the drain, A first inductor L _inter connected between the first and second transistors M _A1 and M _A2 and connected to the first and second transistors M _A1 and M _A2 to increase the power gain, .

As described above, the amplifier stage 100 uses a structure in which the amplification direction can be easily changed by changing the bias using a common gate circuit. And the first inductor (L _inter ) in the middle of the amplification stage is added to increase the power gain which is a disadvantage of the common gate.

In this case, a resistor R _A and a capacitor C _ACG connected in parallel to each other are formed between the amplifier stage 100 and the DC control switch (DPDP switch) 300 in a multi-stage common gate structure.

The first conversion matching stage 200a includes a third transistor M _{W1 to} which an amplification stage and a drain are connected, a power source V _sw to apply a constant voltage to a gate of the third transistor M _W1 , a third transistor (M _W1) and the power (V _sw) resistor connected in series between the (R _SW) and, on one side is a ground power supply (V _sw) and a resistor (R _SW) a first capacitor connected in parallel with (C _ACG) and the third transistor of claim in which the second inductor (L _SWIT1) and, connected in series between the source of the first port and the transistors (M _W1) connecting the source and the drain of the (M _W1) second capacitor (C ₁₎ and the third transistor are connected in parallel between the source and the second capacitor (C ₁₎ of the (M _W1) direct current to change the conversion matching stage (200a) to control the direction for the amplification direction A control switch (SPDP switch) 400a, a DC control switch (SPDP switch) 400a, Connected to the source of the first inductor (L ₁₎ and the direct-current control switch (SPDP switch) (400a) and the third transistor (M _W1) connected in series in the connection line connected with the source of the (M _W1) And a third capacitor (C _ACG ) connected in parallel to the connection line.

For reference, the second conversion matching stage 200b has the same configuration as the first conversion matching stage 200a, and a description thereof will be omitted. In addition, only functions of the first conversion matching stage 200a will be described below, and redundant description of the second conversion matching stage 200b having the same function will be omitted.

With such a configuration, the first conversion matching stage 200a is adjusted in accordance with the directionality of the amplification stage 100. That is, when a predetermined voltage of Vsw is applied to the gate of the third transistor M _{W1 in} the first conversion matching stage 200a and the directionality of the SPDT switch 400a is adjusted, the conversion matching stage 200a matching the amplification direction You can change it freely.

Also, the multi-stage common gate structure composed of the resistor R _SW and the first capacitor C _ACG has a feature that the input impedance is small and the output impedance is large. And a conversion matching circuit capable of having a conjugate value of the input impedance and the output impedance when determining the amplification direction using the direct current control switch (SPDP switch) 400a.

Accordingly, when a constant voltage is applied to the transistor of the conversion matching circuit, switching is automatically performed as the DC voltage of the drain and the source is converted.

The conversion matching circuit is configured to have a minimum AC current loss using the second inductor L _SWIT1 and the third transistor M _W1 (Deep-n-well transistor). Accordingly, when the third transistor M _W1 is turned on, it operates like a short, and conversely, when the transistor is turned off, it operates like an inductor.

For reference, the third transistor applying a constant voltage to 1.3V, the gate through the power (V _sw) of the (M _W1) haejugo, the third transistor (M _W1) and the power (V _sw) which is connected in series between the The resistor (R _SW ) is preferably connected to a large resistance of 20 Kohm.

를 나타내는데, 이는 현재까지 CMOS로 설계된 양방향 증폭기 회로 중 크기가 가장 작다는 장점을 보여준다.Such a structure enables the input and output sections of the circuit to be designed symmetrically with respect to each other, so that the gain and phase in both directions can be the same. It is easy to apply to a high-frequency phase shifting system, and has a small chip size by utilizing a structure capable of reusing a transistor. The size of the chip actually implemented is 470 x 544

Which shows the advantage that the size of the bidirectional amplifier circuit designed to CMOS is the smallest to date.

It is easy to apply to a high-frequency phased array system, and has a small chip size by utilizing a transistor reusable structure.

FIG. 2 is a graph showing S parameter and noise figure characteristics in a forward direction in a circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of FIG. 1. FIG.

As shown in Fig. 2, it can be seen that the maximum gain is 9.8 dB, the isolation is 19 dB or more, and the minimum noise figure is 7.2 dB in forward operation.

FIG. 3 is a graph showing the reflection loss characteristics in the forward direction in the circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of FIG.

As shown in Fig. 3, it can be seen that the reflection loss in the forward direction operation is about -7 dB.

FIG. 4 is a graph showing the S-parameter and the noise figure characteristic in the reverse direction in the circuit diagram showing the configuration of the C-band CMOS bidirectional amplifier of FIG.

As shown in FIG. 4, it can be seen that the maximum gain is 9.5 dB, the isolation is 21 dB or more, and the minimum noise figure is 7.2 dB in the reverse operation.

FIG. 5 is a graph showing a reflection loss characteristic in a reverse direction in a circuit diagram showing a configuration of a C-band CMOS bidirectional amplifier of FIG. 1. FIG.

As shown in Fig. 5, it can be seen that the insertion phase difference is < 6 [deg.], So that the forward and reverse characteristics are almost identical.

FIG. 6 is a graph showing linearity characteristics in a circuit diagram showing a configuration of the C-band CMOS bidirectional amplifier of FIG. 1; FIG.

As shown in Fig. 6, it can be seen that the output P1dB of 4.2 dBm is shown.

As shown in FIGS. 2 to 6, the maximum gain measured at the operating frequency is 9.8 dB, the outputs P1dB and NF are 4.2 dBm and 7.7 dB, respectively, and NF contains the loss value of the measured GSG It can be seen that this structure allows the input and output sections of the circuit to be designed symmetrically with respect to each other, so that both gain and phase can be made equal.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications may be made without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (7)

An amplification stage which is constituted by a central transmission line in the horizontal direction around the first port and the second port and which is formed between the first port and the second port and which is capable of bi-
And a first and a second conversion matching stage which are respectively provided between the first port and the amplifying stage and between the second port and the amplifying stage and which change the direction of the current corresponding to the amplifying direction according to the directionality of the amplifying stage. C-band CMOS bi-directional amplifier using transform matching circuit. 2. The receiver of claim 1,
A first and a second transistor M _A1 (M _A2 ) connected in common gate structure to a direct current control switch (DPDP switch), each having a first conversion matching node and a second conversion matching node connected to the drain, )Wow,
And a first inductor L _inter connected between the first and second transistors M _A1 and M _A2 to increase a power gain. . The method according to claim 1,
And a resistor (R _A ) and a capacitor (C _ACG ) connected in parallel to each other between the amplifier stage and the DC control switch (DPDP switch) are formed in a multi-stage common gate structure. amplifier. 2. The apparatus of claim 1, wherein the first conversion match stage or the second conversion match stage
A third transistor M _{W1 to} which an amplification stage and a drain are connected,
A power source V _sw for applying a constant voltage to the gate of the third transistor M _W1 ,
A resistor R _SW serially connected between the third transistor M _W1 and the power source V _sw ,
A first capacitor C _ACG grounded on one side and connected in parallel to the power source V _sw and the resistor R _SW ,
A second inductor L _SWIT1 connecting a source and a drain of the third transistor M _W1 ,
A second capacitor (C ₁ ) serially connected between the first port and the source of the transistor (M _W1 )
A direct current control switch (SPDP switch) connected in parallel between the source of the third transistor M _W1 and the second capacitor C ₁ to adjust the direction matching with the amplification direction to change the conversion matching stage 200a,
A first inductor L ₁ connected in series to a connection line connected to the source of the DC control switch SPDP switch and the third transistor M _W1 ,
And a third capacitor (C _ACG ) connected in parallel to a connection line connected to the source of the third transistor (M _W1 ) and the DC control switch (SPDP switch) 400a. C - band CMOS bi - directional amplifier using circuit. 5. The method of claim 4,
Band CMOS bi-directional amplifier using a conversion matching circuit, wherein the third transistor M _W1 operates as a short when turned on and vice versa. 5. The method of claim 4,
And a constant voltage is applied to the gate of the third transistor M _W1 at a voltage of 1.3 V through a power source V _sw . 5. The method of claim 4,
Wherein the resistor R _SW connected in series between the third transistor M _W1 and the power supply V _sw is comprised of a resistor of 20 Kohm.

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