KR20160116286A - Placement method of parallel multiplier - Google Patents

Abstract

The present invention relates to a method of placing parallel multipliers, capable of optimizing power, performance, and a space. According to the present invention, the method of placing the parallel multipliers using an arrangement-routing tool run on a computer includes the steps of: receiving a datapath netlist of the parallel multipliers; extracting locations of primary input and output cells from the datapath netlist using a structure analysis module; mapping the primary input and output cells onto a predetermined array using the arrangement-routing tool; and aligning columns of the primary input cells and the primary output cells based on physical sizes of the primary input cells using the arrangement-routing tool. The size of the specific array is determined based on the number of the primary input cells.

Description

{PLACEMENT METHOD OF PARALLEL MULTIPLIER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging logic circuits, and more particularly, to a method of arranging parallel multipliers.

Recently, the system-on-chip is fabricated through an automated place and route (P & R) technique for designs where datapath logic is often used, such as high performance microprocessors due to its short design schedule. However, it is difficult to obtain power, performance, and spatially optimized placement results because placement algorithms that generally minimize wire length can not account for the structural features of the data path. In order to avoid this algorithmic problem, the structural optimization work is usually done in manual. Thus, although a structurally optimized result can be obtained, this manual layout method requires considerable time.

Recently, system - on - chip with enhanced multimedia function has many parallel multipliers. The parallel multiplier receives the multiplicand and multiplier and performs a multiplication operation in parallel. Such a parallel multiplier includes a portion capable of automatically performing a structurally optimized arrangement.

It is an object of the present invention to provide a method of arranging a parallel multiplier in which a partial multiplication generator and a final multiplier included in a parallel multiplier are arranged in consideration of a structure so as to optimize power, performance and space.

A method for arranging a parallel multiplier using a batch-routing tool driven by a computer according to the present invention comprises the steps of: receiving a data passnet list for the parallel multiplier; receiving initial data from the data passnet list And mapping the initial input cells and the initial output cells to a particular array using the placement-routing tool, and using the placement-routing tool to map the initial input cells And aligning each column of the initial input cells and the initial output cells based on a physical size, the size of the particular array being determined by the number of the initial input cells.

A method for arranging a parallel multiplier using a computer-driven logic synthesis tool and a placement-routing tool according to the present invention includes the steps of: generating a data path netlist for the parallel multiplier through the logic synthesis tool; Extracting positions of initial input cells and initial output cells from the data path netlist using the multiplicand and multiplier input to the parallel multiplier, Mapping the initial input cells and the initial output cells to a specific array using information about the initial input cells and the initial output cells based on the physical size of the initial input cells using the placement- Comprising: arranging each column of cells, Is determined according to the number of initial input cells.

According to an embodiment of the present invention, it is possible to provide a method of arranging a parallel multiplier in which a partial multiplier generator and a final multiplier included in a parallel multiplier are arranged in consideration of a structure to optimize power, performance and space.

1 is a block diagram illustrating a parallel multiplier placement system in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a parallel multiplier arranged by a parallel multiplier arrangement method according to an embodiment of the present invention. Referring to FIG.
FIG. 3 is a diagram showing the arrangement of the partial product generator and the final adder of FIG. 2. FIG.
4 is a flowchart illustrating a parallel multiplier arrangement method according to an embodiment of the present invention.
5 is an exemplary diagram illustrating an initial input cell extracted by the parallel multiplier arrangement system of the present invention.
6 is an exemplary illustration of the compression cells included in the partial multiplication reduction module of the parallel multiplier.
7 is an exemplary diagram illustrating a Min-cost Maximum Flow (MCF) algorithm according to an embodiment of the present invention.
8 is an exemplary diagram illustrating a bit-slice alignment algorithm according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a logic circuit including a parallel multiplier arranged according to a parallel multiplier arrangement method according to an embodiment of the present invention. Referring to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. In addition, like reference numerals designate like elements throughout the specification.

Although specific terms are used herein, they are used for the purpose of describing the invention and are not used to limit the scope of the invention as defined in the claims or the meaning of the claims. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / connected " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a parallel multiplier placement system 100 in accordance with an embodiment of the present invention. 1, a parallel multiplier placement system 100 may include a CPU 110, a working memory 130, an input / output device 150, a storage device 170, and a bus 190. Here, the parallel multiplier placement system 100 may be provided as a dedicated device for placing a parallel multiplier, but may also be a computer for driving various placement tools or design tools.

The CPU 110 executes software (application programs, operating systems, device drivers) to be executed in the parallel multiplier placement system 100. The CPU 110 will execute an operating system (OS, not shown) that is loaded into the working memory 130. The CPU 110 may execute various application programs or batch tools to be operated on an operating system (OS) basis. For example, the CPU 110 may drive datapath generation tools, structure analysis tools, placement / routing tools loaded into the working memory 130, and so on. In particular, the structure analysis module 131 provided by the placement tool of the present invention will be driven by the CPU 110. [ In particular, the structure analysis module 131 may extract the location and structural characteristics of the logic cells included in the parallel multiplier. In addition, the CPU 110 may drive a placement and routing tool (P & R Tool) 132 for placing the various logic cells in the chip in the optimal location.

An operating system (OS) and application programs are loaded into the working memory 130. An OS image (not shown) stored in the storage device 170 at the boot time of the parallel multiplier placement system 100 will be loaded into the working memory 130 based on the boot sequence. All operations of the parallel multiplier arrangement system 100 by the operating system (OS) can be supported. Similarly, application programs may be loaded into the working memory 130 for selection by the user or provision of basic services. In particular, the placement tools 131, 132 of the present invention may be loaded into the working memory 130.

In particular, the structure analysis module 131 or the placement / routing tool 132 as a placement tool will also be loaded from the storage device 170 into the working memory 130. Although not shown, the working memory 130 may further include logic synthesis tools that generate a datapath netlist of parallel multipliers. The working memory 130 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory such as a PRAM, an MRAM, a ReRAM, a FRAM, and a NOR flash memory.

The structure analysis module 131 may analyze the structure of the parallel multiplier. For example, the structure analysis module 131 may receive a data passnet list of a parallel multiplier. The structure analysis module 131 may estimate the location of the logic cells included in the parallel multiplier through the data pathnet list. In addition, the structure analysis module 131 may output the structure information of the parallel multiplier in consideration of the physical size of the logic cells. The placement / routing tool 132 may place the logic cells of the parallel multiplier at optimal locations using the location and structure information of the logic cells extracted by the structure analysis module 131. [

The input / output device 150 controls user input and output from the user interface devices. For example, the input / output device 150 may include an input device such as a keyboard, a mouse, and a touch pad and an output device such as a monitor to receive a Template containing structure layout information for analyzing the structure of the logic cells . The structure placement information may include specific cells capable of inducing a structural arrangement of logic cells, a location of a specific cell, an algorithm capable of analyzing specific cells, and the like. The input / output device 150 may display the arrangement procedure of the parallel multiplier arrangement system 100, the layout result, and the like.

The storage device 170 is provided as a storage medium of the parallel multiplier placement system 100. The storage device 170 may store application programs, an OS image, and various data. The storage device 170 may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.) or a hard disk drive (HDD). The storage device 170 may include a NAND-type flash memory having a large storage capacity. Alternatively, the storage device 170 may include a next generation nonvolatile memory such as PRAM, MRAM, ReRAM, FRAM, or the like, or a NOR flash memory.

The system bus 190 may be provided as an interconnector for providing a network within the parallel multiplier placement system 100. The CPU 110, the working memory 130, the input / output device 150, and the storage device 170 are electrically connected through the system bus 190 and exchange data with each other. However, the configuration of the system bus 190 is not limited to the above description, and may further include arbitration means for efficient management.

According to the above description, the parallel multiplier placement system 100 can analyze the location and structure of logic cells by referring to the input data pathnet list. The parallel multiplier arrangement system 100 can arrange the logic cells of the parallel multiplier in an optimum position in consideration of power, performance, and space according to the analyzed position and structure. Thus, the parallel multiplier is designed in a short time and can be placed in a logic circuit.

FIG. 2 is a block diagram illustrating a parallel multiplier arranged by a parallel multiplier arrangement method according to an embodiment of the present invention. Referring to FIG. Referring to FIG. 2, the parallel multiplier 200 may include a partial product generator 210, a partial product reduction module 220, and a final adder 230. The parallel multiplier 200 receives a multiplicand and a multiplier, multiplies the multiplicand and multiplier, and outputs a final product. The parallel multiplier 200 can calculate the product of the multiplicand and the multiplier in parallel.

The partial product generator 210 generates partial products of the multiplicand and the multiplier. For example, by multiplying a multiplicand of 8 bits by a multiplier of 8 bits, the partial product generator 210 can generate 64 partial products. That is, the partial product generator 210 will have 64 logic cells that produce 64 partial products.

The partial product reduction module 220 generates Sum-bits and Carry-bits for accumulating the generated partial products to generate a final product. For example, the logic cells of the partial product reduction module 220 may use a Wallace tree that receives three inputs and outputs a sum bit and a carry bit. The three inputs may include a sum bit and a carry bit from the previous row (Row), and one of the outputs from the partial product generator (210).

The final adder 230 may sum the sum bits and carry bits output from the partial product reduction module 220 to output the final product. For example, the logic cells of the final adder 230 may form a column with at least one logic cell included in the partial product generator 210.

FIG. 3 is a diagram illustrating the arrangement of the partial product generator 210 and the final adder 230 of FIG. Referring to FIG. 3, the partial product generator 210 may include logic cells a1b1 through a8b8 that compute a partial product of a multiplicand and a multiplier. Also, the final adder 230 may include sum bit cells Sum1 to Sum15 and carry bit cells Ca1 to Ca15. In the following, the multiplicand and multiplier are assumed to be 8 bits. However, the multiplicand and multiplier may be greater or less than 8 bits. The multiplicand includes each bit of a1 to a8. The multiplier includes bits of b1 to b8.

The partial product generator 210 may comprise an array of logic cells a1b1 through a8b8. For example, the logic cells a1b1 to a8b8 may be arranged in a parallelogram shape similar to rhombus on a two-dimensional plane. The logic cells a1b1 to a8b8 may be included in each row (Row1 to Row8). The logic cells a1b1 to a8b8 may be included in the columns Col1 to Col16.

The partial product reduction module 220 may accumulate the partial products to transfer sum bits and carry bits to the sum bit cells Sum1 to Sum15 and carry bit cells Ca1 to Ca15 of the final adder 230. [ For example, the partial product reduction module 220 may use a Wallace tree. Thus, although not shown, the logic cells included in the partial product reduction module 220 may have the same shape and size as one another.

The final adder 130 may include sum bit cells Sum1 to Sum15 and carry bit cells Ca1 to Ca15. The sum bit cells Sum1 to Sum15 can form one row (Row). The carry bit cells Ca1 to Ca15 can form one row.

Various types of datapath logic are used for logic circuitry such as system-on-chip (SoC). The parallel multiplier 200 is one of the datapath logic. In addition, the logic circuit includes a plurality of parallel multipliers (200). Therefore, if the parallel multiplier 200 is arranged quickly considering power, performance, and space, the time for designing the logic circuit can be shortened.

4 is a flowchart illustrating a parallel multiplier arrangement method according to an embodiment of the present invention. Referring to FIG. 4, the parallel multiplier 200 according to the parallel multiplier arrangement method can be quickly disposed in the logic circuit in consideration of power, performance, and space.

In step S110, the parallel multiplier placement system 100 may receive the data passnet list of the parallel multiplier 200. [ For example, the parallel multiplier placement system 100 may receive a netlist file created by a user. In addition, the parallel multiplier placement system 100 may generate a netlist using a logic synthesis tool. The Logic Synthesis tool has the parameters necessary to generate the partial product generator 210, mathematical information, and relationship information between the logic cells.

In step S120, the parallel multiplier arrangement system 100 may determine a row and a column of primary input cells (PIs). For example, the parallel multiplier placement system 100 may define some of the logic cells a1b1 through a8b8 as Primary Input Cells (PIs). The initial input cell PI can induce a structural arrangement of other logic cells. The initial input cell (PI) is defined as a cell connected to the net of inputs of multiplicand and multiplier.

The method of extracting the initial input cell PI may vary depending on the type of the logic cell of the partial product generator 210. For example, the logic cell of the partial product generator 210 may have a Booth type and a Non-Booth type. For the booth type, the initial input cell (PI) is extracted using only the net of the multiplicand. For the non-Booth type, the initial input cell (PI) is extracted using the net of multiplicand and multiplier.

The extracted initial input cell (PI) estimates the position. For example, a row of an initial input cell PI may be determined through a row inference algorithm. Referring to FIG. 3, the rows of logic cells a1b1 to a8b8 may be determined by a multiplier. Illustratively, the logic cells a1b1 to a8b1 included in the first row Row1 are cells multiplied by the multiplier b1. The logic cells a1b2 to a8b2 included in the second row Row2 are cells multiplied by the multiplier b2. The logic cells a1b3 to a8b3 included in the third row Row3 are the cells multiplied by the multiplier b3. Thus, the position of the row including the initial input cell PI can be determined by the multiplier.

In addition, the column of the initial input cell PI can be determined through a column inference algorithm. The columns of the logic cells a1b1 to a8b8 can be determined by a multiplicand and a multiplier. The logic cells included in each column are cells having the same number of digits of the multiplicand and the multiplier of the multiplier. Illustratively, the logical cell a1b1 included in the first column Col1 has a sum of the multiplicand and the multiplier of the multiplier 2. The logic cells a2b1 and a1b2 included in the second column Col2 have a sum of the multiplicand and multiplier of 3. The logic cells a3b1, a2b2 and a1b3 included in the third column Col3 have a sum of the multiplicand and multiplier of four. Thus, the position of the column including the initial input cell PI can be determined by the multiplicand and the multiplier.

In step S130, the parallel multiplier placement system 100 may determine an initial output cell (PO) included in each column. The initial output cell (PO) can be obtained by tracing the sum bits in the netlist. For example, the output of the initial input cell may be coupled to a compression cell included in the partial product reduction module 220. The compressed cell can receive a plurality of inputs and output a sum output (Sum-out) and a carry output (Carry-out). Here, the sum output can be connected to the initial output cell PO without variation of the columns Col1 to Col16. Therefore, by tracing the sum output of the compressed cells of the partial product reduction module 220 connected to the initial input cell PI, the columns Col1 to Col16 of the initial output cells PO can be determined.

In step 140, the parallel multiplier placement system 100 may map initial input cells (PIs) and initial output cells (POs) to a given array. For example, the parallel multiplier placement system 100 creates a predetermined array to map initial input cells and initial output cells. The predetermined array has a structure of a logical parallel multiplier 200 logically. If the size of a given array is allotted so that all of the logic cells are allotted, the aspect ratio of the array to which the logic cells are mapped will increase, and the quality of result (QoR) of the parallel multiplier 200 may decrease have. Thus, the parallel multiplier placement system 100 determines the size of a given array according to the number of initial input cells. For example, the parallel multiplier placement system 100 may preset the number of rows of a given array. The parallel multiplier placement system 100 may be determined by dividing the number of initial input cells to be mapped into each column by the number of rows that are set in advance. However, at this time, mis-mapped initial input cells may occur.

The parallel multiplier placement method of the present invention allows mis-mapping of initial input cells. Mis-mapping refers to mapping of initial input cells and initial output cells to locations other than the extracted location. The parallel multiplier placement system 100 performs an optimization operation that maximizes the number of logic cells mapped while minimizing mis-mapped logic cells.

The parallel multiplier placement system 100 may map the initial input cells according to the Min-cost Maximum Flow (MCF) algorithm to minimize the sum of the difference between the estimated position of the initial input cells and the actual mapped position have. However, the MCF algorithm does not consider a net connection between logic cells. Thus, the parallel multiplier placement system 100 may also implement a Half-Perimeter Wire Length (HPWL) algorithm to account for the net connection between the logic cells. The parallel multiplier placement system 100 can give different weights to the MCF and HPWL algorithms.

In step S150, the parallel multiplier placement system 100 may align the columns of a given array based on the physical size of the initial input cells and the initial output cells. For example, until step S140, the sizes of the initial input cells and the initial output cells are not considered. However, the initial input cells and the initial output cells may each have a different size. Therefore, the array mapped in step S140 needs to be rearranged considering the sizes of the initial input cells and the initial output cells.

For example, the parallel multiplier placement system 100 may perform a Bit-Slice Alignment algorithm. The bit-slice alignment algorithm adjusts initial input cells and initial output cells so that mis-alignment is minimized within a predetermined limit width. Mis-alignment refers to the degree to which each of the initial input cells and the initial output cells deviate from the mapped row.

The parallel multiplier arrangement method according to the embodiment of the present invention has been described above. The parallel multiplier placement system 100 may receive the data passnet list and extract initial input cells and initial output cells. The parallel multiplier placement system 100 may map initial input cells and initial output cells to a predetermined array according to placement algorithms. The parallel multiplier placement system 100 may derive the initial input cells and the initial output cells and then the placement of the remaining logic cells. Thus, the parallel multiplier placement system 100 can place the parallel multipliers faster than the manual method considering power, performance, and space.

5 is an exemplary diagram illustrating an initial input cell extracted by the parallel multiplier arrangement system of the present invention. Referring to FIG. 5, an initial input cell may have a booth type or a non-booth type. However, the type of the initial input cell is not limited to this. The initial input cell may have various types of shapes.

The parallel multiplier placement system 100 may apply the location estimation algorithm differently depending on the type of initial input cell. For example, the partial product output (PP _ij ) of the initial input cell of the non-booth type is made up of a combination of inputs (X _i , Y _j ). Where X is a multiplier, Y is a multiplicand, i represents the ith row of the partial product, and j represents the jth column of the partial product. Therefore, in the case of the non-booth type, the row and column to which the initial input cell belongs can be known through the inputs X _i and Y _j . For example, the partial products output from the initial input cell of the booth type (PP _ij) is the _input-are made of a combination of _{(X 2i -1, X 2i,} X 2i +1, Y j, Y j 1). In the case of the booth type, the position of the row of the initial input cell is estimated by dividing the inputs (X _{2i -1} , X _2i , X _{2i + 1} ) by 2 and performing a floor operation.

6 is an exemplary illustration of the compression cells included in the partial multiplication reduction module of the parallel multiplier. Referring to FIG. 6, each of the compressed cells 221 to 224 receives three inputs and transmits two outputs. For example, the three inputs may include an initial input cell output (PI) of one of the sum output SUM and the carry output CA from the previous row and the outputs from the partial product generator 210 . However, the compressed cells 221 to 224 are not limited to this.

In Fig. 6, the compressed cells 221 and 222 belong to the j-th column. The compressed cells 223 and 224 belong to the (j + 1) th column. Here, sum outputs (SUM) are transmitted along one column, without changing the column. On the other hand, the carry outputs (CAs) change the column every time a row is changed. Accordingly, the parallel multiplier placement system 100 can extract the column to which the initial input cell belongs by tracking the sum bits (SUM) of the compressed cells connected to the initial input cell.

7 is an exemplary diagram illustrating a Min-cost Maximum Flow (MCF) algorithm according to an embodiment of the present invention. Referring to FIG. 7, a mapping method of an initial input cell (PI cell [j]) is shown. The initial input cell (PI cell [j]) is a cell estimated to belong to the jth column. For example, each column j + 1, j, j-1 may include a respective slot Slot [i + 1], Slot [i], Slot [i-1]. The initial input cell PI cell [i] may be mapped to one of the slots Slot [i + 1], Slot [i], Slot [i-1] Therefore, the initial input cell PI cell [i] can be compared with the adjacent initial input cells PI cell [i + 1] and PI cell [i-1]. Each arrow indicates that the initial input cells (PI cell [i + 1], PI cell [i], PI cell [i-1]) are in the slots Slot [i + 1], Slot [i] 1]). And can have different cost and flow capacity according to each case (① ~ ⑦). Thus, the parallel multiplier placement system 100 may map the initial input cells (PI cell [i]) to a given array to minimize cost and maximize flow capacity.

Although FIG. 7 exemplarily illustrates a single cell (PI cell [j]), the parallel multiplier placement system 100 can perform the MCF algorithm on all extracted initial input cells. The parallel multiplier placement system 100 may map the initial input cells to a given array so that the sum of the results for all initial input cells is minimized through the MCF algorithm.

8 is an exemplary diagram illustrating a bit-slice alignment algorithm according to an embodiment of the present invention. Considering the size of the initial input cells mapped to a given array, the corners of the initial input cells may deviate laterally in each column. You can then find the difference between the corners of the cells that are most out of the bounds of the columns. For example, the maximum edge difference g1 between the j + 2 column Col [j + 2] and the j + 1 column Col [j + 1] 2] and the cell C [i, j + 1] or the cell C [i + 1, j + 1]. The maximum edge difference g2 between the j + 1 column (Col [j + 1]) and the jth column (Col [j] i, j]). The maximum edge difference g3 between the jth column Col [j] and the jth column Col [j-1] is the sum of the cell C [i, j] j-1] or the cell C [i + 1, j-1]. The maximum edge difference g4 between the j-th column Col [j-1] and the j-2 column Col [j-2] May be determined by the cell C [i, j-2]. The empty space cells B [i, j + 2] and B [i + 1, j + 2] can be allocated to the slots to which the initial input cells are not mapped.

The parallel multiplier placement system 100 can adjust the position of the initial input cells so that the sum of the maximum edge differences g1 to g4 determined as described above is minimized within a predetermined width constraint. Although illustratively described with three rows and five columns in FIG. 8, the parallel multiplier placement system 100 can perform a bit-slice alignment algorithm on the initial input cells mapped in the same manner have.

FIG. 9 is a diagram illustrating a logic circuit including a parallel multiplier arranged according to a parallel multiplier arrangement method according to an embodiment of the present invention. Referring to FIG. Referring to FIG. 9, the logic circuit 1000 may include a plurality of logic cells. For example, the logic circuit 1000 may include a CPU, a GPU, a system-on-chip (SoC), or an application processor (AP). In arranging the logic cells, the parallel multipliers 200 may be arranged first according to the parallel multiplier arrangement method of the present invention. After the parallel multipliers 200 are placed, the remaining logic cells may be arranged according to their function. Thus, logic cells can be quickly arranged to optimize power, performance, and space in the logic circuit 1000.

The embodiments have been disclosed in the drawings and specification as described above. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: Parallel multiplier placement system
130: Working memory
131: Structural Analysis Module
132: Placement / Routing Tools
150: input / output device
170: Storage device
190: System bus
200: parallel multiplier
210: partial product generator
220: partial product reduction module
230: final adder
1000: logic circuit

Claims (10)

A method of arranging a parallel multiplier using a batch-routing tool driven by a computer, the method comprising:
Receiving a data pathnet list for the parallel multiplier;
Extracting locations of initial input cells and initial output cells from the data passnet list using a structure analysis module;
Mapping the initial input cells and the initial output cells to a particular array using the placement-routing tool; And
And aligning each column of the initial input cells and the initial output cells based on the physical size of the initial input cells using the placement-routing tool,
Wherein the size of the particular array is determined by the number of initial input cells. The method according to claim 1,
Wherein the structure analyzing module extracts positions of the initial input cells and the initial output cells using a multiplicand and a multiplier input to the parallel multiplier. The method according to claim 1,
Wherein a row to which the initial input cells belong is estimated using a multiplier input to the parallel multiplier,
Wherein the column to which the initial input cells belong is estimated using the multiplier and the multiplicand input to the parallel multiplier. The method according to claim 1,
Wherein the column to which the initial output cells belong is determined by tracking the sum output of the compressed cells connected to the initial input cells. The method according to claim 1,
In the step of mapping to the specific array,
The particular array comprising a plurality of slots,
Wherein the placement-routing tool is configured to provide the initial input cells and the initial output to the plurality of slots such that each of the initial input cells has a minimum cost and a maximum flow capability when mapped to one of the plurality of slots. A mapping method for mapping cells. 6. The method of claim 5,
Wherein the cost is determined by a distance between an estimated location of the initial input cells and a location actually mapped. 6. The method of claim 5,
Wherein the flow capability is proportional to the amount of data per time transmitted from the initial input cells to the initial output cells. 6. The method of claim 5,
Wherein the batch-routing tool applies different weights to the cost and the flow capability to map the initial input cells and the initial output cells to the particular array. The method according to claim 1,
The method of claim 1, wherein in the step of aligning each of the columns, in the first and second columns adjacent to each other, an edge of a first cell out of the initial input cells included in the first column, Wherein the initial input cells included in the first column and the second column are relocated to minimize a distance between edges of a second cell out of the initial input cells that deviates most in the first column direction. The method according to claim 1,
Wherein in the step of aligning the columns, empty space cells having a specific size are mapped to slots to which the initial input cells in the specific array are not mapped.

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