KR20160092143A - Organic Light Emitting Display - Google Patents

Abstract

The present invention relates to an organic light emitting display device which can sense changes in a characteristic of a drive element without an additional sensing wire. The organic light emitting display device includes a sensing circuit sensing a source voltage of the drive element. The organic light emitting display device includes: a first switch thin film transistor (TFT) connecting a data line and a first node; a drive TFT including a gate connected to the first node, a drain provided with a high voltage drive voltage, and a source connected to an anode of an organic light emitting diode; a storage capacitor connected between the first node and a second node; and the sensing circuit sensing the source voltage of the drive TFT through a cathode of the organic light emitting diode.

Description

[0001] The present invention relates to an organic light emitting display,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to an organic light emitting display device that improves image quality based on a result of sensing a change in characteristics of a driving device.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, has a high response speed, and has a large luminous efficiency, luminance, and viewing angle. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

Each of the pixels of the organic light emitting display includes a driving element for controlling a current flowing in the OLED. The driving device may be implemented by a TFT (Thin Film Transistor). Though it is preferable that the electrical characteristics of the driving device such as threshold voltage, mobility, etc. are designed to be the same in all pixels, the electrical characteristics of the driving TFT are not uniform due to process conditions, driving environment, and the like. As the driving time becomes longer, the driving device receives a lot of stress and there is a stress difference according to the data voltage. The electrical characteristics of the driving device are affected by the stress. Therefore, the driving characteristics of the driving TFTs are different when the driving time elapses.

An organic light emitting display device has been applied to a technique of sensing a change in a characteristic of a driving element, such as a threshold voltage and a mobility, from each pixel, and compensating image quality by properly modulating input image data based on the sensing result. In order to sense changes in the characteristics of the driving elements, sensing wires must be added to the display panel. The voltage change of the driving element is read through the sensing wirings. However, the aperture ratio (AR) of the pixel is reduced due to the sensing wirings. When the aperture ratio is reduced, the current flowing through the OLED must be increased to prevent the luminance from decreasing. When the data voltage applied to the gate of the driving device is increased to increase the current of the OLED, the driving device is stressed to accelerate deterioration of the driving device, thereby deteriorating the image quality of the display device and shortening the life span. Therefore, there is a demand for a method capable of sensing the change in the characteristics of the driving element without reducing the aperture ratio of the pixel.

The present invention provides an organic light emitting display device capable of sensing a change in characteristics of a driving element without a separate sensing wiring.

The organic light emitting diode display of the present invention includes a first switch TFT connecting a data line and a first node in accordance with a scan pulse from a first gate line, a gate connected to the first node, a drain supplied with a high- And a source connected to the anode of the OLED via a second node, a storage capacitor connected between the first node and the second node, and a source connected to the source of the drive TFT when the second switch TFT is turned on, And a sensing circuit for sensing a voltage through the cathode of the OLED.

The present invention detects a change in element characteristics of a driving element through a cathode of an OLED. As a result, the present invention can omit a separate sensing wiring in the organic light emitting diode display, thereby increasing the aperture ratio of the pixel, thereby reducing the stress of the driving element and improving the image quality and lifetime of the display.

1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.
2 is a plan view showing a cathode pattern according to an embodiment of the present invention.
3 is a cross-sectional view showing a cross section of the cathode pattern taken along the line "I-I" in Fig. 2.
4 is a plan view showing parts of the cathode baton and wires connected to the pixels.
5 and 6 are circuit diagrams showing the circuit configuration and operation of the pixel according to the embodiment of the present invention.
7 is a waveform diagram showing the sensing mode operation of the pixel.
FIGS. 8A to 8D are diagrams showing the sensing mode operation of the pixels by the sections shown in FIG. 7. FIG.
9 is a waveform diagram showing the data write and display mode operation of the pixel.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention. 2 is a plan view showing a cathode pattern according to an embodiment of the present invention. 3 is a cross-sectional view showing a cross section of the cathode pattern shown in FIG. 4 is a plan view showing parts of the cathode baton and wires connected to the pixels.

1 to 4, an OLED display according to an embodiment of the present invention includes a display panel 10, a data driver 12, a gate driver 13, and a timing controller 11.

A plurality of data lines 14 and a plurality of gate lines 16 are intersected with each other in the display panel 10 and the pixels P11 to P34 are arranged in a matrix form. The display panel 10 is formed with an EVDD line to which a high potential driving voltage EVDD is supplied. The gate lines 15 are divided into gate lines to which the scan pulses SCAN1 to SCAN4 are supplied and gate lines to which the sense pulses SENSE1 to SENSE4 are supplied as shown in FIG. One pixel is connected to one data line, one gate line pair, one EVDD line, and a PRE line not shown. The gate line pair includes one gate line to which a scan pulse is supplied and another gate line to which a sense pulse is supplied. The PRE line supplies the initialization voltage Vpre to the pixels P11 to P34 as shown in FIGS.

The initializing voltage Vpre and the sensing data voltage Vdata are set to be the same as those of the driving TFTs for compensating for the characteristics of the analog-to-digital converter (hereinafter referred to as "ADC " Can be set differently according to the change of the threshold voltage range. The initialization voltage Vpre is set to a low voltage at which the OLED does not emit light. The high-potential driving voltage (EVDD) can be adjusted according to the characteristics of the OLED.

The display panel 10 includes a plurality of cathode patterns CAT1 to CAT3 patterned in a stripe shape in the column direction as shown in FIG. The column direction is the y-axis direction or the data line direction in Fig.

The cathode pattern CAT can be patterned in such a way that it is divided by the barrier rib RIB. The barrier rib (RIM) has a reverse tapered cross section as shown in FIG. 3 so that the cathode metal can be separated with the partition wall therebetween when the cathode metal is deposited. The cathode pattern (CAT) can be patterned without a photolithography process because it is separated into barrier ribs. The anode ANO of the OLED is separated with the bank pattern BANK therebetween. The cathode pattern (CAT) and the organic compound layer (EL) are stacked on the bank pattern (BANK) and the anode pattern. In Fig. 3, the TFTs, the wirings and the substrate under the OLED are omitted.

Each of the pixels P11 to P34 may include an OLED, a driving TFT DT, a first and a second switching TFT ST1 and ST2, and a storage capacitor Cst as shown in Figs. 5 and 6, It does not. The OLED includes an organic compound layer (EL) formed between the anode (ANO) and the cathode pattern (CAT). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL).

The TFTs of the pixels P11 to P34 are illustrated as n-type MOSFETs in FIGS. 5 and 6, but may be implemented as a p-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The TFTs may be formed of an amorphous silicon (a-Si) TFT, a polysilicon TFT, or an oxide semiconductor TFT.

Neighboring OLEDs along the column direction are connected to the same cathode pattern. Therefore, the cathodes of neighboring pixels along the column direction share one cathode pattern and are connected to each other. For example, the pixels P11 to P14 arranged in the first column are connected to the first cathode pattern CAT1. And the pixels P21 to P24 disposed in the second column are connected to the second cathode pattern CAT2. The pixels P31 to P34 arranged in the third column are connected to the third cathode pattern CAT3. The cathode patterns CAT1 to CAT3 act as the cathode of the OLED when the data of the input image is displayed and the driving TFTs of the pixels disposed along the column direction when the change in the device characteristics of the driving TFT is sensed are shown in Figs. To form a sensing path. Hereinafter, the operation mode of the pixel in which the data of the input image is displayed is referred to as "data write and display mode ", and the operation mode of the pixel in which the change in device characteristics of the drive TFT is sensed is referred to as a" sensing mode ". The data write and display mode includes an active period of the N-th frame period in which the N-th (N is a positive integer) frame image data is displayed in the pixel array, and an (N + 1 And can be executed in the active period of the frame period. The sensing mode may be executed in a vertical blank period in which no new data is written to pixels between the Nth frame period and the (N + 1) th frame period in which the input image is displayed. During the vertical blank period, no new data is written to the pixels. The ADC outputs the result of sensing the source voltage change of the driving TFT in the sensing mode as digital data.

The pixels are simultaneously selected on a line-by-line basis according to the scan pulse and the sense pulse supplied through the gate lines 15 to receive the data voltage of the input image or to sense a change in device characteristics of the drive TFT. When the cathode patterns CAT1 to CAT3 are formed in a stripe pattern in the row line direction (or y-axis direction) side by side with the gate lines 15, since neighboring driving TFTs along the line direction are connected to each other, The device characteristic changes of the driving TFTs that are driven by the driving TFTs are simultaneously sensed and it is not possible to individually detect the change of the device characteristics of the driving TFTs in each of the pixels. Therefore, the cathode patterns CAT1 to CAT3 must be formed in the column direction intersecting with the gate lines 15 as in the example of Figs.

The data driver 12 supplies the pixels P with a sensing data voltage synchronized with the scan pulses SCAN1 to SCAN4 under the control of the timing controller 11 in a sensing mode for sensing a change in device characteristics of the driving TFT . The sensing data voltage is a data voltage independent of the data of the input image. The timing controller 11 transmits the sensing data previously stored in the internal memory to the data driver 12 in the sensing mode and the data driver 12 converts the sensing data received as digital data into a sensing data voltage. The sensing data voltage is applied to the gate of the driving TFT in the sensing mode. The sensed data voltage turns on the driving TFT in the sensing mode so that current flows in the driving TFT. Therefore, the sensing data voltage is set to a voltage higher than the Muntun voltage of the driving TFT. The data driver 12 converts the sensing voltage received from the pixels P11 to P34 through the cathode pattern CAT in the sensing mode into digital data and outputs the sensing data SEN. The data driver 12 transmits the sensing data SEN to the timing controller 11. [ The sensing voltage is the source voltage (Vsen) of the driving TFT as described later.

The data driver 12 converts the digital video data MDATA of the input video received from the timing controller 11 into a data voltage under the control of the timing controller 11 in a data write and display mode for displaying an input video The data voltage is supplied to the data lines 14 in synchronization with the scan pulse. The digital video data MDATA supplied to the data driver 12 is supplied to the data modulator 20 in order to compensate for the change in the device characteristics based on the sensing result of the change in the device characteristics of the drive TFT, Modulated compensation data.

The data driver 12 includes a digital-to-analog converter (DAC), an ADC, and switches SPRE and SAM shown in FIGS. 5 and 6. The DAC converts the digital data received by the data driver 12 into an analog data voltage Vdata. The ADC converts the sensing voltage (Vsen) showing the device characteristics of the driving TFT into the digital data sensing data (SEN).

The initialization switch SPRE is connected between the PRE line and the third node n3 and supplies the initialization voltage Vpre to the third node n3 in response to the initialization control signal. A sampling switch (SAM) is connected between the third node (n3) and the ADC to supply a sensing voltage (Vsen) to the ADC in response to a sampling control signal. The switches SPRE and SAM are turned on / off in the sensing mode under the control of the timing controller 11 as shown in FIG. 7, and turned on / off in the data write and display mode as shown in FIG.

The gate driver 13 supplies the scan lines SCAN1 to SCAN4 and the sense pulses SENSE1 to SENSE4 to the gate lines 16 under the control of the timing controller 11 as shown in Figs. The gate driver 13 shifts the scan pulses SCAN1 to SCAN4 and the sense pulses SENSE1 to SENSE4 by using a shift register and sequentially supplies the pulses to the gate lines 16. [ The gate driver 13 may be formed directly on the display panel 10 by a gate-driver In Panel (GIP) process. 7 shows the scan pulses SCAN1 to SCAN4 and the sense pulses SENSE1 to SENSE4 generated in the sensing mode. FIG. 9 shows scan pulses SCAN1 to SCAN4 and sense pulses SENSE1 to SENSE4 generated in the data write and display mode.

The timing controller 11 receives digital video data (DATA) of an input video from a host system (not shown) and a timing signal synchronized with the digital video data (DATA). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 11 includes a data timing control signal DDC for controlling the operation timing of the data driver 12 based on the timing signal received from the host system and a timing control signal DDC for controlling the operation timing of the gate driver 13 And generates a timing control signal GDC. The timing controller 11 supplies the sensing data SEN received from the data driver 12 to the data modulator 20 and supplies the data MDATA modulated by the data modulator 20 to the data driver 12, Lt; / RTI >

The data modulator 20 selects an offset value for compensating for a threshold voltage change of the drive TFT and a gain value for compensating for a change in mobility of the drive TFT with reference to the sensing data SEN, The digital video data (DATA) of the input image is modulated. The offset value is added to the digital video data (DATA) of the input image to compensate the threshold voltage change of the driving TFT. The gain value is multiplied by the digital video data (DATA) of the input image to compensate for the mobility variation of the driving TFT. The memory of the data modulator 20 stores compensation values necessary for calculation of an offset value and a gain value. The data modulation unit 20 may be incorporated in the timing controller 11. [

5 and 6 are circuit diagrams showing the circuit configuration and operation of the pixel according to the embodiment of the present invention.

5 and 6, the pixel includes an OLED, a driving TFT DT, a storage capacitor Cst, a first switch TFT ST1, a second switch TFT ST2, and the like. The pixel circuit is not limited to Fig. 5 and Fig. For example, a pixel may be further added with a TFT or a capacitor based on Figs. 5 and 6. Fig.

The present invention includes a sensing circuit for sensing the source voltage Vsen of the driving TFT DT through the cathode pattern CAT of the OLED when the second switching TFT ST1 is turned on. The sensing circuit includes a second switch TFT (ST2), an ADC, an initialization switch (SPRE), and a sampling switch (SAM).

The anode of the OLED is connected to the second node n2. The cathode pattern (CAT) is a cathode of an OLED connected in common to a plurality of pixels arranged along the column direction. Thus, one cathode pattern CAT is connected to the plurality of OLEDs arranged along the column direction through the third node n3.

The driving TFT DT controls the current Ioled flowing in the OLED according to the gate-source voltage Vgs. The driving TFT DT includes a gate connected to the first node n1, a drain supplied with the high potential driving voltage EVDD, and a source connected to the second node n2.

The storage capacitor Cst is connected between the first node n1 and the second node n2.

The first switch TFT (ST1) applies the data voltage (Vdata) from the data line (14) to the first node (n1) in response to the scan pulse (SCAN). The first switch TFT ST1 includes a gate to which the scan pulse SCAN is supplied, a drain connected to the data line 14, and a source connected to the first node n1.

The second switch TFT (ST2) switches the current path between the second node (n2) and the third node (n3) in response to the sense pulse SENSE. The second switch TFT ST2 includes a gate to which the sense pulse SENSE is supplied, a drain connected to the second node n2, and a source connected to the third node n3. And the second node n2 is connected to the anode of the OLED. And the third node n2 is connected to the cathode pattern (CAT) of the OLED. The second switch TFT (ST2) selectively connects both ends of the OLED.

The DAC, the ADC, and the switches (SPRE, SAM) shown in FIGS. 5 and 6 may be incorporated in the data driver 12.

The DAC supplies the sensing data voltage (Vdata) to the data line 14 in the sensing mode. The DAC supplies the data voltage (Vdata) of the input image to the data line 14 in the data write and display mode.

The initialization switch SPRE supplies the initialization voltage Vpre to the third node n3 in response to the initialization timing control signal from the timing controller 11. [ The sampling switch (SAM) switches the current path between the third node (n3) and the ADC in response to the sampling timing control signal from the timing controller (11).

7 is a waveform diagram showing the sensing mode operation of the pixel. FIGS. 8A to 8D are diagrams showing the sensing mode operation of the pixels by the sections shown in FIG. 7. FIG.

Referring to FIG. 7, the sensing mode of the pixel is divided into an initialization period T1, a programming period T2, a sensing period T3, and a sampling period T4.

The scan pulse SCAN and the initialization control signal are generated at the high logic level H in the initialization period T1 to turn on the first switch TFT ST1 and the initialization switch SPRE as shown in FIG. As a result, the sensing data voltage Vdata is applied to the gate of the driving TFT DT and the initializing voltage Vpre is supplied to the cathode pattern CAT as shown in Fig. 8A. The initialization voltage Vpre may be a voltage between 0 and 2 V, but is not limited thereto.

The high logic level (H) is the ON level for turning on the TFT of the n-type MOSFET structure. The low logic level (L) is an off level which turns off the TFT of the n-type MOSFET structure. The on-level and off-level of the p-type MOSFET structure TFT are opposite to those of the n-type MOSFET.

The sense pulse SENSE is then generated at the high logic level H in the programming period T2 to connect the anode of the OLED to the cathode pattern CAT. The scan pulse SCAN and the initialization control signal maintain a high logic level during the programming period T2. During the programming period T2, the first switch TFT ST1 and the initialization switch SPRE maintain the ON state and the second switch TFT ST2 is turned on as shown in Fig. 8B. At this time, the initializing voltage Vpre is applied to the source of the driving TFT DT through the cathode pattern CAT. As a result, the source voltage Vsen of the driving TFT DT is set to the initializing voltage Vpre during the programming period T2.

Then, in the sensing period T3, the initialization control signal is inverted to the low logic level L, and the initialization switch SPRE is turned off. During the sensing period T3, the first and second switch TFTs ST1 and ST2 maintain the ON state and the gate voltage Vg of the drive TFT DT is turned on as shown in FIG. 8C. The switches SPRE and SAM remain off during the sensing period T3. As a result, the cathode pattern CAT becomes floating during the sensing period T3. The source voltage Vsen of the driving TFT DT during the sensing period T3 is a voltage Vg-Vth obtained by subtracting the threshold voltage Vth of the driving TFT DT from the gate voltage Vg of the driving TFT DT ). This voltage Vg-Vth is stored in the storage capacitor Cst.

Then, during the sampling period T4, the sampling control signal is generated at a high logic level (H) to turn on the sampling switch SAM. During the sensing period T3, the first and second switch TFTs ST1 and ST2 maintain the ON state and the initialization switch SPRE maintains the OFF state, as shown in FIG. 8D. The second switch TFT (ST2) is turned off before the first switch TFT (ST1). As a result, the source voltage Vsen of the driving TFT is sampled through the ADC and converted into digital data SEN. At this time, the source voltage (Vsen) of the driving TFT is stored in the capacitor (C). The capacitor C does not need to be formed separately because it is the parasitic capacitance of the cathode pattern.

The present invention detects a change in device characteristics of the driving TFT DT through the cathode of the OLED as described above. As a result, the present invention can omit a separate sensing wiring in the organic light emitting diode display, thereby increasing the aperture ratio of the pixel, thereby reducing the stress of the driving element and improving the image quality and lifetime of the display.

9 is a waveform diagram showing the data write and display mode operation of the pixel.

Referring to FIG. 9, in the data write and display mode, the scan pulse SCAN and the sense pulse SENSE are simultaneously generated at a high logic level (H). In the data write and display mode, the initialization control signal is held at the high logic level (H) and the sampling control signal is held at the low logic level (L). In the data write and display mode, the first and second switch TFTs ST1 and ST2 are simultaneously turned on, and the initialization switch SPRE remains on. In the data write and display mode, the sampling switch SAM maintains the OFF state. As a result, the pixel operates as shown in FIG. 5 in the data write and display mode. In the data write and display mode, the data voltage (Vdata) of the input image is charged to the first node (n1) and set to the initial voltage (Vpre) at the source of the drive TFT (DT). In the data write and display mode, when the scan pulse SCAN and the sense pulse SENSE are inverted to a low logic level, a current flows to the OLED through the drive TFT DT to increase the source voltage of the drive TFT DT, The gate voltage Vg of the driving TFT DT rises by the source following. Therefore, in the data write and display mode, the OLED can emit light after the scan pulse SCAN and the sense pulse SENSE are inverted to a low logic level.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Data driver 13: Gate driver
14: Data line 15: Gate line
20: data modulation unit CAT: cathode pattern
RIB: barrier EL: organic compound layer of OLED
ANO: anode of OLED

Claims (6)

A first switch TFT connecting the data line and the first node in accordance with a scan pulse from the first gate line;
A driving TFT including a gate connected to the first node, a drain to which a high potential driving voltage is supplied, and a source connected to an anode of the organic light emitting diode via a second node;
A storage capacitor coupled between the first node and the second node; And
And a sensing circuit for sensing a source voltage of the driving TFT through the cathode of the organic light emitting diode when the second switch TFT is turned on. The method according to claim 1,
Wherein the cathode includes a plurality of cathode patterns having stripe shapes in a column direction crossing the first and second gate lines and separated from each other with a partition wall therebetween,
And organic light emitting diodes of pixels arranged in the column direction are connected to the cathode pattern. 3. The method of claim 2,
The sensing circuit
The source of the driving TFT and the anode of the organic light emitting diode are connected through the second node to the cathode pattern through a third node, A second switch TFT connecting a third node;
An analog digital converter for converting the source voltage of the driving TFT supplied through the second switch TFT to digital data;
An initialization switch for supplying an initialization voltage to the third node in response to an initialization control signal; And
And a sampling switch for supplying a source voltage of the driving TFT to the analog digital converter in response to a sampling control signal. The method of claim 3,
The analog-to-digital converter senses the source voltage of the driving TFT in the sensing mode, converts the source voltage into digital data,
Wherein the pixels display data of an input image in a data write and display mode. 5. The method of claim 4,
The sensing mode is divided into an initialization period, a programming period, a sensing period, and a sampling period,
In the initialization period, the scan pulse and the initialization control signal are generated at an on level in the initialization period to turn on the first switch TFT and the initialization switch to apply a sensing data voltage to the gate of the drive TFT Supplying the initialization voltage to the cathode pattern,
During the programming period, the scan pulse, the sense pulse, and the initialization control signal are generated at an on level to turn on the first and second switch TFTs, turn on the initialization switch, Applying the initializing voltage to the source of the driving TFT, applying the initializing voltage to the gate of the driving TFT, connecting the anode to the cathode pattern,
The scan pulse and the sense pulse are generated at the on level and the initialization control signal is inverted to the off level so that the cathode pattern is floated and the source voltage of the drive TFT is higher than the gate voltage of the drive TFT To a voltage obtained by subtracting the threshold voltage of the TFT,
During the sampling period, the scan pulse, the sense pulse, and the sampling control signal are generated at the on level and the initialization control signal is maintained at the off level, so that the source voltage of the drive TFT is sampled through the analog digital converter, An organic diode display which is converted. 6. The method of claim 5,
In the data write and display mode, the scan pulse and the sense pulse are simultaneously generated to an on logic level, then are simultaneously inverted to an off level, the initialization control signal is maintained at an on level, and the sampling control signal is maintained at an off level Display device.

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