KR20160079409A - Thin film transistor array substrate - Google Patents

Abstract

The present application provides a thin film transistor array substrate which is capable of facilitating a repair of separating a defective sensing transistor from a reference line. According to an embodiment of the present application, the thin film transistor array substrate comprises: a reference line which extends in a second direction; and a third transistor which corresponds to each of a plurality of sub-pixel regions and is connected to the reference line. The third transistor of each of first and second sub-pixel regions among the plurality of sub-pixel regions comprises first and second gate electrodes which are insulated from an active layer, overlap the active layer, and are respectively disposed above and below the active layer, and the entire region of the second gate electrode overlaps the first gate electrode in the third transistor of the second sub-pixel region adjacent to the reference line.

Description

[0001] THIN FILM TRANSISTOR ARRAY SUBSTRATE [0002]

The present invention relates to a thin film transistor array substrate, and more particularly, to a thin film transistor array substrate applicable to an organic light emitting display device (OLED).

As the era of informationization becomes full-scale, the display field for visually displaying electrical information signals is rapidly developing. Accordingly, studies have been continuing to develop performance such as thinning, lightening, and low power consumption for various flat display devices.

Typical examples of such flat panel display devices include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display (FED) An electroluminescence display device (ELD), an electro-wetting display device (EWD), and an organic light emitting display device (OLED).

Such flat panel display devices necessarily include a flat panel display panel for realizing an image. A flat panel display panel is a structure in which a unique light emitting material or a polarizing material is interposed between a pair of oppositely facing substrates.

In addition, when the flat panel display panel is driven in the active matrix driving mode (active matrix driving mode), one of the pair of substrates of the flat panel display panel is provided as a thin film transistor array substrate. The thin film transistor array substrate defines a plurality of sub pixel regions in the display region, and independently drives the light emission of each sub pixel region.

On the other hand, the organic light emitting display OLED includes a plurality of organic light emitting elements corresponding to a plurality of sub pixel regions, and displays an image using an organic light emitting element that is a self light emitting type element. The organic light emitting device includes first and second electrodes facing each other and a light emitting layer formed between the first and second electrodes and an organic light emitting material therebetween. This organic light emitting element emits light based on the driving current between the first and second electrodes.

1 is an equivalent circuit diagram showing each sub pixel region of a thin film transistor array substrate provided in a general organic light emitting diode display.

As shown in FIG. 1, a general thin film transistor array substrate includes a switching transistor SW_TR, a driving transistor DR_TR, a storage capacitor Cst, and a sensing transistor SE_TR corresponding to each sub pixel region.

When the switching transistor SW_TR is turned on based on the gate signal Vgate, the switching transistor SW_TR turns on the driving transistor DR_TR in accordance with the data signal Vdata of the data line. At this time, the storage capacitor Cst is charged by the output signal of the switching transistor SW_TR.

The driving transistor DR_TR is turned on based on the output signal of the switching transistor SW_TR or the storage capacitor Cst and supplies the driving current corresponding to the driving power supply VDD of the power supply line to the organic light emitting diode OLED.

When the driving transistor DR_TR is turned on, the organic light emitting element OLED emits light based on the driving current corresponding to the voltage difference between the driving power supply VDD and the common power supply VSS.

The sensing transistor SE_TR is turned on based on the sense signal Vsense. With this sensing transistor SE_TR, the first node N1 between the driving transistor DR_TR and the organic light emitting element OLED is initialized based on the reference signal Vref of the reference line.

Although not shown in detail in FIG. 1, a reference line for supplying a reference signal Vref corresponds to a unit pixel region including two or more sub pixel regions that are adjacent to each other and emit different colors. That is, the reference lines are shared by two or more sensing transistors SE_TR included in each unit pixel region. The sensing transistor SE_TR is connected to the organic light emitting diode OLED through the first node N1.

Accordingly, when the sensing transistor SE_TR of one of the sub pixel regions is defective, not only the corresponding sub pixel region but also other sub pixel regions sharing the reference line to which the defective sensing transistor SE_TR is connected, There is a problem that it can be diffused. Therefore, a repair is required to separate the bad sensing transistor SE_TR from the reference line.

The present invention provides a thin film transistor array substrate which can be provided in an organic light emitting display, and which can facilitate repairing detaching a defective sensing transistor from a reference line.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: first and second data lines extending in a second direction crossing the first direction and mutually adjacent to define a plurality of sub pixel regions together with a gate line; A reference line extending in the second direction and neighboring the second data line; And a third transistor corresponding to each of the plurality of sub pixel regions and connected to the reference line, wherein the third transistor of each of the first and second sub pixel regions of the plurality of sub pixel regions is isolated from the active layer And a first and a second gate electrode overlapping the active layer and respectively disposed at the lower and upper portions of the active layer, wherein in the third transistor of the second sub-pixel region adjacent to the reference line, And the entire region of the gate electrode overlaps with the first gate electrode.

The present invention also provides a liquid crystal display device comprising: first and second data lines extending in a second direction intersecting with the first direction and mutually adjacent to define a plurality of sub pixel regions together with a gate line; A reference line extending in the second direction and neighboring the second data line; And a third transistor corresponding to each of the plurality of sub pixel regions and connected to the reference line, wherein the third transistor of each of the first and second sub pixel regions of the plurality of sub pixel regions is isolated from the active layer Wherein the third transistor of the second sub-pixel region adjacent to the reference line comprises a first transistor and a second transistor, the first and second gate electrodes overlapping the active layer and respectively disposed below and above the active layer, A first gate electrode which is insulated and overlaps with the active layer and is disposed under the active layer.

A thin film transistor array substrate according to an embodiment of the present invention includes a transistor corresponding to each sub pixel region and connected to a reference line, the transistor being disposed at the top and bottom of the active layer and isolated from the active layer, And a second gate electrode. At this time, among the plurality of sub-pixel regions, the transistors of the sub-pixel region adjacent to the reference line include a second gate electrode whose entire region overlaps the first gate electrode. As a result, the margin for the repair point between the transistor and the reference line in the sub pixel region adjacent to the reference line is prevented from being reduced by the second gate electrode. Therefore, when the transistor in the sub pixel region adjacent to the reference line is defective, Repair can be easily carried out to separate the transistor from the reference line.

According to another embodiment of the present invention, the transistor of the sub pixel region adjacent to the reference line includes only the first gate electrode and does not include the second gate electrode. This eliminates the possibility that the reference line may include a region overlapping with the second gate electrode due to a process error or the like, so that the margin for the repair point between the reference line and the transistor in the adjacent sub pixel region and the reference line is The reduction by the second gate electrode can be completely eliminated.

1 is an equivalent circuit diagram showing each sub pixel region of a thin film transistor array substrate provided in a general organic light emitting diode display.
2 is an equivalent circuit diagram showing first to fourth sub pixel regions arranged in parallel in the thin film transistor array substrate according to each embodiment of the present application.
3 is a plan view of a third transistor of the first and second sub pixel regions according to the first embodiment of the present invention.
4 is a cross-sectional view showing I-I 'of Fig.
5 is a cross-sectional view showing II-II 'of FIG.
FIG. 6 is an equivalent circuit diagram of first and second sub pixel regions showing the first and second repair points in FIG. 3; FIG.
7 is a plan view showing a case where the second gate electrode includes a region overlapping with an extended reference line.
8 is a sectional view showing III-III 'in Fig.
FIG. 9 is an equivalent circuit diagram of first and second sub pixel regions showing the first and second repair points in FIG. 7; FIG.
10 is a plan view showing a third transistor of the first and second sub pixel regions according to the second embodiment of the present invention.

Hereinafter, a thin film transistor array substrate according to each embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is an equivalent circuit diagram showing first to fourth sub pixel regions arranged in parallel in the thin film transistor array substrate according to each embodiment of the present application. 3 is a plan view showing a third transistor of the first and second sub pixel regions according to the first embodiment of the present invention, FIG. 4 is a cross-sectional view of FIG. 3 I-I ', FIG. 5 is a cross- Quot; -II ". FIG. 6 is an equivalent circuit diagram of first and second sub pixel regions showing the first and second repair points in FIG. 3; FIG. 7 is a plan view showing a case where the second gate electrode includes a region overlapping with an extended reference line, FIG. 8 is a sectional view showing III-III 'in FIG. 7, FIG. 9 is a cross- 2 is an equivalent circuit diagram of first and second sub pixel regions showing two repair points. 10 is a plan view showing a third transistor of the first and second sub pixel regions according to the second embodiment of the present invention.

2, the thin film transistor array substrate according to the first embodiment of the present invention includes a gate line GL extending in a first direction (the lateral direction in FIG. 2), a gate line GL, The first and second data lines DL1 and DL2 extend in a second direction (vertical direction in FIG. 2) intersecting the first direction to define the pixel regions SP1, SP2, SP3 and SP4, A power supply line PL extending in two directions and adjacent to the first data line DL1, a reference line RL extending in the second direction and adjacent to the second data line DL2, T1, T2, and T3, a storage capacitor Cst, and an organic light emitting diode (OLED) corresponding to the first, second, third, and fourth transistors SP2, SP3, and SP4.

The first transistor T1 of each of the sub pixel regions SP1, SP2, SP3 and SP4 is connected between the gate line GL and one of the first and second data lines DL1 and DL2, . This first transistor T1 turns on-off based on the gate signal of the gate line GL. When the first transistor T1 is turned on, the first transistor T1 outputs a signal to turn on the second transistor T2 based on the data signal of the first or second data line DL1 or DL2. That is, the first transistor T1 is an element for switching whether each sub pixel region is driven or not.

The second transistor T2 is connected to the first transistor T1 and the power supply line PL and is connected to the organic light emitting diode OLED. The second transistor T2 is turned on based on the output signal of the first transistor T1. When the second transistor T2 is turned on, the second transistor T2 supplies the driving current to the organic light emitting diode OLED based on the driving power supplied from the power supply line PL. That is, the second transistor T2 is a device for supplying driving current to the organic light emitting device OLED of each sub pixel area.

The organic light emitting element OLED emits light based on the driving current supplied through the second transistor T2.

The storage capacitor Cst is charged according to the output signal of the first transistor T1. Since the second transistor T2 is turned on not only by the output signal of the first transistor T1 but also by the voltage charged in the storage capacitor Cst, the turn-on period of the second transistor T2 is the same as that of the storage capacitor Cst Corresponds to the charging voltage.

The second transistor T2 is an element for converting the driving power supplied through the power supply line PL into a current to supply a driving current to the organic light emitting diode OLED. Accordingly, the second transistor T2 is gradually deteriorated during the turn-on period, thereby gradually increasing the threshold voltage of the second transistor T2, so that the driving current supplied to the organic light emitting element OLED can be lowered.

The thin film transistor array substrate includes a third transistor T3 for detecting characteristics of the second transistor T2 and for initializing the output terminal of the second transistor T2 to compensate for deterioration of the second transistor T2, And a reference line RL connected thereto.

Although not shown in FIG. 2, the thin film transistor array substrate further includes a sensing line (SL in FIG. 3) extending in a first direction parallel to the gate line GL.

The third transistor T3 is connected to the sensing line SL of FIG. 3 and the reference line RL and is connected to the node between the second transistor T2 and the organic light emitting diode OLED.

The third transistor T3 is turned on based on the sense signal of the sensing line (SL in Fig. 3). When the third transistor T3 is turned on, a node between the second transistor T2 and the organic light emitting diode OLED is initialized based on the reference signal of the reference line RL, The voltage level of the node between the organic light emitting diode OLED and the OLED is transferred to the reference line RL.

At this time, based on the voltage level of the node between the second transistor T2 and the organic light emitting diode OLED transferred to the reference line RL, characteristics such as threshold voltage and mobility of the second transistor T2 are detected .

The reference lines RL are shared by the third transistors T3 of the first to fourth sub pixel regions SP1, SP2, SP3 and SP4 arranged on both sides of the reference line RL so as to be parallel to each other.

The first and second sub pixel regions SP1 and SP2 are disposed between any one power supply line PL and the reference line RL and are connected to each other through the first and second data lines DL1 and DL2. Neighborhood. The third and fourth sub pixel regions SP3 and SP4 are disposed between the other power supply line PL and the reference line RL and are connected to the first and second data lines DL1 and DL2 They are neighbors.

Illustratively, the first through fourth sub pixel regions SP1, SP2, SP3, and SP4 arranged in parallel to each other with respect to the reference line RL emit different colors, And may be defined as any one unit pixel region.

In the case of the first and fourth sub pixel regions SP1 and SP4 disposed between the first data line DL1 and the power source line PL, the third transistor T3 is connected to the first and second data lines DL1, To the reference line RL through a separate bridge pattern (BR in FIG.

On the other hand, the third transistor T3 of the second sub pixel region SP2 disposed between the second data line DL2 and the reference line RL is connected to the reference line RL and the third transistor T3 without a separate bridge pattern BR. Directly connected.

Specifically, as shown in Fig. 3, the sensing line SL extends in the first direction (the lateral direction in Fig. 3). The bridge pattern BR corresponds to two or more sub pixel regions SP1 and SP2 and extends in the first direction in parallel with the sensing line SL and crosses the reference line RL. Illustratively, the bridge pattern BR may correspond to each unit pixel region composed of two or more sub pixel regions SP1, SP2, SP3, SP4 emitting different colors.

The first and second data lines DL1 and DL2, the power supply line PL and the reference line RL extend in the second direction (vertical direction in FIG. 3) so as to intersect the sensing line SL.

The first and second data lines DL1 and DL2 are disposed adjacent to each other.

The power supply line PL is disposed adjacent to the first data line DL1 with the first sub pixel area SP1 therebetween.

The reference line RL is disposed adjacent to the second data line DL2 with the second sub pixel region SP2 therebetween.

The third transistor T3 of each of the first and second sub pixel regions SP1 and SP2 includes a first gate electrode GE1 which is insulated from the active layer ACT and is respectively disposed below and above the active layer ACT, And a second gate electrode GE2.

Here, the first gate electrode GE1 is formed on the substrate (101 in Figs. 4 and 5) and insulated from the active layer (ACT) by the gate insulating film (102 in Fig. 4 and Fig. 5). The second gate electrode GE2 is formed on the interlayer insulating film (103 in Figs. 4 and 5) covering the active layer ACT, thereby being insulated from the active layer ACT.

The second gate electrode GE2 is connected to the first gate electrode GE1 and the sensing line SL through the first contact hole CT1 passing through the gate insulating film 102 and the interlayer insulating film 103. [ The entire area of the second gate electrode GE2 overlaps the first gate electrode GE1, i.e., the sensing line SL.

In addition, the third transistor T3 further includes a source electrode SE and a drain electrode DE which are mutually spaced on the active layer ACT and contact different portions of the active layer ACT.

4 and 5, the third transistor T3 of each of the first and second sub pixel regions SP1 and SP2 is formed on the substrate 101 and is connected to the sensing line SL, An active layer ACT formed on the gate insulating film 102 and overlapping with the first gate electrode GE1; a first insulating film 102 formed on the gate insulating film 102 and spaced apart from each other, A source electrode SE and a drain electrode DE which are in contact with different portions of the active layer ACT and a channel between the source electrode SE and the drain electrode DE in the active layer ACT, And a second gate electrode (GE2) overlapping the region.

The first gate electrode GE1 may be formed on the substrate 101 and branched in the sensing line SL or may be provided as a part of the sensing line SL. Here, the metal pattern in the first direction, that is, the gate line (GL in FIG. 2) and the bridge pattern BR, which are connected to the first gate electrode GE and the sensing line SL and the first gate electrode GE1, , Is formed on the substrate 101 and covered with the gate insulating film 102. [

The active layer ACT is formed on the gate insulating film 102 and overlaps with the first gate electrode GE1. Illustratively, the entire region of the active layer ACT may overlap the first gate electrode GE1.

The third thin film transistor T3 is formed so as to cover at least the channel region of the active layer ACT in order to prevent the channel region between the source electrode SE and the drain electrode DE in the active layer ACT from being damaged. And may further include an etch stopper (ES).

The source electrode SE and the drain electrode DE are spaced apart from each other with the channel region of the active layer ACT interposed therebetween, thereby contacting different portions of the active layer ACT.

One of the source electrode SE and the drain electrode DE of the third transistor T3 is connected to the reference line RL and the other one of the source electrode SE and the drain electrode DE, Drain electrode DE) is connected to a node between the second transistor (T2 in Fig. 2) and the organic light emitting element (OLED in Fig. 2).

Each of the active layer ACT formed on the gate insulating film 102, the etch stopper ES, the source electrode SE and the drain electrode DE includes an interlayer insulating film 103 formed on the entire surface of the gate insulating film 102, .

A reference line RL connected to either the source electrode SE or the drain electrode DE and a metal pattern in the second direction or the first and second data lines DL1 and DL2 and a power supply line PL are formed on the gate insulating film 102 and covered with the interlayer insulating film 103 in the same manner as the source electrode SE and the drain electrode DE.

The second gate electrode GE2 is formed on the interlayer insulating film 103 and overlaps the channel region of the active layer ACT. 4 and 5, the second gate electrode GE2 is electrically connected to the substrate 101 (not shown) through the first contact hole (CT1 in FIG. 4) passing through the gate insulating film 102 and the interlayer insulating film 103, ) Or the sensing line (SL) on the first gate electrode (GE1).

On the other hand, as shown in FIG. 4, a first sub pixel region SP1 (first sub pixel region) SP2 spaced apart from the reference line RL via the first and second data lines DL1 and DL2 and the second sub pixel region SP2, One of the source electrode SE and the drain electrode DE of the third transistor T3 (for example, the source electrode SE) is connected to the first and second data lines DL1 and DL2 And is connected to the reference line RL via the avoiding bridge pattern BR.

The bridge pattern BR is connected to the third transistor T3 and the reference line RL through the second contact hole CT2 passing through the gate insulating film 102 in FIG.

Accordingly, the first repair point RP1 for the third transistor T3 in the first sub pixel region SP1 is selected as a portion where the short failure due to the laser cutting in the bridge pattern BR does not occur . That is, when the third transistor T3 of the first sub-pixel region SP1 is defective, a portion of the bridge pattern BR that does not overlap with another metal pattern but is spaced apart from the other metal pattern by a predetermined distance or more, When the repair point RP1 is irradiated with a laser, a repair which separates the defective third transistor T3 from the reference line RL can be implemented.

Although not shown in FIGS. 3 and 4, the third transistor T3 of the fourth sub pixel region (SP4 in FIG. 2) disposed between the first data line DL1 and the other power source line PL is defective , A part of the bridge pattern BR that does not cause a short defect due to laser cutting is selected as a repair point for irradiating the laser.

On the other hand, as shown in FIG. 5, in the case of the second sub pixel region SP2 disposed between the second data line DL2 and the reference line RL and adjacent to the reference line RL, the third transistor T3 (For example, the source electrode SE) of the source electrode SE and the drain electrode DE of the pixel electrode (not shown) is formed directly in the form of being directly connected to the reference line RL.

The second repair point RP2 for the third transistor T3 of the second sub pixel region SP2 is defective when the laser cut of the reference line RL extending toward the second sub- As shown in FIG. That is, when the third transistor T3 of the second sub-pixel region SP2 is defective, the reference line RL extending from the second sub-pixel region SP2 does not overlap with another metal pattern, When a laser is irradiated to the second repair point RP2 selected as a part spaced apart from the predetermined interval, a repair which separates the defective third transistor T3 from the reference line RL can be implemented.

At this time, according to the first embodiment of the present invention, the entire area of the second gate electrode GE2 on the interlayer insulating film 103 overlaps the first gate electrode GE1, so that the second gate electrode GE2 is divided into the second sub- But does not include a region that overlaps only the reference line RL extending to the pixel region SP2 side. Therefore, the margin MG for the second repair point RP2 corresponds only to the separation distance between the first gate electrode GE1 and the bridge pattern BR, and is not reduced by the second gate electrode GE2 .

As described above, the second repair point RP2 between the third transistor T3 and the reference line RL in the second sub pixel area SP2 is secured with a sufficient margin (MG) such that no short failure occurs . 6, when the third transistor T3 of the second sub pixel region SP2 is defective, the third transistor T3, which is defective, is turned on by using the second repair point RP2 Repairing to separate from the reference line RL can be easily performed.

On the other hand, unlike the first embodiment, when a part of the second gate electrode GE2 overlaps with the reference line RL extending toward the second sub-pixel region SP2, the second gate electrode GE2 There is a problem that the margin (MG) of the two repair points (RP2) is reduced.

7 and 8, in the general thin film transistor array substrate, the second gate electrode GE2 'of the third transistor T3 is connected to the first gate electrode GE1 ). ≪ / RTI > At this time, the reference line RL extending toward the second sub-pixel region SP2 includes a region overlapping only the second gate electrode GE2 'protruding out of the first gate electrode GE1. Therefore, the margin MG 'for the second repair point RP2 between the third transistor T3 and the reference line RL of the second sub pixel region SP2 is equal to that of the reference line RL between the reference line RL and the second gate electrode RL, (GE2 ') is reduced by the overlapping area. As a result, the second repair point RP2 can not have a margin (MG ') sufficient to prevent a shot defect caused by the laser. That is, when the third transistor T3 of the second sub pixel region SP2 is defective, the second repair point RP2 of the narrow margin MG 'is used to detect the defective second sub pixel region SP2 Quot;) from the reference line RL is practically impossible.

As described above, when the third transistor T3 is disconnected from the reference line RL using the second repair point RP2 of the narrow margin MG 'in the case of a general thin film transistor substrate, a short failure occurs The risk is high.

7 and 9, if the third transistor T3 of the second sub pixel region SP2 adjacent to the reference line RL in the general thin film transistor substrate is defective, the second repair point The third transistor T3 which is defective may be connected to the organic light emitting element OLED (OLED) by using the third repair point RP3 between the third transistor T3 and the organic light emitting element ) Can be implemented. However, since the defective third transistor T3 is continuously connected to the reference line RL in this way, there is a problem that it is impossible to prevent the spread of defective defects due to the defective third transistor T3 .

As described above, according to the first embodiment of the present invention, the third transistor T3 of the sub pixel regions SP2 and SP3 adjacent to the reference line RL is formed by overlapping the first gate electrode GE1 with the first region The second repair point RP2 between the third transistor T3 and the reference line RL can secure a sufficient margin MG so as to prevent a short circuit failure, And the third transistor T3 of the sub pixel areas SP2 and SP3 adjacent to the reference line RL is defective.

10, in the thin film transistor array substrate according to the second embodiment of the present invention, the third transistor T3 of the second sub pixel region SP2 adjacent to the reference line RL is electrically connected to the interlayer insulating film 5) of the second gate electrode (GE2 of FIG. 5) formed on the second gate electrode (not shown) of the first embodiment. Therefore, redundant description will be omitted below.

That is, according to the second embodiment, the first sub pixel region SP1 separated from the reference line RL via the first and second data lines DL1 and DL2 and the second sub pixel region SP2, The third transistor T3 includes the second gate electrode GE2 formed on the interlayer insulating film 103 (FIG. 4).

On the other hand, in the case of the second sub pixel region SP2 adjacent to the reference line RL, the margin MG for the second repair point RP2 between the third transistor T3 and the reference line RL 5). In order to reliably secure the gate electrode, only the first gate electrode GE1 on the substrate (101 in Fig. 5) is included and does not include the second gate electrode (GE2 in Fig. 5) on the interlayer insulating film (103 in Fig. 5).

In this case, the region where the reference line RL extending to the second sub pixel region SP2 overlaps the second gate electrode GE2 due to a process error at the time of forming the second gate electrode GE2 is completely The possibility that the margin MG for the second repair point RP2 is reduced by the second gate electrode GE2 can be completely excluded.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

RL: Reference line
DL1, DL2: first and second data lines
PL: power line GL: gate line
SP1, SP2, SP3, and SP4: first, second, third, and fourth sub-
T1, T2, T3: First, second, and third transistors
Cst: Storage capacitor OLED: Organic light emitting device
SL: sensing line GE1, GE2: first and second gate electrodes
ACT: active layer SE, DE: source electrode, drain electrode
BR: Bridge patterns CT1 and CT2: First and second contact holes
RP1: First repair point RP2: Second repair point
MG: margin for second repair point
101: substrate 102: gate insulating film
103: Interlayer insulating film RP3: Third repair point

Claims (8)

A gate line extending in a first direction;
First and second neighboring data lines extending in a second direction crossing the first direction so that a plurality of sub-pixel regions are defined;
A power supply line extending in the second direction and adjacent to the first data line;
A reference line extending in the second direction and neighboring the second data line;
A first transistor corresponding to each of the plurality of sub pixel regions, the first transistor being connected to either one of the first and second data lines and the gate line;
A second transistor which corresponds to each of the plurality of sub pixel regions and is connected to the first transistor and the power supply line and supplies a driving current to the organic light emitting element; And
And a third transistor corresponding to each of the plurality of sub pixel regions and connected to the reference line and connected to a node between the second transistor and the organic light emitting element,
The plurality of sub pixel regions include a first sub pixel region disposed between the first data line and the power source line and a second sub pixel region disposed between the second data line and the reference line,
The third transistor of each of the first and second sub pixel regions includes first and second gate electrodes which are insulated from the active layer and overlap with the active layer and are respectively disposed under and over the active layer,
The entire region of the second gate electrode overlaps with the first gate electrode in the third transistor of the second sub pixel region. A gate line extending in a first direction;
First and second neighboring data lines extending in a second direction crossing the first direction so that a plurality of sub-pixel regions are defined;
A power supply line extending in the second direction and adjacent to the first data line;
A reference line extending in the second direction and neighboring the second data line;
A first transistor corresponding to each of the plurality of sub pixel regions, the first transistor being connected to either one of the first and second data lines and the gate line;
A second transistor which corresponds to each of the plurality of sub pixel regions and is connected to the first transistor and the power supply line and supplies a driving current to the organic light emitting element; And
And a third transistor corresponding to each of the plurality of sub pixel regions and connected to the reference line and connected to a node between the second transistor and the organic light emitting element,
The plurality of sub pixel regions include a first sub pixel region disposed between the first data line and the power source line and a second sub pixel region disposed between the second data line and the reference line,
The third transistor of the first sub pixel region includes first and second gate electrodes which are insulated from the active layer and overlapped with the active layer and respectively disposed on the lower and upper sides of the active layer,
The third transistor of the second sub-pixel region includes only a first gate electrode that is isolated from the active layer and overlaps with the active layer and is disposed under the active layer. 3. The method according to claim 1 or 2,
And a sensing line extending in the first direction so as to be parallel to the gate line,
The first gate electrode is formed on the substrate and extends to the sensing line,
The active layer is formed on a gate insulating film covering the first gate electrode,
Wherein the second gate electrode is formed on an interlayer insulating film covering the active layer and connected to the first gate electrode through a first contact hole passing through the gate insulating film and the interlayer insulating film. The method of claim 3,
Wherein the third transistor is formed on the gate insulating layer and is spaced apart from each other and further comprises a source electrode and a drain electrode which are in contact with different portions of the active layer. 5. The method of claim 4,
And one of the source electrode and the drain electrode included in the third transistor of the second sub pixel region is connected to the reference line. 6. The method of claim 5,
And a part of the reference line extending to the second sub pixel region is removed when the third transistor of the second sub pixel region is defective. 5. The method of claim 4,
And a gate electrode formed on the substrate in the first direction and intersecting with the reference line, through a contact hole passing through the gate insulating film and the interlayer insulating film, And a bridge pattern connecting one of the electrode and the drain electrode and the reference line. 8. The method of claim 7,
And a portion of the bridge pattern is removed when the third transistor of the first sub pixel region is defective.

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