KR20160067239A - Memory Comprising Cell with Low Power and High Speed - Google Patents

Memory Comprising Cell with Low Power and High Speed Download PDF

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Publication number
KR20160067239A
KR20160067239A KR1020140171868A KR20140171868A KR20160067239A KR 20160067239 A KR20160067239 A KR 20160067239A KR 1020140171868 A KR1020140171868 A KR 1020140171868A KR 20140171868 A KR20140171868 A KR 20140171868A KR 20160067239 A KR20160067239 A KR 20160067239A
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South Korea
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discharge path
bit line
path portion
transistor
cell
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KR1020140171868A
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Korean (ko)
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승문 유 스캇
정민철
이현석
김준석
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(주)에이디테크놀로지
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Priority to KR1020140171868A priority Critical patent/KR20160067239A/en
Publication of KR20160067239A publication Critical patent/KR20160067239A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory device is disclosed. The cell of the memory device of the present invention further includes a discharge path for discharging the precharged voltage to the bit line or the bit line bar in the read operation so that the voltage difference between the bit line and the bit line bar can be rapidly advanced. The cell of the present invention can reduce the consumption of the standby current in the standby state other than the read operation by configuring the discharge path having the excellent current driving capability separately instead of improving the current driving ability of the conventional flip- Read operation is possible.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory device having a cell capable of high-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory capable of high-speed and low-power processing, and more particularly, to a memory device having a cell having a structure capable of reducing a standby current while improving cell access speed.

The memory has a structure in which a plurality of cells are arranged, and stores data corresponding to so-called logic '1' or logic '0' for each cell.

On the other hand, SRAM (Static Random Access Memory) is widely used in various fields because it is nonvolatile to hold data as long as the power is supplied. The requirements for ESRAM vary widely, but the demand for high-speed access and low power continues to grow. The high-speed access and low-power processing in ESRAM is also related to a control method such as correct timing of a sense amplifier enable (SAE) signal for operating a sense amplifier, Separate operation and standby current are the most important.

1 shows a unit cell of a conventional ESRAM. Referring to FIG. 1, four transistors M1, M2, M3, and M4, each of which has a flip-flop structure for storing data, and a pair of bit lines And two transistors M5 and M6 connected to the bit line pairs BL and BLB.

The first through fourth transistors M1, M2, M3, and M4 are flip-flops in which two inverters are connected to each other through an input feedback structure to store data. Each gate of the first and second transistors M1 and M2 disposed between the first power supply voltage Vdd and the second power supply voltage Vss is connected to the second node Qb, The gates of the third and fourth transistors M3 and M4, which are disposed between the first power supply voltage Vdd and the second power supply voltage Vss, are connected to the first node Q. [ The first and third transistors M1 and M3 are P-MOS transistors and the second and fourth transistors M2 and M4 are NMOS transistors.

A fifth transistor M5 of anemost type which is enabled by the word line WL is connected between the first node Q and the bit line BL and is also connected to the bit line BL by the word line WL. The sixth transistor M6 of the NMOS type which is enabled is connected between the second node Qb and the bit line bar BLB.

The word line WL maintains a logic low when the data write / read operation is not performed and the bit line BL and the bit line bar BLB are normally at the operating voltage Vdd or higher And precharged at a slightly lower voltage (Vdd-Vtn). The first node Q and the second node Qb maintain the power supply voltage Vdd or Vss according to the data stored in the cells and become complementary states with respect to each other.

For example, when the data stored in the cell is logic '1', the first node Q has the power supply voltage Vdd and the second node Qb maintains the power supply voltage Vss. Therefore, the first transistor M1 and the fourth transistor M4 of the flip-flop are turned on and the second transistor M2 and the third transistor M3 are turned off. State. In this state, when the word line WL is enabled to perform the reading process and the fifth transistor M5 and the sixth transistor M6 are turned on, the bit line BL and the first node Q and between the bit line bar BLB and the second node Qb. The precharged voltage of the bit line BLB is discharged along the path leading to the turned on sixth transistor M6 and the fourth transistor M4 while the voltage of the bit line BL is maintained. Therefore, a voltage difference (VS) is generated between the bit line BL and the bit line BLB and the voltage difference is read by a sense amplifier (not shown).

Since the speed at which data is read relates to how fast the voltage difference between the bit line BL and the bit line bar BLB occurs, the voltage precharged to the bit line BL or bit line bar BLB is discharged quickly A method of increasing the data access speed by increasing the current driving capability of the transistors M2 and M5 or M4 and M6 is used.

Meanwhile, the memory cell can be designed as a dual-port structure capable of reading data stored in the same cell through at least two ports. In a dual-port memory architecture, a reduction in processing speed occurs when data is read simultaneously on two ports. In other words, the voltages precharged to the two bit lines BL / BL-1 and BLB / BLB-1 are simultaneously discharged through the second transistor M2 or the fourth transistor M4 of the cell The discharge is delayed and the entire read operation is delayed. The second transistor M2 and the fourth transistor M4 must have a larger current driving capability in comparison with that of the single port cell to maintain the similar or the same speed.

In order to improve the current driving capability of a transistor, conventionally, a method of increasing the size of the transistor, reducing the length, or lowering the threshold voltage of the transistor has been used.

However, if the current driving capability of the transistor is improved in order to improve the reading speed of the cell data, an inevitable problem of increasing the standby current consumed in the standby state occurs.

In other words, when there is no cell access, most of the standby current flows through the short channel current flowing through the channel of the turned off transistor and the gate terminal of the transistor to the substrate Gate leakage current (gate leakage). If the current driving capability in the turn-on state is increased, the short-channel current in the turn-off state increases. The gate leakage current increases as the operating voltage increases with respect to the thickness of the same gate oxide (Oxide).

Therefore, if the transistor's turn-on current driving capability is increased to improve the read speed of the cell, the standby current in the standby state also increases. Particularly, as the semiconductor process is further refined, the threshold voltage of the transistor is further lowered, and the short-channel current is further increased, so that the quiescent current becomes a more serious problem.

Quiescent current problems are an important issue that must be addressed in products that require low power or in products that have more memory capacity. For example, even in the case of a 0.18 탆 process, the short channel current per 탆 of the transistor is several to several tens of 므로. Therefore, if the leakage current per cell combined with the short channel current and the gate leakage current is 10 ㎁ and the total memory capacity is 1 mega Bit, 1024 × 1024), the standby current becomes approximately 10.5 mA (= 10 × 1024 × 1024), which can not be ignored.

In summary, in order to improve the access speed of the cell, the larger the turn-on current driving capability of the transistor, the more the problem of overcoming the quiescent current occurs. This problem becomes more serious as the process becomes finer.

[Related Technical Literature]

Korean Patent Publication No. 1996-0036081 (Synchronous ESRAM device)

The present invention proposes a method for improving the speed of the SRAM by reducing the time during which the word line is turned on during the operation of the chip, thereby reducing the current consumption and improving the operating speed by precharging the bit line and the bit line. However, this approach uses a completely different approach from the present invention.

An object of the present invention is to solve the above problems and provide a memory device having a cell having a structure capable of reducing a standby current while improving a cell access speed.

In order to achieve the above object, the present invention is applied to a memory device in which a plurality of cells are arranged. The cell of the present invention further includes a secondary lead portion in a storage portion corresponding to a conventional cell. The auxiliary lead portion provides a separate discharge path for assisting the discharge of the voltage of the bit line and the bit line bar when the word line is enabled for a read operation.

For example, the auxiliary lead portion may include a first discharge path portion and a second discharge path portion. A first discharge path portion is provided between the bit line and the second power supply voltage to provide a discharge path for discharging the precharged voltage to the bit line when the word line is enabled for a read operation, A first switch controlled by a line and a second switch controlled by the second node voltage may be designed in a structure in which they are connected in series.

A second discharge pathway portion is provided between the bit line and the second power supply voltage to provide a discharge path for discharging the precharged voltage to the bit line bar when the word line is enabled for a read operation, And a fourth switch controlled by the first node voltage are connected in series to each other.

According to an embodiment, the cell may further include a fifth switch that is turned on during a data read operation and connects the first discharge path portion and the second discharge path portion to the second power supply voltage. The fifth switch connects the first discharge path portion and the second discharge path portion to the second power supply voltage during a read operation.

Meanwhile, when the memory has a plurality of different cells sharing the bit line and the bit line bar, the fifth switch may be provided for each cell, but may be shared among the plurality of different cells, The first discharge path portion and the second discharge path portion may also be connected to the second power supply voltage.

Here, the fifth switch is controlled by a separate control signal, and the control signal is enabled while the word line WL is enabled to turn on the fifth switch. On the other hand, even when the bit line and the bit line bar are shared with a plurality of different cells and the fifth switch is provided for each cell, the fifth switch for each cell may be simultaneously controlled by one control signal .

In the above example, the first to fourth switches may be NMOS transistors, and the fifth switch may be a PMOS transistor.

The present invention is also applicable to a multiport cell structure in which one cell is connected to a plurality of sets of bit lines, bit line bars and word lines. In this case, the cell of the present invention may further include a pair of discharge path portions corresponding to the first discharge path portion and the second discharge path portion corresponding to the respective bundles.

For example, in the case of a dual port cell, each cell further includes a third discharge path portion and a fourth discharge path portion in addition to the first discharge path portion, the second discharge path portion, and the fifth switch.

A third discharge path portion is provided between the second bit line and the fifth switch to provide a discharge path for discharging the precharged voltage to the second bit line when the second word line is enabled for a read operation A fourth discharge path portion provided between the second bit line and the fifth switch to provide a discharge path for discharging the precharged voltage to the second bit line bar when the second word line is enabled for a read operation can do.

According to the embodiment, the third discharge path portion may be designed to have a structure in which a sixth switch controlled by the second word line and a seventh switch controlled by the second node voltage are connected in series, The fourth discharge path portion may be designed to have a structure in which an eighth switch controlled by the second word line and a ninth switch controlled by the first node voltage are connected in series.

The memory according to the present invention can achieve a high-speed read operation by configuring a separate discharge path using a transistor having excellent current driving capability. This method is completely different from the conventional method, that is, the method of improving the current driving capability of the transistors of the flip-flop structure which actually stores the data in order to improve the data processing speed in the read operation.

In addition, since the separate discharge path according to the present invention is designed to operate only in the read operation, the consumption of the standby current in the standby state other than the read operation can be minimized. In addition, the cell structure of this structure can be designed to reduce the current driving capability of the transistors that form the flip-flop structure while maintaining the speed of the read operation, thereby improving the processing speed compared to the prior art, Can be reduced.

The present invention can be applied not only to a memory cell of a single port structure but also to a memory of a multiport structure. In the case of a multiport cell, the effect of reducing a standby current in a standby state is further increased.

1 is a circuit diagram of a unit cell of a conventional ESRAM,
2 is a circuit diagram of a single port SRAM cell according to an embodiment of the present invention.
3 is a timing diagram provided in the operation description of the cell of FIG. 2, and
4 is a circuit diagram of a multi-port SRAM cell according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings.

Referring to FIG. 2, a memory cell 200 according to the present invention includes a storage part 210 and an auxiliary lead part 230, And the auxiliary lead unit 230 is added to the storage unit 210. The cell structure of the present invention can be applied not only to a single-port RAM structure but also to a multi-port RAM structure. A plurality of cells 200 of the present invention are collectively arranged to form one memory.

The storage unit 210 includes the first through sixth transistors M1, M2, M3, M4, M5, and M6, and has the same structure as that of the conventional ESRAM shown in FIG. The storage unit 210 stores data of the SRAM cell 200 of the present invention and performs a read and write operation of the cell of the conventional SRAM, .

However, since the cell 200 of the present invention includes the auxiliary lead unit 230 in order to improve the data reading speed, the storage unit 210 of the present invention, in which cell data is mainly stored, It is not necessary to adopt a design for increasing the current driving capability. Rather, each of the transistors M1, M2, M3, M4, M5, and M6 of the storage unit 210 may be designed to increase the threshold voltage, decrease the size, or increase the length, A design that minimizes current is possible.

The auxiliary lead unit 230 operates only in the read operation. The auxiliary lead portion 230 provides a separate discharge path for assisting the discharge of the voltages of the bit line BL and the bit line bar BLB when the word line WL is enabled for a read operation, The speed of the read operation performed by the controller 210 is increased. To this end, the auxiliary lead portion 230 includes a first discharge path portion 231 and a second discharge path portion 233.

The first discharge path portion 231 is provided between the bit line BL and the second power source voltage Vss so that the precharged voltage is applied to the bit line BL when the word line WL is enabled for a read operation Thereby providing a path for discharging. The second discharge path portion 233 is provided between the bit line bar BLB and the second power source voltage Vss so that the bit line bar BLB is precharged when the word line WL is enabled for a read operation Thereby providing a path for discharging the voltage.

According to the embodiment, the first discharge path portion 231 may be designed such that a first switch controlled by a word line WL and a second switch controlled by a second node (Qb) voltage are connected in series . In the example of FIG. 2, the first switch and the second switch are the seventh and eighth transistors M7 and M8 (N-MOS) transistors arranged between the bit line BL and the second power supply voltage Vss )to be.

The seventh transistor M7 has a drain terminal connected to the bit line BL, a source terminal connected to the drain terminal of the eighth transistor M8, a gate terminal connected to the word line WL, . The gate terminal of the eighth transistor M8 is connected to the second node Qb to be controlled.

The second discharge path portion 233 may be designed such that a third switch controlled by the word line WL and a fourth switch controlled by the first node (Q) voltage are connected in series. In the example of FIG. 2, the third switch and the fourth switch are the ninth and tenth transistors M9 and M10, which are the NMOS transistors arranged between the bit line bar BLB and the second power supply voltage Vss.

The ninth transistor M9 has a drain terminal connected to the bit line bar BLB, a source terminal connected to the drain terminal of the tenth transistor M10, and a gate terminal connected to the word line WL. The gate terminal of the tenth transistor M10 is connected to the first node Q and controlled. Therefore, the seventh transistor M7 and the ninth transistor M9 are controlled by the word line WL, the eighth transistor M8 is controlled by the second node Qb voltage, and the tenth transistor M10 is controlled by the word line WL. And is controlled by the first node (Q) voltage.

In the case where the first discharge path portion 231 and the second discharge path portion 233 are implemented by the seventh to tenth transistors M7, M8, M9 and M10 of FIG. 2, And a fifth switch that is turned on only during a read operation by the control signal pread. The fifth switch is turned on during a data read operation to connect the first discharge path portion 231 and the second discharge path portion 233 to the second power source voltage Vss.

According to an embodiment, the fifth switch may be provided for each of a plurality of cells, but when a plurality of cells are arranged in the form of a cell array sharing the same bit line / bit line bar, May be commonly used for each cell of the cell array. In this case, the fifth switch connects the first discharge path portion and the second discharge path portion of each cell to the second power supply voltage Vss.

In the example of FIG. 2, the fifth switch is an 11th transistor (P-MOS) transistor provided between the first discharge path portion 231 and the second discharge path portion 233 and the second power source voltage Vss, (M11). The eleventh transistor M11 is turned on by the control signal pread linked to the clock so that the first discharge path portion 231 and the second discharge path portion 233 are turned on by the second power source voltage Vss, Lt; / RTI >

It is sufficient if the control signal pread is enabled during the read operation period defined by the word line WL. According to an embodiment, the control signal pread operates in synchronism with the clock, after the word line WL is enabled before the word line WL is enabled and after the word line WL is disabled and the read operation is terminated . During the writing process, the eleventh transistor M11 remains turned off since the control signal pread is not enabled, and thus the first discharge path portion 231 of the auxiliary lead portion 230 and the second discharge path The portion 233 is not opened and does not operate.

The control signal pread may be generated separately for each cell, or may be shared for each cell array. This means that one control signal pread is commonly used for each cell array regardless of whether one fifth switch is used or a fifth switch for each cell is used. Furthermore, all of the plurality of cells included in one memory may commonly use one control signal pread.

The transistors of the first discharge path portion 231 and the second discharge path portion 233 can be designed to sufficiently improve the current driving capability. Accordingly, the seventh to tenth transistors M7, M8, M9, and M10 may be designed in such a manner that the threshold voltage is reduced, the size thereof is increased, or the length thereof is reduced. Even if the current driving capability of the transistors of the auxiliary lead unit 230 is increased, since the auxiliary lead unit 230 operates only in the cell data reading operation, it does not affect the standby current in the standby mode without data access Do not.

In contrast, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 of the storage unit 210 are connected to the bit line BL and the bit line bar BLB) is reduced, it can be designed so as to reduce the current driving capability. For example, it is known that when the threshold voltage of the transistors of the storage unit 210 is increased by about 0.2 V, the leakage current per cell is reduced by about one-tenth. Applying to the 0.18 占 퐉 process of the prior art, the quiescent current of the transistor is reduced from 10.5 mA to 1.05 占.. Thus, by reducing the standby current of the storage unit 210, it is possible to realize low power consumption per cell.

Hereinafter, the operation of the auxiliary lead unit 230 of the present invention will be described with reference to FIG. Fig. 3 shows an operation in a cell array sharing the bit line BL and the bit line bar BLB. Each cell of the array is individually selected by WL, WL [1], WL [2] which is a word line mapped to each cell, along with bit line BL / bit line bar BLB.

<Operation of cell in reading process>

Basically, for the read operation, the process of selecting the cell of FIG. 2 is the same as the conventional method. Accordingly, a cell to be accessed among a plurality of cells is selected by a word line WL, a bit line BL, and a bit line bar BLB operating in accordance with a rising edge of a clock.

Assuming that the data stored in the cell is logic '1' (or logic high) in the standby mode, the first node Q has the power supply voltage Vdd and the second node Qb maintains the power supply voltage Vss . Accordingly, the first transistor M1 and the fourth transistor M4 of the flip-flop are turned on and the second transistor M2 and the third transistor M3 are turned off. .

Since the eighth transistor M8 of the auxiliary lead portion 230 is controlled by the voltage of the second node Qb and the tenth transistor M10 is controlled by the voltage of the first node Q, M8 and the tenth transistor M10 are turned on or off by the data stored in the cell. When the first node Q has the first power supply voltage Vdd and the second node Qb maintains the second power supply voltage Vss since the cell data is logic '1' The eighth transistor M8 is turned off, and the tenth transistor M10, which is the NMOS transistor, is turned on.

Conversely, in the standby mode, if the data stored in the cell is a logical '0' (or logic low), the first node Q has the second power supply voltage Vss and the second node Qb is the first And maintains the power supply voltage Vdd. The first transistor M1 and the fourth transistor M4 are turned off and the second transistor M2 and the third transistor M3 are turned on. The eighth transistor M8 of the auxiliary lead portion 230 is turned on and the tenth transistor M10 which is the emmos is turned off.

1. An auxiliary lead section operation (t1) according to control signal enable,

At this time, unlike the conventional cell, the control signal pread is enabled at the time point t1 between the rising edge of the clock and the time point t2 when the word line WL is enabled. The control signal pread maintains a logic high at the standby state and is enabled to a logic low synchronously with the rising edge t1 of the clock and then again after the falling edge of the clock It is disabled. The control signal pread is preferably enabled at least at t1 before the time t2 when the word line WL is enabled, as shown in Figure 3, as it is desirable to keep the enable state during at least the word line WL being enabled , And is disabled at t4 after the time point t3 when the word line WL is disabled again.

When the control signal pread is enabled, the eleventh transistor M11 is turned on so that the first discharge path portion 231 and the second discharge path portion 233 are connected to the second power source voltage Vss, It enters the atmosphere.

At this time, if the data stored in the cell is logic '1', the tenth transistor M10 and the eleventh transistor M11 are turned on, and the eighth transistor M8 of the auxiliary lead unit 230 is turned off to be. On the contrary, when the data stored in the cell is logic '0', the eighth transistor M8 and the eleventh transistor M11 are turned on, and the tenth transistor M10 of the auxiliary lead unit 230 is turned off to be.

2. Operation of the storage unit by the word line (t2)

When the word line WL is enabled, the fifth transistor M5 and the sixth transistor M6 are turned on and between the bit line BL and the first node Q and between the bit line BLB and the bit line BLB. A voltage distribution occurs between the two nodes Qb. The precharged voltage of the bit line BLB is discharged along the path leading to the turned on sixth transistor M6 and the fourth transistor M4 while the voltage of the bit line BL is maintained.

When the cell data is logic '1', the precharged voltage is discharged to the bit line bar BLB because the fourth transistor M4 is turned on, and when the cell data is logic '0' (M2) is turned on, so that the precharged voltage is discharged to the bit line (BL).

Now, the sensor amplifier reads the voltage difference between the bit line BL and the bit line bar BLB.

3. Operation of auxiliary lead part by word line (t2)

On the other hand, when the word line WL is enabled, the seventh transistor M7 and the ninth transistor M9 are also turned on.

The ninth transistor M9 is turned on after the tenth transistor M10 is turned on so that the second discharge path portion 233 is completely turned on do. Since the voltage precharged to the bit line bar BLB is discharged through the second discharge path portion 233 in addition to being discharged through the path leading to the sixth transistor M6 and the fourth transistor M4, It accelerates. In addition, as described above, the discharging speed becomes faster when the current driving capability of the transistors of the second discharging path portion 233 is increased.

At this time, since the eighth transistor M8 is continuously turned off and the first discharge path portion 231 is not opened, the voltage precharged to the bit line BL remains unchanged.

If the cell data is logic '0', the seventh transistor M7 is turned on after the eighth transistor M8 is turned on, so that the first discharge path portion 231 is completely opened. The voltage precharged to the bit line BL is also discharged through the storage part 210 and discharged through the first discharge path part 231 simultaneously. Naturally, when the current driving capability of the transistors of the first discharge path portion 231 is increased, the discharge speed becomes faster and the current driving capability of the transistor of the storage portion 210 may be lowered.

3. Operation of sensor amplifier according to voltage difference in bit line pair

A sensor amplifier (not shown) operates to detect the voltage difference between the bit line BL and the bit line BLB while the voltage difference between the bit line BLa and the bit line BLB advances. And reads the data of the cell 200 by reading the voltage difference. The timing of the operation of the sensor amplifier (not shown) is a design matter of the designer, and it is sufficient if the bit line pair operates at a time when a sufficient voltage difference occurs.

At this time, when each transistor of the first discharge path portion 231 and the second discharge path portion 233 has sufficient current driving capability, the voltage difference between the bit line BL and the bit line bar BLB is very fast Lt; / RTI &gt; Therefore, according to the present invention, a sensor amplifier (not shown) can be designed to operate at a faster time. In addition, all subsequent timings can be shortened and accelerated. That is, it is possible to design a high-speed memory.

Thereafter, in conjunction with the falling edge of the clock, the word line WL is disabled again at t3, and the control signal pread at t4 And is disabled. A precharge pulse designed to operate in conjunction with the falling edge of the word line WL or the rising edge of the control signal pread operates to precharge the bit line BL and the bit line bar BLB again . In the present invention, the operation timing of the pre-charge pulse can also be performed quickly.

Nevertheless, since the first discharge path portion 231 and the second discharge path portion 233 operate only in the read operation, they do not affect the stand-by current in standby mode or write operation without data access .

Example: Dual-port memory structure < RTI ID = 0.0 >

As described above, the present invention is also applicable to a multi-port structure. If the previous single port cell is connected to one set of bit line / bit line bar / word line, then the multiport cell is connected to a plurality of sets of bit line / bit line bar / word line.

In this case, the cell of the present invention may have a pair of discharge path portions corresponding to the first discharge path portion 231 and the second discharge path portion 233 for each bit line / bit line bar / word line bundle.

For example, FIG. 4 illustrates a dual-port cell circuit to which the present invention is applied. The dual-port cell 400 performs access to a port to which a second bit line pair BL-1 / BLB-1 and a second word line WL-1 are additionally provided. Here, the second word line WL-1 is a word line different from WL [1] in Fig.

For a dual port architecture, the cell 400 further includes a port extension in the storage 210 of FIG. The port extension portion includes a 51st transistor M51 of an NMOS type connected between the first node Q and the second bit line BL-1 and enabled by the second word line WL-1, And a 61st transistor M6 of anemos type connected between the second node Qb and the second bit line bar BLB-1 and enabled by the second word line WL-1.

As described in the related art, in the dual port architecture, a reduction in the processing speed occurs when data is simultaneously read in the dual-port. In order to solve such a problem, the auxiliary lead portion 230 of the present invention may further include a third discharge path portion 235 and a fourth discharge path portion 237.

The third discharge path portion 235 is provided between the second bit line BL-1 and the fifth switch (i.e., the eleventh transistor M11) so that the second word line WL- And provides a discharge path for discharging the pre-charged voltage to the second bit line (BL-1) when enabled. The fourth discharge path portion 237 is provided between the second bit line bar BLB-1 and the eleventh transistor M11 so that when the second word line WL-1 is enabled for a read operation, And provides a discharge path for discharging the precharged voltage to the bit line bar (BLB-1).

According to the embodiment, the third discharge path portion 235 includes a sixth switch controlled by the second word line WL-1 and a seventh switch controlled by the second node (Qb) It can be designed as a connected structure. In the example of FIG. 4, the sixth switch and the seventh switch are the 71st and 81st transistors M71 and M81, which are the NMOS transistors arranged between the second bit line BL-1 and the eleventh transistor M11 . The 71st transistor M71 is controlled by the second word line WL-1 and the 81st transistor M81 is controlled by the second node Qb voltage.

The fourth discharge path portion 237 is designed such that an eighth switch controlled by the second word line WL- 1 and a ninth switch controlled by the first node (Q) voltage are connected in series to each other . In the example of FIG. 4, the eighth switch and the ninth switch are ninth and tenth transistors M91 and M101, which are the NMOS transistors disposed between the second bit line bar BLB-1 and the eleventh transistor M11, to be. The nineteenth transistor M91 is controlled by the second word line WL-1, and the eighth transistor M101 is controlled by the first node Q voltage.

The second bit line BL-1 is connected to the bit line BL, the second bit line BLB is connected to the word line WL, The operation of the third discharge path portion 235 and the fourth discharge path portion 237 is the same as the operation of the first discharge path portion 231 and the second discharge path portion 231 described above, The operation of the path unit 233 is the same. In other words, the operations of the 71st transistor M71, the 81st transistor M81, the 91st transistor M91 and the 101st transistor M101 are the same as those of the seventh transistor M7, the eighth transistor M8, The operation of each of the ninth transistor M9 and the tenth transistor M10 is the same.

If the word line WL and the second word line WL-1 are simultaneously enabled so that the two ports simultaneously perform a read operation when the cell 400 data is logic '1' The transistor M9 and the tenth transistor M10 are turned on and the nineteenth transistor M91 and the eighth transistor M101 are turned on so that the second discharge path portion 233 and the fourth discharge path portion 237 are simultaneously opened. Therefore, the bit line bar BLB and the second bit line bar BLB-1 start discharging simultaneously.

If the cell data is logic '0', the seventh transistor M7 and the eighth transistor M8 are turned on, the seventeenth transistor M71 and the eighteenth transistor M81 are turned on, The first discharge path portion 231 and the third discharge path portion 235 are opened at the same time and the bit line BL and the second bit line BL-1 simultaneously start discharging.

When the transistors of the third discharge path portion 235 and the fourth discharge path portion 237 have sufficient current drive capability as in the case of the first discharge path portion 231 and the second discharge path portion 233 , The voltage difference between the second bit line BL-1 and the second bit line bar BLB-1 can proceed very quickly. Therefore, according to the present invention, a sensor amplifier (not shown) can be designed to operate at a faster time. In addition, all subsequent timings are shortened and overall access speed is increased.

Such a dual port structure can be extended as it is in a multi-port structure, for example, a 4-port structure. Even when the number of ports is increased to a plurality, the auxiliary lead unit 230 can be further provided by the same method. As the number of ports increases, the size of the standby current of the present invention is further reduced compared to the standby current of the conventional circuit, and the processing speed of the read operation is further increased.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (8)

In a memory device in which a plurality of cells are arranged,
(M1, M2, M3, and M4) connected to the first node and the second node to store data in a flip-flop structure, and a second transistor A storage unit having two transistors M5 and M6 connected between a bit line BL and a bit line BLB and controlled by a word line WL; And
And an auxiliary lead portion providing a separate discharge path for assisting in discharging the voltage of the bit line and the bit line bar when the word line is enabled for a read operation,
The auxiliary lead portion
A first discharge path portion provided between the bit line and the second power supply voltage to provide a discharge path for discharging the precharged voltage to the bit line when the word line is enabled for a read operation; And
And a second discharge path portion provided between the bit line and the second power supply voltage for providing a discharge path for discharging the precharged voltage to the bit line bar when the word line is enabled for a read operation / RTI &gt;
The method according to claim 1,
Wherein the first discharge path portion has a structure in which a first switch controlled by the word line and a second switch controlled by the second node voltage are connected in series,
Wherein the second discharge path portion has a structure in which a third switch controlled by the word line and a fourth switch controlled by the first node voltage are connected in series.
3. The method of claim 2,
Further comprising a fifth switch that is turned on during a data read operation and connects the first discharge path portion and the second discharge path portion to the second power supply voltage, wherein during the read operation, the first discharge path portion and the second discharge path portion And a second power supply voltage is connected to the second power supply voltage.
The method of claim 3,
Wherein the fifth switch is shared by the plurality of different cells so that the first discharge path portion and the second discharge path portion of each of the other cells are also connected to the bit line and the bit line bar, And to a second power supply voltage.
The method according to claim 3 or 4,
The fifth switch is controlled by a separate control signal,
Wherein the control signal is enabled while the word line (WL) is enabled to turn on the fifth switch.
The method of claim 3,
When the fifth switch is provided for each cell while sharing the bit line and the bit line bar with a plurality of different cells,
And the fifth switch for each cell is simultaneously controlled by a control signal that is enabled while the word line (WL) is enabled.
The method according to any one of claims 3, 4, and 6,
Wherein the first to fourth switches are NMOS transistors, and the fifth switch is a PMOS transistor (M11).
The method of claim 3,
When the cell is a multi-port cell connected to a plurality of sets of bit lines, bit line bars and word lines,
Further comprising a discharge path portion pair corresponding to the first discharge path portion and the second discharge path portion corresponding to each of the bundles.
KR1020140171868A 2014-12-03 2014-12-03 Memory Comprising Cell with Low Power and High Speed KR20160067239A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962324A (en) * 2017-05-24 2018-12-07 华邦电子股份有限公司 Memory storage apparatus
CN113395465B (en) * 2020-03-12 2024-03-05 格科微电子（上海）有限公司 Data reading method of memory cell

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962324A (en) * 2017-05-24 2018-12-07 华邦电子股份有限公司 Memory storage apparatus
CN108962324B (en) * 2017-05-24 2020-12-15 华邦电子股份有限公司 Memory storage device
CN113395465B (en) * 2020-03-12 2024-03-05 格科微电子（上海）有限公司 Data reading method of memory cell

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