KR20160065644A - Memory controller, system including the same, and method thereof - Google Patents

Abstract

Disclosed are a memory controller, a system comprising the same, and an operation method thereof. According to an embodiment of the present invention, the operation method of the memory controller comprises: a step of receiving a command transmitted from a host; and a step of analyzing command queues of a plurality of banks based on the command and controlling the plurality of banks based on the analysis result. Embodiments of the present invention may provide a technique to analyze command queues based on a command transmitted from a host and control a plurality of banks based on the analysis result.

Description

[0001] MEMORY CONTROLLER, SYSTEM INCLUDING THE SAME, AND METHOD THEREOF [0002]

The following embodiments relate to a memory controller, a system including the same, and a method of operation thereof.

The flash conversion layer of the flash memory device tries to write to a predetermined write target page. If another operation is being performed on the corresponding bank, the write operation is delayed even if the other bank is in the idle state. Which is a cause of the overall performance degradation.

In the case of the read operation, if the corresponding bank is performing another operation, the read delay till the transition to the idle state occurs, which causes the overall performance degradation of the flash memory device.

Embodiments can provide a technique for analyzing a command queue based on commands sent from a host and controlling a plurality of banks according to an analysis result.

In addition, the embodiments can provide a technique for selecting a bank having a quick accessibility with respect to a write command and allocating the write command to the selected bank.

In addition, the embodiments may provide a technique of allocating the read command to the bank corresponding to the read command by giving the highest priority to the read command.

A method of operating a memory controller according to an exemplary embodiment includes receiving an instruction transmitted from a host, analyzing a command queue of the plurality of banks based on the instruction, and controlling the plurality of banks according to an analysis result .

When the command is a write command, the controlling step sums the execution time of instructions allocated to each of the plurality of banks in the command queue, and selects a bank having the smallest sum value among the plurality of banks And allocating the write command to the smallest bank.

When the command is a read command, the controlling step may include allocating the read command to the bank corresponding to the read command in the highest order among the plurality of banks.

The allocating step may include sequentially inserting the write command into the instruction queue of the smallest bank.

The allocating may include prioritizing the read command and inserting the read command into the head of the command queue of the bank corresponding to the read command.

The instruction queue may be implemented to correspond to each of the plurality of banks.

The controlling may include controlling the plurality of banks according to a weight of the instruction according to an access type based on an architecture of a memory device including the plurality of banks.

The memory controller according to an exemplary embodiment may include an instruction queue for accumulating instructions transmitted from a host, an assignment module for analyzing the instruction queue based on the instructions, and controlling a plurality of banks according to an analysis result.

When the instruction is a write command, the allocation module sums the execution time of instructions allocated to each of the plurality of banks in the instruction queue and writes the write instruction to the bank having the smallest sum value among the plurality of banks Can be assigned.

When the command is a read command, the allocation module can allocate the read command to the bank corresponding to the read command in the highest order among the plurality of banks.

The instruction queue may be implemented to correspond to each of the plurality of banks.

The command queue may be implemented within the allocation module.

A data storage device according to one embodiment may include the memory controller and a memory device including the plurality of banks.

The data storage device may be a solid state drive (SSD), a universal flash storage (UFS), a flash universal serial bus drive, or an embedded multimedia card (eMMC) )).

An electronic system according to an embodiment may include the memory controller and the host.

1 is a schematic block diagram of an electronic system according to one embodiment.
2 is a schematic block diagram according to one embodiment of the memory controller shown in FIG.
3 is a schematic block diagram of the nonvolatile memory device shown in FIG.
FIG. 4 is a diagram illustrating a hierarchical structure according to an embodiment of the electronic system shown in FIG. 1. FIG. 5 is a flowchart illustrating an operation method of a memory controller according to an embodiment.
FIG. 6 is a diagram for explaining an operation method of the allocation module shown in FIG. 4. FIG.
FIG. 7 is a view for explaining another embodiment of the operation method of the allocation module shown in FIG.
FIG. 8 is a diagram for explaining another embodiment of the operation method of the assignment module shown in FIG.
9 is a schematic block diagram according to another embodiment of the memory controller shown in FIG.
10 is a block diagram according to one embodiment of an electronic system including the memory controller and non-volatile memory device shown in FIG.
11 is a block diagram according to another embodiment of an electronic system including the memory controller and non-volatile memory device shown in FIG.
12 is a block diagram in accordance with another embodiment of an electronic system including the memory controller and non-volatile memory device shown in FIG.
13 is a block diagram in accordance with another embodiment of an electronic system including the data storage device shown in FIG.
14 is a block diagram of an electronic system according to an embodiment of the present invention.

It is to be understood that the specific structural or functional descriptions of embodiments of the present invention disclosed herein are presented for the purpose of describing embodiments only in accordance with the concepts of the present invention, May be embodied in various forms and are not limited to the embodiments described herein.

Embodiments in accordance with the concepts of the present invention are capable of various modifications and may take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, or the like may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example without departing from the scope of the right according to the concept of the present invention, the first element being referred to as the second element, Similarly, the second component may also be referred to as the first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

A module in this specification may mean hardware capable of performing the functions and operations according to the respective names described in this specification and may mean computer program codes capable of performing specific functions and operations , Or an electronic recording medium, e.g., a processor or a microprocessor, equipped with computer program code capable of performing certain functions and operations.

In other words, a module may mean a functional and / or structural combination of hardware for carrying out the technical idea of the present invention and / or software for driving the hardware.

1 is a schematic block diagram of an electronic system according to one embodiment.

Referring to FIG. 1, an electronic system 1 may include a host 10 and a data storage device 20.

The electronic system 1 may be implemented as a personal computer (PC), a server, a data server, a database server, a web server, a network-attached storage (NAS), or a portable electronic device.

Portable electronic devices include, but are not limited to, a laptop computer, a netbook, a mobile phone, a smartphone, a tablet PC, a mobile internet device (MID), a personal digital assistant (PDA) An enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation or portable navigation device (PND), a handheld game console, , Or an e-book (e-book).

The host 10 can communicate with the data storage device 20 via the interface 30. For example, the host 10 may transmit data and / or commands to the data storage device 20 via the interface 30. For example, the host 100 may refer to an application processor or a mobile application processor.

The interface 30 may include an interface protocol for communication.

For example, the interface protocol may be UHI (UHS-I or UHS-II), peripheral component interconnect-express (PCI-E), advanced attached SCSI (ATA), serial advanced technology attachment (SATA) , Or Double Data Rate x (DDRx).

In addition, the interface protocol may be a protocol suitable for a USB (Universal Serial Bus), a multi-media card (MMC), an enhanced small disk interface (ESDI), or an IDE (Integrated Drive Electronics).

The data storage device 20 may include a memory controller 100 and a non-volatile memory device 200.

The data storage device 20 may be a database, a solid state drive (SSD), a universal flash storage (UFS), a flash universal serial bus drive, a secure digital , An MMC (multimedia card), an embedded MMC, a smart card, a memory card, or a RAID (Redundant Array of Independent Disks (RAID) or Redundant Array of Inexpensive Disks But is not limited thereto.

For example, the data storage device 20 may be a flash-based data storage device including a flash memory controller such as an eMMC, UFC, or SSD.

The memory controller 100 can read data or write data by controlling the nonvolatile memory device 200 in response to a command from the host 10. [

The memory controller 100 may also control the operation conditions of the non-volatile memory device 200 or the internal operations necessary for efficient management of the non-volatile memory device 200 (e.g., garbage collection, wear-leveling, etc.).

2 is a schematic block diagram according to one embodiment of the memory controller shown in FIG.

1 and 2, the memory controller 100 includes a first memory 110, a central processing unit (CPU) 120, a second memory 130, a non-volatile memory interface (non) a volatile memory interface 140, and an error correction code (ECC) block 150.

The first memory 110 may store program code or firmware necessary for the operation of the CPU 120. [ The first memory 110 may be implemented as a non-volatile memory, for example, a RAM.

The CPU 120 can control the overall operation of the memory controller 100. [ The CPU 120 can control the exchange of data between the first memory 110, the second memory 130, and the ECC block 150 via the bus 160. [

In addition, the CPU 120 can drive an FTL (Flash Translation Layer) of the nonvolatile memory device 200. [ The FTL will be described later with reference to FIG.

The second memory 130 may be implemented as a volatile memory, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). The second memory 130 may temporarily store or buffer the data transmitted from the host 10 via the interface 30. [ The second memory 130 may also temporarily store or buffer the data output from the nonvolatile memory device 200 for transmission to the host 10 via the interface 30. [ For example, the second memory 130 may be a buffer memory. Although the second memory 130 is illustrated as being implemented in the memory controller 100 in FIG. 2, it may be implemented outside the memory controller 100.

The non-volatile memory interface 140 may interface the exchange of data between the non-volatile memory device 200 and the memory controller 100.

An error correction code (ECC) block 150 is an error correction code (ECC) for error contained in data to be stored in the nonvolatile memory device 200 or data read from the nonvolatile memory device 200. [ Can be detected and corrected.

The non-volatile memory device 200 may store various programs and data.

3 is a schematic block diagram of the nonvolatile memory device shown in FIG.

1 to 3, the non-volatile memory device 200 may be a flash memory device, but is not limited thereto, and may be a PRAM, an MRAM, a ReRAM, or a FeRAM device. When the nonvolatile memory device 200 is a flash memory device, the nonvolatile memory device 200 may be a floating gate type NAND flash memory device or a CTF (Charge Trap Flash) type NAND flash memory device. The memory cell transistors of the nonvolatile memory device 200 may have a two-dimensionally arranged structure or a three-dimensionally arranged structure.

The non-volatile memory device 200 may include a plurality of banks 210. Each of the plurality of banks may include a memory cell array 211 leveled from the bank (Bank0) to the bank (BankN). The memory cell array 211 may include non-volatile memory cells.

Each of the non-volatile memory cells may be electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM, spin transfer torque MRAM, conductive bridging RAM (CBRAM), FeRAM A ferroelectric RAM, a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM) ), A holographic memory, a Molecular Electronics Memory Device, or an Insulator Resistance Change Memory. Each of the non-volatile memory cells may store one or more bits. For example, non-volatile memory cells may store single-level cells (SLCs) capable of storing 1-bit information per cell and / or 2-bit information per cell And may include multi-level cells (MLCs).

FIG. 4 is a diagram illustrating a hierarchical structure according to an embodiment of the electronic system shown in FIG. 1. FIG. 5 is a flowchart illustrating an operation method of a memory controller according to an embodiment.

1, 4, and 5, electronic system 1A includes a host 10A according to one embodiment of host 10 of FIG. 1 and an embodiment of data storage device 20 of FIG. 1 And a data storage device 20A according to FIG.

The data storage device 20A includes a flash controller 100A according to one embodiment of the memory controller 100 of Figure 1 and a flash memory device 200A according to one embodiment of the non- .

The flash controller 100A may include a flash translation layer 170 and an interface layer 140A.

The interface layer 140A is a layer that provides a flash interface so that the flash controller 100A can access the flash memory device 200A. The interface layer 140A may correspond to all or part of the non-volatile memory interface 140 shown in FIG.

The FTL 170 includes a logical-physical address mapping module 172, a garbage collection module 174, a wear-leveling module 176, an allocation module 178.

Each of the logical-physical address mapping module 172, the garbage collection module 174, the ware-leveling module 176, and the allocation module 178 may be functionally and logically separate, It does not mean that it is separated into separate physical devices or written in separate codes.

The logical-physical address mapping module 172 may map the logical address of the file system and the physical address of the flash memory device 200A using an address mapping table.

The garbage collection module 174 may control a garbage collection operation for managing valid pages in a block of the flash memory device 200A. The garbage collection operation is an operation for copying a valid page in an existing block of the flash memory device 200A to a new block, erasing the existing block, and reusing it as a free block.

Leveling module 176 may perform a wear-leveling operation to increase the lifetime of the flash memory device 200A. The wear-leveling operation is an operation for uniformly managing the number of erase functions of the blocks to prevent the life of a specific block from being shortened.

The assignment module 178 may receive the command transmitted from the host 10A (S110).

The assignment module 178 analyzes the instruction queues of the plurality of banks based on the instruction output from the host 10A, and controls the plurality of banks according to the analysis result (S130).

In addition, the allocation module 178 can control a plurality of banks according to the weight of the instruction according to the access type based on the architecture of the memory device including a plurality of banks, for example, the flash memory device 200A .

FIG. 6 is a diagram for explaining an operation method of the allocation module shown in FIG. 4. FIG.

Referring to FIG. 6, the assignment module 178 may receive commands transmitted from the host 10A. The allocation module 178 analyzes the instruction queue 179 of the plurality of banks (Bank0 to BankN) based on the instruction and controls the plurality of banks (Bank0 to BankN) according to the analysis result.

The instruction queue 179 may include a plurality of instruction queues 179-1 through 179-n. Each of the plurality of command queues 179-1 to 179-n may correspond to each of the plurality of banks (Bank0 to BankN). For example, the first instruction queue 179-1 corresponds to the first bank (Bank0), the second instruction queue 179-2 corresponds to the second bank (Bank1), the nth instruction queue 179 -n) may correspond to the n-th bank (Bank N).

When the command sent from the host 10A is the write command W, the allocation module 178 can sum up the execution times of the commands allocated to each of the plurality of banks (Bank0 to BankN) in the command queue 179 have. The allocation module 178 can estimate the delay time of each of the plurality of banks (Bank0 to BankN) through the command queue 179. [ At this time, the allocation module 178 can select the bank having the smallest sum of execution times of the allocated commands among the plurality of banks (Bank0 to BankN).

The assignment module 178 can assign the write command W to the bank having the smallest sum value. For example, the assignment module 178 may sequentially insert into the instruction queue of the bank with the smallest sum value.

For convenience of explanation, the instructions a1 to a9 are accumulated in the first instruction queue 179-1, the instructions b1 to b7 are accumulated in the second instruction queue 179-2, It is assumed that the instruction queues 179-n accumulate instructions n1 through n8.

For example, the assigning module 178 assigns the instructions a1 to a9 accumulated in the first instruction queue 179-1 to know the execution time of the instructions a1 to a9 assigned to the first bank (Bank0) Can be summed up. The allocation module 178 calculates the execution time of the instructions b1 to b7 accumulated in the second instruction queue 179-2 to determine the execution time of the instructions b1 to b7 allocated to the second bank Bank1 Can be added. The assignment module 178 compares the execution time of the instructions n1 to n8 accumulated in the nth instruction queue 179-n to determine the execution time of the instructions n1 to n8 allocated to the nth bank BankN Can be added.

The allocation module 178 can select the second bank Bank1 as the bank having the smallest sum of the execution times of the allocated instructions among the plurality of banks Bank0 to BankN.

The assignment module 178 can be inserted sequentially into the command queue 179-2 of the second bank Bank1. Therefore, the write command W can be executed sequentially after the commands b1 to b7 are executed.

With respect to the write command W, the flash memory device 200A can minimize the delay time and improve the write performance by selecting the bank with a high temporal accessibility and inserting the write command W into the command queue of the selected bank .

FIG. 7 is a view for explaining another embodiment of the operation method of the allocation module shown in FIG.

Referring to Fig. 7, the assignment module 178 may receive the command transmitted from the host 10A. The allocation module 178 analyzes the instruction queue 179 of the plurality of banks (Bank0 to BankN) based on the instruction and controls the plurality of banks (Bank0 to BankN) according to the analysis result.

When the command transmitted from the host 10A is the read command R, the allocation module 178 can select a bank corresponding to the read command R from among the plurality of banks (Bank0 to BankN). The allocation module 178 may assign the read command R to the bank corresponding to the read command R in the highest order. For example, the assignment module 178 may prioritize the read command R and insert the read command R into the head of the command queue of the bank corresponding to the read command R. [

For convenience of explanation, the instructions a1 to a9 are accumulated in the first instruction queue 179-1, the instructions b1 to b7 are accumulated in the second instruction queue 179-2, It is assumed that the instruction queues 179-n accumulate instructions n1 through n8.

The allocation module 178 may receive the read command R from the host 10A and select a bank corresponding to the read command R from among the plurality of banks Bank0 to BankN as the first bank Bank0 .

The assignment module 178 may insert the read command R into the head of the command queue 179-1 by giving priority to the commands a1 to a9. Therefore, the read command R can be executed first before the instructions a1 to a9.

The read command R is given the highest priority and the read command R is inserted into the command queue of the bank corresponding to the read command R so that the flash memory device 200A minimizes the delay time, Can be improved.

FIG. 8 is a diagram for explaining another embodiment of the operation method of the assignment module shown in FIG.

8, the allocation module 178 may be used to store instructions (e.g., program (s)) based on an access type based on the architecture of a memory device including a plurality of banks, for example, a flash memory device 200A. a plurality of banks can be controlled according to a weight of a program, a read, an erase, and a write. For example, an architecture may include an SLC NAND architecture and an MLC NAND architecture.

Each instruction, for example, program, read, erase, and write, can have different time requirements depending on the access type based on the architecture. For example, program commands and read commands that look the same can have different times. Thus, each instruction can have different weights or be given different depending on the access type based on the architecture.

FIG. 8 shows experimental values assuming that only the LSB page is programmed and the MSB page is programmed in the MLC NAND structure.

As shown in FIG. 8, the weights of the program command and the read command may differ depending on the access type based on the architecture of the flash memory device 200A. In addition, it can be seen that the operation of reading the LSB page in the programmed state only in the LSB page requires about 3 ~ 4 times less tR time than the operation of reading the LSB page in the state where the MSB page is programmed.

As shown in FIG. 8, the weight of the command can be set to an experimental value, but not limited thereto, and the weight of the command can be set by the user and / or the designer.

6, FIG. 7, and FIG. 8, the assignment method of the assignment module 178 is separately described. However, the assignment method is not limited to this, The operation method described in Fig. 8 can be added to control the plurality of banks.

9 is a schematic block diagram according to another embodiment of the memory controller shown in FIG.

Referring to FIG. 9, the assignment module 178 may be implemented outside the FTL 170.

For example, the allocation module 178 may be implemented as independent hardware other than the CPU 120.

In another example, when the assignment module 178 is implemented in firmware or software, the assignment module 178 may be executed by the CPU 120. [

The structure and operation of the memory controller 100B of FIG. 9 may be substantially the same as the structure and operation of the memory controller 100 of FIG.

10 is a block diagram according to one embodiment of an electronic system including the memory controller and non-volatile memory device shown in FIG.

1 and 10, the electronic system 400 may be implemented as a cellular phone, a smart phone, a personal digital assistant (PDA), or a wireless communication device.

The electronic system 400 includes a nonvolatile memory device 200, a memory controller 100 that can control the operation of the nonvolatile memory device 200, a processor 410, a display 420, a wireless transceiver a radio transceiver 430, and an input device 440.

The memory controller 100 controls the data access operation of the nonvolatile memory device 200, for example, a program operation, an erase operation, or a read operation under the control of the processor 410 can do.

The data programmed into the non-volatile memory device 200 may be displayed via the display 420 under the control of the processor 410 and / or the memory controller 100.

The processor 410 is connected to the display 420 so that data output from the memory controller 100, data output from the wireless transceiver 430, or data output from the input device 440 may be displayed via the display 420. [ Can be controlled.

The wireless transceiver 430 may receive or receive a wireless signal via the antenna ANT. For example, the wireless transceiver 430 may convert the wireless signal received via the antenna ANT into a signal that can be processed by the processor 410. [

Thus, the processor 410 may process the signal output from the wireless transceiver 430 and transmit the processed signal to the memory controller 100 or the display 420.

In addition, the wireless transceiver 430 may convert the signal output from the processor 410 into a wireless signal and output the modified wireless signal to an external device through the antenna ANT.

The input device 440 is a device capable of inputting a control signal for controlling the operation of the processor 410 or data to be processed by the processor 410 and includes a touch pad and a computer mouse Such as a pointing device, a keypad, a keyboard, or the like.

For example, the memory controller 100, which may control the operation of the non-volatile memory device 200, may be implemented as part of the processor 410 and may be implemented as a separate chip from the processor 410. [

11 is a block diagram according to another embodiment of an electronic system including the memory controller and non-volatile memory device shown in FIG.

Referring to FIGS. 1 and 11, the electronic system 500 may be implemented as a memory card, a smart card, or the like.

The electronic system 500 includes a memory controller 100, a non-volatile memory device 200, and a card interface 520.

The memory controller 100 can control the exchange of data between the nonvolatile memory device 200 and the card interface 520. [

The card interface 520 may interface data exchange between the host 530 and the memory controller 100 according to the protocol of the host 530.

For example, the card interface 520 may be, but is not limited to, a secure digital (SD) card interface or a multi-media card (MMC) interface.

For example, the card interface 520 may support USB (Universal Serial Bus) protocol, IC (InterChip) -USB protocol. Here, the card interface may refer to hardware capable of supporting the protocol used by the host 530, software installed in the hardware, or a signal transmission method.

The host 530 may be implemented as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box.

When the electronic system 500 is connected to the host interface 550 of the host 530, the host interface 550 is connected to the card interface 520 and the memory controller 100, under the control of the microprocessor 540, And can perform data communication with the volatile memory device 200.

12 is a block diagram in accordance with another embodiment of an electronic system including the memory controller and non-volatile memory device shown in FIG.

Referring to Figures 1 and 12, the electronic system 600 may be implemented as a solid state drive (SSD).

The electronic system 600 may include a memory controller 100, a plurality of non-volatile memory devices 200, a buffer manager 620, a volatile memory device 630, and a host 640.

The memory controller 100 can control the data processing operation of each of the plurality of nonvolatile memory devices 200. [

The buffer manager 620 can control storing data to be exchanged between the memory controller 100 and the host 640 in the volatile memory device 630. [

The volatile memory device 630 can buffer the data exchanged between the memory controller 100 and the host 640. For example, the volatile memory device 630 may be implemented as a dynamic random access memory (DRAM).

13 is a block diagram in accordance with another embodiment of an electronic system including the data storage device shown in FIG.

1 and 13, a data processing system 700, which may be implemented as a redundant array of independent disks (RAID) system, includes a RAID controller 710 and a plurality of memory systems 700-1 through 700-n. n is a natural number).

Each of the plurality of memory systems 700-1 through 700-n may be the data storage device 20 shown in FIG. The plurality of memory systems 700-1 through 700-n may constitute a RAID array. For example, the data processing system 700 may be implemented as a personal computer (PC) or an SSD.

While the program operation is being performed, the RAID controller 710 transfers the program data output from the host (HOST) to the plurality of memory systems 700-1 to 700- n).

During the read operation, the RAID controller 710 reads data read from at least one of the plurality of memory systems 700-1 to 700-n according to the read command output from the host (HOST) To the host (HOST).

The host (HOST) in FIG. 13 may mean the host 10 in FIG.

14 is a block diagram of an electronic system according to an embodiment of the present invention.

Referring to Figures 1 and 14, the electronic system 1 of Figure 1 may be implemented in the electronic system 1000 of Figure 14. Electronic system 1000 may be a data processing device that can use or support a mobile industry processor interface (MIPI), such as personal digital assistants (PDA), portable multimedia player (PMP), internet protocol television (IPTV) smart phone).

A CSI host (CSI host) 1012 implemented in the application processor 1010 can communicate with the CSI device 1041 of the image sensor 1040 through a camera serial interface. At this time, for example, the CSI host 1012 may include a deserializer (DES), and the CSI device 1041 may include a serializer (SER).

The DSI host 1011 implemented in the application processor 1010 can communicate with the DSI device 1051 of the display 1050 through a display serial interface (DSI). At this time, for example, the DSI host 1011 may include a serializer (SER), and the DSI device 1051 may include a deserializer (DES).

For example, the electronic system 1000 may further include an RF chip 1060 capable of communicating with the application processor 1010. The PHY 1061 included in the PHYsical layer 1013 and the RF chip 1060 included in the application processor 1010 can exchange data according to the MIPI DigRF.

For example, the electronic system 1000 includes a GPS receiver 1020, a storage 1070, a microphone (MIC) 1080, a dynamic random access memory (DRAM) 1085, and a speaker 1090 .

The host 10 of FIG. 1 is implemented with the AP 1010 of FIG. 14, and the data storage 20 of FIG. 1 may be implemented with the storage 1070 of FIG.

The electronic system 1000 may communicate using a world interoperability for microwave access (WIMAX) module, a wireless LAN (WLAN) module 1100, and / or an ultra wideband (UWB)

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA) , A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (16)

Receiving an instruction transmitted from a host;
Analyzing a command queue of the plurality of banks based on the command, and controlling the plurality of banks according to an analysis result
The memory controller comprising:
The method according to claim 1,
When the command is a write command,
Wherein the controlling comprises:
Summing execution times of instructions allocated to each of the plurality of banks in the instruction queue and selecting a bank having the smallest sum value among the plurality of banks; And
Assigning the write command to the smallest bank;
The memory controller comprising:
The method according to claim 1,
When the command is a read command,
Wherein the controlling comprises:
Allocating the read command to the bank corresponding to the read command in the highest order among the plurality of banks
The memory controller comprising:
3. The method of claim 2,
Wherein the assigning comprises:
Sequentially inserting the write command into a command queue of the smallest bank
The memory controller comprising:
The method of claim 3,
Wherein the assigning comprises:
Assigning a priority to the read command and inserting the read command into the head of the command queue of the bank corresponding to the read command
The memory controller comprising:
The method according to claim 1,
Wherein the instruction queue is implemented to correspond to each of the plurality of banks.
The method according to claim 1,
Wherein the controlling comprises:
Controlling the plurality of banks according to a weight of the instruction according to an access type based on an architecture of a memory device including the plurality of banks,
The memory controller comprising:
A command queue for stacking commands transmitted from a host; And
An allocation module for analyzing the instruction queue based on the instruction and controlling a plurality of banks according to an analysis result,
.
9. The method of claim 8,
When the command is a write command,
Wherein the allocation module sums the execution time of instructions allocated to each of the plurality of banks in the instruction queue and allocates the write instruction to a bank having the smallest sum value among the plurality of banks.
9. The method of claim 8,
When the command is a read command,
Wherein the allocation module allocates the read command to the bank corresponding to the read command in the highest order among the plurality of banks.
9. The method of claim 8,
Wherein the instruction queue is implemented to correspond to each of the plurality of banks.
9. The method of claim 8,
Wherein the instruction queue is implemented within the allocation module.
The memory controller of claim 8; And
And a memory device including the plurality of banks.
14. The method of claim 13,
The data storage device may be a solid state drive (SSD), a universal flash storage (UFS), a flash universal serial bus drive, or an embedded multimedia card (eMMC) ).
The memory controller of claim 8; And
And the host.
A computer-readable recording medium having recorded thereon a program for executing the method according to any one of claims 1 to 8.

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