KR20160050840A - The method and apparatus for controlling logic of fast current mode - Google Patents

Abstract

Disclosed are an apparatus and a method for controlling logic in a fast current mode, which can prevent an operation delay by a parasitic capacitor without any capacitors requiring an excessive chip space. The method for controlling logic in a fast current mode includes the steps of: allowing a reference current to flow into a first transistor of a multi-level active bias device and a third transistor for determining a bias voltage when a first switch of the multi-level active bias device is turned on and a second switch is turned off in a sleep mode; allowing the reference current to flow into the third transistor when the first and second switches are turned off in a fast wake-up mode; allowing the reference current to flow into the second and third transistors when the first switch is turned off and the second switch is turned on in a general operation mode; and allowing the reference current to flow into the first to third transistors when the first and second switches are turned on in a fast turning-off mode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high-

The present invention relates to an apparatus and method for a fast current mode logic controller, and more particularly, to a fast current mode logic controller and method based on fast switching.

A frequency synthesizer is an integrated circuit generated by synthesizing a desired carrier frequency in a wireless communication field and is a core part of most communication equipment and radar. In recent years, the role of frequency synthesizer has been greatly increased due to the development of wireless communication. Also, in order to accommodate various techniques for higher frequency, wide frequency bandwidth and security, such a frequency synthesizer needs to be designed with low power and high performance circuits Is emerging. These frequency synthesizers can be divided into phase locked loop (PLL) and direct digital frequency synthesizer (DDFS). DDFS is designed to replace PLL, which is a popular analog circuit, with digital. The PLL, which has been used as a typical frequency synthesizer, is slow in frequency conversion and difficult to precisely adjust the frequency. Recently, a new method called digital frequency synthesis method has been attracting attention.

Although DDFS has a disadvantage that it consumes much more energy than PLL, it does not need fixing time, it is able to perform fast frequency conversion, has excellent frequency interference and security, and is widely applied to military products. Especially strong against frequency interference.

This direct digital frequency synthesizer enables digitally synthesized frequency to overcome the disadvantages of the existing PLL structure, and has more sophisticated resolution and good phase noise, and can operate within the fast frequency conversion time of ns.

KR 10-2005-7019669

One aspect of the present invention provides a fast current mode logic control method that solves the operation delay problem due to parasitic capacitance without a capacitor requiring excessive chip space.

Another aspect of the present invention provides a fast current mode logic controller which solves the operation delay problem due to parasitic capacitance without a capacitor by a simple configuration.

In the fast current mode logic control method according to an aspect of the present invention, when the first switch of the plurality of levels of the activation bias device is in the on state and the second switch is in the sleep mode in the off state, To a third transistor for determining a bias voltage, wherein when the first switch is in the off state and the second switch is in the off state, the reference current flows to the third transistor The reference current flows to the second transistor and the third transistor when the first switch is in the off state and the second switch is in the on state, Off state in which the first switch is in the on state and the second switch is in the on state, (W / L ratio) of the width of the gate of the first transistor to the length of the gate of the first transistor is less than the W / L ratio of the second transistor, And may be greater than the W / L ratio of the third transistor.

The W / L ratio of the first transistor may be 20 times the W / L ratio of the second transistor and the W / L ratio of the third transistor.

The first switch and the second switch may have a delay, and the delay may be generated by one inverter connected to the two inverters connected to the second switch and connected to the first switch.

Also, the bias voltage of each of the plurality of levels of activation biasing devices may be supplied to operate a pre-skewing F / F included in the phase accumulator according to a frequency control word (FCW).

이고, 상기 N은 FCW 입력 비트의 개수, P는 파이프 라인의 뎁스(depth)일 수 있다.Also, the number of the pre skewing F / Fs disabled in the phase accumulator is

N is the number of FCW input bits, and P is the depth of the pipeline.

A fast current mode logic controller according to another aspect of the present invention operates multiple levels of activation biasing device in one of the sleep mode, rapid wakeup mode, normal operation mode and fast turning off mode, Wherein the bias device supplies a reference current to a first transistor of a plurality of levels of the activation bias device and a third transistor that determines a bias voltage when the first switch is on and the second switch is in the off state, Wherein the plurality of levels of the activation bias device are configured to allow the reference current to flow to the third transistor when the first switch is in the off state and the second switch is in the off wakeup mode, The apparatus is characterized in that the first switch is in the off state, the second switch is in the on state Wherein said plurality of levels of activation biasing devices are configured such that said first switch is in the on state and said second switch is in the on state, (W / L ratio) of the gate of the first transistor to the first transistor, the second transistor, and the third transistor, W / L ratio and the W / L ratio of the third transistor.

The W / L ratio of the first transistor may be 20 times the W / L ratio of the second transistor and the W / L ratio of the third transistor.

The first switch and the second switch may have a delay, and the delay may be generated by one inverter connected to the two inverters connected to the second switch and connected to the first switch.

Also, the bias voltage of each of the plurality of levels of activation biasing devices may be supplied to operate a pre-skewing F / F included in the phase accumulator according to a frequency control word (FCW).

이고, 상기 N은 FCW 입력 비트의 개수, P는 파이프 라인의 뎁스(depth)일 수 있다.
Also, the number of the pre skewing F / Fs disabled in the phase accumulator is

N is the number of FCW input bits, and P is the depth of the pipeline.

According to an aspect of the present invention, various devices (for example, a flip-flop and a frequency synthesizer using a flip-flop series) that require low-power driving based on fast switching can be operated effectively while suppressing increase in complexity and chip area .

1 is a conceptual diagram illustrating a conventional bias device.
2 is a diagram illustrating a bias voltage recovery time of a bias device that operates based on a charge sharing capacitor.
3 is a conceptual diagram illustrating a multi-level fast activation biasing device according to an embodiment of the present invention.
FIG. 4 is a graph illustrating an operation mode of the multi-level rapid activation biasing device according to the embodiment of the present invention.
FIG. 5 is a conceptual diagram illustrating a direct digital frequency synthesizer (DDFS) operating on a plurality of levels of fast activation biasing devices in accordance with an embodiment of the present invention.
6 is a conceptual diagram illustrating a disabling operation of a pre skewing F / Fs included in a phase accumulator according to an embodiment of the present invention.
FIG. 7 is a conceptual diagram illustrating a control unit for a front end of a plurality of levels of quick activation biasing apparatuses according to an embodiment of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a conceptual diagram illustrating a conventional bias device.

Referring to FIG. 1, a conventional bias device may include a first switch 100 and a second switch 150, which are two opposed non-overlapping switches.

When the first switch 100 is switched to the on mode, the charge sharing capacitor Cbig is connected in parallel with the first switch 100 to prevent the voltage recovery delay from occurring, Can be implemented.

When the first switch 100 is turned on (i.e., recovery is started), the bias voltage quickly approaches the initial value by the charge previously charged to the charge sharing capacitor. That is, the charge sharing capacitor can quickly supply sufficient voltage to switch the logic gates of the disabled blocks.

However, in the method using such a charge sharing capacitor, the voltage quickly reaches a certain voltage value, but it is difficult to accurately meet the voltage initial value. This is because, after the charge charged in the charge sharing capacitor is used, the charging for the charge sharing capacitor is performed again and the bias voltage is restored. Hereinafter, a fast current mode logic controller and method according to an embodiment of the present invention discloses a problem of such a conventional bias device for a multi-level momentarily activated bias device.

2 is a diagram illustrating a bias voltage recovery time of a bias device that operates based on a charge sharing capacitor.

A bias device that operates based on a charge sharing capacitor can take one clock to restore to a voltage level close to the bias voltage. However, it takes more than four clocks to restore to the correct bias voltage. In the embodiment of the present invention, a plurality of rapid activation biasing devices for reducing the time required for restoration to a correct bias voltage to accelerate the recovery of the bias voltage are disclosed.

3 is a conceptual diagram illustrating a multi-level fast activation biasing device according to an embodiment of the present invention.

In Fig. 3, a plurality of levels of fast activation biasing devices for quickly reaching a bias voltage value are disclosed.

Referring to FIG. 3, a multi-level fast activation biasing device includes two switches 305 and 310 and transistors 320 and 340 connected to two diodes.

The W / L ratio of the first transistor 320 may be 20 times larger than the W / L ratio of the second transistor 340 and the third transistor 360. [

The first transistor 320 and the second transistor 340 may be controlled by SW1 305 and SW2 310 that perform switching based on a complementary signal. SW1 305 and SW2 310 can be driven with a constant delay through the inverter. Specifically, SW1 305 operates in conjunction with one inverter, and SW2 310 operates based on two inverters 300. The SW1 305 and the SW2 310 perform different on / off operations with a constant delay based on the two inverters 300, so that the pre skewing F / Fs connected to the plural-level quick activation biasing device are divided into four And can be operated in different operation modes.

The four operation modes of the pre-skewing F / Fs according to the ON / OFF operation of the SW1 305 and the SW2 310 are a sleep mode, a rapidly waking-up mode, May be a normal operation mode or a rapidly turning-off mode. The respective modes are specifically described in Fig.

FIG. 4 is a graph illustrating an operation mode of the multi-level rapid activation biasing device according to the embodiment of the present invention.

Referring to FIG. 4, the pre-skewing F / Fs may be switched to the sleep mode 400, the rapid wakeup mode 420, the general operation mode 440, or the fast turning-off mode 460 according to on / off of SW1 and SW2. As shown in FIG.

If SW1 is 'on' and SW2 is 'off', the pre skewing F / Fs may be the sleep mode 400. In this case, since the W / L ratio of the first transistor connected to SW1 is 20 times larger than the W / L ratio of the second transistor and the third transistor, I _ref flows mostly through SW1 to the first transistor, Trafficking register flows to the bias voltage V _b may have a lower value.

The pre skewing F / Fs may be a rapid wakeup mode 420 when SW1 is off and SW2 is off. As described above, SW1 and SW2 can have a constant delay in performing an on / off operation based on an inverter. Therefore, in the process of switching SW1 to the off state and SW2 to the on state, SW1 may be in an off state and SW2 may be in an off state temporarily. When both switches are off, I _ref flows to the third transistor, and the magnitude of V _b may surge. In the rapid wakeup mode, the parasitic capacitor C _par can be charged and the voltage V _b can be increased quickly to turn on the third transistor. The charging rate of the parasitic capacitor in the rapid wakeup mode 420 may be expressed by Equation 1 below.

Since the charging time is inversely proportional to the parasitic capacitor, the size of the bias transistor can be determined to be a small value to improve the charging time.

If SW1 is 'off' and SW2 is 'on', pre skewing F / Fs may be the normal mode of operation 440. In the normal operation mode 440, SW2 may be 'on' and a portion of I _ref may flow through SW2 to the second transistor. And the remaining I _ref can flow to the third transistor. The second transistor has the same W / L ratio as the third transistor. Accordingly, the bias voltage V _b in the normal operation mode 440 may be a voltage higher than the sleep mode 400. In addition, the magnitude of V _b in the normal mode of operation 440 may be a value less than the magnitude of V _b in the rapid wakeup mode 420.

If SW1 is 'on' and SW2 is 'on', pre skewing F / Fs may be fast turning off mode 460. In the process of switching to the sleep mode 400, SW1 can be switched to the on state and SW2 can be switched to the off state. The fast turning off mode 460 may be in the SW1 and SW2 are 'on' state, the majority of I _ref flows to the first transistor and the second transistor via the SW1 and SW2 has a remainder I _ref to flow to the third transistor . Thus, the magnitude of V _b in fast turning off mode 460 may decrease rapidly below the magnitude of V _b in sleep mode 400. In this case, the voltage input to the third transistor rapidly decreases, and the third transistor can be quickly turned off.

When the above method is used, the pre skewing F / Fs can be turned on / off more quickly than the conventional activation bias device.

FIG. 5 is a conceptual diagram illustrating a direct digital frequency synthesizer (DDFS) operating on a plurality of levels of fast activation biasing devices in accordance with an embodiment of the present invention.

Referring to FIG. 5, a direct digital frequency synthesizer may generate a desired frequency signal directly from a given phase value. The direct digital frequency synthesizer may include a phase accumulator (PACC) 500 having a multi-stage pipeline structure for high-speed operation.

The phase accumulator 500 is based on current mode logic and may include a plurality of flip-flops in a pipeline structure (e.g., pre skewing F / Fs). A plurality of levels of quick activation biasing devices according to embodiments of the present invention may be used to supply a bias voltage to the pre skewing F / Fs included in the phase accumulator 500 according to a frequency control word (FCW).

In the digital frequency synthesizer, an N-bit FCW is input to the phase accumulator 500 every clock, and the FCW can be added to the value stored in the phase accumulator 500. In the phase accumulator 500, overflow occurs because the FCW is continuously added. The upper J bits of the N bits stored in the phase accumulator 500 are input to the signal generator 510 .

The signal generator 510 may include a phase-sine value converter, a digital-analog converter, and a low-pass filter. The signal generator 510 may generate a signal having a desired frequency using the J-bit output of the phase accumulator 500 A sine wave) can be generated.

Specifically, the digital frequency synthesizer according to the present embodiment may include an FCW load unit 520, a phase accumulator 500, a controller 520, a bias voltage generator 530, and a clock driver 540.

The FCW load unit 520 can load the input FCWs in parallel and output them to the phase accumulator 500. The phase accumulator 500 forms a pipeline structure with a plurality of blocks such as a flip-flop (e.g., pre skewing F / Fs) and an adder, and can propagate and add the input FCW to adjacent blocks.

The control unit 520 determines whether there is a change in the input FCW and outputs the phase accumulator 500 to one of the four operation modes (the sleep mode, the rapid wakeup mode, the normal operation mode, or the fast turning off mode) Operation mode.

For example, the controller 520 can quickly turn on / off the bias voltage supplied to the phase accumulator 500 by turning on / off the multi-level fast activation biasing device for four operations. In addition, the controller 520 may generate a control signal (disable signal) to change from the normal operation mode to the sleep mode through the fast turning-off mode when the predetermined clock or more FCW is in the idle state.

The bias voltage generator 530 may generate and apply a bias voltage for operating a block included in the phase accumulator 500 according to a control signal of the controller 520. [

The clock driver 540 may provide a clock for the operation of the pre skewing F / Fs included in the phase accumulator connected to the multiple-level quick activation biasing device according to the embodiment of the present invention.

6 is a conceptual diagram illustrating a disabling operation of a pre skewing F / Fs included in a phase accumulator according to an embodiment of the present invention.

When the disabling operation of the pre skewing F / Fs is performed, the bias voltage may be rapidly reduced while the fast activation biasing device of a plurality of levels proceeds from the fast turning-off mode to the sleep mode.

The number of pre skewing F / Fs disabled in the phase accumulator can be expressed as Equation 2 below.

In Equation (2), N may be the number of FCW input bits and P may be the depth of the pipeline. For example, N = 32 and P = 8. In this case, the number of disabled pre skewing F / Fs may be 98.

Because of the fast transition, the bias voltage of the pre skewing F / Fs located in each column is sequentially activated and can be conserved for two clock cycles to minimize power consumption. The pre skewing F / Fs can be turned off after two clocks. After two clock cycles the pre skewing F / Fs can be turned off.

Referring to FIG. 6, a certain overlap is required between the bias voltages V _b1 and V _b7 between adjacent rows of the pre skewing F / Fs to pass the data to the next column.

FIG. 7 is a conceptual diagram illustrating a control unit of a preceding stage of a multi-level quick activation biasing device M ² AB according to an embodiment of the present invention.

Referring to FIG. 7, the control unit of the previous stage may include 7 F / Fs and 7 OR gates. The OR gate may generate a sequentially shifted load signal in two clock cycle periods to control multiple levels of fast activation biasing device.

This control can consume 5mW of power, but the power reduction at 2GHz operation is 35mW. The pre skewing F / Fs included in the proposed PACC can be biased to 200uA at 1V supply. The power reduction size of 35mW may include 20mW reduced from 98 disabled pre skewing F / Fs and 15mW reduced from the power of the local clock buffer at each pipeline stage of the PACC. Since the local clock buffer associated with the disabled pre skewing F / Fs is also turned off. As a result, the power consumption of the multi-level quick activation biasing device according to the embodiment of the present invention can be reduced by 30 mW as compared with the power consumption consumed in the conventional PACC operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

300: Inverter
305: SW1
310: SW2
320: first transistor
340: second transistor

Claims (10)

A fast current mode logic control method,
When the first switch of the plurality of levels of the activation biasing device is in the on state and the second switch is in the off mode, the reference current is applied to the first transistor of the activation bias device of plural levels and the third transistor which determines the bias voltage Flowing phase;
The reference current flows to the third transistor when the first switch is in the off state and the second switch is in the off wakeup mode;
The reference current flows to the second transistor and the third transistor when the first switch is in the off state and the second switch is in the on operation state; And
Wherein the reference current flows to the first transistor, the second transistor and the third transistor when the first switch is in the on state and the second switch is in the on-state fast turning-off mode, ,
Wherein a width-to-length ratio (W / L ratio) of the gate of the first transistor is greater than a W / L ratio of the second transistor and a W / L ratio of the third transistor.
The method according to claim 1,
Wherein the W / L ratio of the first transistor is 20 times the W / L ratio of the second transistor and the W / L ratio of the third transistor.
3. The method of claim 2,
Wherein the first switch and the second switch have a delay,
Wherein the delay is connected to two inverters connected to the second switch and is generated by one inverter connected to the first switch.
The method of claim 3,
Wherein the bias voltage of each of the plurality of levels of activation biasing devices is provided to operate a pre-skewing F / F included in the phase accumulator according to a frequency control word (FCW).
5. The method of claim 4,
The number of pre-skewing F / Fs disabled in the phase accumulator is

ego,
Wherein N is the number of FCW input bits and P is the depth of the pipeline.
A fast current mode logic controller comprising:
Wherein the fast current mode control device operates the plurality of levels of the activation biasing device in one of the sleep mode, the rapid wakeup mode, the normal operation mode, and the fast turning off mode,
Wherein the plurality of levels of activation biasing devices are configured such that when the first switch is on and the second switch is in the sleep mode the reference current is applied to the first transistor of the plurality of levels of activation biasing device and the third transistor Flowing into the transistor,
Wherein the plurality of levels of the activation biasing device is configured to allow the reference current to flow to the third transistor when the first switch is in the off state and the second switch is in the off wakeup mode,
The plurality of levels of the activation biasing device may cause the reference current to flow to the second transistor and the third transistor when the first switch is in the off state and the second switch is in the on operation state,
Wherein the plurality of levels of the activation biasing device are configured so that when the first switch is in the on state and the second switch is in the on-state fast turning-off mode, the reference current is supplied to the first transistor, 3 transistor,
Wherein a width-to-length ratio (W / L ratio) of the gate of the first transistor is greater than a W / L ratio of the second transistor and a W / L ratio of the third transistor.
The method according to claim 6,
Wherein the W / L ratio of the first transistor is 20 times the W / L ratio of the second transistor and the W / L ratio of the third transistor.
8. The method of claim 7,
Wherein the first switch and the second switch have a delay,
Wherein the delay is connected to two inverters connected to the second switch and is generated by one inverter connected to the first switch.
9. The method of claim 8,
Wherein the bias voltage of each of the plurality of levels of activation biasing devices is provided to operate a pre-skewing F / F included in the phase accumulator according to a frequency control word (FCW).
10. The method of claim 9,
The number of pre-skewing F / Fs disabled in the phase accumulator is

ego,
Wherein N is the number of FCW input bits and P is the depth of the pipeline.

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