KR20160047647A - Display device - Google Patents

Abstract

According to an embodiment of the present invention, a display device connects pixels to diagonal gate lines and data lines. The pixels are arranged in a matrix shape along a first direction and a second direction vertical to the first direction and classified by scan units. The diagonal gate lines are extended toward a third direction which cross the first and second directions. The data lines are extended along the first direction. The diagonal gate lines are connected by connection lines so that each of the scan units includes the same number of pixels.

Description

Display device {DISPLAY DEVICE}

Embodiments of the present invention relate to a display device, and more particularly, to a display device capable of providing a single side driving structure.

The display device includes a display panel for displaying an image, and a data driver and a gate driver for driving the display panel. The display panel includes a gate line, a data line, and a pixel. The pixel is connected to the gate line and the data line. The gate lines extend along a first direction, and the data lines extend along a second direction orthogonal to the first direction. The data driver outputs the data voltage to the data line, and the gate driver outputs the gate signal for driving the gate line. The data driver may be disposed along one side of the display panel extending along the first direction and the gate driver may be disposed along the other side of the display panel extending along the second direction.

As described above, when the gate driver and the data driver are disposed along different sides of the display panel, the area occupied by the bezel in the display panel is increased. Recently, studies are being conducted to minimize the area occupied by the bezel of the display panel.

Embodiments of the present invention provide a display device capable of providing a single side driving structure.

In addition, embodiments of the present invention provide a display device capable of reducing load deviation per scan unit.

A display device according to an embodiment of the present invention is arranged in a matrix form along a first direction and a second direction perpendicular to the first direction and is provided with a pixel row along a third direction crossing the first and second directions Pixels divided into a plurality of scan units; Data lines extending along the first direction and arranged along the second direction, the data lines being connected to the pixels; Diagonal gate lines extending in the third direction and connected to the pixels in the pixel line unit direction and arranged in a fourth direction crossing the first to third directions; And connection lines extending along the second direction to connect the diagonal gate lines such that each of the scan units includes the same number of pixels.

Wherein the pixel rows constituted by the pixels are composed of the same number of pixels as the reference number, the first pixel rows arranged in the first pixel region; Second pixel rows arranged in a second pixel region adjacent to one side of the first pixel region, the second pixel rows being composed of a smaller number of pixels than the reference number; And third pixel rows arranged in a third pixel region facing the second pixel region with the first pixel region interposed therebetween, the third pixel rows being composed of a smaller number of pixels than the reference number. The number of pixels constituting each of the second and third pixel rows increases as the pixel area approaches the first pixel area.

The pixel rows may be composed of pixels arranged in an M x N matrix with M > N.

The pixel rows may be composed of pixels arranged in an M x N matrix with M = N.

Wherein the diagonal gate lines are connected to the first diagonal gate line connected to the first pixel line; Second diagonal gate lines connected to the second pixel rows and increasing in length toward the first pixel region; And third diagonal gate lines connected to the third pixel rows and increasing in length toward the first pixel region. In this case, each of the connection lines defines the scan units by connecting the second and third diagonal gate lines having different lengths to one another, and the number of pixels constituting each of the scan units is equal to the reference number same.

A gate driver and a data driver connected to the display panel along one side of a display panel including the pixels to provide a driving signal to the pixels; And a dummy line extending along the second direction on the upper side of the display panel adjacent to the one side of the display panel or below the display panel facing the one side of the display panel and connected to the first diagonal gate line .

The dummy lines may be equal to the length of the connection lines, or may be shorter than the lengths of the connection lines.

The pixel rows may include a plurality of pixels arranged in an M × N matrix including M <N, including a plurality of the first pixel rows.

The diagonal gate lines may include a pair of first diagonal gate lines connected to a pair of edge pixel rows arranged at the outermost of the plurality of first pixel rows; Second diagonal gate lines connected to the center pixel rows disposed between the first diagonal gate lines of the plurality of first pixel rows; Third diagonal gate lines connected to the second pixel rows and increasing in length toward the first pixel region; And fourth diagonal gate lines connected to the third pixel rows and increasing in length toward the first pixel region. In this case, the connection lines may include a first connection line connecting the first diagonal gate lines; Second connection lines connecting the second and third diagonal gate lines in pairs; And third connection lines connecting the second and fourth diagonal gate lines pair by pair.

One ends of the second diagonal gate lines are arranged in a line and connected to the second connection lines, the other ends of the second diagonal gate lines are arranged in a line and connected to the third connection lines, Lines and the third connection lines may be connected to each of the second diagonal gate lines by a pair.

And a dummy line connected to any one of the first diagonal gate lines and extending along the second direction.

And a plurality of odd-numbered data lines and even-numbered data lines arranged in the first direction, wherein the odd-numbered data lines and the even-numbered data lines are arranged in the first direction, Th data line.

The display device according to the embodiment of the present invention can extend the data lines along the direction parallel to one side of the display panel and extend the gate lines in the diagonal direction of the display panel intersecting the data lines to provide a one- have.

A display device according to an exemplary embodiment of the present invention defines scan units by connecting diagonal gate lines extending in a diagonal direction of a display panel and having different lengths through connection lines. Thus, the display device according to the embodiment of the present invention can reduce the load deviation per scan unit of the display device having the single-sided driving structure and can equalize the number of pixels distributed by the scan unit.

1 is a view showing a display device according to an embodiment of the present invention.
2 is a block diagram of the display device shown in Fig.
3 is a diagram illustrating pixels according to an embodiment of the present invention.
FIGS. 4A to 4E are views showing a display device according to an embodiment of the present invention including pixels arranged in an M × N matrix in which M> N.
5 is a diagram illustrating a display device according to an embodiment of the present invention including pixels arranged in an M x N matrix in which M = N.
FIG. 6 is a diagram illustrating a display device according to an embodiment of the present invention including pixels arranged in an M × N matrix in the form of M <N.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a view showing a display device according to an embodiment of the present invention. 2 is a block diagram of the display device shown in Fig.

1 and 2, a display device 1000 includes a display panel 100, a flexible printed circuit board 200, a printed circuit board 300, a timing controller 400, a gate driver 500, A driver 600 may be included.

The display panel 100 may include an organic light emitting display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, And a display panel (electrowetting display panel).

The display panel 100 may be formed in four deformations including four sides. Hereinafter, a direction in which one of the four sides of the display panel 100 is extended is defined as a first direction DR1, and a direction perpendicular to the first direction DR1 is defined as a second direction DR2.

The display panel 100 includes an active area and an inactive area.

In the active area of the display panel 100, pixels for displaying an image are arranged. The pixels are arranged in the display panel 100 in a matrix form along the first direction DR1 and the second direction DR2. The pixels are connected to the data lines DL and the diagonal gate lines DG. The pixels form a pixel row along the extending direction of the diagonal gate lines DG. The specific arrangement of the pixels will be described later with reference to FIG. 3 to FIG.

The inactive area of the display panel 100 is an area where no image is displayed. One ends of the data lines DL may extend toward the inactive area of the display panel 100 and may be connected to data pad parts (not shown) formed in the inactive area. The data pad portions may be disposed along one side of the display panel 100. [ In addition, gate pads (not shown) may be disposed along one side of the display panel 100 where the data pad portions are disposed. The gate pads may be connected to one ends of the diagonal gate lines DG extending from the active area of the display panel 100 toward the inactive area, or may be connected to dummy lines connected to the diagonal gate lines DG. A detailed description of the dummy line will be given later with reference to Figs. 4D to 6.

Data lines DL, diagonal gate lines DG, and connection lines LL are arranged in the active area of the display panel 100. [ The data lines DL, the diagonal gate lines DG and the connection lines LL may be formed in different layers with an insulating layer (not shown) therebetween. The diagonal gate lines DG and the connection lines LL may be connected via contacts CT through the insulating layer.

The data lines DL extend along the first direction DR1 and are arranged along the second direction DR2 perpendicular to the first direction DR1. One ends of the data lines DL extend toward one side of the display panel 100 and can be connected to the data driver 600 via a data pad unit (not shown).

The diagonal gate lines DG extend in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 and extend in the first direction DR1 and the third direction DR2 intersecting the first direction DR1 to DR3. Are arranged along the four directions (DR4). The angle formed by the third direction DR3 and the fourth direction DR4 may be variously set. Hereinafter, an example in which the third direction DR3 and the fourth direction DR4 intersect each other is described as an example.

According to the above arrangement, the diagonal gate lines DG extend along the diagonal direction of the display panel 100. [ The diagonal gate lines DG may extend in various shapes such as a linear shape along a third direction DR3, which is a diagonal direction of the display panel 100, or a zigzag shape or a step shape.

The diagonal gate lines DG are formed to have different lengths. More specifically, the diagonal gate lines DG are formed to have a shorter length as they approach the edge of the display panel 100. Some of the diagonal gate lines DG formed in a partial area of the display panel 100 may be formed to have the same length.

The diagonal gate lines DG are connected to the pixels on a pixel line basis. The pixels may be connected in different numbers depending on the length of the diagonal gate lines DG. More specifically, the number of pixels connected to each of the diagonal gate lines DG decreases as the length of the diagonal gate lines DG becomes shorter. The connection relationship between the pixels and the diagonal gate lines DG will be described later with reference to Figs. 4A to 6.

The connection lines LL extend along the second direction DR2. The connection lines LL are superimposed on the black matrix (not shown) of the display panel 100 so as not to lower the aperture ratio of the display panel 100 without being visualized. Both ends of each of the connection lines LL are disposed on opposite sides of the display panel 100. [ For example, one ends of the connection lines LL are disposed along the first side of the display panel 100, and the other ends of the connection lines LL are disposed on the second side of the display panel 100, . The connection lines LL define a plurality of scan units by connecting two or more diagonal gate lines DG so that the pixels can be divided into the same number of scan units. The connection lines LL may be connected to the diagonal gate lines DG through the contacts CT.

Each of the scan units is a unit in which the same gate signal GS outputted from the gate driver 500 during the same horizontal period is supplied. That is, the same gate signal GS provided for the same horizontal period for each scan unit is supplied to the connection lines LL, the diagonal gate lines DG, and the pixels included in the same scan unit.

The number of diagonal gate lines DG constituting one scan unit via the connection lines LL and the contacts CT can be variously changed according to the arrangement of the pixels. The connection structure of the diagonal gate lines DG constituting the scan unit will be described later in more detail with reference to FIGS. 4A to 6. The connection lines LL may be formed to have the same length.

The flexible printed circuit board 200 electrically connects the display panel 100 and the printed circuit board 300. The flexible printed circuit board 200 includes an integrated circuit chip 220. The flexible printed circuit board 200 is electrically connected between the display panel 100 and the printed circuit board 300. The flexible printed circuit board 200 is connected to one side of the display panel 100. The flexible printed circuit board 200 may be of various numbers. Although not shown, the flexible printed circuit board 200 may be mounted on the back surface of the display panel 100 in a state of being bent in a "C" shape.

The printed circuit board 300 may include a plurality of circuit components mounted to drive the display panel 100. The printed circuit board 300 may be mounted on the rear surface of the display panel 100 in a state in which the flexible printed circuit board 200 is bent and mounted.

The timing controller 400 receives the input video signal DATA_IN and the control signal CS from an external graphic controller (not shown). The timing controller 400 receives a first control signal SG1 and a second control signal SG2 by receiving a control signal CS, for example, a vertical synchronization signal, a horizontal synchronization signal, a main clock, a data enable signal, And outputs it. The timing controller 400 converts the input video signal DATA_IN into a data signal DATA_SG in accordance with the specification of the data driver 600 and outputs the data signal to the data driver 600.

The first control signal SG1 is a gate control signal for controlling the operation of the gate driver 500. The first control signal SG1 may include a gate clock, an output enable signal, and a vertical start signal.

The second control signal SG2 is a data control signal for controlling the operation of the data driver 600. [ The second control signal SG2 includes a horizontal start signal for starting the operation of the data driver 600, an inverted signal for inverting the polarity of the data voltage, and an output instruction for determining the timing at which the data voltage is output from the data driver 600 Signal and the like.

The gate driver 500 generates the gate signal GS based on the first control signal SG1. The gate driver 500 provides the gate signals GS to the diagonal gate lines DG via a pad portion (not shown) formed on the display panel 100. [ Gate signals (GS) are sequentially output from the gate driver (500). The pulse width of each of the gate signals GS may be defined as a horizontal period. Each of the gate signals GS is provided for each scan unit. Since the number of pixels according to the exemplary embodiment of the present invention is uniformly allocated to each scan unit, the number of pixels driven by each of the gate signals GS is the same.

The data driver 600 outputs the data voltage DATA in which the data signal DATA_SG is converted based on the second control signal SG2 to the data lines DL via the pad unit (not shown).

The gate driver 500 and the data driver 600 may be formed of one integrated integrated circuit chip 220. The gate driver 500 and the data driver 600 may be formed as separate chips and mounted on the flexible printed circuit board 200, the printed circuit board 300, or the display panel 100, .

The data lines DL according to the embodiment of the present invention extend in a direction parallel to one side of the display panel 100 and the diagonal gate lines DG extend in a diagonal direction of the display panel 100 , DR3. The gate driver 500 and the data driver 600 can be disposed along one surface except for three surfaces of the display panel 100 through the arrangement of the data lines DL and the diagonal gate lines DG . Accordingly, the embodiment of the present invention can provide a single-sided driving structure, thereby reducing the area occupied by the bezel.

Since the diagonal gate lines DG according to the embodiment of the present invention extend toward the diagonal direction of the display panel 100, they may be formed to have different lengths and may be connected to different numbers of pixels. The embodiment of the present invention connects the diagonal gate lines DG through the connection lines LL so as to extend along the second direction DR2 so that each of the scan units includes the same number of pixels, Load variation can be reduced.

3 is a diagram illustrating pixels according to an embodiment of the present invention.

Referring to FIG. 3, the pixels PX are arranged in a matrix form along a first direction DR1 and a second direction DR2 that are perpendicular to each other. In the drawing, the pixels PX arranged in the form of 8 × 5 matrix are exemplified, but the present invention is not limited thereto.

The pixels PX arranged in a line along the third direction DR3 constitute a pixel row. That is, the pixel row direction is defined as the third direction DR3 and follows the extending direction of the diagonal gate lines DG. The third direction DR3 extends in the direction of the diagonal gate lines DG and intersects the first and second directions DR1 and DR2.

The number of pixels PX constituting each of the pixel rows PXR1 to PXR12 may be equal to or less than the reference number. The pixel rows PXR1 to PXR12 can be divided into first to third pixel rows according to the number of pixels constituting each of them and the region in which they are arranged.

The first pixel rows PXR5 to PXR8 are composed of the same number of pixels PX as the reference number and are arranged in a line along the fourth direction DR4. An area where the first pixel rows PXR4 are arranged is defined as a first pixel area A1.

The second pixel rows PXR1 to PXR4 are formed of a number of pixels PX smaller than the reference number and are arranged in the second pixel region A2 adjacent to one side of the first pixel region A1 in the fourth direction DR4 ).

The third pixel rows PXR9 to PXR12 are constituted by a number of pixels PX that is smaller than the reference number and the third pixel region AX facing the second pixel region A2 with the first pixel region A1 therebetween. Are arranged in a line along the fourth direction DR4 in the region A3.

The number of the second pixel rows PXR1 to PXR4 and the number of the third pixel rows PXR9 to PXR12 are the same. The number of pixels PX constituting each of the second pixel rows PXR1 to PXR4 and the third pixel rows PXR9 to PXR12 increases as they approach the first pixel region A1. The number of pixels constituting each of the second pixel rows PXR1 to PXR4 and the third pixel rows PXR9 to PXR12 can be increased uniformly and thermally as they approach the first pixel region A1. For example, as the number of the pixels PX constituting each of the second pixel rows PXR1 to PXR4 and the third pixel rows PXR9 to PXR12 becomes closer to the first pixel region A1, It can be increased by two pixels each time it is changed.

As will be described later, each of the pixels PX is connected to any one of the diagonal gate lines and the data lines. Each of the pixels PX may be provided with a gate signal from the diagonal gate line, and may be supplied with a data voltage from the data line.

The planar shape of the pixels PX may be variously set according to the shape of the diagonal gate lines and the data lines. In order to increase the aperture ratio in the active area of the display panel, each of the pixels PX may be formed in four deformations having four sides parallel to the four sides of the display panel. For example, when each of the pixels PX is formed of a rhombic pattern having four sides intersecting four sides of the display panel, a portion that reduces the aperture ratio occurs at the edge of the display panel. In order to implement the pixels PX having the shape of increasing the aperture ratio, the embodiment of the present invention is characterized in that the data lines DL1 and DL2 are arranged in a straight line extending in a first direction DR1 parallel to one side of the display panel And the diagonal gate lines DG1 and DG2 may be formed in the form of a step extending toward the third direction DR3. According to the shape of the data lines DL1 and DL2 and the shapes of the diagonal gate lines DG1 and DG2 according to the embodiment of the present invention, each of the pixels PX has four sides parallel to the four sides of the display panel Respectively.

Although not shown in the figure, each of the pixels PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

FIGS. 4A to 4E are views showing a display device according to an embodiment of the present invention including pixels arranged in an M × N matrix in which M> N. A display panel composed of pixels arranged in an M x N matrix in which M > N can be a display panel (for example, a display panel having an aspect ratio of 16: 9) that is longer than the vertical.

FIGS. 4A and 4B are diagrams for explaining a method for connecting second pixel rows and third pixel rows among the first through third pixel rows defined in FIG. 3 through connection lines. For convenience of explanation, the first diagonal gate lines connected to the first pixel rows are not shown in Figs. 4A and 4B.

4A and 4B, the second pixel rows are connected to the second diagonal gate lines DG1 to DG4, and the third pixel rows are connected to the third diagonal gate lines DG9 to DG12. The second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG9 and DG12 may be formed in a stepped shape for a display panel having a high aperture ratio as described above with reference to FIG.

The number of pixels PX constituting each of the second pixel rows and the number of pixels PX constituting each of the third pixel rows are set to be equal to the number of pixels PX constituting each of the first pixel rows And increases as it approaches the pixel region. Accordingly, the length of the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG9 to DG12 increases as they approach the first pixel region between them.

Each of the connection lines LL1 to LL4 includes second diagonal gate lines DG1 to DG4 having different lengths so as to connect a pair of second pixel lines and a third pixel line including a different number of pixels, The third diagonal gate lines DG9 to DG12 are connected in pairs. A pair of the second pixel row and the third pixel row connected through the connection lines LL1 to LL4 define one scan unit. The connection lines LL1 to LL4 may extend in the second direction DR2 and connect the second diagonal gate lines DG1 to DG4 and third diagonal gate lines DG9 to DG12 having different lengths have. The connection lines LL1 to LL4 may be formed of the same conductive material in the same layer with the same length. The connection lines LL1 to LL4 are arranged along the first direction DR1.

And the second diagonal gate lines DG1 to DG4 are connected to the ends of the connection lines LL1 to LL4 via the contacts CT. And the third diagonal gate lines DG9 to DG12 are connected to the other ends of the connection lines LL1 to LL4 through the contacts CT.

As shown in FIG. 4A, each of the connection lines LL1 to LL4 may extend along a second direction DR2 between a pair of second pixel rows and a third pixel row connected thereto. 4B, each of the connection lines LL1 to LL4 is connected in a second direction DR2 between a pair of second pixel rows connected thereto and pixel rows one row below the third pixel row, Lt; / RTI &gt; The extension lengths of the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG9 to DG12 may be varied depending on the positions of the connection lines LL1 to LL4.

According to the above-described connection structure, the second and third pixel row pairs constituting the scan unit may include the same number of pixels PX as the number of the pixels PX constituting each of the first pixel rows have. Accordingly, the embodiment of the present invention can equally distribute the number of the pixels PX driven for each scan unit, thereby stabilizing the driving characteristics of the display device.

The embodiment of the present invention connects pairs of the second diagonal gate lines DG1 to DG4 and third diagonal gate lines DG9 to DG12 having different lengths through the connection lines LL1 to LL4, . Thus, the embodiment of the present invention can uniformly form the lengths of signal lines for each scan unit, thereby reducing the load deviation per scan unit.

The embodiment of the present invention can reduce the scan time because one scan unit is formed by connecting the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG9 to DG12 in pairs.

4C to 4E are views for explaining a method of connecting dummy lines to first pixel rows among the first to third pixel rows defined in FIG. For convenience of explanation, the second and third diagonal gate lines connected to the second and third pixel rows are not shown in Figs. 4C to 4E.

Referring to Figures 4C-4E, the first pixel rows are connected to the first diagonal gate lines DG5 to DG8. The first diagonal gate lines DG5 to DG8 are disposed between the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG9 to DG12 described above with reference to Figs. 4A and 4B. The first diagonal gate lines DG5 to DG8 may be formed in a stepped shape for a display panel having a high aperture ratio, as described above with reference to FIG.

The number of pixels PX constituting each of the first pixel rows is equal to the total number of pixels PX of the pair of second pixel rows and the third pixel row constituting one scan unit. Accordingly, each of the first pixel rows can constitute one scan unit. The first diagonal gate lines DG5 to DG5 connected to the first pixel rows are connected to the first pixel rows in order to reduce the load difference per scan unit composed of the scan units of the first pixel rows and the pair of second and third pixel rows, The dummy lines DLL1 to DLL4 can be connected to the respective bit lines DG1 to DG8. The dummy lines DLL1 to DLL4 may be connected to the first diagonal gate lines DG5 to DG8 through the contacts CT.

The dummy lines DLL1 to DLL4 may be formed of the same metal in the same layer as the connection lines (LL1 to LL4 in Figs. 4A and 4B). In this case, the dummy lines DLL1 to DLL4 and the connection lines LL1 to LL4 can be formed simultaneously using one mask.

The dummy lines DLL1 to DLL4 may be arranged in the first direction DR1. The dummy lines DLL1 to DLL4 are formed so as to overlap the black matrix (not shown) of the display panel. The dummy lines DLL1 to DLL4 may be formed with the same line width as the connection lines (LL1 to LL4 in Figs. 4A and 4B).

As shown in FIG. 4C, the dummy lines DLL1 to DLL4 may extend along the second direction DR2 from the lower side of the display panel. The lower side of the display panel is a portion facing one side of the display panel 100 adjacent to the gate driver 500 and the data driver 600 shown in Fig.

As shown in FIG. 4D, the dummy lines DLL1 to DLL4 may extend along the second direction DR2 from above the display panel. The upper side of the display panel is a portion adjacent to one side of the display panel 100 adjacent to the gate driver 500 and the data driver 600 shown in Fig.

The dummy lines DLL1 to DLL4 may be formed to have the same length as the connection lines LL1 to LL4, as shown in Figs. 4C and 4D.

In order to minimize the formation area of the dummy lines DLL1 to DLL4, the dummy lines DLL1 to DLL4 may be formed to have different lengths as shown in Fig. 4E. For example, the dummy lines DLL1 to DLL4 may be formed so that their lengths decrease as they go down. In this case, the lengths of the dummy lines DLL1 to DLL2 may be shorter than the lengths of the connection lines LL1 to LL4.

The data lines DL1 to DL8 shown in FIGS. 4A to 4E extend in the first direction DR1 and are connected to the pixels PX as described in FIG. 2, and the second direction DR2 . The data lines DL1 to DL8 are formed to be insulated from the dummy lines DLL1 to DLL4, the connection lines LL1 to LL4, and the first to third diagonal gate lines DG1 to DG12.

5 is a diagram illustrating a display device according to an embodiment of the present invention including pixels arranged in an M x N matrix in which M = N. A display panel composed of pixels arranged in an M x N matrix in which M = N can be a display panel having an aspect ratio of 1: 1. Hereinafter, the definitions of the first to third pixel rows are the same as those described above in Fig.

Referring to FIG. 5, the second pixel rows are connected to the second diagonal gate lines DG1 to DG4, and the third pixel rows are connected to the third diagonal gate lines DG6 to DG9. One first pixel row may be disposed between the second and third pixel rows, and the first pixel row is connected to the first diagonal gate line DG5. The first to third diagonal gate lines DG1 to DG9 may be formed in a stepped shape for a display panel having a high aperture ratio, as described above with reference to FIG.

The connection lines LL1 to LL4 are connected to the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG1 to DG4 having different lengths so that the second pixel rows and the third pixel rows can constitute a pair of scan units. The lines DG6 to DG9 are connected in pairs. The connection lines LL1 to LL4 are connected to the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG6 to DG9 via the contacts CT. The specific connection relationships of the connection lines LL1 to LL4, the second diagonal gate lines DG1 to DG4, and the third diagonal gate lines DG6 to DG9 are the same as those described in Figs. 4A and 4B.

The number of the pixels PX constituting the first pixel row is equal to the total number of the pixels PX of the pair of second pixel rows and the third pixel row constituting one scan unit. Accordingly, the first pixel row can constitute one scan unit. A dummy line (DLL) may be connected to the first diagonal gate line (DG5) to reduce the load difference per scan unit consisting of a load per scan unit composed of the first pixel line and a pair of second and third pixel lines .

The dummy line (DLL) may be connected to the first diagonal gate line (DG5) through the contact (CT). The dummy line (DLL) may be formed of the same metal on the same layer as the connection lines (LL1 to LL4), and is formed to overlap the black matrix (not shown) of the display panel. The dummy lines DLL are formed along the second direction DR2 and may have the same line width and the same length as the connection lines LL1 to LL4. The dummy line (DLL) may be disposed on the lower side of the display panel or on the upper side of the display panel as described above with reference to FIG. 4D.

The data lines DL1 to DL5 shown in FIG. 5 extend along the first direction DR1 to connect to the pixels PX and are arranged along the second direction DR2 as described in FIG. 2 . The data lines DL1 to DL5 are formed so as to be insulated from the dummy line DLL, the connection lines LL1 to LL4, and the first to third diagonal gate lines DG1 to DG9.

According to the structure shown in FIG. 5, each of the second and third pixel row pairs constituting the scan unit has the same number of pixels PX as the number of the pixels PX constituting each of the first pixel rows . Accordingly, the embodiment of the present invention can equally distribute the number of the pixels PX driven for each scan unit, thereby stabilizing the driving characteristics of the display device.

The embodiment of the present invention connects pairs of the second diagonal gate lines DG1 to DG4 and third diagonal gate lines DG6 to DG9 having different lengths through the connection lines LL1 to LL4, . Thus, the embodiment of the present invention can uniformly form the lengths of signal lines for each scan unit, thereby reducing the load deviation per scan unit.

The embodiment of the present invention can reduce the scan time by connecting one pair of the second diagonal gate lines DG1 to DG4 and the third diagonal gate lines DG6 to DG9 to form one scan unit.

FIG. 6 is a diagram illustrating a display device according to an embodiment of the present invention including pixels arranged in an M × N matrix in the form of M <N. (For example, a display panel having an aspect ratio of 16: 8 (= 2: 1)) that is longer than the horizontal can be used as the display panel composed of pixels arranged in the form of an MxN matrix with M & have. Hereinafter, the definitions of the first to third pixel rows are the same as those described above in Fig.

Referring to FIG. 6, a plurality of first pixel rows are disposed between the second pixel rows and the third pixel rows. The first diagonal gate lines DG5 and DG10 are connected to a pair of edge pixel lines arranged at the outermost of the first pixel rows. The second diagonal gate lines DG6 to DG9 are connected to the center pixel rows arranged between the first diagonal gate lines DG5 and DG10 among the first pixel rows. The second pixel rows are connected to the third diagonal gate lines DG1 to DG4, and the third pixel rows are connected to the fourth diagonal gate lines DG11 to DG14. The first to fourth diagonal gate lines DG1 to DG14 may be formed in the form of a step for implementing a display panel having a high aperture ratio, as described above with reference to FIG.

The number of pixels PX constituting each of the second pixel rows and the number of pixels PX constituting each of the third pixel rows are set to be equal to the number of pixels PX constituting each of the first pixel rows And increases as it approaches the pixel region. Accordingly, the third diagonal gate lines DG1 to DG4 and the fourth diagonal gate lines DG10 to DG14 increase in length as they approach the first pixel region between them.

The first to fourth diagonal gate lines DG1 to DG14 are formed of the same conductive layer in the same layer and can be formed using one mask.

The connection lines LL1 to LL9 extend along the second direction DR2 and are arranged along the first direction DR1. The connection lines LL1 to LL9 include a first connection line LL5, second connection lines LL1 to LL4, and third connection lines LL6 to LL9. The connection lines LL1 to LL9 are formed of the same conductive material in the same layer, and can be formed using one mask. An insulating layer (not shown) may be disposed between the layer in which the connection lines LL1 to LL9 are formed and the layer in which the first to fourth diagonal gate lines DG1 to DG14 are formed.

The first connection line LL5 extends in the second direction DR2 to connect the first diagonal gate lines DG5 and DG10. First diagonal gate lines DG5 and DG10 connected to the edge pixel rows of the first pixel rows are connected to both ends of the first connection line LL5 through the contacts CT. The first connection line LL5 is disposed between the second connection lines LL1 to LL4 and the third connection lines LL6 to LL9.

The second connection lines LL1 to LL4 extend in the second direction DR2 and connect the second diagonal gate lines DG6 to DG9 and the third diagonal gate lines DG1 to DG4 in pairs. The third diagonal gate lines DG1 to DG4 connected to the second pixel rows are connected to one ends of the second connection lines LL1 to LL4 through the contacts CT, The second diagonal gate lines DG6 to DG9 connected to the center pixel rows are connected via the contacts CT.

The third connection lines LL6 to LL9 extend in the second direction DR2 to connect the second diagonal gate lines DG6 to DG9 and the fourth diagonal gate lines DG10 to DG14 in pairs. Four diagonal gate lines DG10 to DG14 connected to the third pixel rows are connected to one ends of the third connection lines LL6 to LL9 through the contacts CT, The second diagonal gate lines DG6 to DG9 connected to the center pixel rows are connected via the contacts CT.

One ends of the second diagonal gate lines DG6 to DG9 are arranged in a line and connected to the second connection lines LL1 to LL4 and the other ends are arranged in a line to connect to the third connection lines LL6 to LL9 do. Thus, the second connection lines LL1 to LL4 and the third connection lines LL6 to LL9 can be connected in pairs to each of the second diagonal gate lines DG6 to DG9. That is, any one of the second connection lines LL1 to LL4 and the third connection lines LL6 to LL9 may be commonly connected to any one of the second diagonal gate lines DG6 to DG9 .

The second diagonal gate lines DG6 to DG9, the third diagonal gate lines DG1 to DG4 and the fourth diagonal gate lines DG10 to DG14 are connected to the second connection lines LL1 to LL4, And are connected in a scan unit by the connection lines LL6 to LL9. The second pixel row and the third pixel row constituting the scan unit include different numbers of pixels PX. At this time, the total number of pixels PX of the second pixel row and the third pixel row constituting the scan unit is equal to the total number of pixels PX constituting the first pixel row. And the third diagonal gate lines DG1 to DG4 and the fourth diagonal gate lines DG10 to DG14 connected to each other constitute a scan unit.

The first diagonal gate lines DG5 and DG10 are connected through a first connection line LL5 to form a scan unit.

According to the above-described connection structure, the total number of the pixels PX constituting the scan unit can be made twice as large as the number of the pixels PX constituting each of the first pixel rows. Accordingly, the embodiment of the present invention can equally distribute the number of the pixels PX driven for each scan unit, thereby stabilizing the driving characteristics of the display device.

The embodiment of the present invention is characterized in that the third diagonal gate lines DG1 to DG4 having different lengths through the second connection lines LL1 to LL4 and the third connection lines LL6 to LL9 and the fourth diagonal line The gate line (any one of DG10 to DG14) can be defined as one scan unit. Accordingly, the embodiment of the present invention can uniformly form the lengths of the signal lines for each scan unit, thereby reducing the load deviation per scan unit.

The embodiment of the present invention disposes the first to third connection lines LL1 to LL9 so that at least two of the first to fourth diagonal gate lines DG1 to DG14 can operate in one scan unit, Time can be reduced.

The first diagonal gate lines DG5 and DG10 connected to the first pixel rows may be connected in one scan unit by only one first connection line LL5. A dummy line (DLL) is connected to any one of the first diagonal gate lines DG5 and DG10. Thereby, a load of a scan unit composed of first pixel rows connected to the first diagonal gate lines DG5 and DG10, a load of a scan unit composed of a pair of second and third pixel lines and a first pixel row, The difference can be reduced.

The dummy line (DLL) may be connected to either one of the first diagonal gate lines (DG5, DG10) through the contact (CT). The dummy line (DLL) may be formed of the same metal on the same layer as the connection lines (LL1 to LL9). In this case, the dummy line (DLL) and the connection lines (LL1 to LL9) may be formed using one mask at the same time. The dummy lines (DLL) are formed to overlap the black matrix (not shown) of the display panel and can be formed with the same line width and the same length as the connection lines LL1 to LL9. The dummy line (DLL) may extend along the second direction DR2 on the lower side or the upper side of the display panel.

The data lines DL1 to DL10 shown in FIG. 6 extend along the first direction DR1 and are connected to the pixels PX as described in FIG. 2, and are spaced along the second direction DR2 . The data lines DL1 to DL10 are formed so as to be insulated from the dummy lines DLL, the connection lines LL1 to LL9, and the first to fourth diagonal gate lines DG1 to DG14.

The pixels PX constitute a pixel column along the first direction DR1 and the pixel columns correspond to the odd data lines DL1, DL3, DL5, DL7 and DL9 and the even data lines DL2, DL4, DL8, and DL10. The pixels PX constituting the pixel column are divided into odd-numbered data lines DL1, DL3, DL5, DL7 and DL9 and even-numbered data lines DL2, DL4, DL6, DL8, DL10). Thus, the display device according to the embodiment of the present invention can be driven to have the polarity arrangement as shown in Fig.

In the embodiments described above with reference to FIGS. 4A to 6, the channels for receiving signals from the gate driver and the data driver may be arranged in various ways on one side of the display panel adjacent to the gate driver and the data driver depending on the position of the dummy line.

The embodiments of the present invention described above can extend the data lines along the direction parallel to one side of the display panel and extend the gate lines in the diagonal direction of the display panel intersecting the data lines to provide a cross sectional drive structure.

Also, embodiments of the present invention define scan units by connecting diagonal gate lines extending in the diagonal direction of the display panel and having different lengths through connection lines. Thus, the embodiments of the present invention can reduce the load deviation per scan unit of a display device having a single-sided driving structure, and can uniformize the number of pixels to be distributed per scan unit.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

PX: Pixels PXR1 to PXR12:
DL, DL1 to DL10: Data line DG, DG1 to DG14: Diagonal gate line
LL, LL1 to LL9: connection line DLL, DLL1 to DLL4: dummy line
500: Gate driver 600: Data driver
100: display panel

Claims (12)

A plurality of scan units arranged in a matrix along a first direction and a second direction perpendicular to the first direction and having pixel rows along a third direction intersecting the first and second directions, Pixels;
Data lines extending along the first direction and arranged along the second direction, the data lines being connected to the pixels;
Diagonal gate lines extending in the third direction and connected to the pixels in the pixel line unit direction and arranged in a fourth direction crossing the first to third directions; And
And connection lines extending along the second direction to connect the diagonal gate lines such that each of the scan units includes the same number of pixels. The method according to claim 1,
The pixel rows composed of the pixels
A first pixel row composed of the same number of pixels as the reference number and arranged in the first pixel region;
Second pixel rows arranged in a second pixel region adjacent to one side of the first pixel region, the second pixel rows being composed of a smaller number of pixels than the reference number; And
And third pixel rows arranged in a third pixel region facing the second pixel region with the first pixel region interposed therebetween, the third pixel rows being made up of a smaller number of pixels than the reference number,
Wherein the number of pixels constituting each of the second and third pixel rows increases as the pixel region approaches the first pixel region. 3. The method of claim 2,
The pixel rows
And M > N matrices. 3. The method of claim 2,
The pixel rows
And pixels arranged in an M x N matrix in which M = N. The method according to claim 3 or 4,
The diagonal gate lines
A first diagonal gate line connected to the first pixel line;
Second diagonal gate lines connected to the second pixel rows and increasing in length toward the first pixel region; And
And third diagonal gate lines connected to the third pixel rows and increasing in length toward the first pixel region,
Each of the connection lines defines the scan units by connecting a pair of the second and third diagonal gate lines having different lengths,
Wherein the number of pixels constituting each of the scan units is equal to the reference number. 6. The method of claim 5,
A gate driver and a data driver connected to the display panel along one side of a display panel including the pixels to provide a driving signal to the pixels; And
Further comprising a dummy line extending along the second direction on the upper side of the display panel adjacent to the one side of the display panel or below the display panel facing the one side of the display panel and connected to the first diagonal gate line / RTI &gt; The method according to claim 6,
Wherein the dummy lines are formed to be equal to or shorter than the lengths of the connection lines. 3. The method of claim 2,
Wherein the pixel rows are composed of pixels arranged in an M x N matrix shape including M <N, including a plurality of the first pixel rows. 9. The method of claim 8,
The diagonal gate lines
A pair of first diagonal gate lines connected to a pair of edge pixel rows arranged at the outermost of the plurality of first pixel rows;
Second diagonal gate lines connected to the center pixel rows disposed between the first diagonal gate lines of the plurality of first pixel rows;
Third diagonal gate lines connected to the second pixel rows and increasing in length toward the first pixel region; And
And fourth diagonal gate lines connected to the third pixel rows and increasing in length toward the first pixel region,
The connection lines
A first connection line connecting the first diagonal gate lines;
Second connection lines connecting the second and third diagonal gate lines in pairs; And
And third connection lines connecting the second and fourth diagonal gate lines in pairs. 10. The method of claim 9,
One ends of the second diagonal gate lines are arranged in a line and connected to the second connection lines, the other ends of the second diagonal gate lines are arranged in a line and connected to the third connection lines, Lines and the third connection lines are connected to each of the second diagonal gate lines by a pair. 10. The method of claim 9,
And a dummy line connected to any one of the first diagonal gate lines and extending along the second direction. 10. The method of claim 9,
Pixel rows arranged in the first direction are arranged between odd-numbered data lines and even-numbered data lines among the data lines,
And the pixels constituting the pixel column are alternately connected to the odd-numbered data line and the even-numbered data line along the first direction.

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