KR20160046203A - Data driving circuit and display device including the same - Google Patents

Abstract

Provided are a data driving circuit which can reduce the size of the data driving circuit by reducing the number of components and a display device including the same. The data driving circuit includes a first gamma voltage generation unit and a second gamma voltage generation unit. The first gamma voltage generation unit and the second gamma voltage generation unit generate a gamma voltage corresponding to a 255 gradation level from a voltage provided from the outside, and the rest gamma voltages corresponding to 0 to 192 gradation levels can be generated by distributing the voltage provided from the outside by using a decoder and a buffer.

Description

[0001] The present invention relates to a data driving circuit and a display device including the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving circuit of a display device, and more particularly, to a data driving circuit and a display device including the same, which can reduce the size and manufacturing cost by reducing the number of components.

Due to the development of the information society, display devices capable of displaying information are actively being developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

1 is a view showing a conventional liquid crystal display device.

1, a conventional liquid crystal display device 1 includes a liquid crystal panel 10, a timing control unit 20, a gate driving unit 30, a data driving unit 40, and a gamma voltage generating unit 50 .

The liquid crystal panel 10 includes two substrates (not shown) and a liquid crystal layer (not shown) therebetween, and a plurality of gate lines GL and a plurality of data lines DL are formed on the substrate. Pixels are defined in the intersecting region of the gate line GL and the data line DL and a thin film transistor TFT, a liquid crystal capacitor Clc and a storage capacitor Cst are formed in each pixel.

The timing controller 20 generates a gate control signal GCS, a data control signal DCS, and image data RGB.

The gate driver 30 generates a gate signal according to the gate control signal GCS provided by the timing controller 20 and sequentially outputs the gate signal to the plurality of gate lines GL.

The data driver 40 generates a data signal having positive and negative polarities from the image data RGB according to the data control signal DCS provided from the timing controller 20, (DL). The data signal is generated using the gamma voltage VG corresponding to the image data RGB among the gamma voltages VG provided from the gamma voltage generator 50. [

The gamma voltage generator 50 generates an analog gamma voltage VG corresponding to each gradation level of the image data RGB and outputs it to the data driver 40. [

The gamma voltage generator 50 generates at least one representative voltage from an externally provided voltage and divides the voltage to generate a plurality of gamma voltages VG. To this end, the gamma voltage generator 50 includes a plurality of buffers (not shown), a plurality of decoders (not shown), and a resistor string (not shown).

For example, the gamma voltage generator 50 includes five input and output buffers and five decoders for generating five representative voltages from an external voltage. The gamma voltage generator 50 is provided with at least one resistor string to divide the five representative voltages and generate a plurality of gamma voltages VG corresponding to the 255 gradation levels.

The gamma voltage generator 50 generates the positive gamma voltage VG and the negative gamma voltage VG in accordance with the driving method of the liquid crystal panel 10, that is, the inversion driving of the liquid crystal panel 10. Therefore, the buffer, decoder, and resistor string of the gamma voltage generator 50 described above are each configured to generate the positive gamma voltage VG and the negative gamma voltage VG.

That is, in the conventional gamma voltage generator 50, the configuration of the buffer and decoder required to generate the positive / negative gamma voltage VG corresponding to the 255th gray level is increased, Is increased.

When the data driving unit 40 and the gamma voltage generating unit 50 are constituted by one data driving circuit, the size of the data driving circuit is also increased by the gamma voltage generating unit 50, The manufacturing cost of the semiconductor device is increased.

An object of the present invention is to provide a data driving circuit and a display device including the same that can reduce the size by reducing the number of components by simplifying the configuration.

According to an aspect of the present invention, there is provided a data driving circuit including a first gamma voltage generating unit and a second gamma voltage generating unit.

The first gamma voltage generator outputs a first voltage as a first positive gamma voltage, a second through a fifth positive gamma voltage from the first voltage and a reference voltage, And outputs the positive gamma voltage.

The second gamma voltage generating unit outputs the second voltage to the first negative gamma voltage, generates the second to fifth negative gamma voltages from the second voltage and the reference voltage, and the second to fifth negative gamma voltages And outputs a plurality of negative gamma voltages.

According to an aspect of the present invention, there is provided a display device including a display panel, a gate driving circuit, and a data driving circuit. The data driving circuit includes a first gamma voltage generator and a second gamma voltage generator.

The data driving circuit according to the present invention can reduce the number of buffers and decoders required for generating positive / negative gamma voltages corresponding to 0 to 255 gradation levels, Can be reduced.

Accordingly, it is possible to reduce the size and manufacturing cost of the gamma voltage generator and the data driving circuit including the same, and further reduce the manufacturing cost of the display device provided with the data driving circuit.

1 is a view showing a conventional liquid crystal display device.
2 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
3 is a diagram illustrating a configuration of a gamma voltage generator according to an exemplary embodiment of the present invention.
FIG. 4 is a diagram showing the configuration of the positive gamma voltage generator shown in FIG. 3. FIG.
5 is a diagram showing a configuration of the negative gamma voltage generator shown in FIG.
6 is a diagram illustrating a configuration of a gamma voltage generator according to another embodiment of the present invention.
FIG. 7 is a diagram showing the configuration of the positive gamma voltage generator shown in FIG. 6. FIG.
8 is a diagram showing the configuration of the negative gamma voltage generator shown in FIG.

Hereinafter, a data driving circuit and a display device including the same according to the present invention will be described in detail with reference to the accompanying drawings.

For convenience of explanation, the present invention will be described by taking a liquid crystal display device and a data driving circuit included therein as an example. However, the present invention is not limited thereto, and it will be apparent that, in addition to a liquid crystal display, a data driving circuit such as an organic light emitting display may be used in various display devices for supplying data signals to the data lines of the display panel.

2 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

2, the liquid crystal display 100 according to the present embodiment includes a display panel 110, a timing controller 120, a gate driver 130, a data driver 140, and a gamma voltage generator 150 . Here, the data driver 140 and the gamma voltage generator 150 may be formed of one circuit, that is, one data driver circuit.

The display panel 110 may include a liquid crystal layer (not shown) interposed between two substrates (not shown). A plurality of gate lines GL and a plurality of data lines DL may be formed to intersect with each other in the display panel 110 to define pixels. A thin film transistor (TFT), a storage capacitor Cst, and a liquid crystal capacitor Clc may be formed in each pixel.

The timing controller 120 may generate a gate control signal GCS and a data control signal DCS from the control signals provided from an external system (not shown). The timing controller 120 may generate image data RGB by rearranging the image signals provided from the external system to the resolution of the display panel 110. [

The gate driver 130 generates a gate signal according to the gate control signal GCS provided from the timing controller 120 and sequentially outputs the gate signal to a plurality of gate lines GL of the display panel 110. [

The data driver 140 generates a data signal from the image data RGB according to the data control signal DCS provided from the timing controller 120 and outputs the data signal to a plurality of data lines DL of the display panel 110 . Here, the data driver 140 applies one of the gamma voltages corresponding to the gradation levels of the image data RGB among the gamma voltages provided by the gamma voltage generator 150, for example, the positive gamma voltage VGP and the negative gamma voltage VGN, The data signal can be generated using the gamma voltage.

The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, an output enable signal GOE, and the like. The data control signal DCS may include a source start pulse SSP, a source sampling clock SSC, an output enable signal SOE, a polarity control signal POL, and the like.

The gamma voltage generator 150 may generate a plurality of positive gamma voltages VGP and a plurality of negative gamma voltages VGN using a plurality of voltages VE provided from an external system. A plurality of positive gamma voltages VGP and a plurality of negative gamma voltages VGN may be output to the data driver 140.

The gamma voltage generator 150 may generate and output a positive gamma voltage VGP and a negative gamma voltage VGN in the form of analog voltages corresponding to the 0 to 255 gradation levels of the liquid crystal display 100, respectively. The data driver 140 may generate the data signal using one of the positive gamma voltage VGP and the negative gamma voltage VGN according to the inversion method of the display panel 110. [

3 is a diagram illustrating a configuration of a gamma voltage generator according to an exemplary embodiment of the present invention.

2 and 3, the gamma voltage generator 150 of the present embodiment may include a positive gamma voltage generator 151 and a negative gamma voltage generator 152. [

The positive gamma voltage generator 151 may generate a plurality of positive gamma voltages VGP from the externally input first voltage VE1 and the second voltage VE2.

The positive gamma voltage VGP may be generated as an analog voltage having a positive level based on the reference voltage HVDD. The positive gamma voltage VGP may be generated at a voltage corresponding to the 0 to 192 and 255 gradation levels of the liquid crystal display device 100. [

Here, the reference voltage HVDD may be generated from the fifth voltage VE5 input to the gamma voltage generator 150 from the outside. That is, the gamma voltage generator 150 further includes a reference voltage buffer 155. The reference voltage buffer 155 may stabilize the externally provided fifth voltage VE5 and output it as the reference voltage HVDD . The reference voltage HVDD may be a half of the driving voltage VDD input to the liquid crystal display 100, for example, about 3.9 to 4.2 V. [

FIG. 4 is a diagram showing the configuration of the positive gamma voltage generator shown in FIG. 3. FIG.

3 and 4, the positive gamma voltage generator 151 includes a first input buffer module 201, a first resistor string 202, a first resistor string 204, a first decoder module 205, A second resistor string 206 and a second resistor string 207.

The first input buffer module 201, 202 may include a first input buffer 201 and a second input buffer 202. The first input buffer modules 201 and 202 may stabilize the first voltage VE1 and the second voltage VE2 and output the stabilized voltage. For example, the first input buffer 201 may stabilize and output the first voltage VE1, and the second input buffer 202 may stabilize and output the second voltage VE2.

Here, the first input buffer 201 may output the stabilized first voltage VE1 as a first gamma voltage, for example, the first positive gamma voltage VGP255. The first positive gamma voltage VGP255 may be a voltage corresponding to a 255th gradation level. The 255 gradation level may be a black gradation of the display panel 110. [

The first resistor string 204 may be located between the first input buffer 201 and the second input buffer 202. The first resistor string 204 may be configured by connecting a plurality of resistors R1 having a predetermined resistance value in series.

The first resistor string 204 may generate a plurality of reference voltages by voltage-dividing the first voltage VE1 and the second voltage VE2. A plurality of reference voltages may be input to the first decoder module 205.

The first decoder module 205 may select and output a plurality of representative gamma voltages from a plurality of reference voltages generated by voltage division by the first resistor string 204 according to the first control signal CNT1. The first decoder module 205 generates four gamma voltages corresponding to four gradation levels among the plurality of reference voltages provided through the first resistor string 204, for example, the second through fifth positive gamma voltages VGP192, VGP128, and VGP64 , VGP0) can be selected and output as the representative gamma voltage.

The first decoder module 205 may include first through fourth decoders PD1 through PD4. The first decoder PD1 may output one of the plurality of reference voltages output from the first resistor string 204 as the second positive gamma voltage VGP192. The second decoder PD2 may output one of the plurality of reference voltages output from the first resistor string 204 to the third positive gamma voltage VGP128. The third decoder PD3 may output one of the plurality of reference voltages output from the first resistor string 204 as the fourth positive gamma voltage VGP64. The fourth decoder PD4 may output one of the plurality of reference voltages output from the first resistor string 204 as the fifth positive gamma voltage VGP0.

The second positive gamma voltage VGP192 is a voltage corresponding to 192 gradation levels, the third positive gamma voltage VGP128 is a voltage corresponding to 128 gradation levels, and the fourth positive gamma voltage VGP64 corresponds to 64 gradation levels And the fifth positive gamma voltage VGP0 may be a voltage corresponding to the 0 gradation level.

In this case, eight reference voltages are input from the first resistor string 204 to each decoder of the first decoder module 205, and according to the first control signal CNT1 input from the outside to the first decoder module 205, Each decoder can select one of eight reference voltages as a representative gamma voltage and output it. That is, the first resistor string 204 may generate more than 32 reference voltages from the first voltage VE1 and the second voltage VE2, and the first decoder module 205 may generate the first control signal CNT1, , Four of the 32 or more reference voltages can be selected as representative gamma voltages and output.

The first control signal CNT1 may be a signal composed of 3-bit binary data. The first control signal CNT1 may be input to the first to fourth decoders PD4 separately or simultaneously.

The first output buffer module 206 may be connected to corresponding outputs of the first to fourth decoders PD1 to PD4 of the first decoder module 205, respectively. The first output buffer module 206 may include first through fourth output buffers PB1 through PB4.

The first output buffer PB1 is connected to the output of the first decoder PD1 to stabilize and output the second positive gamma voltage VGP192 output from the first decoder PD1. The second output buffer PB2 is connected to the output of the second decoder PD2 to stabilize and output the third positive gamma voltage VGP128 output from the second decoder PD2. The third output buffer PB3 is connected to the output of the third decoder PD3 to stabilize and output the fourth positive gamma voltage VGP64 output from the third decoder PD3. The fourth output buffer PB4 is connected to the output of the fourth decoder PD4 to stabilize and output the fifth positive gamma voltage VGP0 output from the fourth decoder PD4.

The second resistor string 207 may be located between the first output buffer PB1 and the fourth output buffer PB4. The second resistor string 207 may be configured by connecting a plurality of resistors R2 in series. The second resistor string 207 may generate a plurality of gamma voltages by voltage-dividing the second positive gamma voltage (VGP192) to the fifth positive gamma voltage (VGP0).

For example, the second resistor string 207 positioned between the first output buffer PB1 and the second output buffer PB2 distributes the second positive gamma voltage (VGP192) and the third positive gamma voltage (VGP128) It is possible to output a plurality of positive gamma voltages VGP corresponding to a plurality of gamma voltages, for example, a gradation level between 192 gradation levels and 128 gradation levels. The second resistor string 207 positioned between the second output buffer PB2 and the third output buffer PB3 is used for voltage dividing the third positive gamma voltage VGP128 and the fourth positive gamma voltage VGP64 It is possible to output a plurality of positive gamma voltages (VGP) corresponding to the gradation levels between 128 gradation levels and 64 gradation levels. The second resistor string 207 placed between the third output buffer PB3 and the fourth output buffer PB4 distributes the voltage between the fourth positive gamma voltage VGP64 and the fifth positive gamma voltage VGP0 It is possible to output a plurality of positive gamma voltages (VGP) corresponding to the gradation levels between the 64th gradation level and the 0th gradation level.

As described above, the positive gamma voltage generator 151 according to the present embodiment outputs the first voltage VE1 provided from the outside to the first positive gamma voltage VGP255 corresponding to the 255th gradation level, , For example, the gamma voltage corresponding to the 0 to 192 gradation level can be generated from the first voltage VE1 and the second voltage VE2 using four decoders.

Accordingly, the gamma voltage generator 150 of the present invention can reduce the number of buffers and decoders required when a positive gamma voltage of 0 to 255 gradation levels is generated as compared with a conventional gamma voltage generator.

2 and 3, the negative gamma voltage generator 152 may generate a plurality of negative gamma voltages VGN from the externally input third voltage VE3 and the fourth voltage VE4 .

The negative gamma voltage VGN may be generated in the form of an analog voltage having a level with respect to the reference voltage HVDD. The negative gamma voltage VGN may be generated at a voltage corresponding to the 0 to 192 and 255 gradation levels of the liquid crystal display device 100. [

The reference voltage HVDD may be generated from the fifth voltage VE5 input to the gamma voltage generator 150 from the outside as described above with reference to the positive gamma voltage generator 151. [

5 is a diagram showing a configuration of the negative gamma voltage generator shown in FIG.

3 and 5, the negative gamma voltage generator 152 includes a second input buffer module 211, 212, a third resistor string 214, a second decoder module 215, A second resistor string 216 and a fourth resistor string 217.

The second input buffer modules 211 and 212 may include a third input buffer 211 and a fourth input buffer 212. The second input buffer modules 211 and 212 may stabilize and output the third voltage VE3 and the fourth voltage VE4. For example, the third input buffer 211 may stabilize and output the third voltage VE3, and the fourth input buffer 212 may stabilize the fourth voltage VE4.

Here, the fourth input buffer 212 may output the stabilized fourth voltage VE4 as a first gamma voltage, for example, the first negative gamma voltage VGN255. Here, the first negative gamma voltage VGN255 may be a voltage corresponding to the 255 gradation level. The 255 gradation level may be a black gradation of the display panel 110. [

The third resistor string 214 may be located between the third input buffer 211 and the fourth input buffer 212. The third resistor string 214 may be configured by connecting a plurality of resistors R1 having a predetermined resistance value in series. The third resistor string 214 may generate a plurality of reference voltages by voltage dividing the third voltage VE3 and the fourth voltage VE4. A plurality of reference voltages may be input to the second decoder module 215.

The second decoder module 215 may select and output a plurality of representative gamma voltages from a plurality of reference voltages generated by voltage division by the third resistor string 214.

The second decoder module 215 may include fifth to eighth decoders ND5 to ND8. The fifth decoder ND5 outputs one of the plurality of reference voltages output from the third resistor string 214 in response to the second control signal CNT2 to the representative gamma voltage, for example, the fifth negative gamma voltage VGN0 . The sixth decoder ND6 may output one of the plurality of reference voltages output from the third resistor string 214 as the fourth negative gamma voltage VGN64 in response to the second control signal CNT2. The seventh decoder ND7 may output one of the plurality of reference voltages output from the third resistor string 214 to the third negative gamma voltage VGN128 in response to the second control signal CNT2. The eighth decoder ND8 may output one of the plurality of reference voltages output from the third resistor string 214 as the second negative gamma voltage VGN192 in response to the second control signal CNT2.

Here, the second negative gamma voltage (VGN192) output from the second decoder module 215 is a voltage corresponding to the 192th gradation level, the third negative gamma voltage (VGN128) is a voltage corresponding to the 128th gradation level, The negative gamma voltage VGN64 may be a voltage corresponding to 64 gradation levels and the fifth negative gamma voltage VGN0 may be a voltage corresponding to a 0 gradation level.

Each of the decoders of the second decoder module 215 receives eight reference voltages from the third resistor string 214 and receives a second reference signal from the outside according to the second control signal CNT2 input from the second decoder module 215 to the second decoder module 215. [ One of the eight reference voltages can be selected and output as the representative gamma voltage.

That is, the third resistor string 214 may generate more than 32 reference voltages from the third voltage VE3 and the fourth voltage VE4, and the second decoder module 215 may generate the second control signal CNT2, , Four of the 32 or more reference voltages can be selected as representative gamma voltages and output.

Here, the second control signal CNT2 may be a signal composed of 3-bit binary data. The second control signal CNT2 may be input to the first to fourth decoders PD4 separately or simultaneously.

The second output buffer module 216 may be connected to corresponding outputs of the fifth to eighth decoders ND8 of the second decoder module 215. [ The second output buffer module 216 may include fifth through eighth output buffers NB5 through NB8.

The fifth output buffer NB5 is connected to the output of the fifth decoder ND5 to stabilize and output the representative gamma voltage output from the fifth decoder ND5, that is, the fifth negative gamma voltage VGN0. The sixth output buffer NB6 may be connected to the output of the sixth decoder ND6 to stabilize and output the fourth negative gamma voltage VGN64 output from the sixth decoder ND6. The seventh output buffer NB7 is connected to the output of the seventh decoder ND7 to stabilize and output the third negative gamma voltage VGN128 output from the seventh decoder ND7. The eighth output buffer NB8 is connected to the output of the eighth decoder ND8 to stabilize and output the second negative gamma voltage VGN192 output from the eighth decoder ND8.

The fourth resistor string 217 may be located between the fifth output buffer NB5 and the eighth output buffer NB8. The fourth resistor string 217 may be constructed by connecting a plurality of resistors R2 in series. The fourth resistor string 217 may generate a plurality of gamma voltages by voltage-dividing the second negative gamma voltage (VGN192) to the fifth negative gamma voltage (VGN0).

For example, the fourth resistor string 217 located between the fifth output buffer NB5 and the sixth output buffer NB6 distributes the fifth negative gamma voltage VGN0 and the fourth negative gamma voltage VGN64 It is possible to output a plurality of negative gamma voltages (e.g., a plurality of negative gamma voltages VGN) corresponding to the gradation levels between the 0-gradation level and the 64-gradation level. The fourth resistor string 217 located between the sixth output buffer NB6 and the seventh output buffer NB7 distributes the voltage between the fourth positive gamma voltage VGP64 and the third positive gamma voltage VGP128 It is possible to output a plurality of negative gamma voltages VGN corresponding to the gradation levels between 128 gradation levels and 64 gradation levels. The fourth resistor string 217 located between the seventh output buffer NB7 and the eighth output buffer NB8 distributes the voltage between the second positive gamma voltage VGP192 and the third positive gamma voltage VGP128 A plurality of negative gamma voltages VGN corresponding to the gradation levels between 128 gradation levels and 192 gradation levels can be output.

As described above, the negative gamma voltage generator 152 according to the present embodiment outputs the externally supplied fourth voltage VE4 as the first negative gamma voltage VGN255 corresponding to the 255th gradation level, For example, the gamma voltage corresponding to the 0 to 192 gradation levels may be generated using the second decoder module 215 having four decoders and the second output buffer module 216 corresponding thereto.

Accordingly, the gamma voltage generator 150 of the present invention can reduce the number of buffers and decoders required when generating negative gamma voltages of 0 to 255 gradation levels as compared with the conventional gamma voltage generator.

The gamma voltage generator 150 generates the positive / negative gamma voltages VGP and VGN corresponding to 0 to 192 and 255 gradation levels, and generates the positive / negative gamma voltages VGP and VGN corresponding to the gradation levels between the 192 gradation level and the 255 gradation level Does not generate a gamma voltage. This is because the human visual characteristics are taken into consideration, and the gradation change between 193 and 254 gradation levels is not perceived by a person. Here, the 255 gradation level may mean black gradation.

Referring again to FIGS. 2 and 3, the gamma voltage generator 150 may further include a gamma voltage selector 153.

The gamma voltage selector 153 selects the positive gamma voltage VGP and the negative gamma voltage VGN generated in the positive gamma voltage generator 151 and the negative gamma voltage generator 152, respectively, according to the third control signal CNT3, And outputs the selected data to the data driver 140. Here, the third control signal CNT3 may be a control signal by the inversion driving method of the liquid crystal display device 100. [

As described above, the gamma voltage generator 150 according to the present embodiment generates the gamma voltage corresponding to the 255 gradation level from the externally provided voltage, and the gamma voltage corresponding to the remaining 0 to 192 gradation levels is generated from the externally provided And distributing the voltage using a decoder and a buffer.

Accordingly, the gamma voltage generator 150 of the present invention can reduce the number of decoders and buffers included in the gamma voltage generator 150 in comparison with the conventional gamma voltage generator, thereby reducing the size of the gamma voltage generator. Also, the size of the data driver circuit including the gamma voltage generator can be reduced, and the manufacturing cost of the data driver circuit and the liquid crystal display device 100 having the data driver circuit can be reduced.

6 is a diagram illustrating a configuration of a gamma voltage generator according to another embodiment of the present invention.

The gamma voltage generator 150 'of this embodiment is substantially the same as the gamma voltage generator 150' described above with reference to FIG. 3 except for the following. That is, the gamma voltage generator 150 'according to the present embodiment can generate the positive gamma voltage VGP and the negative gamma voltage VGN using the reference voltage HVDD.

2 and 6, the gamma voltage generator 150 'of the present embodiment may include a positive gamma voltage generator 151' and a negative gamma voltage generator 152 '.

The positive gamma voltage generator 151 'may generate a plurality of positive gamma voltages VGP from the externally input first voltage VE1 and the reference voltage HVDD.

The positive gamma voltage VGP may be generated as an analog voltage having a positive level based on the reference voltage HVDD. The positive gamma voltage VGP may be generated at a voltage corresponding to the 0 to 192 and 255 gradation levels of the liquid crystal display device 100. [

The reference voltage HVDD is generated by externally stabilizing the third voltage input to the gamma voltage generator 150 ', for example, the fifth voltage VE5 described above through the reference voltage buffer 155 . The reference voltage HVDD may be a half of the driving voltage VDD input to the liquid crystal display 100, for example, about 3.9 to 4.2 V. [

FIG. 7 is a diagram showing the configuration of the positive gamma voltage generator shown in FIG. 6. FIG.

6 and 7, the positive gamma voltage generator 151 'includes a first input buffer 201, a first resistor string 204, a first decoder module 205, a first output buffer module 206 And a second resistor string 207.

The first input buffer 201 may stabilize the externally supplied first voltage VE1 and output the stabilized first positive gamma voltage VGP255. The first positive gamma voltage (VGP255) may be a voltage corresponding to the 255 gradation level.

The first resistor string 204 may be located between the first input buffer 201 and the reference voltage buffer 155. The first resistor string 204 may generate a plurality of reference voltages by voltage-dividing the first voltage VE1 and the reference voltage HVDD through a plurality of resistors R1 connected in series.

The first decoder module 205 outputs a representative gamma voltage, for example, a second to a fifth positive gamma voltage VGP0, from a plurality of reference voltages output from the first resistor string 204 according to the first control signal CNT1 can do. The first decoder module 205 may include first to fourth decoders PD4.

The first decoder PD1 of the first decoder module 205 may output one of the plurality of reference voltages output from the first resistor string 204 as the second positive gamma voltage VGP192. The second decoder PD2 may output one of the plurality of reference voltages output from the first resistor string 204 to the third positive gamma voltage VGP128. The third decoder PD3 may output one of the plurality of reference voltages output from the first resistor string 204 as the fourth positive gamma voltage VGP64. The fourth decoder PD4 may output one of the plurality of reference voltages output from the first resistor string 204 as the fifth positive gamma voltage VGP0. The second positive gamma voltage VGP192 is a voltage corresponding to 192 gradation levels, the third positive gamma voltage VGP128 is a voltage corresponding to 128 gradation levels, and the fourth positive gamma voltage VGP64 corresponds to 64 gradation levels And the fifth positive gamma voltage VGP0 may be a voltage corresponding to the 0 gradation level.

The first control signal CNT1 is a signal composed of 3-bit binary data. The first decoder module 205 can select and output a representative gamma voltage among a plurality of reference voltages according to the first control signal CNT1.

The first output buffer module 206 may include first through fourth output buffers PB4 corresponding to the first through fourth decoders PD4, respectively.

The first output buffer PB1 may stabilize and output the second positive gamma voltage VGP192 output from the first decoder PD1. The second output buffer PB2 may stabilize and output the third positive gamma voltage VGP128 output from the second decoder PD2. The third output buffer PB3 can stabilize and output the fourth positive gamma voltage VGP64 output from the third decoder PD3. The fourth output buffer PB4 can stabilize and output the fifth positive gamma voltage VGP0 output from the fourth decoder PD4.

A second resistor string 207 may be placed between the first output buffer PB1 and the fourth output buffer PB4. The second resistor string 207 divides the second to fifth positive gamma voltages VGP0 output from the first output buffer module 206 through a plurality of resistors R2 connected in series to generate a plurality of positive gamma voltages (VGP).

For example, the second resistor string 207 may divide the second positive gamma voltage VGP192 and the third positive gamma voltage VGP128 to output a plurality of positive gamma voltages VGP between 128 and 192 gradation levels have. The third positive gamma voltage (VGP128) and the fourth positive gamma voltage (VGP64) are voltage-divided to output a plurality of positive gamma voltages (VGP) between 64 and 128 gradation levels. The fourth positive gamma voltage (VGP64) and the fifth positive gamma voltage (VGP0) are voltage-divided to output a plurality of positive gamma voltages (VGP) between 0 and 64 gradation levels.

As described above, the positive gamma voltage generator 151 'according to the present embodiment outputs the externally provided first voltage VE1 as the first positive gamma voltage VGP255 corresponding to the 255th gradation level, and the remaining 0 The gamma voltages corresponding to the 192 gradation levels can be generated from the first voltage VE1 and the reference voltage HVDD using a decoder and a buffer.

Accordingly, the gamma voltage generator 150 according to the present invention generates the gamma voltage of 0 to 255 gradation levels in comparison with the conventional gamma voltage generator, in addition to the number of buffers and decoders required to generate the positive gamma voltage, The number of wirings can be reduced.

Referring again to FIGS. 2 and 6, the negative gamma voltage generator 152 'generates a negative gamma voltage from a second input voltage externally input, for example, the fourth voltage VE4 and the reference voltage HVDD, (VGN).

The negative gamma voltage VGN may be generated as an analog voltage having a negative level based on the reference voltage HVDD. The negative gamma voltage VGN may be generated at a voltage corresponding to the 0 to 192 and 255 gradation levels of the liquid crystal display device 100. [

The reference voltage HVDD may be generated from the externally input fifth voltage VE5 using the reference voltage buffer 155 as described above with reference to the positive gamma voltage generator 151 '.

8 is a diagram showing the configuration of the negative gamma voltage generator shown in FIG.

6 and 8, the negative gamma voltage generator 152 'includes a fourth input buffer 212, a third resistor string 214, a second decoder module 215, a second output buffer module 216 And a fourth resistor string 217. [

The fourth input buffer 212 may stabilize the externally supplied fourth voltage VE4 and output it as the first negative gamma voltage VGN255. The first negative gamma voltage VGN255 may be a voltage corresponding to the 255th gradation level.

The third resistor string 214 may be located between the reference voltage buffer 155 and the fourth input buffer 212. The third resistor string 214 may generate a plurality of reference voltages by voltage dividing the reference voltage HVDD and the fourth voltage VE4 through a plurality of resistors R1 connected in series.

The second decoder module 215 outputs the second to fifth negative gamma voltages VGN0 from the plurality of reference voltages output from the third resistor string 214 as representative gamma voltages in accordance with the second control signal CNT2 . The second decoder module 215 may include a fifth to an eighth decoder ND8.

The fifth decoder ND5 may output one of the plurality of reference voltages output from the third resistor string 214 as the fifth negative gamma voltage VGN0. The sixth decoder ND6 may output one of the plurality of reference voltages output from the third resistor string 214 as the fourth negative gamma voltage VGN64. The seventh decoder ND7 may output one of the plurality of reference voltages output from the third resistor string 214 to the third negative gamma voltage VGN128. The eighth decoder ND8 may output one of the plurality of reference voltages output from the third resistor string 214 as the second negative gamma voltage VGN192.

The second output buffer module 216 may include fifth through eighth output buffers NB8 corresponding to the fifth through eighth decoders ND8, respectively.

The fifth output buffer NB5 may stabilize and output the fifth negative gamma voltage VGN0 output from the fifth decoder ND5. The sixth output buffer NB6 may stabilize and output the fourth negative gamma voltage VGN64 output from the sixth decoder ND6. The seventh output buffer NB7 can stabilize and output the third negative gamma voltage VGN128 output from the seventh decoder ND7. The eighth output buffer NB8 may stabilize and output the second negative gamma voltage VGN192 output from the eighth decoder ND8.

The fourth resistor string 217 may be located between the fifth output buffer NB5 and the eighth output buffer NB8. The fourth resistor string 217 divides the second to fifth negative gamma voltages VGN0 output from the second output buffer module 216 through a plurality of resistors R2 connected in series to generate a plurality of negative gamma voltages (VGN).

For example, the fourth resistor string 217 may divide the second negative gamma voltage VGN192 and the third negative gamma voltage VGN128 to output a plurality of negative gamma voltages VGN between 128 and 192 gradation levels have. The third negative gamma voltage (VGN128) and the fourth negative gamma voltage (VGN64) are voltage-divided to output a plurality of negative gamma voltages (VGN) between 64 and 128 gradation levels. In addition, the fourth negative gamma voltage VGN64 and the fifth negative gamma voltage VGN0 may be voltage-divided to output a plurality of negative gamma voltages VGN between 0 and 64 gradation levels.

As described above, the negative gamma voltage generator 152 'according to the present embodiment outputs the externally provided fourth voltage VE4 as the first positive gamma voltage VGP255 corresponding to the 255th gradation level, and the remaining 0 The gamma voltages corresponding to the 192 gradation levels can be generated from the fourth voltage VE4 and the reference voltage HVDD using a decoder and a buffer.

Accordingly, the gamma voltage generator 150 of the present invention generates an external gamma voltage corresponding to the number of buffers and decoders required when generating negative gamma voltages of 0 to 255 gradation levels as compared with the conventional gamma voltage generator, The number of wirings can be reduced.

Referring again to FIGS. 2 and 6, the gamma voltage generator 150 'may further include a gamma voltage selector 153.

The gamma voltage selector 153 selects the positive gamma voltage VGP and the negative gamma voltage VGP generated in the positive gamma voltage generator 151 'and the negative gamma voltage generator 152', respectively, according to the third control signal CNT3, (VGN) to the data driver 140. Here, the third control signal CNT3 may be a control signal by the inversion driving method of the liquid crystal display device 100. [

As described above, the gamma voltage generator 150 according to the present embodiment generates the gamma voltage corresponding to the 255 gradation level from the externally provided voltage, and the gamma voltage corresponding to the remaining 0 to 192 gradation levels is generated from the externally provided And distributing the voltage using a decoder and a buffer. Also, the gamma voltage generator 150 of the present embodiment can commonly use the reference voltage HVDD as a voltage for generating the positive / negative gamma voltage VGP. VGN.

Accordingly, the gamma voltage generator 150 of the present invention can reduce the number of internal decoders and buffers as compared with the conventional gamma voltage generator, and can reduce the number of external voltages required and the number of wirings . Accordingly, the gamma voltage generator 150 of the present invention can reduce the size and manufacturing cost of the conventional gamma voltage generator, and can reduce manufacturing costs of the data driving circuit and the liquid crystal display including the same. .

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: liquid crystal display device 110: liquid crystal panel
120: timing controller 130: gate driver
140: Data driver 150: Gamma voltage generator
151: Positive gamma voltage generator 152: Negative gamma voltage generator

Claims (12)

A first positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, A first gamma voltage generator for generating a first gamma voltage; And
Outputting a second voltage to a first negative gamma voltage, generating second to fifth negative gamma voltages from the second voltage and the reference voltage, and generating a plurality of negative gamma voltages from the second to fifth negative gamma voltages And a second gamma voltage generating unit for outputting the second gamma voltage. The apparatus of claim 1, wherein the first gamma voltage generator comprises:
A first input buffer for outputting the first voltage as the first positive gamma voltage;
A first resistor string for dividing the first voltage and the reference voltage and outputting a plurality of voltages;
A first decoder module for outputting the second to fifth positive gamma voltages from the plurality of voltages according to a control signal; And
And a second resistor string for voltage-dividing the second to fifth positive gamma voltages to output the plurality of positive gamma voltages. 3. The method of claim 2,
And the second resistor string outputs a plurality of positive gamma voltages corresponding to 0 to 192 gradation levels from the second to fifth positive gamma voltages. 3. The method of claim 2,
Wherein the first decoder module includes four decoders for selecting and outputting the second to fifth positive gamma voltages from among the plurality of voltages, respectively. 5. The method of claim 4,
And a plurality of output buffers correspondingly connected to outputs of each of the four decoders. The apparatus of claim 1, wherein the second gamma voltage generator comprises:
A second input buffer for outputting the second voltage as the first negative gamma voltage;
A third resistor string outputting a plurality of voltages by voltage division of the reference voltage and the second voltage;
A second decoder module for outputting the second to fifth negative gamma voltages from the plurality of voltages according to a control signal; And
And a fourth resistor string for voltage dividing the second to fifth negative gamma voltages to output the plurality of negative gamma voltages. The method according to claim 6,
And the fourth resistor string outputs a plurality of negative gamma voltages corresponding to 0 to 192 gradation levels from the second to fifth negative gamma voltages. The method according to claim 6,
And the second decoder module includes four decoders for selecting and outputting the second to fifth negative gamma voltages from among the plurality of voltages, respectively. 9. The method of claim 8,
And a plurality of output buffers correspondingly connected to outputs of each of the four decoders. The method according to claim 1,
Wherein the first positive gamma voltage and the first negative gamma voltage are voltages corresponding to 255 gradation levels. The method according to claim 1,
And a reference voltage buffer for stabilizing the third voltage and outputting the stabilized third voltage as the reference voltage. Display panel;
A gate driving circuit for outputting a gate signal to a plurality of gate lines of the display panel; And
And a data driving circuit for outputting a data signal to a plurality of data lines of the display panel,
The data driving circuit includes:
A first positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, a second positive gamma voltage, A first gamma voltage generator for generating a first gamma voltage; And
Outputting a second voltage to a first negative gamma voltage, generating second to fifth negative gamma voltages from the second voltage and the reference voltage, and generating a plurality of negative gamma voltages from the second to fifth negative gamma voltages And a second gamma voltage generator for outputting the second gamma voltage,
Wherein the data driving circuit outputs one of the plurality of positive gamma voltages and the plurality of negative gamma voltages as the data signal according to image data.

Images