KR20160030908A - Light emitting diode having plurality of light emitting cells and method of fabricating the same - Google Patents

Abstract

The present invention relates to a light emitting diode and a method of fabricating the same. The light emitting diode according to one embodiment of the present invention, may comprise: a plurality of light emitting cells spaced apart from each other on a single substrate, each of which comprises a lower part semiconductor layer, an upper part semiconductor layer located on the top of one area of the lower part semiconductor layer, and an active layer interposed between the lower part semiconductor layer and the upper part semiconductor layer; a first insulating layer, which is formed to make contact along areas where the substrate between the light emitting cells spaced apart each other is exposed; lines, which are formed on the first insulating layer, and electrically connects the adjacent light emitting cells; a second insulating layer, which covers the first insulating layer and the lines; and a phosphor layer formed on the second insulating layer. The first insulating layer and the second insulating layer are made of identical materials, and the first insulating layer, which covers the area between the light emitting cells, is relatively thicker than the second insulating layer, and the lines have a multi-layered structure which has a lower part layer in contact with the first insulating layer and an upper part layer in contact with the second insulating layer, and the upper part layer can be a Cr layer or a Ti layer. According to the present invention, the first insulating layer and the second insulating layer are made of the identical materials, and also the first insulating layer is formed to be relatively thicker than the second insulating layer, so that adhesiveness between the first insulating layer and the second insulating layer is strengthened and exfoliation of the second insulating layer can be prevented.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a light emitting diode having a plurality of light emitting cells and a method of manufacturing the light emitting diode.

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly, to a light emitting diode having an insulating layer for protecting the light emitting cells and the wirings and having wirings connecting a plurality of light emitting cells and light emitting cells, And a method for manufacturing the same.

Since blue light emitting gallium nitride (GaN) series light emitting diodes have been developed, various attempts have been made to improve the light emitting efficiency of light emitting diodes, and many structural improvements have been made for various applications. Blue or UV emitting gallium nitride based LEDs are now being used in a variety of applications including color LED display devices, LED traffic signals, white LEDs, and are expected to replace white fluorescent lamps in general lighting applications.

Such a light emitting diode generally emits light by a forward current and requires supply of a direct current. There has been attempted to connect a plurality of light emitting cells in antiparallel connection or operate a plurality of light emitting cells under an alternating current power supply using a bridge rectifier in consideration of the characteristics of light emitting diodes operating under forward currents, . In addition, a light emitting diode capable of outputting high output and high efficiency light under a high voltage direct current (DC) power source has been developed by forming a plurality of light emitting cells on a single substrate and connecting them in series and parallel. These light emitting diodes form a plurality of light emitting cells on a single substrate and connect the light emitting cells through wiring, so that light with high output and high efficiency can be emitted under AC or DC power.

A light emitting diode which can be used by connecting a plurality of light emitting cells to a high voltage AC or DC power source is disclosed in International Publication No. WO 2004/023568 (Al), entitled " LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS (SAKAI et al.).

The light emitting cells are electrically connected to each other by air bridge wirings, and a light emitting diode capable of being driven under an AC or DC power supply through the connection of these wirings is provided.

However, the connection of the light emitting cells using the air bridge wiring tends to cause problems such as reliability of the wirings, that is, disconnection of the wirings due to external moisture or external impact, increase of wiring resistance, and the like. In order to protect such disadvantages, a wiring forming technique using a step cover process is used. The step coverage process is a technique of forming an insulation layer covering light emitting cells and forming wirings on the insulation layer, which is structurally stable compared to an air bridge because the wirings are placed on an insulation layer.

However, as the wiring using the step cover process is also exposed to the outside, the wiring may be broken due to moisture or an external impact. In the case of a light emitting diode using a plurality of light emitting cells, a large number of wirings are used, and even if one of the wirings is disconnected, the entire light emitting diode can not be operated. Also, since a large number of wirings are used, the moisture from the outside easily penetrates into the light emitting cells, thereby lowering the light emitting efficiency of the light emitting cells.

On the other hand, when a light emitting diode is used in practical applications such as general illumination, it is necessary to realize light of various colors such as white light by converting ultraviolet or blue light into light of a long wavelength by using a fluorescent material. Conventionally, such a fluorescent material has been applied to epoxy resin or the like covering a light emitting diode chip emitting monochromatic light at a package level. Since the color conversion material layer containing the fluorescent material is formed in the white light emitting device separately from the manufacturing process of the LED chip, the packaging process of the light emitting diode is complicated, resulting in a high process defect rate in the packaging process. The defective packaging process results in a considerable cost loss as compared with the defect of the light emitting diode chip manufacturing process.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode capable of preventing breakage of a wiring due to moisture penetration or external impact from the outside, increase in wiring resistance or deterioration of performance of light emitting cells, and a method of manufacturing the same.

According to another aspect of the present invention, there is provided a light emitting diode having an insulating layer for protecting wires and light emitting cells, and capable of enhancing an adhesion between the insulating layer and a base layer on which the insulating layer is formed, .

Another object of the present invention is to provide a light emitting diode having a fluorescent material for converting the wavelength of light emitted from a light emitting cell at a chip level, and a method of manufacturing the same.

A light emitting diode according to an exemplary embodiment of the present invention includes a lower semiconductor layer, an upper semiconductor layer located on one region of the lower semiconductor layer, A plurality of light emitting cells including an active layer interposed between the light emitting cells; A first insulating layer formed between the light emitting cells spaced apart from each other to contact the exposed region of the substrate; Wirings formed on the first insulating layer and electrically connecting adjacent light emitting cells; A second insulating layer covering the first insulating layer and the wirings; And a phosphor layer formed on the second insulating layer, wherein the first insulating layer and the second insulating layer are formed of the same material, and the first insulating layer covering the region between the light emitting cells is formed of the same material as the second insulating layer, Layer structure having a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer, the upper layer may be a Cr layer or a Ti layer.

At this time, the phosphor layer may be a layer formed by dispersing a phosphor in a resin and formed on the second insulating layer, or may be a deposition layer formed on the second insulating layer by an electrophoresis method.

In addition, the phosphor layer may be formed to cover the entire second insulation layer.

Meanwhile, the light emitting diode according to an embodiment of the present invention includes a lower semiconductor layer, an upper semiconductor layer located on one region of the lower semiconductor layer, A plurality of light emitting cells including an active layer sandwiched between semiconductor layers; A first insulating layer formed between the light emitting cells spaced apart from each other to contact the exposed region of the substrate; Wirings formed on the first insulating layer and electrically connecting adjacent light emitting cells; And a second insulating layer covering the first insulating layer and the wirings and including a phosphor, wherein the first insulating layer and the second insulating layer are formed of the same material, and a region between the light emitting cells Layer structure having a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer, wherein the upper layer is a Cr layer Or a Ti layer.

Here, the first insulating layer may include a phosphor, and the first insulating layer or the second insulating layer may be silicon nitride or a polymer.

The first insulating layer may have a thickness within a range of 4500 ANGSTROM to 1 mu m, and the second insulating layer may have a thickness greater than 500 ANGSTROM.

Here, the first insulating layer and the second insulating layer may be a silicon oxide film deposited at a temperature of 200 to 300 ° C by a plasma enhanced chemical vapor deposition method, and the second insulating layer may be a silicon oxide film, May be deposited at a temperature in the range of 20% to + 20%.

The lower layer may be a Cr layer or a Ti layer. And an Au layer, an Au / Ni layer or an Au / Al layer interposed between the lower layer and the upper layer.

The first insulating layer may extend to cover a part of the light emitting cells.

The transparent electrode layer may further include transparent electrode layers interposed between the first insulating layer and the upper semiconductor layers, and the transparent electrode layer may be ITO. The transparent electrode layers may include at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr, and Ti.

Here, the transparent electrode layers may have openings for exposing the upper semiconductor layers, and the wirings may fill the openings of the transparent electrode layers.

According to the present invention, since the first insulating layer and the second insulating layer are made of the same material and the first insulating layer is formed relatively thicker than the second insulating layer, the adhesive force between the first insulating layer and the second insulating layer And the peeling of the second insulating layer can be prevented. In addition, since the second insulating layer covers the wirings and the light emitting cells, it is possible to prevent moisture from penetrating into the light emitting diode from the outside, and to protect the wiring and the light emitting cells from external impacts.

Further, since the Cr layer or the Ti layer having a strong adhesive force to the insulating layer is formed as the lower layer and the upper layer of the wiring, the adhesion between the wiring and the insulating layer is strengthened, and accordingly, the peeling of the second insulating layer can be further prevented.

In addition, light of various colors, such as white light, can be realized at the chip level by containing the fluorescent material in the second insulating layer or by forming the fluorescent substance layer on the second insulating layer, so that the packaging process can be simplified.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
2 shows the reliability test passing rate according to the deposition temperature of the first insulating layer and the second insulating layer.
FIGS. 3 to 9 are cross-sectional views illustrating a method of fabricating a light emitting diode according to an embodiment of the present invention.
10 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
11 to 13 are cross-sectional views illustrating a method of fabricating a light emitting diode according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

1, the light emitting diode includes a substrate 51, a plurality of light emitting cells 56, a first insulating layer 63, wirings 65, and a second insulating layer 67, A light emitting layer 53, a transparent electrode layer 61, and a phosphor layer 69. The substrate 51 may be an insulating substrate, for example, a sapphire substrate.

On the single substrate 51, a plurality of light emitting cells 56 are located apart from each other. Each of the light emitting cells 56 includes a lower semiconductor layer 55, an upper semiconductor layer 59 located on one region of the lower semiconductor layer, and an active layer 57 interposed between the lower semiconductor layer and the upper semiconductor layer. . Here, the lower and upper semiconductor layers are n-type and p-type, respectively, or p-type and n-type.

The lower semiconductor layer 55, the active layer 57 and the upper semiconductor layer 59 may each be formed of a gallium nitride semiconductor material, that is, (Al, In, Ga) N. The compositional element and the composition ratio are determined so that the active layer 57 emits light of a desired wavelength such as ultraviolet or blue light and the lower semiconductor layer 55 and the upper semiconductor layer 59 have a band gap It is formed of a large material.

The lower semiconductor layer 55 and / or the upper semiconductor layer 59 may be formed as a single layer or may have a multi-layer structure as shown in the figure. In addition, the active layer 57 may have a single quantum well structure or a multiple quantum well structure.

On the other hand, a buffer layer 53 may be interposed between the light emitting cells 56 and the substrate 51. The buffer layer 53 may be employed to alleviate the lattice mismatch between the substrate 51 and the underlying semiconductor layer 55 to be formed thereon.

The first insulating layer 63 covers the entire surface of the light emitting cells 56. [ The first insulating layer 63 has openings on other regions of the lower semiconductor layers 55, that is, a region adjacent to the region where the upper semiconductor layer 59 is formed, and also has openings on the upper semiconductor layers 59 Openings. The openings are spaced apart from each other, so that the sidewalls of the light emitting cells 56 are covered by the first insulating layer 63. The first insulating layer 63 also covers the substrate 51 in the regions between the light emitting cells 56. The first insulating layer 63 may be formed of a silicon oxide film (SiO 2) or a silicon nitride film, and may be formed at a temperature ranging from 200 to 300 ° C. by a plasma CVD method. At this time, the first insulating layer 63 may be formed to a thickness of 4500 Å to 1 μm. When the thickness is less than 4500 ANGSTROM, a first insulating layer having a relatively thin thickness is formed by the layer covering property below the light emitting cells, and an electrical short circuit occurs between the wiring formed on the first insulating layer and the light emitting cell . On the other hand, it is preferable that the thickness of the first insulating layer does not exceed 1 탆, because it is possible to prevent an electrical short circuit as the first insulating layer becomes thicker, but the light transmittance is lowered to decrease the luminous efficiency.

On the other hand, wirings 65 are formed on the first insulating layer 63. The wirings 65 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings. The wirings 65 may form a serial array of the light emitting cells 56 by electrically connecting the lower semiconductor layers 55 and the upper semiconductor layers 59 of the adjacent light emitting cells 56 . A plurality of such arrays may be formed, and a plurality of arrays may be connected in antiparallel to each other and connected to an AC power source to be driven. Further, a bridge rectifier (not shown) connected to the serial array of the light emitting cells may be formed, and the light emitting cells may be driven by the bridge rectifier under the AC power. The bridge rectifier can be formed by connecting the light emitting cells having the same structure as the light emitting cells 56 by using the wirings 65.

Alternatively, the wirings may connect the lower semiconductor layers 55 of adjacent light emitting cells to each other, or may connect the upper semiconductor layers 59 to each other. Accordingly, a plurality of light emitting cells 56 connected in series and in parallel can be provided.

The wirings 65 may be formed of a conductive material, for example, a doped semiconductor material such as polycrystalline silicon, or a metal. In particular, the wirings 65 may be formed in a multi-layer structure, for example, a lower layer 65a of Cr or Ti, or an upper layer 65c of Cr or Ti. In addition, an intermediate layer 65b of Au, Au / Ni or Au / Al may be interposed between the lower layer 65a and the upper layer 65c.

On the other hand, the transparent electrode layers 61 may be interposed between the upper semiconductor layers 59 and the insulating layer 63. The transparent electrode layers 61 are exposed by the openings formed on the upper semiconductor layers 59. The transparent electrode layers 65 transmit the light generated in the active layer 57 and distribute and supply the current to the upper semiconductor layers 59. The wirings 65 may be electrically connected to the upper semiconductor layers 55 by contacting the transparent electrode layers 65 exposed by the openings. The transparent electrode layers 61 may have openings to expose the upper semiconductor layers 59, and the wirings 65 may fill the openings in the transparent electrode layers.

And the second insulating layer 67 covers the wirings 65 and the first insulating layer 63. The second insulating layer 67 prevents the wirings 65 from being contaminated by moisture or the like and prevents the wirings 65 and the light emitting cells 56 from being damaged by an external impact.

The second insulating layer 67 may be formed of the same material as the first insulating layer 63 and may be formed of a silicon oxide film (SiO 2) or a silicon nitride film. The second insulating layer 67 may be a layer formed at a temperature ranging from 200 to 300 캜 by a plasma chemical vapor deposition method such as a first insulating layer. The second insulating layer 67 may be formed to a thickness of about -20% to about +20 [deg.] Relative to the deposition temperature of the first insulating layer 63. For example, when the first insulating layer 63 is formed using plasma- %, And more preferably a layer deposited at the same deposition temperature.

These results can be seen from FIG. FIG. 2 is a graph showing the results of a reliability test for 1,000 hours in a sample in which a silicon oxide film is deposited at 250 ° C. with a first insulating layer 63 and a silicon oxide film is deposited by changing a deposition temperature with a second insulating layer 67 The percentage of the passed sample is expressed in%. Twenty samples were prepared for each deposition temperature of the second insulating layer and each sample was tested under humid conditions. 2 shows that the reliability of the second insulating layer is excellent when the second insulating layer is deposited at a deposition temperature of 20% relative to the deposition temperature (250 ° C) of the first insulating layer, , It can be confirmed that the reliability is drastically reduced. In addition, when the first insulating layer and the second insulating layer are deposited at the same deposition temperature, 100% through-rate is exhibited and reliability is the most excellent.

The second insulating layer 67 may have a thickness smaller than that of the first insulating layer 63, and may have a thickness of 500 ANGSTROM or more. Since the second insulating layer 67 is relatively thin compared to the first insulating layer 63, it is possible to prevent the second insulating layer from being peeled off from the first insulating layer. In addition, when the second insulating layer is thinner than 2500 angstroms, it is difficult to protect the wiring and the light emitting cells from external shock or moisture penetration.

The phosphor layer 69 may be a layer in which a phosphor is dispersed in a resin or a layer deposited by an electrophoresis method. The phosphor layer 69 covers the second insulating layer 67 to wavelength-convert the light emitted from the light emitting cells 56.

3 to 9 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 3, a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59 are formed on a substrate 51. Further, the buffer layer 53 may be formed on the substrate 51 before the lower semiconductor layer 55 is formed.

The substrate 51 may be formed of a material selected from the group consisting of Al 2 O 3, SiC, ZnO, Si, GaAs, GaP, LiAl ₂ O ₃ , But not limited to, boron nitride (BN), aluminum nitride (AlN), or gallium nitride (GaN), and may be variously selected depending on the material of the semiconductor layer to be formed on the substrate 51.

The buffer layer 53 is formed to relax the lattice mismatch between the substrate 51 and the semiconductor layer 55 to be formed thereon and may be formed of gallium nitride (GaN) or aluminum nitride (AlN), for example. When the substrate 51 is a conductive substrate, the buffer layer 53 is preferably formed of an insulating layer or a semi-insulating layer, and may be formed of AlN or semi-insulating GaN.

The lower semiconductor layer 55, the active layer 57 and the upper semiconductor layer 59 may be formed of a gallium nitride semiconductor material, that is, (Al, In, Ga) N. The lower and upper semiconductor layers 55 and 59 and the active layer 57 may be formed using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, or hydride vapor phase epitaxy (HVPE) Or intermittently or continuously.

Here, the lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively. In the gallium nitride-based compound semiconductor layer, the n-type semiconductor layer may be formed by doping silicon (Si) as an impurity, for example, and the p-type semiconductor layer may be formed by doping magnesium (Mg) as an impurity.

Referring to FIG. 4, the upper semiconductor layer 59, the active layer 57, and the lower semiconductor layer 55 are patterned to form light emitting cells 56 spaced from each other. At this time, the upper semiconductor layer 59 is located on a partial region of the lower semiconductor layer 55, and other regions of the lower semiconductor layer 55 are exposed. Meanwhile, the buffer layer 53 may be removed between the light emitting cells to expose the substrate 51.

Referring to FIG. 5, a transparent electrode layer 61 may be formed on the upper semiconductor layer 59 of the light emitting cell 56. The transparent electrode layer 65 may be formed of a metal oxide such as indium tin oxide (ITO) or a transparent metal. In the case of a transparent metal, the transparent electrode layer 61 may include at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr, and Ti, or an alloy thereof.

Meanwhile, the transparent electrode layer 61 may have an opening 61a for exposing the upper semiconductor layer 59. The transparent electrode layer 61 may be formed on the light emitting cells 56. The transparent electrode layer 61 may be formed on the upper semiconductor layer 59 before the light emitting cells 56 are formed, Before being patterned.

The transparent electrode layer 61 may be heat-treated in a temperature range of, for example, 500 to 800 ° C. for ohmic contact with the upper semiconductor layer 59.

Referring to FIG. 6, a continuous first insulating layer 63 is formed on a substrate 51 having light emitting cells 56. The first insulating layer 63 covers the sidewalls and the upper surface of the light emitting cells 56 and covers the upper portion of the substrate 51 in the region between the light emitting cells 56. The first insulating layer 63 may be formed of, for example, a silicon oxide film or a silicon nitride film by plasma enhanced chemical vapor deposition (CVD). In this case, the first insulating layer 63 may be deposited at a temperature ranging from 200 to 300 ° C., and may be formed to a thickness of 4500 Å to 1 μm.

The first insulating layer 63 is patterned to form openings 63a on the upper semiconductor layers 59 and openings 63b are formed on other regions of the lower semiconductor layers 55. [ . When the transparent electrode layers 61 are formed, the transparent electrode layers 61 are exposed by the openings. The openings 63a of the first insulating layer 63 expose the openings 61a of the transparent electrode layers 61 when the transparent electrode layers 61 have openings 61a.

Referring to FIG. 7, wirings 65 are formed on the first insulating layer 63 having the openings 63a. The wirings 65 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings 63a and 63b and electrically connect the adjacent light emitting cells 56 .

The wirings 65 may be formed using plating techniques or general electron beam deposition, chemical vapor deposition, or physical vapor deposition techniques.

Meanwhile, the wirings 65 may be formed of a conductive material, for example, a doped semiconductor material such as polycrystalline silicon, or a metal. In particular, the wirings 65 may be formed in a multi-layer structure, and may include, for example, a lower layer of Cr or Ti (65a of FIG. 1), or an upper layer of Cr or Ti (65c of FIG. Further, an intermediate layer (65b in Fig. 1) of Au, Au / Ni or Au / Al may be interposed between the lower layer and the upper layer. The wirings 65 may be heat-treated in a temperature range of 300 to 500 ° C to improve adhesion with the first insulating layer 63.

Referring to FIG. 8, a first insulating layer 67 is formed on a substrate 51 on which the wirings 65 are formed. The second insulating layer 67 covers the wirings 65 and the first insulating layer 63. The second insulating layer may be formed of the same material as the first insulating layer 63, for example, a silicon oxide film or a silicon nitride film, and may be formed at a temperature ranging from 200 to 300 ° C. by plasma enhanced chemical vapor deposition (CVD). Particularly, it is preferable that the second insulating layer 67 is deposited within a temperature range of -20% to + 20% with respect to the deposition temperature of the first insulating layer 63.

Referring to FIG. 9, a phosphor layer 69 may be formed on the second insulating layer 67. The phosphor layer 69 may be formed by dispersing a phosphor in a resin and then coating the phosphor on the second insulating layer 67 or may be formed on the second insulating layer 67 using electrophoresis have. Thus, a light emitting diode having a fluorescent material at the chip level is completed.

10 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention. Here, a light emitting diode employing a polymer as the first insulating layer and the second insulating layer will be described.

10, the light emitting diode includes a substrate 51, a plurality of light emitting cells 56, a first insulating layer 83, wirings 85, and a second insulating layer 87 And may include a buffer layer 53 and a transparent electrode layer 61. The substrate 51, the light emitting cells 56, and the transparent electrode layer 61 are the same as those of the light emitting diode described with reference to FIG. 1, and a detailed description thereof will be omitted.

The first insulating layer 83 is formed of SOG or BCB, or another transparent polymer, to fill the space between the light emitting cells 56. The first insulating layer 83 may cover other regions of the lower semiconductor layers 55 and in this case have openings exposing the lower semiconductor layers 55. The first insulating layer 83 exposes the upper semiconductor layers 59 or the transparent electrode layers 61. The sidewalls of the light emitting cells 56 are covered with a first insulating layer 83.

On the other hand, wirings 85 are formed on the first insulating layer 83 and electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59. The wirings 85 are electrically connected to the lower semiconductor layers 55 through the openings and also electrically connected to the upper semiconductor layers 59. The wirings 85 may also form a serial array of the light emitting cells 56 by electrically connecting the lower semiconductor layers 55 and the upper semiconductor layers 59 of the adjacent light emitting cells 56 . A plurality of such arrays may be formed, and a plurality of arrays may be connected in antiparallel to each other and connected to an AC power source to be driven. Further, a bridge rectifier (not shown) connected to the serial array of the light emitting cells may be formed, and the light emitting cells may be driven by the bridge rectifier under the AC power. The bridge rectifier can be formed by connecting the light emitting cells having the same structure as the light emitting cells 56 by using the wirings 85.

Alternatively, the wirings 85 may connect the lower semiconductor layers 55 of adjacent light emitting cells to each other, or may connect the upper semiconductor layers 59 to each other. Accordingly, a plurality of light emitting cells 56 connected in series and in parallel can be provided.

The wirings 65 may be formed of a conductive material, for example, a doped semiconductor material such as polycrystalline silicon, or a metal. In particular, the wirings 65 may be formed in a multi-layered structure.

The second insulating layer 87 covers the wirings 85 and the first insulating layer 83. The second insulating layer 87 is formed of a polymer having the same material as that of the first insulating layer 83. Thus, the adhesion between the first insulating layer 83 and the second insulating layer 87 is strengthened. The second insulating layer 87 may be relatively thinner than the first insulating layer 83 filling the space between the light emitting cells 56.

Meanwhile, the second insulating layer 87 may contain a phosphor. Accordingly, a light emitting diode capable of wavelength conversion at the chip level can be provided.

According to the present embodiment, since the first insulating layer is formed by using the polymer, the wirings 85 and the second insulating layer 87 can be formed on the relatively flat first insulating layer, Can be improved.

11 to 13 are cross-sectional views for explaining a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 11, a plurality of light emitting cells 56 and a transparent electrode layer 61 are formed on a single substrate 51, as described above with reference to FIGS. 3 to 5. Each of the light emitting cells 56 has a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59. Meanwhile, the transparent electrode layer 61 may have openings 61a for exposing the upper semiconductor layers 59.

Referring to FIG. 12, a first insulating layer 83 covering the light emitting cells 56 and the transparent electrode layer 61 is formed. The first insulating layer 83 is formed of a polymer and fills a space between the light emitting cells 56 to cover the entire surface of the light emitting cells 56.

Referring to FIG. 13, the first insulating layer 83 is partially etched to expose the transparent electrode layer 61. Thereafter, wirings 85 are formed on the first insulating layer 83 and the light emitting cells 56. The wirings 85 may be formed of a material as described with reference to Fig.

Thereafter, a second insulating layer (87 in Fig. 10) covering the wirings 85 and the first insulating layer 83 is formed. The second insulating layer may be formed of a polymer having the same material as that of the first insulating layer 83, and may include a phosphor.

On the other hand, when the second insulating layer is thicker than the first insulating layer, the light transmittance is deteriorated and the second insulating layer or the first insulating layer can be peeled off from the light emitting cells due to an external impact. Therefore, it is preferable that the second insulating layer 87 is thinner than the thickness of the first insulating layer 83 (here, the thickness of the insulating layer 83 filling the space between the light emitting cells).

In the present embodiment, it is described that the phosphor is contained in the second insulating layer 87, but the phosphor may be also contained in the first insulating layer 83. Further, a phosphor layer may be separately formed on the second insulating layer 87. [

Claims (17)

A plurality of light emitting cells arranged on a single substrate and spaced apart from each other and each including a lower semiconductor layer, an upper semiconductor layer positioned above one region of the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, field;
A first insulating layer formed to contact the substrate between the light emitting cells spaced apart from each other along the exposed region;
Wirings formed on the first insulating layer and electrically connecting adjacent light emitting cells;
A second insulating layer covering the first insulating layer and the wirings; And
And a phosphor layer formed on the second insulating layer,
Wherein the first insulating layer and the second insulating layer are formed of the same material,
The first insulating layer covering the region between the light emitting cells is relatively thicker than the second insulating layer,
Wherein the wirings have a multilayer structure having a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer, wherein the upper layer is a Cr layer or a Ti layer The method according to claim 1,
Wherein the phosphor layer is a layer formed by dispersing a phosphor in a resin and formed on the second insulating layer. The method according to claim 1,
Wherein the phosphor layer is a deposition layer formed on the second insulating layer by an electrophoresis method. The method according to claim 1,
And the phosphor layer covers the entirety of the second insulating layer. A plurality of light emitting cells arranged on a single substrate and spaced apart from each other and each including a lower semiconductor layer, an upper semiconductor layer positioned above one region of the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, field;
A first insulating layer formed to contact the substrate between the light emitting cells spaced apart from each other along the exposed region;
Wirings formed on the first insulating layer and electrically connecting adjacent light emitting cells; And
And a second insulating layer covering the first insulating layer and the wirings and including a phosphor,
Wherein the first insulating layer and the second insulating layer are formed of the same material,
The first insulating layer covering the region between the light emitting cells is relatively thicker than the second insulating layer,
Wherein the wirings have a multilayer structure having a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer, wherein the upper layer is a Cr layer or a Ti layer. The method of claim 5,
Wherein the first insulating layer comprises a phosphor. The method of claim 5,
Wherein the first insulating layer or the second insulating layer is silicon nitride or a polymer. The method according to claim 1 or 5,
Wherein the first insulating layer has a thickness within a range of 4500 ANGSTROM to 1 mu m and the second insulating layer has a thickness greater than 500 ANGSTROM. The method according to claim 1 or 5,
Wherein the first insulating layer and the second insulating layer are silicon oxide films deposited at a temperature of 200 to 300 DEG C by a plasma enhanced chemical vapor deposition method. The method according to claim 1 or 5,
Wherein the second insulating layer is deposited at a temperature within a range of -20% to + 20% of a deposition temperature of the first insulating layer. The method according to claim 1 or 5,
Wherein the lower layer is a Cr layer or a Ti layer. The method of claim 11,
And an Au layer, an Au / Ni layer or an Au / Al layer interposed between the lower layer and the upper layer. The method according to claim 1 or 5,
And the first insulating layer extends to cover a part of the light emitting cells. The method according to claim 1 or 5,
And a transparent electrode layer interposed between the first insulating layer and the upper semiconductor layers. 15. The method of claim 14,
Wherein the transparent electrode layer is ITO. 15. The method of claim 14,
Wherein the transparent electrode layers include at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr, and Ti. 15. The method of claim 14,
Wherein the transparent electrode layers have openings for exposing the upper semiconductor layers, and the wirings fill the openings of the transparent electrode layers.

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