KR20160030157A - Apparatus and method for generating digital value using process variation - Google Patents

Abstract

The present invention relates to an apparatus and a method for generating a digital value using a process variation. Provided is a semiconductor chip for generating an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal and may have a characteristic that short-circuits or opens between the first terminal and the second terminal. Moreover, an input terminal of the first inverter, an output terminal of the second inverter and the first terminal of the first switch are connected to a first node, and an output terminal of the first inverter, an input terminal of the second inverter and the second terminal of the first switch are connected to a second node.

Description

TECHNICAL FIELD [0001] The present invention relates to a digital value generating apparatus and method using a process deviation,

Embodiments of the present invention relate to a semiconductor chip and an identification key generation method for generating an identification key.

Background Art [0002] With the recent development of electronic tags and the like, there has been an increasing need to insert a unique ID (hereinafter referred to as identification key) into a chip produced in large quantities. Thus, there is a need to develop systems and methods for generating random digital values (such as identification keys or unique identifiers, etc.).

As an example of a method for producing a random digital value, a method using hardware or software has been proposed.

However, the generation of digital values through hardware or software has a problem of increase in the unit price of chips due to the expense required for hardware or software development or manufacture, and the production speed is limited.

Accordingly, a system and a method for generating and managing a digital value that is low in manufacturing cost, simple in manufacturing process, and impossible to duplicate are desperately required.

On the other hand, in the manufacture of IC chips, a plurality of identical circuit elements may be integrated in one chip. In this case, the plurality of identical elements are fabricated in accordance with the same design rule on the same wafer by the same manufacturing process.

Thus, the macroscopic electrical characteristics (or digital characteristics) are the same, but the microscopic electrical characteristics (or analog characteristics) are not exactly the same. These slight differences are due to the process variations present in the semiconductor process, and it is impossible to completely eliminate the process variation (to the extent that it is difficult to measure), no matter how good the process is.

Some embodiments of the present invention provide a semiconductor chip that generates a digital value (hereinafter also referred to as an " identification key ") that is simple in structure and can not be physically copied using the process variation of the manufacturing process of the semiconductor chip .

Another aspect of the present invention is to provide a semiconductor chip capable of generating an identification key by comparing logical thresholds of two inverter elements manufactured in the same process even when the exact logic threshold of the inverter element is unknown .

According to an embodiment of the present invention, there is provided a semiconductor chip comprising N unit cells outputting N bits of digital value (where N is a natural number), each of the N unit cells including a pair of elements Wherein the output of the first element of the pair of elements is connected to the input of the second element and the output of the second element is connected to the input of the first element to form a feedback structure with respect to each other, The output value of the first element and the output value of the second element are generated as digital values different from each other due to a difference in electric characteristic value of each of the first element and the second element of the pair of elements.

Here, the pair of devices are manufactured in the same process, and the difference in the electrical characteristic values may be caused by process variation.

According to an embodiment of the present invention, there is provided a semiconductor memory device including N (N is a natural number) unit cells and generating an N-bit identification key using a logical level of an output voltage value of the N unit cells Chip is provided.

In this case, each of the N unit cells may include a pair of inverters and a switch. In this case, at least one of the N unit cells includes a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch.

The first switch includes a first terminal and a second terminal, and short-circuits or opens the first terminal and the second terminal according to a first voltage value inputted thereto. The input terminal of the first inverter, the output terminal of the second inverter, and the first terminal of the first switch are connected to a first node, and the output terminal of the first inverter, the input terminal of the second inverter And a second terminal of the first switch is coupled to the second node.

On the other hand, the first inverter and the second inverter are manufactured in the same process, and the first logic threshold and the second logic threshold may not be equal to each other due to the process variation of the process.

On the other hand, when the first switch is closed, the first node and the second node are short-circuited, and the voltage value of the short-circuited first node and the second node is lower than the voltage value between the first logic threshold and the second logic threshold Lt; / RTI >

The identification key is generated based on the logical level of the voltage value of at least one of the output terminal of the first inverter and the output terminal of the second inverter when the first switch is opened again after being closed.

According to an embodiment of the present invention, when the switch is opened after being closed, the identification key is generated as 1 when the logical level of the voltage value of the output terminal of the first inverter is high, and the output of the first inverter And generates the identification key as 0 when the logical level of the voltage value of the terminal is low.

The first unit cell of the semiconductor chip includes a second switch connected between the first node and ground and being always in an open state and a second switch connected between the second node and an output terminal of the first unit cell, And a third switch for transmitting the voltage of the second node to the output terminal of the first unit cell when recognition of the identification key is required

According to another embodiment of the present invention, there is provided a semiconductor chip including an identification key generating unit for generating an N-bit identification key, and a security key generating unit for generating a security key using the generated identification key. In this case, the identification key generator may include N unit cells, and each of the N unit cells may generate a 1-bit identification key based on a process deviation.

In this case, the first one of the N unit cells may include a first inverter having a first logic threshold and a second inverter having a second logic threshold, and the second inverter having an input terminal of the first inverter, The output terminal of the inverter is connected to the first node, and the output terminal of the first inverter and the input terminal of the second inverter can be connected to the second node.

In this case, the first inverter and the second inverter are manufactured in the same process, and the first logic threshold and the second logic threshold may not be the same due to the process variation of the process.

And a second node, when the first node and the second node are opened after short-circuiting the first node and the second node, based on a logical level of a voltage value of at least one of the first node and the second node, A 1-bit identification key corresponding to the first unit cell can be generated.

The semiconductor chip may further include a processor for performing at least one of digital signature, user identification / authentication, and data encryption / decryption using the security key.

According to another embodiment of the present invention, there is provided a semiconductor chip including a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The semiconductor chip can generate a 1-bit identification key.

In this case, the first switch has a first terminal and a second terminal, and short-circuits or opens the first terminal and the second terminal according to an input first voltage value. The input terminal of the first inverter, the output terminal of the second inverter, and the first terminal of the first switch are connected to a first node, and the output terminal of the first inverter, the input terminal of the second inverter, And a second terminal of the first switch is coupled to the second node.

In this case, the first inverter and the second inverter are manufactured in the same process, and the first logic threshold and the second logic threshold are not equal to each other, which is caused by the process variation of the process.

In this embodiment, when the logical level of the input first voltage value is high, the first switch short-circuits between the first node and the second node. In this case, the voltage value of the short-circuited first node and the second node may be a value between the first logical threshold and the second logical threshold.

Then, after the first node and the second node are short-circuited, if the logical level of the input first voltage value changes from high to low, the first switch is opened. Therefore, the voltage value of the first node and the voltage value of the second node are different from each other.

In this case, the logical level of the voltage value of the first node and the voltage value of the second node may be different (for example, if one of the two logical levels is "1" "). Thus, in the present embodiment, an identification key can be generated based on the logical level of at least one of the first node or the second node

According to an embodiment of the present invention, when the logical level of the voltage value of the second node is high after the opening of the first switch, the identification key is recognized as 1, and the voltage value of the second node If the logical level is low, the identification key is recognized as zero.

According to an embodiment of the present invention, the semiconductor chip further comprises a second switch connected between the first node and ground and always in an open state, and a second switch connected between the second node and the output terminal, And a third switch having a characteristic of shorting or opening between the second node and the output terminal according to a value of the second switch.

According to another embodiment of the present invention, there is provided a method of generating a security key, the method including generating an identification key of N bits (where N is a natural number) based on a process variation, A semiconductor chip including a security key generation unit is provided. In this case, the identification key generation unit may include N unit cells, and each of the N unit cells may generate a 1-bit identification key based on a process deviation.

The semiconductor chip may further include a processor for performing at least one of a digital signature, a user identification / authentication, and a data encryption / decryption using the security key.

According to another embodiment of the present invention, there is provided a semiconductor chip comprising a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a comparator. In this case, the comparator may include a first input terminal, a second input terminal, and an output terminal, and may be configured to have a logical relationship between the voltage of the first input terminal and the voltage of the second input terminal, Determine the level.

The input terminal of the first inverter and the output terminal of the first inverter are connected to the first input terminal of the comparator and the input terminal of the second inverter and the output terminal of the second inverter are connected to the second terminal of the comparator To the input terminal.

In this case, the first inverter and the second inverter are manufactured in the same process, and the first logic threshold and the second logic threshold may not be the same due to the process variation of the process.

According to another embodiment of the present invention, there is provided an inverter having N (where N is a natural number) inverter in which an input terminal and an output terminal are short-circuited, a first inverter having a first logic threshold value of the N inverters, And a comparator for comparing the voltage of the output terminal of the selected first inverter with the voltage of the output terminal of the selected second inverter. In this case, the comparator determines the logical level of the voltage of the output terminal of the comparator according to the comparison result.

On the other hand, the first inverter and the second inverter are manufactured in the same process, and the first logic threshold and the second logic threshold may not be the same due to the process variation of the process.

According to another embodiment of the present invention, there is provided a semiconductor chip including a differential amplifier and a comparator. In this case, the differential amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. In addition, when the first input terminal and the second input terminal are short-circuited and the same voltage is input, the voltages of the first output terminal and the second output terminal are not equal to each other due to a process deviation. The comparator determines a logical level of an output voltage of the comparator based on a result of comparing a voltage of a first output terminal of the differential amplifier with a voltage of a second output terminal of the differential amplifier.

According to another embodiment of the present invention, there is provided a differential amplifier circuit comprising N (where N is a natural number) differential amplifier, a selector for selecting a first differential amplifier among the N differential amplifiers And a second output terminal of the selected first differential amplifier and a second output terminal of the selected first differential amplifier, wherein the voltage of the first output terminal of the selected first differential amplifier and the voltage of the second output terminal of the selected first differential amplifier And a comparator that compares the output voltage of the comparator with a reference voltage.

In this case, when the first input terminal and the second input terminal are short-circuited and the same voltage is input, the voltage of the first output terminal and the second output terminal is different from each other It may not be the same. The comparator may determine a logical level of a voltage of an output terminal of the comparator according to the comparison result.

According to another embodiment of the present invention, there is provided a method of driving an inverter, comprising: a first node coupled to an input terminal of a first inverter having a first logic threshold and an output terminal of a second inverter having a second logic threshold; Closing the first switch connected between the first node and the second node connected to the input terminal of the second inverter to short-circuit between the first node and the second node, reopening the closed first switch, Comprising the steps of: opening said first node and said second node; and recognizing an identification key based on a logical level of a voltage value of at least one of said first node and said second node, Method is provided.

In this case, the first inverter and the second inverter may be manufactured in the same process, and the first logic threshold and the second logic threshold may not be the same due to the process variation of the process.

Meanwhile, in the step of recognizing the identification key, when the logical level of the voltage value of the second node is high, the identification key is generated as "1 ", and when the logical level of the voltage value of the second node is low , The identification key can be generated as "0 ".

According to some embodiments of the present invention, the structure of the circuit for generating the identification key using the process deviation of the manufacturing process of the semiconductor chip is simplified, and the manufacturing cost is reduced.

Also, physical cloning of the circuit is not possible (the same identification key is not generated even if other circuits are made under the same design), ensuring high security.

According to some other embodiments of the present invention, even if the exact logic threshold of the inverter element is not known, the identification key can be generated by comparing the logic thresholds of the two inverter elements manufactured in the same process. Therefore, the generation frequency of "0" and the generation frequency of "1" are similar to each other in the generated identification key (digital value).

Further, according to another embodiment of the present invention, it is possible to increase the number of bits of the generated identification key while using a very small area on the semiconductor chip.

1 shows a semiconductor chip according to an embodiment of the present invention.
2 is a conceptual diagram for explaining the operation of the semiconductor chip according to an embodiment of the present invention.
FIG. 3 is a graph showing the logical threshold differences of two inverters according to the embodiment of FIG. 2. FIG.
FIG. 4 illustrates an implementation of the circuit of FIG. 1 using a CMOS inverter and a transmission gate, in accordance with an embodiment of the present invention.
FIG. 5 illustrates a semiconductor chip according to the embodiment of FIG. 1 as a unit cell block.
6 is a flowchart of a logical level of a voltage input to each terminal of the unit cell block of FIG. 5 according to an embodiment of the present invention.
7 shows a semiconductor chip for generating an (M + N) bit identification key by using M * N unit cells of FIG. 5 according to an embodiment of the present invention.
8 illustrates an RFID communication device including a semiconductor chip according to an embodiment of the present invention.
9 illustrates an embedded system including a semiconductor chip according to an embodiment of the present invention.
10 illustrates a public key based communication system including a semiconductor chip according to an embodiment of the present invention.
11 illustrates a Hash Message Authentication Code (HMAC) module including a semiconductor chip according to an embodiment of the present invention.
Figure 12 illustrates a system based on the process variation of the logic threshold of two inverters, in accordance with one embodiment of the present invention.
13 shows a semiconductor chip according to an embodiment of the present invention.
Figure 14 illustrates a semiconductor chip based on a process variation of a differential amplifier, in accordance with an embodiment of the present invention.
15 shows a semiconductor chip according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

1 shows an identification key generation semiconductor chip 100 according to an embodiment of the present invention. Although the identification key generation semiconductor chip 100 according to some embodiments of the present invention can be implemented on one semiconductor chip, the present invention should not be construed as limiting the invention to a limited number of embodiments, Interconnect, or any other equivalent circuit or apparatus having the same function.

Semiconductor chip, which is the basis of Hyundai Electronics industry, is manufactured using numerous processes and numerous devices and is used in various industrial fields. Using the difference in electrical characteristics between the devices caused by process variations in the semiconductor chip fabrication process, a random digital value (hereinafter referred to as an "identification key " ) ") Can be generated.

In addition, the semiconductor chip may mean various types of chips, modules, and other systems that can be manufactured using various semiconductor devices. Therefore, the semiconductor chips mentioned below should be interpreted as including various kinds of chips produced in processes other than the semiconductor process.

Generally, there are various processes for producing a semiconductor chip, but regardless of the type of process, the semiconductor chip may include at least one identical circuit.

In this case, there are active elements and passive elements in devices implemented on a semiconductor chip. In this case, the active element may be a transistor or a diode, and the passive element may be at least one of a resistor, a capacitor, an inductor, and a wiring between elements. However, the transistors, diodes, resistors, capacitors, inductors, and wirings are merely examples of active / passive elements.

Embodiments of the present invention are capable of making random, physical duplication impossible by using a deviation of a process of manufacturing an element (or a circuit composed of a plurality of elements) implemented on a semiconductor chip, And generates an identification key that does not change after it is manufactured.

The above-mentioned specific elements are merely illustrative, and the scope of the present invention is to generate random digital values using process variations existing in the manufacturing process of various devices or circuits.

In some embodiments of the invention, the circuit may be a transistor circuit, an inverter circuit, an amplifier circuit (such as a differential amplifier circuit, etc.). However, this circuit is only an example of a circuit composed of the above elements. That is, the present invention can widely include an embodiment using a circuit composed of elements included in the chip. For example, the circuit may be a single element circuit or a multiple element circuit comprising at least one of a transistor, a resistor, a capacitor and an inductor.

On the other hand, the process variation can be caused by a deviation of various parameters in a manufacturing process of a device or a circuit. For example, in the case of a transistor, parameters such as effective gate length, doping concentration related index, oxide thickness related index or threshold voltage can make the process variation.

According to an embodiment of the present invention, the semiconductor chip 100 may generate a 1-bit digital identification key (such as "0" or "1").

The semiconductor chip 100 may be used as a unit cell of a larger circuit. Therefore, according to some embodiments of the present invention, it is also possible to generate an N-bit digital identification key by arranging N (N is a natural number) unit cells of the semiconductor chip 100.

The first inverter 110 has a first logic threshold (Logic threshold). And, the second inverter has a second logic threshold.

The first inverter 110 and the second inverter 120 are manufactured by the same manufacturing process, and the first logic threshold and the second logic threshold are not the same due to the process deviation.

The first switch 130 includes a first terminal and a second terminal and short-circuits or opens the first terminal and the second terminal according to a first voltage value input to the reset terminal 131. 1, the first switch 130 may be implemented using a transmission gate. However, the present invention is not limited to this, and may include a switch for shorting or opening nodes, As far as the device is concerned, other applications are possible.

In this case, the input terminal of the first inverter 110, the output terminal of the second inverter 120, and the first terminal of the first switch 130 are connected to the first node 101. The output terminal of the first inverter 110, the input terminal of the second inverter 120, and the second terminal of the first switch are connected to the second node 102.

According to an embodiment of the present invention, the first switch 130 may be implemented by a transmission gate. This is also true for the second switch 150 and the third switch 140, which will be described later.

When a logic level high voltage is input to the reset terminal 131 of the first switch 130, the first switch 130 switches between the first node 101 and the second node 101, Thereby shorting the space 102. At this time, the voltage of the logic level low can be inputted to the reset bar terminal 132.

In this case, the shorted voltage values of the first node 101 and the second node 102 may be a value between the first logical threshold and the second logical threshold.

If the logical level of the voltage value of the reset terminal 131 changes from high to low after the first node 101 and the second node 102 are short-circuited, The first switch 130 is opened. Accordingly, the voltage value of the first node 101 and the voltage value of the second node 102 are different from each other.

For example, if the logical level of one of the two nodes is "1 ", the other logical level may be" 0 ". In this case, when a logical high level voltage is input to the sel terminal 141 of the third switch 140 and a logical low level voltage is input to the sel bar terminal 142 and the third switch 140 is closed the second node 102 and the output terminal 143 are short circuited and the voltage of the second node 102 is transferred to the output terminal 143.

Then, the logical level of the voltage of the output terminal 143 may be determined, and the identification key generated by the semiconductor chip 100 may be determined as "1" or "0 ".

On the other hand, the second switch 150 is always open since the input terminal 151 is grounded and the input bar terminal 152 is connected to VDD. The second switch 150 functions as a dummy switch for maintaining the symmetry of the circuit.

2 is a conceptual diagram for explaining the operation of the semiconductor chip for generating an identification key according to an embodiment of the present invention.

The first inverter 210 has a first logical threshold. And the second inverter 220 has a second logic threshold. The logic threshold is a voltage value when the input voltage and the output voltage of the inverter have the same value. This logic threshold value can be measured as a voltage value when the output terminal and the input terminal of the inverter in operation are short-circuited.

Although the inverters manufactured in the same process are designed to have the same logic threshold in theory, in practice, neither of the two inverters can have exactly the same logic threshold because there is a process deviation in the actual manufacturing process as described above.

According to an embodiment of the present invention, the first inverter 210 and the second inverter 220 are manufactured in the same manufacturing process, and have a difference in logical thresholds due to process variations.

The difference in logic thresholds may vary depending on the process, but may be on the order of several to several tens of millivolts, for example. Therefore, measuring the logic threshold of the first inverter 210 and the logic threshold of the second inverter 220 using a separate comparator circuit may not be accurate due to measurement errors.

Thus, a method is needed that can relatively compare the logic threshold of two inverters (i.e., measure without using a separate comparator circuit). In some embodiments of the invention, the logic threshold between the two inverters can be compared relatively (without itself using a separate comparator circuit) to determine which logic threshold is greater.

If the second inverter 220 is not present, if the input terminal and the output terminal of the first inverter 210 are short-circuited, the output voltage of the first inverter 210 is lower than the logical threshold value of the first inverter 210 . When the input and output terminals of the second inverter 220 are short-circuited, if the first inverter 210 is not present, the output voltage of the second inverter 220 is lower than the output voltage of the second inverter 220 It will be equal to the threshold.

2, the input terminal of the first inverter 210 and the output terminal of the second inverter 220 are short-circuited and connected to the first node, and the output terminal of the first inverter 210 and the output terminal of the second inverter 220 are short-circuited and connected to the second node, the result is different from the above case.

When the first node and the second node are short-circuited by using the switch 230, the voltage values of the two nodes short-circuited are compared with the logical threshold of the first inverter 210 and that of the second inverter 220 (Which may not be an average value, the same shall apply hereinafter) between logical thresholds.

Regardless of which of the logical thresholds of the two inverters is high, the value of the output voltage is the value between the logical thresholds of the two inverters while the switch 230 is closed.

Then, when the switch 230 is opened to open the first node and the second node, a logical level of the voltage value of either the first node or the second node is set to a logic level, Becomes "0 ", and the other logical level becomes" 1 ".

For example, if it is assumed that the logical threshold of the first inverter 210 is lower than the logical threshold of the second inverter 220, the switch 230 is closed and the first and second nodes The voltage of the node is higher than the logic threshold of the first inverter 210. [

Accordingly, after the switch 230 is opened again and the first node and the second node are opened, the first inverter 210 converts the voltage of the first node (which is its input terminal) to a logic level high, And thus makes the voltage of the second node, which is the output terminal of the first inverter 210, logic level low.

In this case, the second inverter 220 recognizes the voltage of the second node (which is its input terminal) as a logic level low, and accordingly, the voltage of the first node, which is the output terminal of the second inverter 220, Make it high.

As a result, the logical level of the voltage of the second terminal, which is the output terminal ("Out") of FIG. 2, becomes high.

Conversely, if it is assumed that the logical threshold of the first inverter 210 is higher than the logical threshold of the second inverter 220, the switch 230 is closed so that the first and second nodes The voltage of the node is lower than the logic threshold of the first inverter 210. [

Accordingly, after the switch 230 is opened again and the first node and the second node are opened, the first inverter 210 recognizes the voltage of the first node (which is its input terminal) as a logical level low , Thereby making the voltage of the second node, which is the output terminal of the first inverter 210, a logical high level.

In this case, the second inverter 220 recognizes the voltage of the second node (which is its input terminal) as a logical level high, and accordingly, the voltage of the first node, which is the output terminal of the second inverter 220, It is made low.

As a result, the logical level of the voltage of the second terminal, which is the output terminal ("Out") in Fig. 2, becomes low.

As described above, the output terminal ("Out") after short-circuiting of the switch 230 changes depending on whether the logic threshold of the first inverter 210 or the logic threshold of the second inverter 220 is high, (Or "1"), or to a low (or "0").

However, it is random whether the logic threshold value of either the first inverter 210 or the second inverter 220 manufactured in the same manufacturing process is high. And once it is manufactured, it does not change whether the logical threshold is higher or higher.

As a result, through the embodiment of FIG. 2, it is possible to generate a 1-bit identification key (a value which is the same as the probability of becoming "1" or "0" but not changed once determined).

This process can be more clearly understood when referring to the graph of Fig.

FIG. 3 shows a voltage characteristic curve when the logic threshold of the first inverter 210 is lower than the logic threshold of the second inverter 220, among the embodiments described above with reference to FIG.

The curve 310 is the voltage characteristic curve of the first inverter 210 and the curve 320 is the voltage characteristic curve of the second inverter 220. [ When the first inverter 210 and the second inverter 220 are manufactured in the same manufacturing process according to an embodiment of the present invention, the curve 310 and the curve 320 are almost the same, .

Once the intersection of the curve 310 and the straight line 330 with a slope of 1 is found, the logical threshold V ₁ of the first inverter 210 can be determined. Further, once the intersection of the curve 320 and the straight line 330 is found, the logical threshold V ₂ of the second inverter 220 can be determined.

In this embodiment, V ₁ is lower than V ₂ . Therefore, when the switch 230 of FIG. 2 is closed and the first node and the second node are short-circuited (hereinafter referred to as "Reset"), the voltage V _??? Which is a value between V ₁ and V ₂ .

Then, after the switch 230 is opened again and the first node and the second node are opened, the first inverter 210 recognizes the voltage V _{??? Epsilon?} Of the first node as a logical level high, The voltage of the second node which is the output terminal of the first inverter 210 is made logic low.

In this case, the second inverter 220 recognizes the voltage of the second node V _{??? Epsilon} as a logic level low, and thus makes the voltage of the first node, which is the output terminal of the second inverter 220, .

Therefore, the logical level of the voltage of the second terminal, which is the output terminal ("Out") in Fig. 2, becomes high.

FIG. 4 illustrates an implementation of the circuit of FIG. 1 using a CMOS inverter and a transmission gate, in accordance with an embodiment of the present invention.

An example that can be arranged as an inverter element on a semiconductor chip is a complementary metal-oxide semiconductor (CMOS) inverter. One PMOS and one NMOS, inverting the logical level of the input terminal to provide the logical level of the output terminal.

The input terminal of the first inverter 410 and the output terminal of the second inverter 420 are connected to the first node. The output terminal of the first inverter 410 and the input terminal of the second inverter 420 are connected to the second node.

When the logic level "1" is input to the reset terminal of the first switch 430, the first node and the second node are short-circuited. In this case, the logical level "0" is input to the Sel terminal of the second switch 440 between the Out terminal and the second node, and thus the second switch 440 is open.

Meanwhile, the third switch 450 connected between the first node and the ground is a dummy switch that is always open. It is as described above with reference to Fig. 1 that the symmetry of the circuit is maintained by the existence of the third switch, and thus the electrical characteristics (such as capacitance, etc.) of both circuits are kept the same.

When the logical level of the reset terminal is changed from "1" to "0", the first switch 430 is opened, and the logical level of the voltage of either the first node or the second node becomes "1" , And the logical level of the other voltage becomes "0 ". The logical level of the Sel terminal of the second switch 440 is still maintained at "0 ".

When the logical level "1" is input to the Sel terminal, the second switch 440 is closed and the voltage of the second node is transferred to the Out terminal. In this case, the logical level of the voltage at the Out terminal can be measured to recognize the 1-bit identification key generated by the semiconductor chip of Fig.

FIG. 5 illustrates a semiconductor chip according to the embodiment of FIG. 1 as a unit cell block.

According to an embodiment of the present invention, the identification key generation semiconductor chip 100 using the process variation of FIG. 1 may be included in a part of a semiconductor chip of a larger scale. In this case, ) Can be expressed as.

The reset terminal 131 of the first switch 130 included in the semiconductor chip 100 is connected to the terminal 501 while the sel terminal 141 of the second switch 140 is connected to the terminal 502, And terminal 143 is represented by terminal 503, respectively. Other terminals such as a DC voltage and a ground terminal are not shown.

According to an embodiment of the present invention, first, logical levels "1" and "0" are input to the reset terminal 501 and the Sel terminal 502, respectively. Then, the logical level of the reset terminal 501 changes from "1" to "0". Thereafter, the logical level of the Sel terminal 502 is changed from "0" to "1", and the logical level of the output terminal 503 is measured to recognize the identification key of "1" or "0".

As described above, in this case, the probability that the logical level of the output terminal 503 is "1" may be the same as the probability of "0 ", and the value may not change even if the above process is repeated many times.

Of course, the circuit shown with reference to FIG. 4 may also be represented by a unit cell 500.

6 is a flowchart of a logical level of a voltage input to each terminal of the unit cell block of FIG. 5 according to an embodiment of the present invention.

In step S610, logical levels "1" and "0" are input to the reset terminal 501 and the Sel terminal 502 of the unit cell 500, respectively. In this case, the first node 101 and the second node 102 in Fig. 1 are short-circuited. The voltage of the first node 101 and the second node 102 is a value between the logic threshold of the first inverter 110 and the logic threshold of the second inverter.

In step S620, the logical level of the reset terminal 501 changes from "1" to "0 ". The logical level of the Sel terminal 502 is maintained at "0 ".

Then, in step S630, the logical level of the Sel terminal 502 is changed from "0" to "1". In this case, the logical level of the reset terminal 501 is still kept at "0 ". The switch 140 is then closed and the voltage of the second node 102 is transferred to the output terminal 503. [

In step S640, it is recognized whether the logical level of the voltage of the output terminal 503 is "0" or "1 ". In this case, the probability that the logical level of the output terminal 503 is "1" and the probability that it is "0"

Also, even if the steps S610 to S620 are repeated a plurality of times in one unit cell 500, the determination result of step S640 is the same.

7 is a block diagram of a semiconductor chip 700 for generating an (M * N) bit identification key by using M * N (M and N are natural numbers) unit cells of FIG. 5 according to an embodiment of the present invention. ).

A column line control logic 710 provides a first input signal to a reset terminal of each unit cell and measures a logical level of a voltage at an output terminal of each unit cell to obtain an identification key.

A row line control logic 720 provides a second input signal to the Sel terminal of each unit cell.

According to one embodiment of the present invention, the Column line control unit 710 applies a voltage of logical level "1" to M terminals of "reset 1" to "reset M". In this case, the row line control unit 720 maintains logical level "0" at N terminals of "row 1"

Then, the Column line control unit 710 changes the voltage of the logical level "1" to the logical level "0" at the M terminals of "reset 1" to "reset M".

Thereafter, when the row line control unit 720 changes the logical level of the "row 1" terminal from "0" to "1", the column line control unit 710 controls the unit cell And recognizes the M-bit identification key.

Then, the row line control unit 720 changes the logical level of the "row 1" terminal from "1" to "0" again and changes the logical level of the "row 2" terminal from "0" to "1". Then, the Column line control unit 710 recognizes the M-bit identification key of the unit cell (Unitcell 21) to the unit cell (Unitcell 2M).

If this process is repeated up to "row N ", since the identification key of M bits is recognized N times, the identification key generation semiconductor chip 700 recognizes the total (M * N) bits of the identification key.

8 illustrates an RFID communication device including a semiconductor chip according to an embodiment of the present invention.

The communication device 800 can transmit and receive data such as identification information to the outside through the antenna 830.

In this case, the communication device 800 may have a unique identification key (such as a binary number of 128 bits). According to one embodiment of the present invention, an identification key of M * N bits is generated by the semiconductor chip 700 of FIG.

The identification key of the M * N bits generated by the identification key generation semiconductor chip 700 can be accessed by the control unit 810 and the control unit 810 can transmit the identification information of the communication device 800 to the external , The identification key can be used.

The M * N bit identification key generated by the semiconductor chip 700 is not stored in the memory 820 or other storage device but is read from the direct control unit 810 only when reading is required, so that the security level is high.

Even if data replication of the memory 820 is performed from the outside, the unique identification key of the communication device 800 may not be exposed.

Figure 9 illustrates an embedded system 900 including a semiconductor chip according to one embodiment of the present invention.

The embedded system 900 can perform functions such as electronic signature through a symmetric key encryption algorithm. According to one embodiment of the present invention, the embedded system 900 may be an automated prescription dispensing device of a hospital. However, the present invention is not limited to some applications, and examples of various embedded systems (such as ATMs) are possible.

The identification key generation semiconductor chip 700 provides the generated M * N bit identification key to the encryption module (Crypto Module) 910. The encryption module 910 may generate an encryption key using the M * N bit identification key. The generated encryption key may be stored in a storage device (e.g., a NAND flash memory)

The processing unit 930 can communicate with the outside through the input / output interface 940 using the encryption key.

10 illustrates a public key based communication system including a semiconductor chip according to an embodiment of the present invention.

In the public key communication system, the identification key generation semiconductor chip 700 generates an identification key of M * N bits and provides it to the public key generation unit 1010. The public key generation unit 1010 generates a public key using the identification key, and transmits the generated public key to the intermediate processing unit 1020 (for example, an RSA (Rivest, A. Shamir, L. Adleman) ECC (Elliptic Curve Cryptosystem) encryption processing unit, etc.).

The central processing unit 1030 of the system 1000 can communicate with the outside via the public key encryption method in the encrypted communication.

11 illustrates a Hash Message Authentication Code (HMAC) module including a semiconductor chip according to an embodiment of the present invention.

According to one embodiment of the present invention, the system 1100 includes an identification key generation semiconductor chip 700 and an HMAC processing unit 1110. [

MAC (Message Authentication Code) is a code for checking the accuracy of a message. These MACs include 1) Unconditionally secure methods, 2) Hash function based methods, 3) Stream cipher based methods, and 4) Block cipher based methods.

According to an embodiment of the present invention, the HMAC processing unit 1110 processes a message M using a hash function to generate a processed message (HMAC (M)). In this process, the HMAC processing unit 1110 can use the identification key generated by the identification key generation semiconductor chip 700. [

12 shows a semiconductor chip for generating an identification key using a difference in logical threshold due to a process deviation of two inverters, according to an embodiment of the present invention.

According to an embodiment of the present invention, the semiconductor chip 1200 includes a first inverter 1210, a second inverter 1220, and a comparator 1230.

According to an embodiment of the present invention, the first inverter 1210 and the second inverter 1220 are manufactured in the same process. However, the logic threshold of the first inverter 1210 and the logic threshold of the second inverter 1220 are not identical to each other due to process variations, as described above with reference to FIGS.

In this embodiment, the input terminal and the output terminal of the first inverter 1210 are shorted to each other and connected to the first input terminal of the comparator 1230. An input terminal and an output terminal of the second inverter 1220 are short-circuited to each other and connected to a second input terminal of the comparator 1230.

In this case, the voltage value of the first input terminal of the comparator 1230 may be a logical threshold value of the first inverter 1210. The voltage value of the second input terminal of the comparator 1230 may be a logical threshold of the second inverter 1220.

As a result, the comparator 1230 compares the logical thresholds of the first inverter 1210 and the second inverter 1220, and may vary the voltage value of the Out terminal depending on which is higher.

According to an embodiment of the present invention, the identification key generated by the semiconductor chip 1200 can be recognized as a 1-bit digital value of "1" or "0" according to the voltage value of the Out terminal.

1, the semiconductor chip 1200 may function as a unit cell. In this case, the semiconductor chip 1200, which is a unit cell, It is possible to generate an N-bit identification key. The above application example will be described later in detail with reference to FIG.

13 shows a semiconductor chip according to an embodiment of the present invention.

The semiconductor chip 1300 includes five inverters of an inverter 1311 to an inverter 1315, a selector 1320, and a comparator 1330. [

The selector 1320 selects either one of the five inverters shown in Fig. For example, inverter 1312 and inverter 1313 may be selected.

In this case, the comparator 1330 compares the logical threshold of the inverter 1312 with the logical threshold of the inverter 1313, and provides the output voltage to the Out terminal according to the comparison result. A 1-bit identification key can be generated according to the logical level of the output voltage of the Out terminal.

If the selector 1320 selects two different inverters, the comparator 1330 may generate a 1-bit identification key again.

When the selector 1320 selects two of the five inverters 1311 to 1315 and the comparator 1330 generates the identification key by comparing the logical thresholds of the two selected inverters, The identification key of the bit can be obtained.

Although five inverters are included in the present embodiment, the present invention is not limited thereto, and various modifications can be made in consideration of the number of bits of the identification key to be generated, the area of the circuit, and the like.

Since the area of the comparator 1330 that can be integrated in the semiconductor chip is considerably larger than the area of the inverters 1331 to 1335, in this embodiment, a plurality of inverters and one Of comparator 1330 is connected. However, in another application, one comparator per pair of inverters may be mated to generate an N-bit identification key.

14 shows a semiconductor chip for generating an identification key using a process deviation of a differential amplifier, according to an embodiment of the present invention.

A semiconductor chip 1400 including a differential amplifier composed of at least one of a transistor and a resistor amplifies a difference between the voltages of the first input terminal 1411 and the second input terminal and is connected to the first output terminal 1421 And the second output terminal 1422 as a voltage difference.

Therefore, when the first input terminal 1411 and the second input terminal 1422 are short-circuited, theoretically, a voltage difference between the first output terminal 1421 and the second output terminal 1422, which is an output voltage value, Should be zero.

However, the voltage of the first output terminal 1421 and the voltage of the second output terminal 1422 are not exactly equal to each other because of the difference in electric characteristics between the elements due to the process variations.

Therefore, if a comparison is made as to which of the two output terminals has a higher voltage in the same manner as the comparison of the logical threshold values of the inverter of Fig. 12, a 1-bit identification key can be generated.

For example, when the first input terminal 1411 and the second input terminal 1412 are short-circuited and the voltage value of the first output terminal 1421 is higher than the voltage value of the second output terminal 1422, Quot; 1 ", and in the opposite case, it can be recognized as a digital value "0 ".

Further, if the semiconductor chip 1400 is a unit cell and N unit cells are formed, an N-bit identification key can be generated. One embodiment of such a configuration is described in more detail below with reference to FIG.

The difference in the output terminal voltages of such a differential amplifier circuit depends not only on the difference in electrical characteristics of the transistor elements but also on the difference in electrical characteristics of passive elements (not shown) such as resistors, capacitors or inductors that can be included in the semiconductor chip 1400 .

That is, a process variation during chip fabrication may cause the shape / structure difference of the passive element, and the passive element may have a difference in the actual numerical value.

Although not shown in FIG. 14, elements similar to the comparator 1230 of FIG. 12 can be used to compare the voltage values of the first output terminal 1421 and the second output terminal 1422. FIG.

15 shows a semiconductor chip according to an embodiment of the present invention.

According to an embodiment of the present invention, the semiconductor chip 1500 includes six differential amplifiers 1511 to 1516, a selector 1520 for selecting one of the six differential amplifiers, and a selector 1520 for selecting one of the six differential amplifiers And a comparator 1530 for comparing the two output voltages of the differential amplifiers selected by the comparator 1530 to generate a 1-bit identification key.

In this case, all the input terminals of the six differential amplifiers 1511 to 1516 are short-circuited and have the same voltage.

According to an embodiment of the present invention, the selector 1520 may be a 6: 1 MUX element. It should be noted that the present invention is not limited to the specific embodiments. Accordingly, the number of input / output ports of the MUX element may be changed, and further, the selection unit 1520 may be an element other than the MUX element. The 6: 1 MUX device outputs the output voltages of six differential amplifiers input through twelve input terminals to two output terminals. These two output terminals are connected to the two input terminals of the comparator 1530.

In this embodiment, the semiconductor chip 1500 can generate a 6-bit digital identification key.

Since the area of the comparator 1330 that can be integrated in the semiconductor chip is considerably larger than the area of the differential amplifiers 1511 to 1516 in the present embodiment, An amplifier and one comparator 1330 are connected. However, the number of differential amplifiers that can be connected to one of the comparators may be variously changed according to the number of bits of the identification key to be generated, the area of the circuit, various constraints in the process, and the like. Should be understood to be included.

The method according to an embodiment of the present invention can be implemented in the form of a program command which can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

Claims (1)

In a semiconductor chip,
A pair of inverter element parts constituting a feedback structure; And
A reset switch connected between the pair of elements;
.

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